Broadband and low-stray down-conversion circuit with self-adaptive input clock power

Abstract

The invention discloses a broadband low-stray down-conversion circuit with self-adaptive input clock power, which comprises a local oscillation circuit, a frequency mixing circuit, an intermediate frequency amplification circuit and a power supply circuit, and is characterized in that the local oscillation circuit receives an external input 100MHz clock signal, the input power is detected through a coupler coupling branch, and the input power is output to a local oscillation source through a straight-through end; the power of the clock signal output to the local oscillator source is adaptively adjusted; the input radio frequency input signal of the frequency mixing circuit is fRF, the local oscillator input signal is fLO, the local oscillator input signal f LO is divided into two orthogonal local oscillator signals through power after passing through the amplifier 2 and the 90-degree bridge, the radio frequency input signal is connected to the input end of the 0-degree power divider and is divided into two paths through the 0-degree power divider, and the two paths of local oscillator signals are connected to the output end of the 0-degree power divider. Two groups of local oscillator signals and radio frequency signals are respectively provided for two frequency mixing circuits with the same performance to generate two paths of down-conversion intermediate frequency signals, the two paths of down-conversion intermediate frequency signals comprise a required intermediate frequency signal fRF-fLO and a third-order spurious signal 2fLO-fRF, the two paths of down-conversion intermediate frequency signals pass through an in-phase power divider, the two paths of intermediate frequency signals fRF-fLO are combined and output, and the two paths of third-order spurious signals 2fLO-fRF are opposite in phase and mutually offset; and the intermediate-frequency amplification circuit filters and amplifies the intermediate-frequency signal output by the combined circuit. The circuit has the advantages of self-adaptive input clock power, wide band, low stray, high reliability and the like.

Description

Technical Field

[0001] The invention relates to the field of intermediate frequency signal processing in electronic communication, in particular to a broadband, low spurious down-conversion circuit with adaptive input clock power. Background Art

[0002] In RF and microwave communication systems, the received broadband RF signal needs to be processed by a down-conversion circuit to convert the RF signal frequency to an intermediate frequency for digital processing. Generally, mixers are electronic components widely used in frequency conversion. By utilizing the nonlinear characteristics of the mixer, the signal frequency can be up-converted or down-converted under the drive of the local oscillator signal to obtain the signal frequency we need. In the down-conversion process, due to the nonlinearity of the mixer, the frequency components of the output signal are very rich. Assuming the input RF signal frequency is fRF, the local oscillator signal frequency is fLO, and the output down-conversion intermediate frequency signal frequency is fIF, then the intermediate frequency output frequency fIF may contain the following frequency products:

[0003] n*fLO-m*fRF, (n*fLO≥m*fRF m≥1, n≥1, m and n are integers);

[0004] m*fRF-n*fLO, (m*fRF≥n*fLO).

[0005] Generally, down-conversion requires fLO-fRF, or fRF-fLO, so a bandpass filter is needed to filter out the required RF frequency. Other frequency products are spurious frequencies and need to be suppressed as cleanly as possible. Figure 2 It is the frequency product produced by down-conversion of the intermediate frequency fIF. Assuming that the signal frequency required for down-conversion is fRF-fLO, the frequency products with closer frequencies on both sides are fLO and 2fLO-fRF. The analysis of the mixing frequency products is used to guide the selection of the performance indicators of the bandpass filter and effectively suppress the spurious frequency. However, the signal in the communication system always has a certain bandwidth. When the bandwidth of the intermediate frequency signal becomes wider, the required down-conversion signal band fRF-fLO will be close to the third-order product 2fLO-fRF band in the spectrum, or even overlap, so the bandpass filter cannot filter out the spurious frequency.

[0006] At the same time, the phase noise of the local oscillator signal and its spurious emission will also affect the spurious emission of the mixer circuit output signal. The external input clock signal is transmitted to the local oscillator. Various frequency sources have high requirements for the input reference signal. The reference signal power and spurious emission will affect the quality of the mixer circuit output signal. The external input reference signal usually needs to be transmitted to the local oscillator through cables and various adapter connectors. When the transmission link shielding effect is poor or other reasons introduce spurious emission, or affect the stability of the reference signal power, the local oscillator signal output by the local oscillator will be affected accordingly.

[0007] Through the above analysis, if the third-order product 2fLO-fRF can be effectively suppressed, the quality of the local oscillator signal and the intermodulation capability of the output intermediate frequency signal can be improved, then the bandwidth can be set to span an octave, or even wider intermediate frequency signal for down-conversion processing.

[0008] In addition, the reliability of the active frequency conversion circuit is significantly affected by the power supply circuit. When the external power supply interface inputs reverse voltage, the back-end circuit often fails or even burns out. Therefore, the anti-mis-power-on design can improve the reliability of the corresponding circuit. At the same time, the output end of the internal voltage regulator of the power supply circuit supplies power to the functional circuits of the back end. When the back-end circuit is powered by positive and negative voltages, and the power supply point is not in a high-impedance state, when one voltage is transmitted to the corresponding power supply point first, the voltage will affect its reverse voltage power supply point, and reversely affect the corresponding voltage regulator to enter the protection state and not output the corresponding voltage. For example, the attached Figure 1 In the process, the -5V level is loaded on a certain type of +5V, -5V dual voltage power supply chip in the frequency source circuit before the +5V level. The two power supply pins of the chip are not in an open circuit state, and the -5V level is connected in series to the +5V pin, making it a negative level, which in turn affects the -5V regulator, causing it to enter a protection state and unable to output -5V normally, causing the -5V branch of this down-conversion circuit to not work normally, affecting the circuit reliability. Summary of the invention

[0009] The purpose of the present invention is to provide a broadband, low-spurious down-conversion circuit with adaptive input clock power, which can effectively suppress spurious signals in signal transmission, improve the quality of the local oscillator output signal, and improve the reliability of the power supply circuit during the broadband down-conversion process.

[0010] The technical solution to achieve the purpose of the present invention is: a broadband, low-spurious down-conversion circuit with adaptive input clock power, including a local oscillator circuit, a mixer circuit, an intermediate frequency amplifier circuit and a power supply circuit, wherein:

[0011] The local oscillator circuit receives an external input 100MHz clock signal, detects it through the coupling branch of the coupler, outputs it to the local oscillator source through the through end, and adaptively adjusts the power of the clock signal output to the local oscillator source;

[0012] The input RF signal of the mixer circuit is fRF, and the input signal of the local oscillator is fLO. The local oscillator input signal fLO is divided into two orthogonal local oscillator signals after passing through amplifier 2 and a 90° bridge. The RF input signal is connected to the input end of the 0° power divider and is divided into two paths through the 0° power divider. The two groups of local oscillator signals and RF signals are respectively provided to two mixer circuits with the same performance to generate two down-converted intermediate frequency signals, including the required intermediate frequency signal fRF-fLO and the third-order spurious signal 2fLO-fRF. The two intermediate frequency signals fRF-fLO are then combined and output through the in-phase 0° power divider. The two third-order spurious signals 2fLO-fRF have opposite phases and cancel each other out.

[0013] The intermediate frequency amplifier circuit filters and amplifies the intermediate frequency signal output by the combined circuit;

[0014] The power supply circuit provides power supply signals for the local oscillator circuit, the mixer circuit and the intermediate frequency amplifier circuit.

[0015] Furthermore, the local oscillator circuit includes a bandpass filter, a variable gain amplifier, a coupler, a detection circuit, a threshold comparison circuit, and a digital controller, wherein the local oscillator circuit receives an external input 100MHz clock signal and filters out the 100MHz out-of-band signal through a high-suppression 100MHz bandpass filter; the clock signal passes through the variable gain amplifier and the coupler, the coupler's through end is connected to the local oscillator source, and the coupling end is connected to the detection circuit, threshold comparison circuit, and digital controller arranged in sequence to feedback to the variable gain amplifier, and the variable gain amplifier is used to adjust the power of the 100MHz reference signal input to the local oscillator source.

[0016] Furthermore, the intermediate frequency amplification circuit includes an intermediate frequency filter and an amplifier 3, wherein the amplifier 3 uses an HGC462 amplifier, the output power 1dB compression point is +23.5dBm, and the output IP3 is +34dBm.

[0017] Furthermore, a diode is connected in series at the input end of the power supply circuit. When the input is at a negative level, the input voltage passes through the series diode normally, otherwise the series diode is cut off to protect the back-end circuit; a diode is connected in parallel to the ground at the output end of the power supply circuit. When the output end is pulled up to a positive level, the parallel diode works and short-circuits the ground, pulling the level at that position to a short circuit to the ground, so that the power supply circuit regulator works normally.

[0018] Furthermore, the power supply circuit includes two voltage branches. The voltage regulator U1 in the first voltage branch is a negative voltage linear voltage regulator of the XC3091DBA type, and a diode D1 of model 1N5819 is connected in series at its input end. When the input is a negative level, the input voltage passes through the diode D1 normally. If the input is a positive level, the diode D1 is cut off to protect the back-end circuit; a diode D2 of model 1N5819 is connected in parallel to the ground at the output end of the voltage regulator U1. When the output end is pulled up to a positive level, the diode D2 works and is short-circuited to the ground, pulling the level to a short circuit to the ground, so that the voltage regulator U1 works normally;

[0019] The voltage regulator U2 in the second voltage branch is a XC5322FCA linear voltage regulator, with a diode D3 connected in series at the input end and a diode D4 connected in parallel at the output end. The diode D3 is model 1N5819, and the diode D4 is model 1N5819.

[0020] Furthermore, the frequency range of the RF input signal is 30 to 40 GHz, the frequency of the local oscillator input signal is 24 GHz, the frequency range of the required output down-converted intermediate frequency signal is 6 to 16 GHz, and the frequency range of the third-order spurious signal fLO*2-fRF is 8 to 18 GHz.

[0021] Furthermore, the performance parameters of the two mixers in the mixing circuit are required to be consistent, and they are preferably monolithic mixers from the same batch and the same wafer that are adjacent to each other.

[0022] Compared with the prior art, the present invention has the following significant advantages:

[0023] 1. After receiving the external input 100MHz clock signal, a high-suppression 100MHz bandpass filter is set to filter out the 100MHz out-of-band signal, which can effectively suppress other low-frequency spurious signals brought in by the external input signal during the transmission process and reduce the impact of spurious signals near the 100MHz signal on the back-end local oscillator source;

[0024] 2. Since the input clock signal passes through the variable gain amplifier and coupler, the coupler through-end is connected to the local oscillator source, and the coupling end is connected to the detection circuit, threshold comparison circuit, and digital controller set in sequence to feed back to the variable gain amplifier. The 100MHz reference signal power input to the local oscillator source is adjusted by the variable gain amplifier, and the reference signal power transmitted to the local oscillator source can be adaptively transmitted, and will not lose lock due to being too small, or affect phase noise due to being too large, thereby improving the phase noise and reliability of the local oscillator source;

[0025] 3. Since the local oscillator signal output by the local oscillator source passes through a 90° bridge, is divided into two paths for frequency conversion, and is combined through a co-phase 0° power divider, in the process of broadband down-conversion, the third-order spurious signals in signal transmission are effectively suppressed, and the spurious signals generated by the mixing circuit are reduced; at the same time, the down-conversion output intermediate frequency bandwidth can reach 1 to 2 octaves, and the down-conversion output bandpass filter bandwidth can be set to 1 to 2 intermediate frequency bandwidths;

[0026] 4. Since the intermediate frequency amplifier uses a high output power 1dB compression point and a high output IP3 amplifier (the Zhongke Haigao HGC462 amplifier can be selected, with an output power 1dB compression point of +23.5dBm and an output IP3 of +34dBm), harmonics and other intermodulation signals are suppressed, which can improve the spurious suppression performance of the down-conversion circuit;

[0027] 5. Since diodes D1 and D3 (Schottky diode 1N5819 from Zhenhua Yongguang Company can be selected, with a reverse working peak voltage of 40V and not easy to break down in the reverse direction) are connected in series at the input end of each voltage branch to prevent reverse voltage input and protect the back-end circuit; diodes D2 and D4 (1N5819) are connected in parallel at the output end to prevent the voltage regulator from not working properly due to reverse voltage at the output end, thereby improving circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The invention discloses a broadband, low spurious down-conversion circuit with adaptive input clock power.

[0029] Figure 2 It is a schematic diagram of the local oscillator circuit in the present invention.

[0030] Figure 3 This is the principle block diagram of the mixer circuit in the present invention.

[0031] Figure 4 It is a schematic diagram of broadband down-conversion spectrum.

[0032] Figure 5 It is a schematic diagram of the power supply stabilizer in the present invention. DETAILED DESCRIPTION

[0033] The invention discloses a broadband, low-spurious down-conversion circuit with adaptive input clock power, comprising a local oscillator circuit, a frequency mixer circuit, an intermediate frequency amplifier circuit and a power supply circuit. The local oscillator circuit receives an external input 100MHz clock signal, detects the clock signal power of the output local oscillator source through the coupling branch of the coupler, and feeds it back to the variable gain amplifier to adaptively adjust the clock signal power output to the local oscillator source; the RF input signal of the mixing circuit is fRF, and the local oscillator input signal is fLO, wherein the local oscillator input signal fLO is powered divided into two orthogonal local oscillator signals, and the RF input signal fRF is powered divided into two in-phase RF signals, which are respectively provided to two mixing circuits with the same performance to generate two intermediate frequency signals; the signal generated by the mixing circuit includes the required intermediate frequency signal fRF-fLO and the third-order spurious signal 2fLO-fRF, and the two intermediate frequency signals fRF-fLO are combined and output through the in-phase 0° power divider, and the two third-order spurious signals 2fLO-fRF have opposite phases and cancel each other out, thereby reducing the output spurious; the intermediate frequency amplification circuit filters and amplifies the combined output intermediate frequency signal fRF-fLO; and the power supply circuit supplies power to the down-conversion circuit.

[0034] The local oscillator circuit receives an external input 100MHz clock signal, and filters out the 100MHz out-of-band signal through a high-suppression 100MHz bandpass filter; the clock signal passes through a variable gain amplifier and a coupler, the coupler through-end is connected to the local oscillator source, and the coupling end is connected to the detection circuit, threshold comparison circuit, and digital controller arranged in sequence to feed back to the variable gain amplifier. The power of the 100MHz reference signal input to the local oscillator source is adjusted through the variable gain amplifier to improve its phase noise and reliability.

[0035] The local oscillator source output port in the mixing circuit passes through the amplifier 2 and the set 90° bridge, and the local oscillator input signal is set to fLO, and the radio frequency input signal is set to fRF, wherein the local oscillator input signal fLO is divided into two orthogonal local oscillator signals after passing through the amplifier 2 and the 90° bridge. The radio frequency signal input port is connected to the input end of the 0° power divider, and the output end of the 0° power divider is divided into two paths, which are respectively provided to two mixing circuits with the same performance to generate two down-converted intermediate frequency signals. The signal generated by the mixing circuit includes the required intermediate frequency signal fRF-fLO and the third-order spurious signal 2fLO-fRF. Through the 0° power divider, the two intermediate frequency signals fRF-fLO are combined and output, and the two third-order spurious signals 2fLO-fRF are opposite in phase and cancel each other, which can effectively suppress the third-order spurious signals in signal transmission. The present invention divides the signal that needs to be frequency-converted into two paths, so that the third-order spurious signals generated by the two signals in the mixer are opposite in phase, thereby achieving mutual cancellation.

[0036] Assume that the input local oscillator signal is: ACos2πfLot, the RF signal is: BCos2πfRFt, the local oscillator signal is divided into two orthogonal signals after a 90-degree bridge: 1 / 2*ACos2πfLot, 1 / 2*ACos(2πfLot+π / 2), the RF signal is divided into two in-phase signals after a 0-degree power divider: 1 / 2*BCos2πfRFt, after mixing, two mixed signals are generated, of which the useful intermediate frequency signals are: 1 / 2*C Cos2π(fRF-fLO)t, 1 / 2*C Cos(2π(fRF-fLO)t±π / 2), the two intermediate frequency signals have equal amplitudes and a phase difference of 90 degrees; the third-order spurious signals are: 1 / 2*DCos(2π(2fLO-fRF)t), 1 / 2*D Cos(2π(2fLO-fRF)t±π)=-1 / 2*D Cos(2π(2fLO-fRF)t), the two third-order spurious signals have equal amplitudes and opposite phases. The two down-converted intermediate frequency signals and the third-order spurious signals are synthesized and output through the 0° power divider. The output down-converted intermediate frequency signal is 1 / 2*C Cos(2π(fRF-fLO)t±π / 4), and the two third-order spurious signals have equal amplitudes and opposite phases, so they cancel each other out and the output is zero.

[0037] The intermediate frequency amplifier circuit suppresses harmonics and other intermodulation signals by designing the intermediate frequency filter and selecting an amplifier with a high output power 1dB compression point and a high output IP3 (the Zhongke Haigao HGC462 amplifier can be selected, with an output power 1dB compression point of +23.5dBm and an output IP3 of +34dBm), thereby improving the spurious suppression performance of the down-conversion circuit.

[0038] The two power branches of the power supply circuit (output -12V to -5V and +6V to +5V respectively) are connected in series with diodes D1 and D3 (Schottky diode 1N5819 from Zhenhua Yongguang Company can be used) at the input end to prevent reverse voltage input and protect the back-end circuit; diodes D2 and D4 (1N5819) are connected in parallel at the output end to prevent the voltage regulator circuit from not working properly due to reverse voltage at the output end.

[0039] In summary, in the process of down-conversion, most of the third-order spurious signals 2fLO-fRF are within the intermediate frequency band and cannot be filtered out. The above method can effectively suppress the third-order spurious signals in signal transmission, and the intermediate frequency bandwidth of the down-conversion output can reach 1 to 2 octaves; then, by designing the intermediate frequency filter and selecting a high output power 1dB compression point and a high output IP3 amplifier D3, the spurious suppression performance of the entire down-conversion circuit can be improved; at the same time, reasonably setting the clock signal power input to the local oscillator source can improve the working reliability of the local oscillator source and improve its output phase noise; in addition, diodes D1 to D4 are connected in series and in parallel at the input and output ends of the regulator in the power supply circuit to improve the reliability of the power supply circuit and provide a stable power output for the down-conversion circuit.

[0040] Example

[0041] This embodiment is a broadband, low spurious down-conversion circuit with adaptive input clock power, such as Figure 1 As shown, it includes a local oscillator circuit, a mixing circuit, an intermediate frequency amplifier circuit, and a power supply circuit. The local oscillator circuit receives an external input 100MHz clock signal, detects the power of the clock signal output to the local oscillator source through a coupling branch of a coupler, and feeds back to a variable gain amplifier to adaptively adjust the power of the clock signal output to the local oscillator source; the input signal of the mixing circuit is fRF, and the input signal of the local oscillator is fLO, wherein the local oscillator input signal fLO is powered to be divided into two orthogonal local oscillator signals, and the radio frequency input signal fRF is powered to be divided into two in-phase radio frequency signals, which are respectively provided to two mixing circuits with the same performance to generate two intermediate frequency signals, and the signal generated by the mixing circuit includes the required intermediate frequency signal fRF-fLO and the third-order spurious signal 2fLO-fRF, and the two intermediate frequency signals fRF-fLO are combined and output through an in-phase 0° power divider, and the two third-order spurious signals 2fLO-fRF have opposite phases and cancel each other out, thereby reducing the output spurious; the intermediate frequency amplifier circuit filters and amplifies the output fRF-fLO intermediate frequency signal; and the power supply circuit supplies power to the down-conversion circuit.

[0042] The local oscillator circuit is as follows: Figure 2 As shown, an external input 100MHz clock signal is received, and a 100MHz bandpass filter with high suppression removes the 100MHz out-of-band signal; the clock signal is fed back to the variable gain amplifier through a variable gain amplifier and a coupler, and the coupler is connected to the detection circuit, threshold comparison circuit, and digital controller that are set in sequence. The power of the 100MHz reference signal input to the local oscillator source is adjusted through the variable gain amplifier to improve its phase noise and reliability.

[0043] The mixing circuit is as follows Figure 3As shown, the local oscillator source output port passes through amplifier 2 and a 90° bridge, and the local oscillator input signal is set to fLO, and the radio frequency input signal is set to fRF, wherein the local oscillator input signal fLO is split into two orthogonal local oscillator signals after passing through amplifier 2 and a 90° bridge. The radio frequency signal input port is connected to the input end of a 0° power divider, and the output end of the 0° power divider is divided into two paths, which are respectively provided to two mixing circuits with the same performance to generate two down-converted intermediate frequency signals. The signals generated by the mixing circuit include the required intermediate frequency signal fRF-fLO and the third-order spurious signal 2fLO-fRF, as shown in FIG. Figure 4 As shown, through the in-phase 0° power divider, the two intermediate frequency signals fRF-fLO are combined and output, and the two third-order spurious signals 2fLO-fRF are in opposite phases and cancel each other out, which can effectively suppress the third-order spurious signals in signal transmission. The present invention divides the signal that needs to be frequency converted into two paths, so that the third-order spurious signals generated by the two signals in the mixer are in opposite phases, thereby canceling each other out. The performance parameter requirements of the two mixers are consistent, and preferably they are monolithic mixers adjacent to the same wafer in the same batch.

[0044] Furthermore, the input RF signal range is 30-40 GHz, the local oscillator signal is 24 GHz, the required output down-conversion intermediate frequency signal range is 6-16 GHz, and the third-order spurious signal range is fLO*2-fRF, i.e., 8-18 GHz. This third-order spurious signal is within the intermediate frequency band and cannot be directly filtered out by a filter, but can only be determined by the performance of the mixer itself. To achieve the spurious suppression requirement of 60 dBc, the amplitude is offset and reduced by the method of the present invention, which can meet the spurious suppression requirement of down-conversion.

[0045] The 30-40 GHz signal is split into two RF signals through a 0° power divider and input into two equal-phase mixer input ends respectively; the 24 GHz local oscillator signal is input into a 90° bridge input end, and the output end of the 90° bridge is divided into two paths and connected to the input end of the first mixer local oscillator and the input end of the second mixer local oscillator respectively; the output end of the first mixer intermediate frequency and the output end of the second mixer are both 6-16 GHz intermediate frequency signals, including third-order spurious signals of 8-18 GHz. The two intermediate frequency signals are connected to the input end of the 0° power divider, and after being combined, they are passed through a bandpass filter and amplified output to offset the third-order spurious signals of 8-18 GHz. The spurious suppression after mixing meets the 60 dBc requirement.

[0046] The intermediate frequency amplifier circuit suppresses harmonics and other intermodulation signals by designing the intermediate frequency filter and selecting an amplifier with a high output power 1dB compression point and a high output IP3 (the Zhongke Haigao HGC462 amplifier can be selected, with an output power 1dB compression point of +23.5dBm and an output IP3 of +34dBm), thereby improving the spurious suppression performance of the down-conversion circuit.

[0047] The power supply circuit is as follows Figure 5 As shown, the voltage regulator U1 is a negative voltage linear voltage regulator of type XC3091DBA, and the diode D1 connected in series at its input end is 1N5819. When the input is at a negative level, the input voltage can pass through D1 normally. If the positive level is connected to the input end, the diode is cut off to protect the back-end circuit; the diode D2 connected in parallel to the ground at the output end of the voltage regulator is 1N5819. When the output end is pulled up to a positive level for some reason, D2 works and short-circuits to the ground, pulling the level at that position to short-circuit to the ground, so that U1 can work normally. Similarly, the voltage regulator U2 is a linear voltage regulator of type XC5322FCA, and the input end is connected in series with D3, and the output end is connected in parallel with D4 to improve the circuit reliability.

[0048] In summary, the circuit of the present invention obtains a reliable local oscillator signal with low phase noise through a local oscillator circuit with adaptive input clock power, the mixing circuit reduces the third-order stray signal, the intermediate frequency amplifier circuit suppresses harmonics and intermediate frequency intermodulation signals, and the power supply circuit provides high-reliability power supply. The present invention has the advantages of adaptive input clock power, broadband, low stray, and high reliability. The above is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A broadband, low spurious down-conversion circuit with adaptive input clock power, characterized in that: It includes a local oscillator circuit, a mixing circuit, an intermediate frequency amplifier circuit and a power supply circuit, wherein: The local oscillator circuit receives an external input 100MHz clock signal, detects the input power through the coupling branch of the coupler, outputs it to the local oscillator source through the direct end, and adaptively adjusts the clock signal power output to the local oscillator source; The input RF signal of the mixer circuit is fRF, and the input signal of the local oscillator is fLO. The local oscillator input signal fLO is divided into two orthogonal local oscillator signals after passing through amplifier 2 and a 90° bridge. The RF input signal is connected to the input end of the 0° power divider and is divided into two paths through the 0° power divider. The two groups of local oscillator signals and RF signals are respectively provided to two mixer circuits with the same performance to generate two down-converted intermediate frequency signals, including the required intermediate frequency signal fRF-fLO and the third-order spurious signal 2fLO-fRF. The two intermediate frequency signals fRF-fLO are then combined and output through the in-phase 0° power divider. The two third-order spurious signals 2fLO-fRF have opposite phases and cancel each other out. The intermediate frequency amplifier circuit filters and amplifies the intermediate frequency signal output by the combined circuit; The power supply circuit provides power supply signals for the local oscillator circuit, the mixer circuit and the intermediate frequency amplifier circuit.

2. The broadband, low spurious down-conversion circuit with adaptive input clock power according to claim 1, characterized in that: The local oscillator circuit includes a bandpass filter, a variable gain amplifier, a coupler, a detection circuit, a threshold comparison circuit, and a digital controller, wherein the local oscillator circuit receives an external input 100MHz clock signal, and filters out the 100MHz out-of-band signal through a high-suppression 100MHz bandpass filter; the clock signal passes through the variable gain amplifier and the coupler, the coupler through-end is connected to the local oscillator source, and the coupling end is connected to the detection circuit, the threshold comparison circuit, and the digital controller arranged in sequence to feed back to the variable gain amplifier, and the variable gain amplifier is used to adjust the power of the 100MHz reference signal input to the local oscillator source.

3. The broadband, low spurious down-conversion circuit with adaptive input clock power according to claim 1, characterized in that: The intermediate frequency amplification circuit includes an intermediate frequency filter and an amplifier 3, wherein the amplifier 3 uses an HGC462 amplifier, the output power 1dB compression point is +23.5dBm, and the output IP3 is +34dBm.

4. The broadband, low spurious down-conversion circuit with adaptive input clock power according to claim 1, characterized in that: A diode is connected in series with the input end of the power supply circuit. When the input is at a negative level, the input voltage passes through the series diode normally, otherwise the series diode is cut off to protect the back-end circuit; a diode is connected in parallel with the ground at the output end of the power supply circuit. When the output end is pulled up to a positive level, the parallel diode works and short-circuits the ground, pulling the level at that position to a short circuit to the ground, so that the power supply circuit regulator works normally.

5. The broadband, low spurious down-conversion circuit with adaptive input clock power according to claim 4, characterized in that: The power supply circuit includes two voltage branches. The voltage regulator U1 in the first voltage branch is a negative voltage linear voltage regulator of type XC3091DBA, whose input end is connected in series with a diode D1 of model 1N5819. When the input is a negative level, the input voltage passes through the diode D1 normally. If the input is a positive level, the diode D1 is cut off to protect the back-end circuit. The output end of the voltage regulator U1 is connected in parallel with a diode D2 of model 1N5819 to the ground. When the output end is pulled up to a positive level, the diode D2 works and is short-circuited to the ground, pulling the level to a short circuit to the ground, so that the voltage regulator U1 can work normally. The voltage regulator U2 in the second voltage branch is a XC5322FCA linear voltage regulator, with a diode D3 connected in series at the input end and a diode D4 connected in parallel at the output end. The diode D3 is model 1N5819, and the diode D4 is model 1N5819.

6. The broadband, low spurious down-conversion circuit with adaptive input clock power according to claim 1, characterized in that: The RF input signal frequency range is 30 to 40 GHz, the local oscillator input signal frequency is 24 GHz, the required output down-converted intermediate frequency signal frequency range is 6 to 16 GHz, and the frequency range of the third-order spurious signal fLO*2-fRF is 8 to 18 GHz.

7. A broadband, low spurious down-conversion circuit with adaptive input clock power according to claim 1, characterized in that: The performance parameters of the two mixers in the mixing circuit are required to be consistent, and the two mixers are selected to be adjacent single-chip mixers from the same batch and the same wafer.

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