High-immunity clock control circuit, power supply control circuit and integrated circuit

Abstract

The invention relates to the technical field of clock control, and discloses a high-immunity clock control circuit, a power supply control circuit and an integrated circuit, the clock control circuit comprises a voltage detection unit, a NOR gate, an AND gate, a plurality of TFF triggers connected in series, a latch LAT and an OR gate; in actual use, the fluctuation of the power supply voltage is detected through the voltage detection unit, when the power supply voltage changes upwards or downwards, a changed high-voltage detection signal or a low-voltage detection signal enables the latch LAT to stop outputting the clock signal through the TFF triggers connected in series, and when the power supply voltage returns to normal, the latch LAT stops outputting the clock signal. The TFF trigger connected in series enables the latch LAT to continuously output the clock signal after timing, so that the abnormal clock signal is prevented from being generated by stopping the clock signal when the power supply voltage is abnormal, and the anti-interference performance of the clock control circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of clock control, and in particular to a clock control circuit, a power supply control circuit and an integrated circuit with high anti-interference performance. Background Art

[0002] In an integrated circuit system, the stability of the clock signal is crucial to the reliable operation of the integrated circuit system, and the stability of the clock signal is related to the power supply voltage. The more stable the power supply voltage, the more stable the clock signal.

[0003] Currently, interference is mostly eliminated by filtering the power supply voltage through a filter circuit. However, when the power supply voltage of the circuit system has a large amount of high-frequency interference, the filter circuit itself will be affected by the voltage fluctuation and generate a glitch signal, and the generated glitch signal will also affect the stability of the clock signal.

[0004] In the existing circuit system, the anti-interference ability of the circuit system is very strong in the dormant state, when the clock is stopped, and the logic circuit that determines the operating state of the circuit system is composed of a large number of triggers, latches and gate circuits; The trigger and latch have their own latch structure and strong anti-interference ability. As long as the trigger and latch state are not affected by interference, the output result of the combinational logic gate circuit will not change. In addition, triggers and latches are clock-sensitive circuits, and have certain requirements on the input setup time and hold time, so the clock cannot have glitches or unstable beats. Summary of the invention

[0005] In view of the shortcomings of the background technology, the present invention provides a clock control circuit, a power supply control circuit and an integrated circuit with high interference resistance. The technical problem to be solved is that the clock in the existing integrated circuit system is affected by power supply voltage fluctuations and has glitches.

[0006] In order to solve the above technical problems, in a first aspect, the present invention provides the following technical solutions: a clock control circuit with high anti-interference performance, comprising: A voltage detection unit, generating a high voltage detection signal and a low voltage detection signal based on a change in a power supply voltage; A NOR gate, used for performing NOR processing on the high voltage detection signal and the low voltage detection signal; An AND gate, one input end of which is electrically connected to the output end of the NOR gate, and the other input end of which is used to input a reset signal; A plurality of TFF triggers connected in series, wherein the series connection is that the QN output end of the preceding TFF trigger is electrically connected to the clock end of the succeeding TFF trigger; the output end of the AND gate is electrically connected to the reset end of each TFF trigger; The Q output terminal of the terminal TFF trigger is electrically connected to the clock terminal of the latch LAT and an input terminal of the OR gate respectively, and is used to output a latch control signal CLK_LAT; The other input terminal of the OR gate and the D input terminal of the latch LAT are used to input the clock signal CLKIN.

[0007] In certain embodiments of the first aspect, the number of TFF triggers connected in series is four.

[0008] In a certain implementation of the first aspect, the voltage detection unit includes a resistor R1, a capacitor C1, a first inverter, and a second inverter; One end of the resistor R1, the power supply end of the first inverter and the input end of the second inverter are respectively used to input the power supply voltage, and the other end of the resistor R1 is respectively electrically connected to the input end of the first inverter and the power supply end of the second inverter, and is grounded through the capacitor C1; The output end of the first inverter is used to output the high voltage detection signal, and the output end of the second inverter is used to output the low voltage detection signal.

[0009] In a certain implementation manner of the first aspect, the first inverter includes a MOS transistor P1 and a MOS transistor N1, a source of the MOS transistor P1 is a power supply terminal of the first inverter, a drain of the MOS transistor P1 is electrically connected to a drain of the MOS transistor N1 and is an output terminal of the first inverter, a gate of the MOS transistor P1 is electrically connected to a gate of the MOS transistor N1 and is an input terminal of the first inverter, and a source of the MOS transistor N1 is grounded; The second inverter includes a MOS transistor P2 and a MOS transistor N2. The source of the MOS transistor P2 is the power supply terminal of the second inverter. The drain of the MOS transistor P2 is electrically connected to the drain of the MOS transistor N2 and is the output terminal of the second inverter. The gate of the MOS transistor P2 is electrically connected to the gate of the MOS transistor N2 and is the input terminal of the second inverter. The source of the MOS transistor N2 is grounded.

[0010] In a certain implementation manner of the first aspect, the size of the MOS transistor P1 is the same as the size of the MOS transistor P2, and the size of the MOS transistor N1 is the same as the size of the MOS transistor N2.

[0011] In a certain implementation of the first aspect, a width-to-length ratio of the MOS transistor P1 is greater than a width-to-length ratio of the MOS transistor N1.

[0012] In a certain implementation of the first aspect, the sizes of the resistor R1, the capacitor C1, the MOS transistor P1, the MOS transistor N1, the MOS transistor P2, and the MOS transistor N2 are adjustable to match different detection sensitivities.

[0013] In a second aspect, the present invention provides a power supply control circuit, comprising the above-mentioned clock control circuit with high anti-interference performance, and further comprising a transmission gate, a resistor R2 and a capacitor C2, wherein one end of the resistor R2 and an input end of the transmission gate are respectively used to input the power supply voltage, the other end of the resistor R2 is respectively electrically connected to the output end of the transmission gate and one end of the capacitor C2, and the other end of the capacitor C2 is grounded; One control terminal of the transmission gate inputs the latch control signal CLK_LAT, and the other control terminal inputs the transmission control signal CLK_LAT_N, and the latch control signal CLK_LAT and the transmission control signal are two opposite signals; The transmission gate is turned on when the latch control signal CLK_LAT is at a high level, and is turned off when the latch control signal CLK_LAT is at a low level.

[0014] In a certain embodiment of the second aspect, the transmission gate includes a MOS transistor P3 and a MOS transistor N3, the source of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N3, and serves as the input end of the transmission gate, the drain of the MOS transistor P3 is electrically connected to the source of the MOS transistor N3, and serves as the output end of the transmission gate, the gate of the MOS transistor N3 is used to input the latch control signal CLK_LAT, and the gate of the MOS transistor P3 is used to input the transmission control signal CLK_LAT_N.

[0015] In a third aspect, the present invention provides an integrated circuit, comprising the above-mentioned power control circuit and a digital circuit, wherein the output end of the transmission gate is electrically connected to the digital circuit to provide an operating voltage for the digital circuit, and the Q output end of the latch LAT is electrically connected to the digital circuit to provide an output clock CLKOUT for the digital circuit.

[0016] Compared with the prior art, the present invention has the following beneficial effects: in actual use, the present invention detects fluctuations in power supply voltage through a voltage detection unit, and when the power supply voltage changes upward or downward, the changed high-voltage detection signal or low-voltage detection signal will cause the latch LAT to stop outputting the clock signal through the series-connected TFF trigger, and when the power supply voltage returns to normal, the series-connected TFF trigger causes the latch LAT to continue outputting the clock signal after timing, thereby avoiding the generation of abnormal clock signals by stopping the clock signal when the power supply voltage is abnormal, thereby improving the anti-interference ability of the clock control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of the present invention in Embodiment 1; Figure 2 is a circuit diagram of a voltage detection unit in Embodiment 1; Figure 3It is a relevant signal waveform diagram of the clock control circuit when the power supply voltage is normal; Figure 4 It is a waveform diagram of related signals of the clock control circuit when the power supply voltage is abnormal upward; Figure 5 It is a waveform diagram of related signals of the clock control circuit when the power supply voltage is abnormally downward; Figure 6 is a circuit diagram of the resistor R2, the capacitor C2 and the transmission gate in the second embodiment; Figure 7 It is a schematic diagram of the structure of the integrated circuit in the third embodiment. DETAILED DESCRIPTION

[0018] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0019] Embodiment 1 like Figure 1 As shown, a clock control circuit with high noise immunity comprises: A voltage detection unit 1 generates a high voltage detection signal and a low voltage detection signal based on a change in a power supply voltage VDD; The NOR gate NOR1 is used for performing NOR processing on the high voltage detection signal and the low voltage detection signal; An AND gate AND1, one input end of which is electrically connected to the output end of the NOR gate NOR1, and the other input end of which is used to input a reset signal RST_N; A plurality of TFF triggers connected in series, wherein the QN output terminal of the preceding TFF trigger is electrically connected to the clock terminal of the succeeding TFF trigger; and the output terminal of the AND gate AND1 is electrically connected to the reset terminal of each TFF trigger; The Q output terminal of the terminal TFF trigger is electrically connected to the clock terminal of the latch LAT and an input terminal of the OR gate OR1 respectively, and is used to output a latch control signal CLK_LAT; The other input terminal of the OR gate OR1 and the D input terminal of the latch LAT are used to input the clock signal CLKIN.

[0020] In actual use, the present invention detects the fluctuation of the power supply voltage VDD through the voltage detection unit 1. When the power supply voltage VDD changes upward or downward, the changed high-voltage detection signal or low-voltage detection signal will stop the latch LAT from outputting the clock signal CLKIN through the series-connected TFF trigger. When the power supply voltage VDD returns to normal, the series-connected TFF trigger allows the latch LAT to continue to output the clock signal after timing, so that when the power supply voltage VDD is abnormal, the clock signal CLKIN is stopped to avoid generating an abnormal clock signal, thereby improving the anti-interference performance of the clock control circuit.

[0021] Specifically, in this embodiment, the number of TFF flip-flops connected in series is four. In a certain implementation manner, the remaining number of TFF flip-flops may be set to set clock signal recovery times of different durations.

[0022] Specifically, in this embodiment, Figure 2 As shown, the voltage detection unit 1 includes a resistor R1, a capacitor C1, a first inverter 10 and a second inverter 11; One end of the resistor R1, the power supply end of the first inverter 10 and the input end of the second inverter 11 are respectively used to input the power supply voltage VDD, and the other end of the resistor R1 is respectively electrically connected to the input end of the first inverter 10 and the power supply end of the second inverter 11, and is grounded through the capacitor C1; The output end of the first inverter 10 is used to output a high voltage detection signal, and the output end of the second inverter 11 is used to output a low voltage detection signal.

[0023] More specifically, in Figure 1 In the embodiment, the first inverter 10 includes a MOS transistor P1 and a MOS transistor N1, the source of the MOS transistor P1 is the power supply terminal of the first inverter 10, the drain of the MOS transistor P1 is electrically connected to the drain of the MOS transistor N1, and is the output terminal of the first inverter 10, the gate of the MOS transistor P1 is electrically connected to the gate of the MOS transistor N1, and is the input terminal of the first inverter 10, and the source of the MOS transistor N1 is grounded; The second inverter 11 includes a MOS transistor P2 and a MOS transistor N2. The source of the MOS transistor P2 is the power supply terminal of the second inverter 11. The drain of the MOS transistor P2 is electrically connected to the drain of the MOS transistor N2 and is the output terminal of the second inverter 11. The gate of the MOS transistor P2 is electrically connected to the gate of the MOS transistor N2 and is the input terminal of the second inverter 11. The source of the MOS transistor N2 is grounded.

[0024] The size of the MOS transistor P1 is the same as that of the MOS transistor P2, and the size of the MOS transistor N1 is the same as that of the MOS transistor N2. In addition, the width-to-length ratio of the MOS transistor P1 is greater than that of the MOS transistor N1.

[0025] Exemplarily, the width of the MOS transistor P1 and the MOS transistor P2 may be 5 um, the length of the MOS transistor P1 and the MOS transistor P2 is 1 um, and both are PMOS transistors; The width of the MOS transistor N1 and the MOS transistor N2 may be 1 um, the length of the MOS transistor N1 and the MOS transistor N2 is 20 um, and both are NMOS transistors; In addition, the resistance value of the resistor R1 can be 5000Ω, and the capacitance value of the capacitor C1 can be 10pf.

[0026] Specifically, in this embodiment, the sizes of the resistor R1, the capacitor C1, the MOS transistor P1, the MOS transistor N1, the MOS transistor P2 and the MOS transistor N2 are adjustable to match different detection sensitivities, where the detection sensitivity refers to the change trend of the power supply voltage VDD that can be detected.

[0027] right Figure 1 and Figure 2 The circuit shown is analyzed as follows: First is the voltage detection unit 1, and its working process is as follows: According to the on-resistance formula between the source and drain of the MOS tube , where u is the majority carrier mobility, Cox is the gate oxide capacitance of the MOS tube, and Vth is the MOS tube turn-on threshold voltage, all of which are only related to the process; when the source-drain voltage Vgs is fixed, the larger the width-to-length ratio W / L, the smaller the on-resistance Ron, and vice versa.

[0028] Since the power supply voltage VDD generates a voltage VDDR through a relatively large resistor R1 and a capacitor C1, the voltage VDDR and the power supply voltage VDD are connected in different ways so that the two first inverters 10 and the second inverter 11 can detect the power supply voltage rise and the power supply voltage drop, and the first inverter 10 outputs a high voltage detection signal, and the second inverter 11 outputs a low voltage detection signal; MOS tubes P1 and P2 are PMOS tubes with a larger W / L (width-to-length ratio), and MOS tubes N1 and N2 are NMOS tubes with a smaller W / L. When W / L is larger, the MOS tube has a stronger conduction capability and a smaller impedance; when W / L is smaller, the MOS tube has a weaker conduction capability and a larger impedance. Therefore, the conduction capability of MOS tubes P1 and P2 is stronger than that of MOS tubes N1 and N2. When the power supply voltage VDD is stable or changes slowly, the first inverter 10 and the second inverter 11 output low-level signals, that is, the high-voltage detection signal and the low-voltage detection signal are both low-level; When the power supply voltage VDD rises rapidly, the voltage VDDR will have a delay due to the output through the RC resistor and capacitor, and the voltage VDDR rises slowly relative to the power supply voltage VDD. At this time, when the power supply voltage VDD is greater than the voltage VDDR, the turn-on voltage Vt of the MOS tube P1, the MOS tube P1 is turned on, and the impedance of the MOS tube P1 is much smaller than that of the MOS tube N1. At this time, the high-voltage detection signal will generate a pulse signal; When the power supply voltage VDD drops rapidly, the voltage VDDR will have a delay in output due to the RC resistor and capacitor, and the voltage VDDR drops slowly relative to the power supply voltage VDD. At this time, when the voltage VDDR is greater than the power supply voltage VDD by the turn-on voltage Vt of the MOS tube P2, the MOS tube P2 is turned on, and the impedance of the MOS tube P2 is much smaller than that of the MOS tube N2. At this time, the low voltage detection signal will generate a pulse signal.

[0029] In some implementations, other circuits that output a pulse signal according to the difference between the power supply voltage VDD and the voltage VDDR when the power supply voltage VDD changes to indicate that the power supply voltage VDD changes too fast can also be understood as the first inverter 10 or the second inverter 11 in the present invention.

[0030] For components such as TFF triggers, the specific process is as follows: During normal operation: When the reset signal RST_N is low, the circuit is in the reset state, the latch control signal CLK_LAT is low, the latch LAT is in the closed state, and the output clock CLKOUT does not change with the clock signal CLKIN; When the reset signal RST_N is released to high, the TFF trigger makes the latch control signal CLK_LAT high after the clock signal CLKIN inputs 8 clocks, the latch LAT is opened, the output clock CLKOUT follows the clock signal CLKIN, the clock is output normally, and at the same time, the latch control signal CLK_LAT shields the clock input of the first-stage TFF trigger through the OR gate OR1, so that the TFF trigger no longer counts, and the latch control signal CLK_LAT remains high at this time; at this time, the power supply voltage VDD has no interference with the timing diagram as shown in the figure. Figure 3 shown.

[0031] When the power supply voltage VDD has high frequency interference: If the power supply voltage VDD drops or rises rapidly, the high voltage detection signal or low voltage detection signal output by the voltage detection unit 1 will generate a short pulse. The pulse signal is output through the NOR gate NOR1 and performs an AND operation with the AND gate AND1 connected to the reset signal RST_N, so that the AND gate AND1 outputs a short low level. The short low level resets the TFF trigger, and the latch control signal CLK_LAT is reset to a low level. At this time, the latch LAT will be closed, and the output clock CLKOUT will stop outputting. The output clock CLKOUT will maintain the current level; At the same time, the clock control of the first stage of the TFF trigger is released (CLK_LAT=0); when the power supply voltage VDD returns to stability, the reset signal of the TFF trigger will be released, and the TFF trigger will make the latch control signal CLK_LAT high after the clock signal CLKIN inputs 8 clocks, the latch LAT opens, and the output clock CLKOUT changes with the clock signal CLKIN, and the clock is output normally; at the same time, the latch control signal CLK_LAT shields the clock input of the first stage TFF trigger through the OR gate OR1 so that the TFF trigger no longer counts, and the latch control signal CLK_LAT remains high at this time; the timing diagram of the power supply voltage VDD rise interference is as follows Figure 4 As shown in the figure, the timing diagram of power supply voltage VDD drop interference is as follows Figure 5 shown.

[0032] Embodiment 2 This embodiment provides a power supply control circuit, including the above-mentioned clock control circuit with high anti-interference performance, such as Figure 6 As shown, it also includes a transmission gate TG1, a resistor R2 and a capacitor C2, one end of the resistor R2 and the input end of the transmission gate TG1 are respectively used to input a power supply voltage VDD, the other end of the resistor R2 is respectively electrically connected to the output end of the transmission gate TG1 and one end of the capacitor C2, and the other end of the capacitor C2 is grounded; One control terminal of the transmission gate TG1 inputs the latch control signal CLK_LAT, and the other control terminal inputs the transmission control signal CLK_LAT_N. The latch control signal CLK_LAT and the transmission control signal CLK_LAT_N are two opposite signals; wherein the latch control signal CLK_LAT outputs the transmission control signal CLK_LAT_N through an inverter; The transmission gate TG1 is turned on when the latch control signal CLK_LAT is at a high level, and is turned off when the latch control signal CLK_LAT is at a low level.

[0033] Specifically, in Figure 6In the embodiment, the transmission gate TG1 includes a MOS transistor P3 and a MOS transistor N3. The source of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N3, which is the input end of the transmission gate TG1. The drain of the MOS transistor P3 is electrically connected to the source of the MOS transistor N3, which is the output end of the transmission gate TG1. The gate of the MOS transistor N3 is used to input the latch control signal CLK_LAT, and the gate of the MOS transistor P3 is used to input the transmission control signal CLK_LAT_N.

[0034] In this embodiment, the MOS transistor P3 may be a PMOS transistor with a width of 200 um and a length of 0.6 um, the MOS transistor N3 may be an NMOS transistor with a width of 100 um and a length of 0.6 um, the resistance value of the resistor R2 may be 1000Ω, and the capacitance value of the capacitor C2 may be 100 pf.

[0035] right Figure 6 The circuit is analyzed as follows: During normal operation: The latch control signal CLK_LAT is at a high level, the transmission control signal CLK_LAT_N is at a low level, the transmission gate TG1 is in the on state, and the W / L ratio is very large, and the on-resistance is very small, so the voltage DVDD is similar to the power supply voltage VDD through a very small resistor. When working, the voltage DVDD is approximately equal to the power supply voltage VDD. When the power supply voltage VDD has high frequency interference: The latch control signal CLK_LAT is low, the transmission control signal CLK_LAT_N is high, and the transmission gate TG1 is in the closed state; The power supply voltage VDD will generate a voltage DVDD through the resistor R2. The RC filter formed by the resistor R2 and the capacitor C2 will filter out the high-frequency interference on the power supply voltage VDD and obtain the voltage DVDD.

[0036] Embodiment 3 like Figure 7 As shown, this embodiment provides an integrated circuit, including the power control circuit in the second embodiment, and also includes a digital circuit 3, the output end of the transmission gate TG1 is electrically connected to the digital circuit 3 to provide a working voltage for the digital circuit 3, and the Q output end of the latch LAT is electrically connected to the digital circuit 3 to provide an output clock CLKOUT for the digital circuit.

[0037] In actual use, when the power supply voltage VDD is normal, the transmission gate TG1 is turned on, the voltage DVDD is input to the digital circuit 3 for power supply, the output clock CLKOUT is input to the digital circuit 3, and the digital circuit 3 works normally.

[0038] When the power supply voltage VDD is abnormal, the output clock CLKOUT stops outputting, the digital circuit 3 stops working, and the power consumption is close to 0. Therefore, there will be no voltage drop between the voltage DVDD and the power supply voltage VDD, and the voltage DVDD of the digital circuit 4 can be kept clean and stable. The timing circuit in the digital circuit 4 has improved anti-interference and maintains the current state; when the interference of the power supply voltage VDD disappears, the transmission gate TG1 will be turned on again, the voltage DVDD obtains a stronger driving ability to continue to power the digital circuit 3, and the output clock CLKOUT starts the digital circuit 3, and the digital circuit 3 continues to work from the previous state.

[0039] In addition, it should be noted that the digital circuit 3 is an existing digital circuit and does not involve the invention of the present application.

[0040] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A clock control circuit with high noise immunity, characterized in that: include: A voltage detection unit, generating a high voltage detection signal and a low voltage detection signal based on a change in a power supply voltage; A NOR gate, used for performing NOR processing on the high voltage detection signal and the low voltage detection signal; An AND gate, one input end of which is electrically connected to the output end of the NOR gate, and the other input end of which is used to input a reset signal; A plurality of TFF triggers connected in series, wherein the series connection is that the QN output end of the preceding TFF trigger is electrically connected to the clock end of the succeeding TFF trigger; the output end of the AND gate is electrically connected to the reset end of each TFF trigger; The Q output terminal of the terminal TFF trigger is electrically connected to the clock terminal of the latch LAT and an input terminal of the OR gate respectively, and is used to output a latch control signal CLK_LAT; The other input terminal of the OR gate and the D input terminal of the latch LAT are used to input the clock signal CLKIN; The voltage detection unit includes a resistor R1, a capacitor C1, a first inverter and a second inverter; One end of the resistor R1, the power supply end of the first inverter and the input end of the second inverter are respectively used to input the power supply voltage, and the other end of the resistor R1 is respectively electrically connected to the input end of the first inverter and the power supply end of the second inverter, and is grounded through the capacitor C1; The output end of the first inverter is used to output the high voltage detection signal, and the output end of the second inverter is used to output the low voltage detection signal.

2. The clock control circuit with high noise immunity according to claim 1, characterized in that: The number of TFF flip-flops connected in series is four.

3. The clock control circuit with high noise immunity according to claim 1, characterized in that: The first inverter comprises a MOS transistor P1 and a MOS transistor N1, the source of the MOS transistor P1 is the power supply terminal of the first inverter, the drain of the MOS transistor P1 is electrically connected to the drain of the MOS transistor N1 and is the output terminal of the first inverter, the gate of the MOS transistor P1 is electrically connected to the gate of the MOS transistor N1 and is the input terminal of the first inverter, and the source of the MOS transistor N1 is grounded; The second inverter includes a MOS transistor P2 and a MOS transistor N2. The source of the MOS transistor P2 is the power supply terminal of the second inverter. The drain of the MOS transistor P2 is electrically connected to the drain of the MOS transistor N2 and is the output terminal of the second inverter. The gate of the MOS transistor P2 is electrically connected to the gate of the MOS transistor N2 and is the input terminal of the second inverter. The source of the MOS transistor N2 is grounded.

4. The clock control circuit with high noise immunity according to claim 3, characterized in that: The size of the MOS transistor P1 is the same as that of the MOS transistor P2, and the size of the MOS transistor N1 is the same as that of the MOS transistor N2.

5. The clock control circuit with high noise immunity according to claim 4, characterized in that: The width-to-length ratio of the MOS transistor P1 is greater than the width-to-length ratio of the MOS transistor N1.

6. The clock control circuit with high noise immunity according to claim 5, characterized in that: The sizes of the resistor R1 , the capacitor C1 , the MOS transistor P1 , the MOS transistor N1 , the MOS transistor P2 , and the MOS transistor N2 are adjustable to match different detection sensitivities.

7. A power supply control circuit, characterized in that it comprises the high-interference-immunity clock control circuit according to any one of claims 1 to 6, and further comprises a transmission gate, a resistor R2 and a capacitor C2, wherein one end of the resistor R2 and the input end of the transmission gate are respectively used to input the power supply voltage, the other end of the resistor R2 is respectively electrically connected to the output end of the transmission gate and one end of the capacitor C2, and the other end of the capacitor C2 is grounded; One control terminal of the transmission gate inputs the latch control signal CLK_LAT, and the other control terminal inputs the transmission control signal CLK_LAT_N, wherein the latch control signal CLK_LAT and the transmission control signal CLK_LAT_N are two opposite signals; The transmission gate is turned on when the latch control signal CLK_LAT is at a high level, and is turned off when the latch control signal CLK_LAT is at a low level.

8. A power control circuit according to claim 7, characterized in that: The transmission gate includes a MOS transistor P3 and a MOS transistor N3. The source of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N3, which is the input end of the transmission gate. The drain of the MOS transistor P3 is electrically connected to the source of the MOS transistor N3, which is the output end of the transmission gate. The gate of the MOS transistor N3 is used to input the latch control signal CLK_LAT, and the gate of the MOS transistor P3 is used to input the transmission control signal CLK_LAT_N.

9. An integrated circuit, characterized in that: The power control circuit comprises the power control circuit as claimed in claim 7 or 8, and further comprises a digital circuit, wherein the output end of the transmission gate is electrically connected to the digital circuit to provide an operating voltage for the digital circuit, and the Q output end of the latch LAT is electrically connected to the digital circuit to provide an output clock CLKOUT for the digital circuit.

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