An intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation

Abstract

The present invention discloses an intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation, comprising: a high-speed ADC, a data buffer module, an envelope elimination module, a phase lag module, an envelope extraction module and an SPWM modulation module. The input end of the high-speed ADC is connected to the signal source of the front-stage communication system, the output end of the high-speed ADC is connected to the input end of the data buffer module, the output end of the data buffer module is respectively connected to the input end of the envelope elimination module and the input end of the envelope extraction module, the output end of the envelope elimination module is connected to the input end of the phase lag module, the output end of the phase lag module serves as the PWM driving signal for the subsequent-stage circuit, the output end of the envelope extraction module is connected to the input end of the SPWM modulation module, and the output end of the SPWM modulation module serves as the SPWM driving signal for the subsequent-stage circuit. The present invention is applicable to high-power intermediate frequency transmitter systems, enabling the power amplifier unit to use a fully digital topology, greatly improving the efficiency of the system and reducing the volume.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and particularly to an intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation. Background Art

[0002] The intermediate frequency digital transmission system mainly provides various message broadcasts such as navigation safety, pirates, search and rescue, weather information, navigation, port information, ship traffic system file transmission, and electronic chart update packages for maritime ships. In order to improve the information transmission efficiency, QAM modulation under OFDM is introduced in the communication system. However, conventional intermediate frequency digital power amplifiers cannot transmit signals with amplitude and phase changes. Therefore, the existing mainstream method is to use linear power amplifiers for power cascading. This method not only has low power and low efficiency, but also requires a large-volume radiator, making the equipment very bulky. Another method is to use the envelope elimination and restoration technology (EER) as shown in Figure 1 Two digital power amplifiers are used. The half-bridge digital power amplifier is used to amplify the envelope signal of the original signal, and the full-bridge digital power amplifier is used to amplify the carrier signal of the original signal. Finally, the two signals are synthesized in the form of multiplication to restore the original signal.

[0003] However, since the system separates the input signal into two signals, the phase shifts on the two signals will be mismatched, resulting in phase distortion. In addition, the phase shift of the low-frequency envelope path is much larger than that of the high-frequency carrier path, exceeding several or even dozens of cycles. Therefore, the phase matching of the two signals is a huge challenge. Currently, in the field of intermediate frequency transmitters, there are very few digital modulators of the same type for EER systems. Therefore, it is an urgent problem to provide a digital modulator for EER systems with high phase lag accuracy, low complexity, and good adjustability. Summary of the Invention

[0004] In order to solve the problems of phase distortion and large equipment volume existing in the existing intermediate frequency digital power amplifier, the present invention proposes an intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation to solve the above problems.

[0005] An intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation includes:

[0006] A high-speed ADC: used to convert an analog signal into a parallel digital signal;

[0007] A data buffer module: used to buffer the parallel digital signal collected by the high-speed ADC and perform sampling rate conversion;

[0008] An envelope elimination module: used to eliminate the envelope change of the analog signal of the pre-stage communication system collected by the high-speed ADC to obtain a square wave signal with a constant envelope, and the square wave signal only carries frequency and phase information;

[0009] Phase lag module: used to control and adjust the phase lag of a square wave signal with only frequency and phase information, and output a PWM drive signal for driving the subsequent stage circuit;

[0010] Envelope extraction module: used to extract the envelope signal of the analog signal of the pre-stage communication system collected by the high-speed ADC;

[0011] SPWM modulation module: used to perform SPWM modulation on the envelope signal extracted by the envelope extraction module, and output two SPWM drive signals with dead-time complementarity;

[0012] The PWM drive signal for driving the subsequent stage circuit output by the phase lag module is in phase with the envelope signal output by the subsequent stage circuit driven by the SPWM modulation module;

[0013] The data buffer module, envelope elimination module, phase lag module, envelope extraction module and SPWM modulation module are arranged inside an FPGA. The input end of the high-speed ADC is connected to the signal source of the pre-stage communication system, the output end of the high-speed ADC is connected to the input end of the data buffer module, the output end of the data buffer module is respectively connected to the input ends of the envelope elimination module and the envelope extraction module, the output end of the envelope elimination module is connected to the input end of the phase lag module, the output end of the phase lag module serves as the PWM drive signal for the subsequent stage circuit, the output end of the envelope extraction module is connected to the input end of the SPWM modulation module, and the output end of the SPWM modulation module serves as the SPWM drive signal for the subsequent stage circuit.

[0014] Preferably, the envelope elimination module includes a first input buffer register, a first symbol decision module, a first data selector, a first register and a second register. The input end of the first input buffer register is connected to the output end of the data buffer module. The output end of the highest bit reg11 of the first input buffer register is connected to the input end of the first symbol decision module. The output end of the first symbol decision module is connected to the control end of the first data selector. The input ends of the first data selector are respectively connected to the output end of the first register storing the logic signal 0 and the output end of the second register storing the logic signal 1. The output end of the first data selector serves as the PWM modulation signal output for envelope elimination.

[0015] Preferably, the phase lag module includes a phase lag controller, an inverter, a read address adder, a write address controller, a write address accumulator, a phase lag buffer array, an input data buffer module, and an output data buffer module. The output end of the phase lag controller is connected to the input end of the inverter, the output end of the inverter is connected to the input end of the read address adder, the output end of the read address adder is connected to the read address control input end of the phase lag buffer array, the output end of the write address controller is connected to the input end of the write address accumulator, the output end of the write address accumulator is respectively connected to the input end of the write address accumulator, the input end of the read address adder, and the phase lag buffer array. The input end of the input data buffer module is connected to the PWM modulation signal output by the first data selector, the output end of the input data buffer module is connected to the read data output end of the phase lag buffer array, and the output end of the output data buffer module is used as the PWM modulation signal with phase lag to output.

[0016] Preferably, the phase lag module uses the buffer array phase lag method to buffer the PWM modulation signal, achieving the phase lag accuracy of the level of, where f is the system clock, and realizing fine phase lag adjustment above one percent of the PWM modulation signal period.

[0017] Preferably, the buffer array phase lag method includes the following steps:

[0018] Use a RAM with a depth of n bits and a width of 1 inside the FPGA as the phase lag buffer array. The write address controller distributes the clock to make the write address accumulator accumulate at the frequency of the system clock f, with each accumulation being 1 bit. The output w_addr of the write address accumulator is used to control the write data address of the phase lag buffer array. The PWM modulation signal generated by the network elimination module passes through the input data buffer module, and the output of the data buffer module is stored in the phase lag buffer array at the address corresponding to the output of the write address accumulator. The data interval time between adjacent addresses is Set the lag time as t. The phase lag controller converts the lag time t into the address difference k according to the system clock f. The difference k is inverted by the inverter to output -k. The output -k of the inverter and the output w_addr of the write address accumulator are added by the read address adder to obtain the output r_addr of the read address adder, where r_addr = w_addr - k. The output data buffer module reads the data from the corresponding address in the phase lag buffer array according to the output r_addr of the read address adder and outputs it as the PWM signal with phase lag.

[0019] Preferably, the envelope extraction module includes a second input buffer register, a second symbol decision module, a symbol inversion module, a second data selector, and a FIR low-pass filter. The input end of the second input buffer register is connected to the output end of the output data buffer module. The output end of the highest bit reg11 of the second input buffer register is connected to the input end of the second symbol decision module. The lowest bit to the second highest bit reg0-reg10 of the input buffer register are connected to the input end of the second data selector and the input end of the symbol inversion module. The output end of the second symbol decision module is connected to the control end of the second data selector. The output end of the second data selector is connected to the input end of the FIR low-pass filter. The output end of the FIR low-pass filter outputs an envelope signal.

[0020] Preferably, the SPWM modulation module includes a triangular wave generation unit, a first comparator, a second comparator, a first dead zone generation unit, and a second dead zone generation unit. The output end of the triangular wave generation unit is respectively connected to the negative input end of the first comparator and the positive input end of the second comparator. The positive input end of the first comparator and the negative input end of the second comparator are both connected to the output end of the FIR low-pass filter. The output end of the first comparator is connected to the input end of the first dead zone generation unit. The output end of the second comparator is connected to the input end of the second dead zone generation unit. The output end of the first dead zone generation unit outputs an N_SPWM signal. The output end of the second dead zone generation unit outputs a P_SPWM signal. The N_SPWM signal and the P_SPWM signal are two signals with complementary dead zones.

[0021] Advantages of the present invention:

[0022] (1) The present invention adopts the buffer array phase lag method to achieve high-precision and long-time phase lag and matching, greatly improving the accuracy of the intermediate frequency digital transmitter.

[0023] (2) The present invention uses an FPGA chip to implement a fully digital digital modulator, greatly reducing the circuit complexity and the volume of the modulator.

[0024] (3) In the intermediate frequency transmitter, the present invention proposes and designs an intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation, which can be used as a modulator for a fully digital power amplifier topology, enabling the intermediate frequency transmitter with amplitude and phase modulation to use the fully digital power amplifier topology, greatly improving the efficiency and power of the intermediate frequency transmitter and reducing the volume of the intermediate frequency transmitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of a typical structure of envelope elimination and restoration technology (EER);

[0026] Figure 2 It is a schematic diagram of the structure of the intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation according to the embodiment of the present invention;

[0027] Figure 3 Schematic diagram of the envelope elimination module according to an embodiment of the present invention;

[0028] Figure 4 Schematic diagram of the phase lag module according to an embodiment of the present invention;

[0029] Figure 5 Schematic diagram of the envelope extraction module according to an embodiment of the present invention;

[0030] Figure 6 Schematic diagram of the SPWM modulation module according to an embodiment of the present invention;

[0031] Figure 7 Waveform diagram of the input signal according to an embodiment of the present invention;

[0032] Figure 8 Waveform diagram of the SPWM output according to an embodiment of the present invention;

[0033] Figure 9 Waveform diagram of the PWM output according to an embodiment of the present invention. Detailed implementation manners

[0034] To make the objectives, technical solutions and advantages of the present application more clear and understandable, the following takes examples with reference to the accompanying drawings and further elaborates on the present application in detail.

[0035] An embodiment of the present application discloses an intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation, as Figure 2 shown, including: a high-speed ADC, a data buffer module, an envelope elimination module, a phase lag module, an envelope extraction module and an SPWM modulation module. Among them, the data buffer module, the envelope elimination module, the phase lag module, the envelope extraction module and the SPWM modulation module are arranged inside an FPGA. In this embodiment, the FPGA uses the AX035B development board with an FPGA chip of XC7A35T on board. The input end of the high-speed ADC accesses the signal source of the front-end communication system, the output end of the high-speed ADC is connected to the input end of the data buffer module, the output end of the data buffer module is respectively connected to the input ends of the envelope elimination module and the envelope extraction module, the output end of the envelope elimination module is connected to the input end of the phase lag module, the output end of the phase lag module serves as the PWM drive signal for the subsequent circuit, the output end of the envelope extraction module is connected to the input end of the SPWM modulation module, and the output end of the SPWM modulation module serves as the SPWM drive signal for the subsequent circuit.

[0036] In this embodiment, the input original signal is a modulation signal with simultaneous changes in amplitude and phase, having a center frequency of 500 kHz and a bandwidth of 10 kHz. The original signal is collected into the FPGA through a high-speed ADC, and the original signal is divided into two paths for processing, separately processing the phase information and amplitude information of the original signal, separating the phase information and amplitude information and generating drive signals for driving the half-bridge and full-bridge power amplifiers as shown in Figure 1 . Since the high-frequency carrier signal in the original signal carries the phase information, while the low-frequency envelope signal carries the amplitude information, and the periods of the two differ greatly, when restoring the two paths of signals subsequently, the phase lag brought by the low-frequency path will be much higher than that of the high-frequency path, possibly a difference of 10 times the period or even more.

[0037] The high-speed ADC is used to convert the analog signal into a parallel digital signal that can be processed by the FPGA. The high-speed ADC in this embodiment is the AD9226 module. The output interface of this module is a 12-bit parallel interface, which can be directly connected to the FPGA for receiving data. The highest sampling rate of the module is 65 Msps, the allowable range of the input signal is ±5V, and the input characteristic impedance is 50Ω.

[0038] Data buffer module: used to buffer the parallel digital signal collected by the high-speed ADC and has the function of sampling rate conversion. Since the highest sampling rate of the front-stage high-speed ADC module is 65 Msps and the sampling clock is selected as 50 MHz, but the FPGA sets the system operating frequency to 100 MHz to ensure the accuracy of the subsequent phase lag and other modules. Therefore, a buffer module needs to be set to perform oversampling on the data. The input of the data buffer module is the 12-bit parallel data of the front-stage high-speed ADC. At this time, it is stored in the register of the data buffer module at a frequency of 50 MHz. The output of the buffer module samples the register using a 100 MHz clock and sends the data to the subsequent module.

[0039] The signal passing through the data buffer module is divided into two paths. The first path will first use the envelope elimination module to eliminate the envelope signal of the original signal, only retaining the carrier phase and frequency information, and the amplitude will be normalized. The first path signal is a high-frequency carrier signal, which will have a lower delay compared to the second path signal. Therefore, a phase lag is added to the first path signal. The buffered array phase lag method is used in the phase lag module to make the phase of the first path signal consistent with that of the second path signal when the final signal is synthesized. The second path signal first uses the envelope extraction module to eliminate the frequency and phase signals of the original signal, only retaining the amplitude information, and extracts the envelope line. Then, the SPWM modulation module is used to convert the envelope information into an SPWM modulation signal for driving the subsequent module.

[0040] The envelope elimination module is used to eliminate the envelope variation of the analog signal of the pre-stage communication system collected by the high-speed ADC, and obtain a square wave signal with normalized amplitude. The square wave signal only carries frequency and phase information. As Figure 3 shown, the envelope elimination module includes a 12-bit first input buffer register, a first symbol decision module, a two-bit 1-bit first data selector, a first register, and a second register. The input end of the first input buffer register is connected to the output end of the data buffer module. The output end of the highest bit reg11 of the first input buffer register is connected to the input end of the first symbol decision module. The output end of the first symbol decision module is connected to the control end of the first data selector. The input ends of the first data selector are respectively connected to the output end of the first register storing the logic signal 0 and the output end of the second register storing the logic signal 1. The output end of the first data selector serves as the PWM modulation signal output of the envelope elimination.

[0041] The input signal of the envelope elimination module is a parallel digital signal converted by the high-speed ADC and is in the form of a complement code. The highest bit of this input signal is the sign bit. When the highest bit is 0, it indicates a positive number, and when the highest bit is 1, it indicates a negative number. The first input buffer register caches the input signal. The first symbol decision device judges the current logic level of the highest bit of the input signal in the first input buffer register. When the highest bit is 0, it indicates that the input signal is positive, and it controls the first data selector to output 1. When the highest bit is 1, it indicates that the input signal is negative, and it controls the first data selector to output 0. In this way, the amplitude of the input signal is normalized and converted into a square wave signal that only contains frequency and phase information. This square wave signal serves as the PWM drive signal after passing through the subsequent phase lag module.

[0042] The following conducts a principle analysis of the envelope elimination module. The original signal s(t) is a signal with amplitude and phase variations:

[0043] s(t) = A k sin(ωt + θ k );

[0044] where ω is the angular frequency, t is the time, k = 1, 2, 3…, A k and θ k respectively represent the discrete amplitude and phase under different encodings. It can be seen that the amplitude A k and the phase θ k in the original signal s(t) carry information.

[0045] After the original signal s(t) passes through the envelope elimination module, a square wave signal x(t) will be obtained:

[0046]

[0047] where n = 0, 1, 2, 3…, T is the signal period, and A is the amplitude of the square wave signal. Expanding x(t) using the Fourier series gives:

[0048]

[0049] It can be seen that the frequency and phase of the original signal are retained, while the amplitude information is eliminated.

[0050] The phase lag module is used to control and adjust the phase lag of the square wave signal that only carries frequency and phase information, and outputs a PWM drive signal for driving the subsequent circuit. As Figure 4 shown, the phase lag module includes a phase lag controller, an inverter, a read address adder, a write address controller, a write address accumulator, a phase lag buffer array, an input data buffer module, and an output data buffer module. The phase lag buffer array includes a read address control input terminal and a read data output terminal. The output terminal of the phase lag controller is connected to the input terminal of the inverter, the output terminal of the inverter is connected to the input terminal of the read address adder, the output terminal of the read address adder is connected to the read address control input terminal of the phase lag buffer array, the output terminal of the write address controller is connected to the input terminal of the write address accumulator, the output terminal of the write address accumulator is respectively connected to the input terminal of the write address accumulator, the input terminal of the read address adder, and the phase lag buffer array. The input terminal of the input data buffer module is connected to the PWM modulation signal output by the first data selector, the output terminal of the input data buffer module is connected to the read data output terminal of the phase lag buffer array, and the output terminal of the output data buffer module is used as the PWM modulation signal with phase lag to output. Figure 4 In it, w_addr is the write address input of the phase lag buffer array, w_data is the write data input of the phase lag buffer array, r_addr is the read address input of the phase lag buffer array, r_data is the read data output of the phase lag buffer array, n is the storage data address of the phase lag buffer array, and dn is the data stored corresponding to the address n of the phase lag buffer array.

[0051] The phase lag module uses the buffer array phase lag method to buffer the PWM modulation signal, achieving Phase lag accuracy at the level where f is the system clock, enabling fine phase lag adjustment over more than one percent of the PWM modulation signal period. The steps of the buffer array phase lag method are as follows: Use a RAM with a depth of n bits and a width of 1 inside the FPGA as the phase lag buffer array. The write address controller, through the allocated clock, causes the write address accumulator to accumulate at the frequency of the system clock f, with each accumulation being 1 bit. The output w_addr of the write address accumulator is used to control the write data address of the phase lag buffer array. The PWM modulation signal generated by the envelope elimination module passes through the input data buffer module, and the output of the data buffer module is stored in the phase lag buffer array at the address corresponding to the output of the write address accumulator. The data interval time between adjacent addresses is Set the lag time as t. The phase lag controller converts the lag time t into the address difference k according to the system clock f. After being inverted by an inverter, the difference k outputs -k. The output -k of the inverter and the output w_addr of the write address accumulator are added by the read address adder to obtain the output r_addr of the read address adder, where r_addr = w_addr - k. The output data buffer module reads the data from the corresponding address in the phase lag buffer array according to the output r_addr of the read address adder and outputs it as the PWM signal with phase lag.

[0052] Since the system clock is f, that is, the system operating frequency is f, then there is a phase lag time t 0 is

[0053]

[0054] Then for the PWM modulation signal x(t) of the envelope elimination module, the PWM modulation signal y(t) with phase lag will be obtained:

[0055]

[0056] By comparing the PWM modulation signal x(t) and the PWM modulation signal y(t) with phase lag, it can be found that the main frequency phase of y(t) lags behind that of x(t)

[0057] Envelope extraction module: Used to extract the envelope signal of the pre-stage communication system analog signal collected by the high-speed ADC. Such as Figure 5As shown in the figure, the envelope extraction module includes a second input buffer register, a second symbol decision module, a symbol inversion module, a second data selector, and a FIR low-pass filter. The input end of the second input buffer register is connected to the output end of the output data buffer module. The output end of the highest bit reg11 of the second input buffer register is connected to the input end of the second symbol decision module. The lowest bit to the second highest bit reg0-reg10 of the input buffer register are connected to the input end of the second data selector and the input end of the symbol inversion module. The output end of the second symbol decision module is connected to the control end of the second data selector. The output end of the second data selector is connected to the input end of the FIR low-pass filter. The output end of the FIR low-pass filter outputs the envelope signal.

[0058] The input signal of the envelope extraction module is a parallel digital signal converted by a high-speed ADC, in the form of two's complement. The highest bit of this input signal is the sign bit. A highest bit of 0 indicates positive, and a highest bit of 1 indicates negative. The second input buffer register caches the input signal. The second symbol decision device judges the current logic level of the highest bit of the input signal in the second input buffer register. When the highest bit is 0, it indicates that the input signal is positive, and it controls the second data selector to directly output the data in the second input buffer register. When the highest bit is 1, it indicates that the input signal is negative, and it controls the second data selector to output the data after being inverted by the symbol inverter. In this way, full-wave rectification operation is performed on the input signal. The signal after full-wave rectification will exhibit the spectral components of the envelope in the spectrum. At this time, the high-frequency carrier frequency components are filtered out by the FIR low-pass filter, and the envelope signal of the original signal will be obtained.

[0059] In this embodiment, the FIR low-pass digital filter uses the window function method and selects the Hamming window. Its function is:

[0060]

[0061] where n is the discrete sequence point, N is the window function length, and R N (n) is a rectangular sequence.

[0062] The frequency range of the envelope signal contained in the signal after full-wave rectification is 0-10 kHz, and the carrier frequency is 500 kHz. Therefore, the order of the FIR low-pass digital filter is 150, the sampling rate is 10 MHz, and the passband cut-off frequency is 15 kHz. The attenuation of the low-pass filter at 10 kHz in the passband is -0.16 dB, and the attenuation at the carrier frequency of 500 kHz is -45.7 dB.

[0063] The following is the principle analysis. The original signal s(t) is a signal with amplitude and phase changes. Its function is:

[0064] s(t) = A k sin(ω c t + θk )

[0065] Replace the discrete variable A among them k Use the function A 0 + m(t) to obtain:

[0066] s(t) = [A 0 + m(t)]sin(ω c t + θ k )

[0067] Its spectrum is:

[0068]

[0069] Among them, A 0 + m(t) is the envelope signal, M(ω) is the frequency-domain expression of the function m(t). Full-wave rectification of the signal s(t) will cause periodic extension of the spectrum of the envelope signal, and the extension interval is ω c , so the function S(ω) is obtained:

[0070]

[0071] In the function S(ω), k is an integer. It can be found that when k is -1, there is a component a(ω) in the positive half of the spectrum, which is the envelope signal:

[0072]

[0073] At this time, perform low-pass filtering on the signal, and only retain the component a(ω) to restore the envelope signal A 0 + m(t).

[0074] The SPWM modulation module is used to perform SPWM modulation on the envelope signal extracted by the envelope extraction module and output two SPWM drive signals with dead-time complementarity. As Figure 6 shown, the SPWM modulation module includes a triangular wave generation unit, a first comparator, a second comparator, a first dead-time generation unit, and a second dead-time generation unit. The output end of the triangular wave generation unit is respectively connected to the negative input end of the first comparator and the positive input end of the second comparator. The positive input end of the first comparator and the negative input end of the second comparator are both connected to the output end of the FIR low-pass filter. The output end of the first comparator is connected to the input end of the first dead-time generation unit, and the output end of the second comparator is connected to the input end of the second dead-time generation unit. The output end of the first dead-time generation unit outputs the N_SPWM signal, and the output end of the second dead-time generation unit outputs the P_SPWM signal. The N_SPWM signal and the P_SPWM signal are two signals with dead-time complementarity.

[0075] The triangular wave generating unit distributes frequencies through the main frequency of the FPGA, and generates a triangular wave with a frequency of 500 kHz by constructing an accumulator. The triangular wave and the envelope signal output by the envelope extraction module are compared by the first comparator and the second comparator. When the amplitude of the triangular wave is greater than the envelope signal, the first comparator outputs 0 and the second comparator outputs 1. When the amplitude of the triangular wave is less than the envelope signal, the first comparator outputs 1 and the second comparator outputs 0. Then, through the first and second dead zone generating units, a pair of SPWM signals with complementary dead zones are generated for driving the subsequent circuit.

[0076] In a specific embodiment, the input original signal is a modulated signal with simultaneous changes in amplitude and phase. Its carrier wave has a frequency of 500 kHz and its phase changes periodically. Its envelope line is a signal containing the superposition of two frequencies of 5 kHz and 10 kHz, as Figure 7 shown. The signal is input into the modulator disclosed in the embodiment of the present application, and two signals will be obtained respectively. One signal carries the envelope information of the original signal, and the other signal carries the phase and carrier frequency information of the original signal. Among them, the signal carrying the envelope information is modulated into an SPWM signal with a modulation frequency of 500 kHz, as Figure 8 shown. The signal carrying the phase and carrier frequency information is modulated into a PWM signal, and its fundamental frequency and phase remain unchanged compared with those before modulation, as Figure 9 shown.

[0077] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification only illustrates the principle of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. An intermediate frequency digital power amplifier modulator for amplitude and phase modulation, characterized in that: include: High-speed ADC: used to convert analog signals into parallel digital signals; Data buffer module: used to buffer the parallel digital signals collected by the high-speed ADC and perform sampling rate conversion; Envelope elimination module: used to eliminate the envelope change of the analog signal of the previous communication system collected by the high-speed ADC, and obtain a square wave signal with a constant envelope, and the square wave signal only carries frequency and phase information; Phase lag module: used to control and adjust the phase lag of the square wave signal with only frequency and phase information, and output a PWM drive signal for driving the subsequent circuit; Envelope extraction module: used to extract the envelope signal of the analog signal of the previous communication system collected by the high-speed ADC; SPWM modulation module: used to perform SPWM modulation on the envelope signal extracted by the envelope extraction module, and output two SPWM drive signals with dead zone complementation; The PWM driving signal output by the phase lag module for driving the subsequent circuit is consistent in phase with the envelope signal output by the subsequent circuit driven by the SPWM modulation module; The data buffer module, envelope elimination module, phase lag module, envelope extraction module and SPWM modulation module are arranged inside an FPGA, the high-speed ADC input end is connected to the front-stage communication system signal source, the high-speed ADC output end is connected to the data buffer module input end, the data buffer module output end is respectively connected to the envelope elimination module input end and the envelope extraction module input end, the envelope elimination module output end is connected to the phase lag module input end, the phase lag module output end is used as the PWM driving signal of the rear-stage circuit, the envelope extraction module output end is connected to the SPWM modulation module input end, and the SPWM modulation module output end is used as the SPWM driving signal of the rear-stage circuit.

2. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 1, characterized in that: The envelope elimination module includes a first input buffer register, a first symbol decision module, a first data selector, a first register and a second register. The input end of the first input buffer register is connected to the output end of the data buffer module, the highest bit reg11 output end of the first input buffer register is connected to the input end of the first symbol decision module, the output end of the first symbol decision module is connected to the control end of the first data selector, the input end of the first data selector is respectively connected to the output end of the first register storing a logic signal 0 and the output end of the second register storing a logic signal 1, and the output end of the first data selector is output as a PWM modulation signal for envelope elimination.

3. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 2, characterized in that: The phase lag module includes a phase lag controller, an inverter, a read address adder, a write address controller, a write address accumulator, a phase lag buffer array, an input data buffer module and an output data buffer module. The output end of the phase lag controller is connected to the input end of the inverter, the output end of the inverter is connected to the input end of the read address adder, the output end of the read address adder is connected to the read address control input end of the phase lag buffer array, the output end of the write address controller is connected to the input end of the write address accumulator, the output end of the write address accumulator is respectively connected to the input end of the write address accumulator, the input end of the read address adder and the phase lag buffer array, the input end of the input data buffer module is connected to the PWM modulation signal output by the first data selector, the output end of the input data buffer module is connected to the read data output end of the phase lag buffer array, and the output end of the output data buffer module is output as a PWM modulation signal with phase lag.

4. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 3, characterized in that: The phase lag module uses a buffer array phase lag method to buffer the PWM modulation signal. The phase lag accuracy of the first level is 1000, where f is the system clock, and the fine phase lag adjustment of more than one hundredth of the PWM modulation signal period can be achieved.

5. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 4, characterized in that: The buffer array phase lag method comprises the following steps: A RAM with a depth of n bits and a width of 1 inside the FPGA is used as a phase lag buffer array. The write address controller distributes the clock so that the write address accumulator accumulates at the frequency of the system clock f, and each accumulation is 1 bit. The output w_addr of the write address accumulator is used to control the write data address of the phase lag buffer array. The PWM modulation signal generated by the network elimination module is input through the data buffer module, and the output of the data buffer module is stored in the phase lag buffer array corresponding to the output address of the write address accumulator. The data interval time between adjacent addresses is The lag time is set to t, and the phase lag controller converts the lag time t into the address difference k according to the system clock f. The difference k is inverted by the inverter and output -k. The output -k of the inverter and the output w_addr of the write address accumulator are added through the read address adder to obtain the read address adder output r_addr, wherein r_addr=w_addr-k. The output data buffer module reads data from the corresponding address of the phase lag buffer array according to the read address adder output r_addr, and outputs it as a PWM signal with phase lag.

6. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 5, characterized in that: The envelope extraction module includes a second input buffer register, a second symbol decision module, a symbol flip module, a second data selector and an FIR low-pass filter. The input end of the second input buffer register is connected to the output end of the output data buffer module, the output end of the second input buffer register (the highest bit reg11) is connected to the input end of the second symbol decision module, the lowest bit to the second highest bit reg0-reg10 of the input buffer register are connected to the input end of the second data selector and the input end of the symbol flip module, the output end of the second symbol decision module is connected to the control end of the second data selector, the output end of the second data selector is connected to the input end of the FIR low-pass filter, and the output end of the FIR low-pass filter outputs an envelope signal.

7. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 6, characterized in that: The SPWM modulation module includes a triangular wave generating unit, a first comparator, a second comparator, a first dead zone generating unit and a second dead zone generating unit. The output end of the triangular wave generating unit is respectively connected to the negative input end of the first comparator and the positive input end of the second comparator. The positive input end of the first comparator and the negative input end of the second comparator are both connected to the output end of the FIR low-pass filter. The output end of the first comparator is connected to the input end of the first dead zone generating unit, and the output end of the second comparator is connected to the input end of the second dead zone generating unit. The output end of the first dead zone generating unit outputs an N_SPWM signal, and the output end of the second dead zone generating unit outputs a P_SPWM signal. The N_SPWM signal and the P_SPWM signal are two signals with complementary dead zones.

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