Common-mode transient interference suppression circuit, receiver and communication interaction system

Abstract

The invention provides a common-mode transient interference suppression circuit, a receiver and a communication interaction system, the common-mode transient interference suppression circuit is integrated in the receiver, and the common-mode transient interference suppression circuit comprises a control module and a signal processing module; the control module and the signal processing module both receive original input signals input by the transmitter; the control module is used for generating a target control instruction when detecting that a common-mode transient interference signal appears in the original input signal; and the signal processing module is used for outputting an original input signal according to the target control instruction so as to suppress the output of an error code signal. Through the arrangement of the control module and the signal processing module, when the control module detects that the common-mode transient interference signal appears in the original input signal, the target control instruction is generated to control the signal processing module to output the original input signal, so that the output of the error code signal is inhibited; the bit error rate of signal transmission between the transmitter and the receiver is effectively reduced, and the anti-interference capability of a signal path is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a common-mode transient interference suppression circuit, a receiver, and a communication interaction system. Background Art

[0002] Figure 1 The figure shows a schematic diagram of data transmission between TX (transmitter) and RX (receiver). The input signal is input from the IN (input) terminal of TX, coupled to the RX terminal through capacitor C, and then the RX terminal outputs the signal from the OUT (output) terminal. Usually TX and RX work in different power domains VCCI (TX power domain) and VCCO (RX power domain), and the input terminals of TX and RX work at fixed common-mode levels. When a large common-mode transient interference signal ±V appears between GNDI (TX ground terminal) and GNDO (RX ground terminal), the TX and RX terminals are connected to the GNDI terminal. CM When the common-mode transient interference signal is coupled from the TX end to the RX end through the capacitor C, the common-mode level of RX will fluctuate greatly, causing the circuit to deviate from the normal operating point, thus generating bit errors. Summary of the invention

[0003] The technical problem to be solved by the present disclosure is to overcome the defects such as bit errors caused by common-mode transient interference during data transmission between a transmitter and a receiver in the prior art, and to provide a common-mode transient interference suppression circuit, a receiver and a communication interaction system.

[0004] The present invention solves the above technical problems through the following technical solutions:

[0005] The present disclosure provides a common-mode transient interference suppression circuit, which is integrated in a receiver and includes a control module and a signal processing module;

[0006] The first output terminal of the control module is electrically connected to the first control terminal of the signal processing module;

[0007] The control module and the signal processing module both receive the original input signal input by the transmitter;

[0008] The control module is used to generate a target control instruction before a set time period if a common mode transient interference signal is detected in the original input signal during signal transmission, and output the target control instruction to the signal processing module;

[0009] The signal processing module is used to output the original input signal according to the target control instruction to suppress the output of the error signal;

[0010] Wherein, the bit error signal is formed by superposition of the original input signal and the common mode transient interference signal;

[0011] A first time required for the control module to output the target control instruction to the signal processing module is less than a second time required for the error signal to be transmitted to the signal processing module.

[0012] Preferably, the signal processing module includes a latch;

[0013] The first output terminal of the control module is electrically connected to the second control terminal of the latch;

[0014] The control module is further configured to generate a first control signal when the common mode transient interference signal is detected, and output the first control signal to the latch;

[0015] The latch is used to latch and output the original input signal according to the first control signal.

[0016] Preferably, the signal processing module further includes a multiplexer;

[0017] The first output terminal of the control module is electrically connected to the third control terminal of the multiplexer;

[0018] The second output terminal of the latch is electrically connected to the first input terminal of the multiplexer;

[0019] The control module is further configured to generate a second control signal when the common-mode transient interference signal is detected, and output the second control signal to the multiplexer;

[0020] The multiplexer is used for receiving and outputting the original input signal output by the latch according to the second control signal.

[0021] Preferably, the second input terminal of the latch is electrically connected to the third input terminal of the multiplexer;

[0022] When the control module does not detect the common-mode transient interference signal, the multiplexer is further configured to receive and output the original input signal.

[0023] Preferably, the common-mode transient interference suppression circuit further includes an amplifier;

[0024] The fourth input terminal of the amplifier is electrically connected to the fifth input terminal of the control module, and the third output terminal of the amplifier is electrically connected to the second input terminal of the latch and the third input terminal of the multiplexer respectively;

[0025] The amplifier is used to amplify the original input signal.

[0026] Preferably, the control module includes a voltage detection unit;

[0027] The voltage detection unit is used to output a target control instruction to control the signal processing module to output the original input signal to suppress the output of the error signal when it detects that the voltage value of the common-mode transient interference signal exceeds a preset voltage range.

[0028] Preferably, the receiver is connected to the transmitter;

[0029] The transmitter is used to receive the original input signal and output the original input signal to the control module and the signal processing module.

[0030] Preferably, a capacitor is provided between the receiver and the transmitter;

[0031] The capacitor is used to perform coupling processing on the original input signal, and output the original input signal after coupling processing to the control module and the signal processing module.

[0032] The present disclosure also provides a receiver, which includes the common-mode transient interference suppression circuit as described above.

[0033] The present disclosure also provides a communication interaction system, which includes a transmitter and a receiver as described above.

[0034] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0035] The positive and progressive effects of this disclosure are:

[0036] The present invention provides a control module and a signal processing module. When the control module detects the presence of a common-mode transient interference signal in the original input signal, it generates a target control instruction to control the signal processing module to output the original input signal, thereby suppressing the output of the error signal. Under the premise of not affecting the normal signal transmission, the error rate of the signal transmission between the transmitter and the receiver is effectively reduced, and the anti-interference ability of the signal path is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The figure is a schematic diagram of data transmission between a transmitter and a receiver in the prior art.

[0038] Figure 2 Schematic diagram of the structure of the common-mode transient interference suppression circuit of Example 1 of the present disclosure.

[0039] Figure 3 Schematic diagram of the structure of the common-mode transient interference suppression circuit of embodiment 2 of the present disclosure.

[0040] Figure 4 This is a schematic diagram of the structure of the receiver of embodiment 3 of the present disclosure.

[0041] Figure 5 This is a structural diagram of the communication interaction system of Example 4 of the present disclosure. DETAILED DESCRIPTION

[0042] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0043] Example 1

[0044] This embodiment provides a common-mode transient interference suppression circuit, which is integrated in a receiver (RX). Figure 2 As shown, the common mode transient interference suppression circuit includes a control module 1 and a signal processing module 2;

[0045] The first output terminal of the control module 1 is electrically connected to the first control terminal of the signal processing module 2;

[0046] The control module 1 and the signal processing module 2 both receive the original input signal input by the transmitter;

[0047] The control module 1 is used to generate a target control instruction before a set time if a common mode transient interference signal is detected in the original input signal during the signal transmission process, and output the target control instruction to the signal processing module 2;

[0048] The signal processing module is used to output the original input signal according to the target control instruction to suppress the output of the error signal;

[0049] The original input signal does not include the common-mode transient interference signal, and the bit error signal is formed by superposition of the original input signal and the common-mode transient interference signal;

[0050] The first time required for the control module 1 to output the target control instruction to the signal processing module 2 is less than the second time required for the error signal to be transmitted to the signal processing module 2 .

[0051] In this embodiment, by setting up a control module and a signal processing module, when the control module detects the presence of a common-mode transient interference signal in the original input signal, it generates a target control instruction to control the signal processing module to output the original input signal, thereby suppressing the output of the error signal, reducing the bit error rate of the signal transmission between the transmitter and the receiver, and improving the anti-interference capability of the signal path.

[0052] Example 2

[0053] This embodiment provides a common-mode transient interference suppression circuit, which is a further improvement on Embodiment 1.

[0054] In one feasible solution, Figure 3 As shown, the signal processing module 2 includes a latch 22;

[0055] The first output terminal 11 of the control module 1 is electrically connected to the second control terminal 211 of the latch 21;

[0056] The control module 1 is also used to generate a first control signal when a common mode transient interference signal is detected, and output the first control signal to the latch 21;

[0057] The latch 21 is used to latch and output the original input signal according to the first control signal.

[0058] Specifically, when a common-mode transient interference signal arrives and the control module detects the common-mode transient interference signal, the latch 21 is immediately controlled to latch the original input signal that does not include the common-mode transient interference signal, and the original input signal is kept output until the common-mode transient interference signal disappears and the circuit returns to normal. After the circuit returns to normal, the latch 21 directly outputs the received original input signal.

[0059] In this scheme, the original input signal excluding the common-mode transient interference signal is latched by a latch and the original input signal is output, which effectively suppresses the output of the error signal caused by the common-mode transient interference signal, reduces the bit error rate of the signal transmission between the transmitter and the receiver, and improves the anti-interference ability of the signal path.

[0060] In an practicable solution, the signal processing module 2 further includes a multiplexer (MUX) 22;

[0061] The first output terminal 11 of the control module 1 is electrically connected to the third control terminal 221 of the multiplexer 22;

[0062] The second output terminal 212 of the latch 21 is electrically connected to the first input terminal 222 of the multiplexer 22;

[0063] The control module 1 is also used to generate a second control signal when a common mode transient interference signal is detected, and output the second control signal to the multiplexer 22;

[0064] The multiplexer 22 is used for receiving and outputting the original input signal output by the latch 21 according to the second control signal.

[0065] Specifically, when a common-mode transient interference signal arrives and the control module detects the common-mode transient interference signal, it immediately controls the latch 21 to latch the original input signal that does not include the common-mode transient interference signal, and outputs the original input signal to the multiplexer 22; at the same time, the control module 1 controls the multiplexer 22 to output the original input signal received by the first input terminal 222. At this time, the bit error signal is blocked at the other input terminal of the multiplexer 22.

[0066] In this solution, a multiplexer is used to output the original input signal excluding the common-mode transient interference signal, thereby effectively suppressing the output of the error signal.

[0067] In one practicable solution, the second input terminal 213 of the latch 21 is electrically connected to the third input terminal 233 of the multiplexer 22;

[0068] When the control module 1 does not detect the common-mode transient interference signal, the multiplexer 22 is also used to receive and output the original input signal.

[0069] Specifically, when no common-mode transient interference signal is detected, ie, the circuit works normally, the original input signal is directly transmitted to the third input terminal 223 of the multiplexer 22 , and the multiplexer 22 outputs the original input signal received by the third input terminal 223 by default.

[0070] In this solution, when no common-mode transient interference signal is detected, the multiplexer 22 is used to output the original input signal received by the third input terminal 223 by default, thereby avoiding the delay caused by the output of the original input signal from the latch 21 and improving the transmission efficiency of the original input signal.

[0071] In an implementable solution, the common mode transient interference suppression circuit further includes an amplifier (AMP) 3;

[0072] The fourth input terminal 31 of the amplifier 3 is electrically connected to the fifth input terminal 12 of the control module 1, and the third output terminal 32 of the amplifier 3 is electrically connected to the second input terminal 213 of the latch 21 and the third input terminal 223 of the multiplexer 22 respectively;

[0073] Amplifier 3 is used to amplify the original input signal.

[0074] Specifically, when the circuit works normally, the original input signal is coupled from the transmitter to the receiver, amplified by the amplifier 3, and then the amplified original input signal is output and then output to the third input terminal 223 of the multiplexer 22, so that the multiplexer 223 directly inputs the original input signal.

[0075] In this solution, the original input signal is amplified by the amplifier, thereby increasing the strength of the original input signal and ensuring the quality of the original input signal.

[0076] In an implementable solution, the control module 1 includes a voltage detection unit 13;

[0077] The voltage detection unit 13 is used to output a target control instruction to control the signal processing module 2 to output the original input signal to suppress the output of the error signal when it is detected that the voltage value of the common mode transient interference signal exceeds the preset voltage range.

[0078] Specifically, when the voltage detection unit 13 detects that the voltage value of the common-mode transient interference signal exceeds the preset voltage range, that is, the common-mode transient interference signal can cause a bit error, the latch 21 is immediately controlled to latch the original input signal that does not include the common-mode transient interference signal, and output the original input signal to the multiplexer 22; at the same time, the control module 1 controls the multiplexer 22 to output the original input signal received by the first input terminal 222. At this time, the bit error signal output by the amplifier 3 is blocked at the third input terminal 223 of the multiplexer 22. The original input signal is maintained by the latch 21 until the common-mode transient interference signal disappears and the circuit returns to normal.

[0079] The voltage detection unit 13 needs to detect the voltage of the fourth input terminal 31 of the amplifier 3 in real time, and the delay from the voltage detection unit 13 detecting the common-mode transient interference signal to sending the first control signal and the second control signal needs to be less than the delay from the amplifier 3 outputting the bit error signal to the second input terminal 213 of the latch 21, that is, before the bit error signal arrives, the latch 21 needs to latch the original input signal that does not include the common-mode transient interference signal, maintain the output of the original input signal, and prevent the output of the bit error signal.

[0080] In this solution, the common-mode transient interference signal is detected in real time by the voltage detection unit. When the common-mode transient interference signal that can cause bit errors is detected, the signal processing module 2 is promptly controlled to output the original input signal, thereby effectively suppressing the output of the bit error signal, reducing the bit error rate of the signal transmission between the transmitter and the receiver, and improving the anti-interference ability of the signal path.

[0081] In one practicable embodiment, the receiver is connected to the transmitter (TX);

[0082] The transmitter is used to receive the original input signal and output the original input signal to the control module 1 and the signal processing module 2.

[0083] In this solution, the receiver receives the original input signal through the transmitter, ensuring the effective transmission of the original input signal.

[0084] In one feasible solution, a capacitor C is provided between the receiver and the transmitter;

[0085] The capacitor is used to perform coupling processing on the original input signal, and output the original input signal after coupling processing to the control module 1 and the signal processing module 2.

[0086] In this solution, the effective transmission of signals between the transmitter and the receiver is achieved through capacitors.

[0087] In this embodiment, the common-mode transient interference signal is detected in real time by the voltage detection unit. When the common-mode transient interference signal that can cause bit errors is detected, the voltage detection unit promptly controls the latch to latch the original input signal that does not include the common-mode transient interference signal and outputs the original input signal to the multiplexer, and promptly controls the multiplexer to output the original input signal. Under the premise of not affecting the normal signal transmission, the output of the bit error signal is effectively suppressed, the bit error rate of the signal transmission between the transmitter and the receiver is reduced, and the anti-interference ability of the signal path is improved.

[0088] Example 3

[0089] This embodiment provides a receiver, such as Figure 4 As shown, the receiver includes the common-mode transient interference suppression circuit as described in Example 1 or 2.

[0090] The receiver in this embodiment integrates the above-mentioned common-mode transient interference suppression circuit, which effectively suppresses the output of error signals without affecting normal signal transmission, reduces the error rate of signal transmission between the transmitter and the receiver, and improves the anti-interference ability of the signal path.

[0091] Example 4

[0092] This embodiment provides a communication interaction system, such as Figure 5 As shown, the communication interaction system includes a transmitter 4 and a receiver 5 as described in Example 3.

[0093] The communication interaction system in this embodiment integrates the transmitter and the above-mentioned receiver, which effectively suppresses the output of error signals without affecting normal signal transmission, reduces the error rate of signal transmission between the transmitter and the receiver, and improves the anti-interference ability of the signal path.

[0094] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A common mode transient interference suppression circuit, characterized in that: The common-mode transient interference suppression circuit is integrated in the receiver, and the common-mode transient interference suppression circuit includes a control module and a signal processing module; The first output terminal of the control module is electrically connected to the first control terminal of the signal processing module; The control module and the signal processing module both receive the original input signal input by the transmitter; The control module is used to generate a target control instruction before a set time period if a common mode transient interference signal is detected in the original input signal during signal transmission, and output the target control instruction to the signal processing module; The signal processing module is used to output the original input signal according to the target control instruction to suppress the output of the error signal; Wherein, the bit error signal is formed by superposition of the original input signal and the common mode transient interference signal; A first time required for the control module to output the target control instruction to the signal processing module is less than a second time required for the error signal to be transmitted to the signal processing module.

2. The common mode transient interference suppression circuit according to claim 1, characterized in that: The signal processing module includes a latch; The first output terminal of the control module is electrically connected to the second control terminal of the latch; The control module is further configured to generate a first control signal when the common mode transient interference signal is detected, and output the first control signal to the latch; The latch is used to latch and output the original input signal according to the first control signal.

3. The common mode transient interference suppression circuit according to claim 2, characterized in that: The signal processing module also includes a multiplexer; The first output terminal of the control module is electrically connected to the third control terminal of the multiplexer; The second output terminal of the latch is electrically connected to the first input terminal of the multiplexer; The control module is further configured to generate a second control signal when the common-mode transient interference signal is detected, and output the second control signal to the multiplexer; The multiplexer is used for receiving and outputting the original input signal output by the latch according to the second control signal.

4. The common mode transient interference suppression circuit according to claim 3, characterized in that: The second input terminal of the latch is electrically connected to the third input terminal of the multiplexer; When the control module does not detect the common-mode transient interference signal, the multiplexer is further configured to receive and output the original input signal.

5. The common mode transient interference suppression circuit according to claim 3 or 4, characterized in that: The common mode transient interference suppression circuit also includes an amplifier; The fourth input terminal of the amplifier is electrically connected to the fifth input terminal of the control module, and the third output terminal of the amplifier is electrically connected to the second input terminal of the latch and the third input terminal of the multiplexer respectively; The amplifier is used to amplify the original input signal.

6. The common mode transient interference suppression circuit according to any one of claims 1 to 4, characterized in that: The control module includes a voltage detection unit; The voltage detection unit is used to output a target control instruction to control the signal processing module to output the original input signal to suppress the output of the error signal when it detects that the voltage value of the common mode transient interference signal exceeds a preset voltage range.

7. The common mode transient interference suppression circuit according to any one of claims 1 to 4, characterized in that: The receiver is connected to the transmitter; The transmitter is used to receive the original input signal and output the original input signal to the control module and the signal processing module.

8. The common mode transient interference suppression circuit according to claim 7, characterized in that: A capacitor is provided between the receiver and the transmitter; The capacitor is used to perform coupling processing on the original input signal, and output the original input signal after coupling processing to the control module and the signal processing module.

9. A receiver, characterized in that: The receiver comprises a common mode transient interference suppression circuit as claimed in any one of claims 1-8.

10. A communication interaction system, characterized in that: The communication interaction system comprises a transmitter and a receiver as claimed in claim 9.

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