Method and device for measuring delay certainty of superheterodyne digital receiver

Abstract

The invention discloses a method and device for measuring delay certainty of a superheterodyne digital receiver, and the method comprises the steps: carrying out the analog down-conversion, analog-to-digital conversion and digital down-conversion of an obtained radio frequency single-tone test signal a, so as to obtain a baseband I / Q test signal m; a pulse reset signal i synchronous with the reference clock d is generated every a preset interval period so as to periodically reset modules such as an ADC and a data interface; delaying the signal i to serve as a data acquisition enabling mark k; when the mark k is received each time, triggering to synchronously collect a section of baseband I / Q test signal m as a test data sample n; and calculating a phase value o corresponding to the sample n, and performing error comparison on the phase value o according to a preset strategy to obtain a main signal link delay state of the superheterodyne digital receiver. According to the method and the device for measuring the delay certainty of the superheterodyne digital receiver, rapid and automatic measurement is realized, and the jump of the link delay can be rapidly identified.

Description

Technical Field

[0001] The present invention relates to the technical field of superheterodyne digital receivers, and in particular to a method and device for measuring the delay determinism of a superheterodyne digital receiver. Background Art

[0002] In modern communication and radar systems, the determinism of the main signal link delay of a superheterodyne digital receiver has a direct impact on the synchronization accuracy, ranging accuracy, and overall signal processing architecture of the system. However, due to factors such as the failure to meet the setup and hold time of the ADC synchronization signal, clock domain conversion, serial-to-parallel conversion, and asynchronous extraction, the signal link delay may have a minimum delay jitter in units of sampling clock cycles. How to determine whether the main signal link delay of a superheterodyne digital receiver is deterministic through measurement is an important issue that needs to be addressed.

[0003] Measuring the deterministic link delay of a superheterodyne digital receiver is challenging. The input signal is an RF signal and the output signal is a baseband digital signal, which makes it impossible to use traditional delay measurement tools such as oscilloscopes or network analyzers directly. One possible method is to evaluate the consistency of the delay by continuously comparing the phase relationship between the transmitter and the receiver through a closed loop with the superheterodyne digital transmitter. However, this method requires an additional dedicated transmitter and a complex test signal generation process. The operation is cumbersome, the equipment is large, and the cost is high.

[0004] Considering this situation, from the perspective of engineering efficiency and cost-effectiveness, it is urgent to develop a simplified, fast and economical measurement method to evaluate the certainty of link delay of superheterodyne digital receivers every time they are turned on. The ideal solution should be able to quickly identify the jump of link delay, without relying on other dedicated equipment, and support automated fast measurement. Summary of the invention

[0005] In order to solve the technical problems existing in the background technology, the present invention proposes a method and device for measuring the delay determinism of a superheterodyne digital receiver.

[0006] The present invention provides a method for measuring the delay determinism of a superheterodyne digital receiver, comprising the following steps:

[0007] S1, performing analog down-conversion, filtering, and amplification processing on the acquired RF single-tone test signal a to obtain an intermediate frequency single-tone test signal f, and performing analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h;

[0008] S2, digitally down-converting the intermediate frequency digital test signal h to obtain a baseband I / Q test signal m;

[0009] S3, generating a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval, and delaying the periodic pulse reset signal i by M reference clock d periods as a data acquisition enable mark k;

[0010] S4. When a data acquisition enable mark k is received each time, a synchronous acquisition of a continuous baseband I / Q test signal m is triggered, and the synchronously acquired baseband I / Q test signal is used as a test data sample n;

[0011] S5. Calculate the phase value o corresponding to the test data sample n, and perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver, where the delay state includes a fixed delay and a variable delay.

[0012] Preferably, calculating the phase value o corresponding to the test data sample n specifically includes:

[0013] Perform fast Fourier transform on the test data sample n to obtain complex spectrum data;

[0014] Determine the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data;

[0015] The phase value corresponding to the peak I / Q data is calculated, and the phase value is used as the phase value o of the test data sample n.

[0016] Preferably, determining the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data specifically includes:

[0017] The complex spectrum data is modulo-calculated to find the position index corresponding to the maximum modulus value, and the corresponding peak I / Q data in the complex spectrum data is retrieved according to the position index.

[0018] Preferably, calculating the phase value corresponding to the peak I / Q data specifically includes:

[0019] The inverse tangent of the peak I / Q data is calculated using a coordinate rotation digital calculation algorithm.

[0020] Preferably, the preset strategy specifically includes:

[0021] Calculate the difference between the maximum value and the minimum value corresponding to the phase value o, and compare the difference with a preset reference error value;

[0022] When the difference is less than the preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a fixed delay;

[0023] When the difference is not less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a delay change.

[0024] Preferably, the calculation process of the preset reference error value λ is as follows:

[0025]

[0026] Among them, f a is the frequency of the RF single-tone test signal a; f LO is the frequency of the simulated local oscillator b; f nco is the frequency of the digital local oscillator j; f adc is the sampling frequency of the ADC, that is, the phase value of the baseband I / Q test signal h converted from the phase difference fluctuation of half the ADC conversion period.

[0027] Preferably, the frequency f of the RF single-tone test signal a a The frequency f of the analog local oscillator b LO The absolute value of the difference between the two is the frequency f of the reference clock d base An integer multiple of |f a -f LO |=K×f base , where K is any positive integer.

[0028] The present invention provides a device for measuring the delay determinism of a superheterodyne digital receiver, comprising:

[0029] The analog frequency conversion channel module is used to perform analog down-conversion, filtering, and amplification processing on the acquired radio frequency single-tone test signal a to obtain an intermediate frequency single-tone test signal f;

[0030] A signal conversion module, used for performing analog-to-digital conversion and clock domain conversion on an intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h;

[0031] A digital down-conversion module, used for digitally down-converting an intermediate frequency digital test signal h to obtain a baseband I / Q test signal m;

[0032] A timing synchronous reset generation module is used to generate a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval to reset the ADC and its related circuits, the data interface module and the digital oscillator used by the digital down-conversion module;

[0033] The delay unit is used to delay the pulse reset signal i by M reference clock d cycles as a data acquisition enable mark k, where M is a fixed integer.

[0034] A synchronous data acquisition module, for triggering synchronous acquisition of a continuous baseband I / Q test signal m when receiving a data acquisition enable mark k, and using the baseband I / Q test signal that triggers synchronous acquisition as a test data sample n;

[0035] A phase calculation module is used to calculate the phase value o corresponding to the test data sample n;

[0036] The delay determination module is used to perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver, and the delay state includes fixed delay and variable delay.

[0037] Preferably, the timing synchronization reset generation module includes:

[0038] A timer, used for generating a cycle counter with a period of N using a reference clock d, the counter is incremented by 1 at each clock cycle, and outputting the cycle counter value to a synchronous reset generating unit;

[0039] The synchronous reset generating unit is used to output a pulse reset signal i synchronized with the reference clock d every time the cycle counter value cycles through a cycle.

[0040] Preferably, the phase calculation module comprises:

[0041] An FFT calculation unit is used to perform a fast Fourier transform on the test data sample n and output complex spectrum data to the peak search calculation unit;

[0042] The peak-finding calculation unit is used to find the modulus of the complex spectrum data, find the position index corresponding to the maximum modulus value, and extract the corresponding peak I / Q data in the complex spectrum data according to the position index, and send it to the CORDIC inverse tangent calculation unit;

[0043] The CORDIC inverse tangent calculation unit uses a coordinate rotation digital calculation algorithm to calculate the inverse tangent of the peak I / Q data, obtains the phase value o of the test data sample n and outputs it.

[0044] In the present invention, the proposed method and device for measuring the delay determinism of a superheterodyne digital receiver, when receiving a data acquisition enable mark k, triggers the synchronous acquisition of a continuous baseband I / Q test signal m, and uses the baseband I / Q test signal that triggers the synchronous acquisition as a test data sample n; calculates the phase value o corresponding to the test data sample n, and performs an error comparison on the phase value o obtained in each reset cycle according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver, and the delay state includes a fixed delay and a variable delay. If the phase value o calculated each time is consistent within the error range, it means that the main signal link delay of the superheterodyne digital receiver is fixed, otherwise it means that the delay will change. In the measurement process, the present invention adopts periodic automatic reset, digital acquisition and calculation, instead of the process of repeated power-on measurement, realizes fast automatic measurement, and can quickly identify the jump of link delay. Therefore, the embodiment of the present invention provides a simple, efficient and low-cost measurement scheme for the link delay determinism of the superheterodyne digital receiver, which greatly facilitates technicians in related fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the working process structure of a method for measuring the delay determinism of a superheterodyne digital receiver proposed by the present invention;

[0046] Figure 2 A schematic diagram of the module architecture of a device for measuring the delay determinism of a superheterodyne digital receiver proposed by the present invention;

[0047] Figure 3 A schematic diagram of the structure of a timing synchronization reset generation module of a superheterodyne digital receiver delay deterministic measurement device proposed by the present invention;

[0048] Figure 4 The present invention provides a schematic structural diagram of a phase calculation module of a device for measuring the delay determinism of a superheterodyne digital receiver. DETAILED DESCRIPTION

[0049] Reference Figure 1-4 The present invention proposes a method for measuring the delay determinism of a superheterodyne digital receiver, comprising the following steps:

[0050] S1. Perform analog down-conversion, filtering, and amplification processing on the acquired RF single-tone test signal a to obtain an intermediate frequency single-tone test signal f, and perform analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h.

[0051] In this embodiment, the signal source generates a coherent radio frequency single-tone test signal a, an analog local oscillator b and a reference clock c; the phase-locked loop generates a reference clock d and a processing clock e according to the reference clock c.

[0052] In this embodiment, the frequency f of the RF single-tone test signal a is a The frequency f of the analog local oscillator b LO The absolute value of the difference between the two is the frequency f of the reference clock d base An integer multiple of |f a -f LO |=K×f base , where K is an arbitrary positive integer. The frequency of the reference clock d is an integer multiple of the reference clock c; the frequency of the processing clock e is an integer multiple of the reference clock d; the signal source shall not be shut down and restarted during the measurement process to ensure that the initial phase difference between the RF single-tone test signal a and the analog local oscillator b remains unchanged during the measurement process.

[0053] In this embodiment, the frequency f of the RF single-tone test signal a is a =5.2GHz, analog local oscillator frequency f LO =5GHz, the frequency of the reference clock c is f c =20MHz, the frequency of the reference clock d is f base =20MHz, the frequency f of the processing clock e e =240MHz.

[0054] In this embodiment, the sampling frequency of the analog-to-digital converter may be equal to the frequency of the processing clock e, and the clock domain conversion refers to switching the collected data from the sampling clock domain to the clock domain of the processing clock e.

[0055] In the embodiment of the present invention, the sampling frequency is 240MSPS.

[0056] S2. Digitally down-convert the intermediate frequency digital test signal h to obtain a baseband I / Q test signal m.

[0057] In this embodiment, the frequency f of the digital local oscillator j used in digital down-conversion is j Not equal to the frequency f of the RF single-tone test signal a a The frequency f of the analog local oscillator b LO The absolute value of the difference between |f a -f LO |, to ensure that the frequency of the baseband I / Q test signal m is not equal to 0.

[0058] In the embodiment of the present invention, the frequency of the digital local oscillator j is 180 MHz.

[0059] S3. Generate a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval, and delay the periodic pulse reset signal i by M reference clock d periods as a data acquisition enable mark k.

[0060] In this embodiment, the pulse reset signal i is used to periodically reset the ADC and its related circuits, the ADC data interface, and the digital oscillator that provides the digital local oscillator j for digital down-conversion.

[0061] In this embodiment, the reset mode of the digital oscillator is synchronous reset; the time interval between generating two pulse reset signals i is greater than the sum of the ADC delay, data interface delay, digital down-conversion delay and the time required for synchronous acquisition of the baseband I / Q test signal h, so as to ensure that each time the baseband I / Q test signal h is acquired, the signal h is stable.

[0062] In the embodiment of the present invention, the time interval between generating two pulse reset signals i is set to 10 ms, which is large enough and is an integer multiple of the period of the reference clock d.

[0063] In this embodiment, the number M of delay periods of the pulse reset signal i is a fixed integer.

[0064] S4. When the data acquisition enable mark k is received, the synchronous acquisition of a continuous baseband I / Q test signal m is triggered, and the baseband I / Q test signal that triggers the synchronous acquisition is used as the test data sample n.

[0065] In the embodiment of the present invention, M takes a value of 50000, that is, the pulse reset signal i is delayed by 5 ms as a data acquisition enable mark k, triggering the synchronous acquisition of 1000 continuous baseband I / Q test signal m data as the test data sample n.

[0066] S5. Calculate the phase value o corresponding to the test data sample n, and perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver, where the delay state includes a fixed delay and a variable delay.

[0067] In this embodiment, if the phase value o calculated each time is consistent within the error range, it means that the main signal link delay of the superheterodyne digital receiver is fixed, otherwise it means that the delay will change.

[0068] In this embodiment, calculating the phase value o corresponding to the test data sample n specifically includes:

[0069] Perform fast Fourier transform on the test data sample n to obtain complex spectrum data;

[0070] Determine the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data;

[0071] The phase value corresponding to the peak I / Q data is calculated, and the phase value is used as the phase value o of the test data sample n.

[0072] In this embodiment, determining the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data specifically includes:

[0073] The complex spectrum data is modulo-calculated to find the position index corresponding to the maximum modulus value, and the corresponding peak I / Q data in the complex spectrum data is retrieved according to the position index.

[0074] In this embodiment, calculating the phase value corresponding to the peak I / Q data specifically includes:

[0075] The inverse tangent of the peak I / Q data is calculated using a coordinate rotation digital calculation algorithm.

[0076] In this embodiment, the preset strategy specifically includes:

[0077] Calculate the difference between the maximum value and the minimum value corresponding to the phase value o, and compare the difference with a preset reference error value;

[0078] When the difference is less than the preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a fixed delay;

[0079] When the difference is not less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a delay change.

[0080] In this embodiment, the calculation process of the preset reference error value λ is as follows:

[0081]

[0082] Among them, f a is the frequency of the RF single-tone test signal a; f LO is the frequency of the simulated local oscillator b; f nco is the frequency of the digital local oscillator j; f adc is the sampling frequency of the ADC, that is, the phase value of the baseband I / Q test signal h converted from the phase difference fluctuation of half the ADC conversion period.

[0083] In the embodiment of the present invention, the number of fast Fourier transform points is 1000. The more points there are, the higher the signal-to-noise ratio of the peak I / Q data is, and the more accurate the calculated phase is.

[0084] The criterion for the consistency of the phase values ​​calculated each time within the error range is that the difference between the maximum and minimum phase values ​​is less than λ;

[0085]

[0086] That is, the range of the phase value calculated each time is less than It can be considered that the main signal link of the superheterodyne digital receiver achieves deterministic delay.

[0087] Reference Figure 1-4 The present invention provides a device for measuring the delay determinism of a superheterodyne digital receiver, comprising:

[0088] The analog frequency conversion channel module is used to perform analog down-conversion, filtering, and amplification processing on the acquired radio frequency single-tone test signal a to obtain an intermediate frequency single-tone test signal f.

[0089] The signal conversion module is used to perform analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h.

[0090] The digital down-conversion module is used to perform digital down-conversion on the intermediate frequency digital test signal h to obtain a baseband I / Q test signal m.

[0091] A timing synchronous reset generation module is used to generate a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval to reset the ADC and its related circuits, the data interface module and the digital oscillator used by the digital down-conversion module;

[0092] The delay unit is used to delay the pulse reset signal i by M reference clock d cycles as a data acquisition enable mark k, where M is a fixed integer.

[0093] The synchronous data acquisition module is used to trigger the synchronous acquisition of a continuous baseband I / Q test signal m when receiving the data acquisition enable mark k, and use the baseband I / Q test signal that triggers the synchronous acquisition as the test data sample n.

[0094] The phase calculation module is used to calculate the phase value o corresponding to the test data sample n.

[0095] The delay determination module is used to perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver, and the delay state includes fixed delay and variable delay.

[0096] In this embodiment, a coherent RF single-tone test signal a and an analog local oscillator b are output to an analog frequency conversion channel module through a signal source, and a coherent reference clock c is output to a phase-locked loop; the analog frequency conversion channel module uses the analog local oscillator b to perform analog down-conversion, filtering, and amplification processing on the RF single-tone test signal a, and outputs an intermediate frequency single-tone test signal f to the ADC module; the ADC module performs analog-to-digital conversion on the intermediate frequency single-tone test signal f, and outputs data g to the data interface module; the data interface module performs clock domain conversion on the data g, and outputs an intermediate frequency digital test signal h to the digital down-conversion module; the digital down-conversion module uses a digital local oscillator j to perform digital down-conversion on the intermediate frequency digital test signal h, and outputs a baseband I / Q test signal m to the synchronous data acquisition module; the synchronous data acquisition module uses the data acquisition enable mark k as a trigger, and synchronously acquires a continuous baseband I / Q test signal m each time, and sends it to the phase Calculation module; phase calculation module, calculates the phase of the test data sample n sent each time, and outputs the phase value o to the phase data upload module; the phase data upload module uploads the phase value o sent each time to the computer display terminal; the phase-locked loop generates a reference clock d according to the reference clock c to the timing synchronization reset generation module, and generates a processing clock e to the digital oscillator and the data interface module; the timing synchronization reset generation module uses the reference clock d, and generates a pulse reset signal i synchronized with the reference clock d every several reference clock d cycles to the ADC module and its related circuits, the data interface module, the digital oscillator and the delay unit; the digital oscillator outputs a digital local oscillator j to the digital down-conversion module, and the pulse reset signal i is used to synchronize the digital oscillator; the delay unit delays the pulse reset signal i by M reference clock d cycles as a data acquisition enable mark k and sends it to the synchronous data acquisition module, where M is a fixed integer.

[0097] In a specific implementation of the embodiment of the present invention, Figure 3 A schematic diagram of the structure of a timing synchronization reset generation module in a delay deterministic measurement device for a superheterodyne digital receiver provided by an embodiment of the present invention, wherein the timing synchronization reset generation module comprises:

[0098] A timer, used for generating a cycle counter with a period of N using a reference clock d, the counter is incremented by 1 at each clock cycle, and outputting the cycle counter value to a synchronous reset generating unit;

[0099] The synchronous reset generating unit is used to output a pulse reset signal i synchronized with the reference clock d every time the cycle counter value cycles through a cycle.

[0100] In a specific implementation of the embodiment of the present invention, Figure 4 A schematic diagram of the structure of a phase calculation module in a device for measuring the delay determinism of a superheterodyne digital receiver provided by an embodiment of the present invention, wherein the phase calculation module comprises:

[0101] An FFT calculation unit is used to perform a fast Fourier transform on the test data sample n and output complex spectrum data to the peak search calculation unit;

[0102] The peak-finding calculation unit is used to find the modulus of the complex spectrum data, find the position index corresponding to the maximum modulus value, and extract the corresponding peak I / Q data in the complex spectrum data according to the position index, and send it to the CORDIC inverse tangent calculation unit;

[0103] The CORDIC inverse tangent calculation unit uses a coordinate rotation digital calculation algorithm to calculate the inverse tangent of the peak I / Q data, obtains the phase value o of the test data sample n and outputs it.

[0104] In this embodiment, CORDIC means a coordinate rotation digital calculation algorithm.

[0105] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for measuring the delay determinism of a superheterodyne digital receiver, characterized in that: The following steps are involved: S1, performing analog down-conversion, filtering, and amplification processing on the acquired RF single-tone test signal a to obtain an intermediate frequency single-tone test signal f, and performing analog-to-digital conversion and clock domain conversion on the intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h; S2, digitally down-converting the intermediate frequency digital test signal h to obtain a baseband I / Q test signal m; S3, generating a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval, and delaying the periodic pulse reset signal i by M reference clock d periods as a data acquisition enable mark k; S4. When a data acquisition enable mark k is received each time, a synchronous acquisition of a continuous baseband I / Q test signal m is triggered, and the synchronously acquired baseband I / Q test signal is used as a test data sample n; S5. Calculate the phase value o corresponding to the test data sample n, and perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver, where the delay state includes a fixed delay and a variable delay.

2. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 1, characterized in that: The calculating of the phase value o corresponding to the test data sample n specifically includes: Perform fast Fourier transform on the test data sample n to obtain complex spectrum data; Determine the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data; The phase value corresponding to the peak I / Q data is calculated, and the phase value is used as the phase value o of the test data sample n.

3. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 2, characterized in that: The determining of the peak I / Q data corresponding to the maximum modulus value in the complex spectrum data specifically includes: The complex spectrum data is modulo-calculated to find the position index corresponding to the maximum modulus value, and the corresponding peak I / Q data in the complex spectrum data is retrieved according to the position index.

4. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 2, characterized in that: The calculating the phase value corresponding to the peak I / Q data specifically includes: The inverse tangent of the peak I / Q data is calculated using a coordinate rotation digital calculation algorithm.

5. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 1, characterized in that: The preset strategy specifically includes: Calculate the difference between the maximum value and the minimum value corresponding to the phase value o, and compare the difference with a preset reference error value; When the difference is less than the preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a fixed delay; When the difference is not less than a preset reference error value λ within the error range, the main signal link delay state of the superheterodyne digital receiver is specifically a delay change.

6. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 5, characterized in that: The calculation process of the preset reference error value λ is as follows: Among them, f a is the frequency of the RF single-tone test signal a; f LO is the frequency of the simulated local oscillator b; f nco is the frequency of the digital local oscillator j; f adc is the sampling frequency of the ADC, that is, the phase value of the baseband I / Q test signal h converted from the phase difference fluctuation of half the ADC conversion period.

7. The method for measuring the delay determinism of a superheterodyne digital receiver according to claim 1, characterized in that: The frequency f of the RF single-tone test signal a a The frequency f of the analog local oscillator b LO The absolute value of the difference between the two is the frequency f of the reference clock d base An integer multiple of |f a -f LO |=K×f base , where K is any positive integer.

8. A device for measuring the delay determinism of a superheterodyne digital receiver, characterized in that: include: The analog frequency conversion channel module is used to perform analog down-conversion, filtering, and amplification processing on the acquired radio frequency single-tone test signal a to obtain an intermediate frequency single-tone test signal f; A signal conversion module, used for performing analog-to-digital conversion and clock domain conversion on an intermediate frequency single-tone test signal f to obtain an intermediate frequency digital test signal h; A digital down-conversion module, used for digitally down-converting an intermediate frequency digital test signal h to obtain a baseband I / Q test signal m; A timing synchronous reset generation module is used to generate a pulse reset signal i synchronized with the reference clock d of the superheterodyne digital receiver at every preset interval to reset the ADC and its related circuits, the data interface module and the digital oscillator used by the digital down-conversion module; The delay unit is used to delay the pulse reset signal i by M reference clock d cycles as a data acquisition enable mark k, where M is a fixed integer. A synchronous data acquisition module, for triggering synchronous acquisition of a continuous baseband I / Q test signal m when receiving a data acquisition enable mark k, and using the baseband I / Q test signal that triggers synchronous acquisition as a test data sample n; A phase calculation module is used to calculate the phase value o corresponding to the test data sample n; The delay determination module is used to perform error comparison on the phase value o according to a preset strategy to obtain the main signal link delay state of the superheterodyne digital receiver, and the delay state includes fixed delay and variable delay.

9. The device for measuring the delay determinism of a superheterodyne digital receiver according to claim 8, characterized in that: The timing synchronous reset generation module includes: A timer, used for generating a cycle counter with a period of N using a reference clock d, the counter is incremented by 1 at each clock cycle, and outputting the cycle counter value to a synchronous reset generating unit; The synchronous reset generating unit is used to output a pulse reset signal i synchronized with the reference clock d every time the cycle counter value cycles through a cycle.

10. The device for measuring the delay determinism of a superheterodyne digital receiver according to claim 8, characterized in that: The phase calculation module includes: An FFT calculation unit is used to perform a fast Fourier transform on the test data sample n and output complex spectrum data to the peak search calculation unit; The peak-finding calculation unit is used to find the modulus of the complex spectrum data, find the position index corresponding to the maximum modulus value, and extract the corresponding peak I / Q data in the complex spectrum data according to the position index, and send it to the CORDIC inverse tangent calculation unit; The CORDIC inverse tangent calculation unit uses a coordinate rotation digital calculation algorithm to calculate the inverse tangent of the peak I / Q data, obtains the phase value o of the test data sample n and outputs it.

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