An ultra-low delay universal simplex transmission method and system based on 8b / 10b coding

Abstract

The present application discloses an ultra-low-latency universal simplex transmission method and system based on 8b / 10b encoding. It adopts a buffer-free, fully synchronous TX transmission architecture to synchronously transmit and eliminate data skew between lanes, thus achieving the minimum time data transmission for multiple lanes. The communication protocol uses comma to achieve receiving byte boundary alignment. After the comma data of each lane, the transmitting end sends a certain length of the same sequence for the receiving end to use as a bond sequence byte sequence, achieving lane alignment and protocol parsing 4-byte boundary positioning. The channel-bonding configuration of the receiving end and the intelligent design of the alignment sequence can improve data transmission efficiency. Modifying the bond sequence or control code can flexibly adjust the output order of the protocol parsing bytes, while minimizing the transmission and reception delay and improving the system's adaptability to different transmission requirements.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to an ultra-low-latency universal simplex transmission method and system based on 8b / 10b encoding. Background Art

[0002] FPGA low-latency, high-speed transmission is typically based on improvements to the Aurora protocol IP and customized high-speed transmission. Aurora protocol improvements optimize FIFO size and cross-clock domain response, compressing data transmission time. Customized high-speed transmission streamlines the transmission protocol to shorten transmission time and utilizes cross-clock buffering for transmission and reception.

[0003] The use of FIFO buffers increases transmission latency and latency uncertainty. Coupled with the necessary overhead of inter-lane alignment and intra-lane byte ordering, transmit and receive latency at 10 Gbps (gigabits per second) is typically reduced to 200-300 ns. Transmission latency fluctuates randomly within this range with varying power cycles and multiple link establishments. Enabling the wrap-around function to reduce bit error rates further increases transmit and receive latency. Figure 1 This is a flowchart of a conventional high-speed transmission latency test method: The FPGA on the left is the high-speed transmitter, and the FPGA on the right is the high-speed receiver. When the transmitting FPGA sends the frame header of a transmission message, it simultaneously sends a frame header pulse or message level signal to the receiving FPGA via the LVDS interface. The receiving FPGA compares the timing relationship between the received high-speed message and the frame header pulse / message level to determine the transmission latency of the high-speed transmission and reception. In applications without latency optimization, transmission latency is typically 500ns to 700ns.

[0004] In the existing technology, FPGAs widely use high-speed transmission interfaces. This type of interface has the advantage of large transmission bandwidth, but generally has a large transmission delay. How to overcome the disadvantage of large delay and enable FPGA high-speed transmission to have a wide range of application scenarios in situations with strong real-time control and requirements of fast timing response speed has become one of the research directions of technical personnel in this field. Summary of the Invention

[0005] The purpose of this application is to overcome the existing technical deficiencies and provide an ultra-low-latency universal simplex transmission method and system based on 8b / 10b encoding. The sending end has a bufferless synchronous drive, and the receiving end has a channel-bonding configuration and an intelligent design of the alignment sequence to improve data transmission efficiency. Modifying the bond sequence or control code can flexibly adjust the internal byte order of the lane, shortening the transmission and reception delay while improving the system's adaptability to different transmission requirements.

[0006] The purpose of this application is achieved through the following technical solutions:

[0007] In a first aspect, the present application proposes an ultra-low latency universal simplex transmission method based on 8b / 10b coding, which is applied to an ultra-low latency universal simplex transmission system, wherein the system includes a controlled slave alignment receiving end and a transmitting end using a bufferless TX slave synchronous transmission architecture, and the method includes:

[0008] The transmitter uses the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels;

[0009] The transmitter configures all lanes in unbuffered slave synchronization mode. After power-on reset, a state machine is used to manually control the internal delay, phase initialization, and transmit phase alignment mechanisms within the channel lanes to eliminate skew between transmitted data lanes. Transmitted data contains continuous comma sequences, which the receiver uses to determine received byte boundaries. Each lane sends the data comma sequence and then sends the same byte or byte sequence for lane alignment.

[0010] The receiving end resets by receiving a continuous comma sequence based on the Lane channel, and returns to the initial state when a non-comma sequence is received after the reset;

[0011] The receiving end sets all lanes as slave lanes in chanel-bond mode and selects the same 4-byte string after the consecutive comma sequences as the bond sequence alignment identification sequence;

[0012] When the receiving end detects that the commadet control signal changes from high level to low level, it sends a control sequence to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the sending end;

[0013] The receiving end reselects the bond sequence or modifies the bondi control sequence code to control the order of the parallel output bytes within the lane.

[0014] In a possible embodiment, the steps of resetting the receiving end by receiving a continuous comma sequence based on a Lane channel and returning to an initial state when receiving a non-comma sequence after the reset include:

[0015] The receiving end receives a continuous comma sequence and starts the reset state machine to count and obtain the comma sequence count value;

[0016] When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state;

[0017] When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

[0018] In a possible embodiment, the steps after the receiving state machine is reset and enters the reset state include:

[0019] The self-state machine using flexible buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all lanes in the receiving channel become high.

[0020] In a possible embodiment, the clock management component adopts MMCM, PLL or BUFG.

[0021] In a first aspect, the present application further proposes an ultra-low latency universal simplex transmission system based on 8b / 10b encoding, the system comprising a controlled slave alignment receiving end and a transmitting end adopting an unbuffered TX slave synchronous transmission architecture, the method comprising:

[0022] The transmitter uses the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels;

[0023] All lanes are configured in unbuffered slave synchronization mode. After power-on reset, a state machine is used to manually control the internal delay, phase initialization, and transmit phase alignment mechanisms within the lanes to eliminate inter-lane skew of transmitted data. Transmitted data contains a continuous comma sequence, which is used by the receiving end to determine the received byte boundary. Each lane sends the data comma sequence and then sends the same byte or byte sequence for lane alignment.

[0024] The receiving end is used to reset based on the continuous comma sequence received by the Lane channel, and return to the initial state when a non-comma sequence is received after the reset;

[0025] Set all lanes as slave lanes in chanel-bond mode, and select the same 4-byte string after the consecutive comma sequence as the bond sequence alignment recognition sequence;

[0026] When the commadet control signal is detected to be converted from high level to low level, a control sequence is sent to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the transmitting end;

[0027] Reselect the bond sequence or modify the bondi control sequence code to control the order of the parallel output bytes within the Lane.

[0028] In a possible embodiment, the receiving end is further configured to: receive a continuous comma sequence through the receiving end, start a reset state machine to count and obtain a comma sequence count value;

[0029] When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state;

[0030] When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

[0031] In a possible embodiment, the receiving end is further configured to:

[0032] The self-state machine of the elastic buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all lanes in the receiving channel become high.

[0033] In a possible embodiment, the clock management component adopts MMCM, PLL or BUFG.

[0034] The above-mentioned main scheme of this application and its further options can be freely combined to form multiple schemes, all of which are schemes that can be adopted and protected by this application; and in this application, (non-conflicting options) can also be freely combined with each other and with other options. After understanding the scheme of this application, those skilled in the art will understand that there are many combinations based on the existing technology and common knowledge, all of which are technical solutions to be protected by this application, and they are not exhaustive here.

[0035] The present application discloses an ultra-low-latency universal simplex transmission method and system based on 8b / 10b encoding. The transmitter adopts an unbuffered TX slave synchronous transmission architecture and uses a clock management component to convert an externally input reference clock into the user clock TXUSERCLK2 to drive all transmit lane channels. The receiver receives a continuous comma sequence for reset and returns to the initial state upon receiving a non-comma sequence. The receiver sets all lane channels as chanel-bond slave lanes and sets the comma and subsequent bytes of the comma sequence, or the subsequent string of the comma sequence, as the bond sequence. When the commadet control signal is detected to transition from high to low, a control sequence is sent to the bondi control sequence code, so that the transmitted data of all lanes is aligned and output according to the byte order of the transmitter. The bond sequence sequence is reselected or the bondi control sequence code is modified to control the byte order within the lane. The unbuffered buffer output and intelligent alignment sequence design of the transmitter can shorten the delay of data transmission, reception, and transmission. Modifying the bond sequence or control code can flexibly adjust the byte order within the lane, thereby improving the system's flexibility in protocol parsing. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 This is a flow chart of a method for testing high-speed transmission delay in the prior art.

[0038] Figure 2 A schematic diagram of an ultra-low latency universal simplex transmission system proposed in an embodiment of the present application is shown.

[0039] Figure 3 A flow chart of an ultra-low-latency universal simplex transmission method based on 8b / 10b encoding proposed in an embodiment of the present application is shown.

[0040] Figure 4 A schematic diagram of a fully slave synchronous transmit Lane clock architecture and a traditional transmit synchronous Lane architecture is shown.

[0041] Figure 5 The control timing diagram of sending all slave lanes proposed in an embodiment of the present application is shown.

[0042] Figure 6The figure shows the adaptive RX end reset flow chart proposed in the embodiment of the present application.

[0043] Figure 7 A schematic diagram of bond sequence change arrangement proposed in an embodiment of the present application is shown.

[0044] Figure 8 A schematic diagram of the byte order fine-tuning delay proposed in an embodiment of the present application is shown.

[0045] Figure 9 A schematic diagram shows 8-Lane JESD204B data channel initialization alignment sequence ILAS data received by the ultra-low latency universal simplex transmission method according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0047] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0048] In the existing technology, FPGAs widely use high-speed transmission interfaces. This type of interface has the advantage of large transmission bandwidth, but generally has a large transmission delay. How to overcome the disadvantage of large delay and enable FPGA high-speed transmission to have a wide range of application scenarios in situations with strong real-time control and requirements of fast timing response speed has become one of the research directions of technical personnel in this field.

[0049] Therefore, in order to solve the above-mentioned technical problems, the embodiment of the present application proposes an ultra-low latency universal simplex transmission method and system based on 8b / 10b encoding, which can shorten the total latency of high-speed transmission and reception to about 100ns under 10Gbps conditions, and the latency jitter does not exceed 1 internal logic clock cycle. At the same time, it enables FPGA high-speed transmission to be applied to long-distance and strong real-time response scenarios, which is described in detail below.

[0050] Please refer to Figure 2 , Figure 2A schematic diagram of the ultra-low latency universal simplex transmission system proposed in an embodiment of the present application is shown, which is divided into a TX transmitter and an RX receiver, both of which process and send data through an FPGA (field programmable gate array). The data is then received through real-time control instructions via digital optical transmission and is applied in a high-speed instruction execution mechanism with fast response requirements, for use in a control environment with high precision and high speed requirements.

[0051] Figure 3 A flow chart of an ultra-low-latency universal simplex transmission method based on 8b / 10b encoding proposed in an embodiment of the present application is shown. The method is applied to the above-mentioned ultra-low-latency universal simplex transmission system. The method includes the following steps:

[0052] Step S100: The transmitting end uses the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels.

[0053] The principle of TXUSERCLK2 generation is to use the reference clock as the benchmark, accurately generate a clock signal with a frequency of 1 / 40 of the high-speed transmission baud rate, and drive it into the TXUSERCLK2 of all transmission lanes through the BUFG.

[0054] If the frequency is appropriate, that is, the input clock has met the clock frequency requirement of 1 / 40 of the high-speed transmission baud rate required by the internal lane of the system, then BUFG (Buffered Global Clock) can be used directly to drive the clock network.

[0055] Step S200: The transmitting end configures all lanes in a bufferless slave synchronization mode. After power-on reset, the state machine is used to manually control the internal delay, phase initialization, and transmit phase alignment mechanisms of the channel lanes to eliminate skew between transmitted data lanes. The transmitted data contains a continuous comma sequence, which is used by the receiving end to determine the received byte boundary. After sending the data comma sequence, each lane sends the same byte or byte sequence for lane alignment.

[0056] Configuring Lane in Bufferless Slave Synchronous Mode: On the sending end of the system, the data channel (Lane) is set to a mode in which there is no additional data buffering and data transmission is synchronized following a master clock source, which helps reduce latency and ensures immediate data transmission.

[0057] Manual control using a state machine after power-on reset: After the system powers on and passes through the reset phase, a state machine logic is used to fine-tune the internal operation of each lane. A state machine is a digital logic circuit that transitions between different states based on input signals, enabling complex and orderly initialization processes.

[0058] Lane-wide delay and phase initialization adjusts the signal path delay and phase within each lane, ensuring precise time alignment across all lanes. This prevents data skew (differences in data arrival times). The transmit phase alignment mechanism further fine-tunes the phase of the transmitted signal, ensuring that data packets from all lanes converge correctly at the receiving end. This eliminates skew between transmitted data lanes and eliminates differences in packet arrival times between lanes due to physical path length differences, ensuring synchronous data transmission.

[0059] A comma sequence is a special character or bit sequence inserted into the data stream. It serves as a reference point for the receiver to identify packet boundaries and perform synchronization, helping it accurately determine the starting position of each packet. A lane sends a comma sequence followed by the same byte or byte sequence. This allows the receiver to compare the reception of each lane based on this known identical data, further refining alignment between lanes.

[0060] The transmitter configures all transmit lanes in an unbuffered, slave-synchronous TX architecture. This reduces buffer write and read latency and avoids transmission delay jitter caused by random read / write address differences. This TX architecture enables synchronous transmission to eliminate inter-lane transmission skew and prevent slow-transmitting lanes from affecting overall transmission latency.

[0061] After power-on, the state machine manually controls lane synchronization, driving the internal delay, initialization, and alignment timing of the lane to achieve precise synchronization between TXUSERCLK2 and the high-speed clock PHYCLK, eliminating transmission skew between lanes and canceling the clock compensation code to achieve full-bandwidth data transmission.

[0062] The high-speed clock PHYCLK of each lane is precisely synchronized with TXUSERCLK2 to ensure that data is sent simultaneously on each lane.

[0063] The fully slave synchronous timing driver generates a common, reliable clock signal, TXUSERCLK2, for all transmitting lanes, enabling precise synchronization between lanes and even interfaces. This is one of the key technologies for ensuring data accuracy and efficiency in high-speed data transmission systems.

[0064] An externally provided clock source serves as the reference for all internal clock signals. This external reference clock is fed into the MMCM or PLL. Using a fully synchronous transmit lane synchronization scheme, all data transmission lanes in a high-speed serial communication system are synchronized using a unified clock signal. This ensures simultaneous transmission of data packets across all lanes, reducing timing skew and improving signal integrity and overall system performance.

[0065] Compare the all-slave transmission Lane synchronous clock architecture of this application with the traditional transmission Lane synchronous architecture, please refer to Figure 4 , Figure 4 A schematic diagram of the all-slave transmission Lane synchronous clock architecture and the traditional transmission Lane synchronous architecture is shown. The left side is the traditional transmission Lane synchronous architecture, which cannot achieve cross-interface synchronous transmission. The right side is the all-slave transmission Lane synchronous clock architecture, which can achieve full-chip cross-interface transmission synchronization.

[0066] XINLINX recommends a master-slave synchronization solution for multi-lane transmission synchronization. Taking 4 lanes as an example, the 4 lanes on the left are divided into one master and three slaves. The master lane's TXOUTCLK2 is driven by the MMCM / PLL and then drives the user clock TXUSERCLK of all its lanes. The 4 lanes on the right are divided into all slaves. The TXOUTCLK of all lanes is driven by the MMCM / PLL and then drives the user clock TXUSERCLK of all lanes.

[0067] Please refer to Figure 5 , Figure 5 The control timing diagram of sending all slave lanes proposed in an embodiment of the present application is shown. After each lane is powered on, the TXDLYSRESET, TXPHINIT and TXPHAIGN processes need to be executed in sequence. The advantage of using all-slave lanes for synchronous transmission is that the control timing gets rid of the constraint on the number of slave lanes caused by the dynamic adjustment of the master lane output clock delay, and is more suitable for large-scale, cross-interface synchronous transmission. In a high-speed digital signal transmission system, in order to ensure that the signals of all data channels (Lane) can arrive at the receiving end accurately and synchronously, all-slave lane control timing is performed. TXDLYSRESET, TXPHINIT and TXPHAIGN are used to calibrate the signal delay and phase of each lane to achieve low-latency synchronous transmission of data.

[0068] TXDLYSRESET (Delay Reset) is used to reset the delay calibration logic on the lane. Executed after power-up or system reset, it clears any previous delay settings and prepares for the next precise delay adjustment.

[0069] The TXPHINIT (Phase Initialization) command initiates a process to determine and set the initial phase of each lane. Phase alignment is critical for high-speed serial data transmission because even small phase deviations can cause data errors.

[0070] TXPHAIGN (phase fine-tuning or eye diagram optimization) fine-tunes the serial bit phase after completing the initial phase alignment in order to transmit precisely synchronized signals.

[0071] Step S300: The receiving end receives a continuous comma sequence based on the Lane channel to perform a reset, and returns to the initial state when a non-comma sequence is received after the reset.

[0072] After the receiver performs a reset operation, in order to ensure that the system is ready to receive data and eliminate the abnormal state of the buffer, when the first non-comma (K28.5) signal is received, it means that data transmission has officially started. The receiver needs to perform steps to return to the initial working state so that it can automatically reset again after receiving the next continuous comma sequence.

[0073] Step S300 includes:

[0074] The receiving end receives a continuous comma sequence and starts the reset state machine to count and obtain the comma sequence count value;

[0075] When the comma sequence count value reaches the preset threshold, the receiving state machine triggers a reset and enters the reset state;

[0076] When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

[0077] The reset mechanism uses a specific control character (comma character K28.5) to trigger the receiver's state reset process, thereby optimizing the receiving performance.

[0078] Since the simplex receiver may not reach its optimal working state immediately upon power-up or high-speed reset, the initial received data may have a high bit error rate. First, the comma count is received: the receiver monitors the input data stream and activates a state machine to count when a continuous comma sequence (K28.5) is detected. When the number of commas reaches the preset threshold, it indicates that the receiver may have stably identified the data stream, and a reset operation is triggered. Reset can recalibrate the timing and phase of the receiver to prepare for data reception. After reset, the system will remain in the reset state for a period of time to ensure that all internal states are fully refreshed, and then gradually return to normal operating mode. Once non-comma data is received, it indicates that normal data transmission has begun, and the reset state machine returns to the initial state to prepare for actual data transmission.

[0079] The transmitter (TX) can proactively guide the receiver (RX) to reset by sending a string of comma characters in advance. This approach is particularly effective for system initialization or fault recovery.

[0080] The comma count is not reset continuously to ensure that occasional comma characters in normal communication will not trigger a reset. This ensures protocol compatibility and data continuity and avoids unnecessary interference.

[0081] The advantage of this method is that it can dynamically adjust based on the characteristics of the actual data stream, ensuring that the receiver can quickly self-adjust to the optimal working state when encountering unfavorable initial conditions or link changes, thereby effectively reducing the bit error rate and improving the reliability and efficiency of communications.

[0082] Figure 6 The figure shows the adaptive RX reset flow chart proposed in an embodiment of the present application. First, power is applied and RX is initialized to enter the initial state. The system inquires whether the specific character "comma" is detected. If not, the comma count is cleared. If it is detected, the number of occurrences of the comma character is checked. If it is the first occurrence, the counter is set to 0. If the count value is not enough to reset, the count continues. If the threshold is met, the RX is reset or initialized and the resetdone function is waited for completion. The system then determines whether non-comma data is received. If not, the system continues to wait. If received, the system resets the state machine and returns to the initial state.

[0083] In one possible implementation, the steps after the receiving state machine is reset and enters the reset state include:

[0084] The self-state machine using flexible buffer coarse alignment sends a reset pulse to RXBUFRESE when it detects that the resetdone signals of all lanes in the receiving channel become high.

[0085] In the reset process described above, a self-state machine for flexible buffer coarse alignment is run while waiting for resetdone. After detecting that resetdone of all lanes in the receiving channel has been pulled high for a period of time, a reset pulse is uniformly given to the RXBUFRESET signal to ensure that the delay characteristics of each buffer are basically consistent.

[0086] Since the original function of chanel-bond is to use a specific string (up to 4 bytes) to synchronize the output character order of the slave lane and the master lane, but it cannot realize the function of arranging the byte order within the lane in the order of the originating end, the subsequent steps are performed to realize the alignment between lanes and the byte order arrangement within the lane based on chanel-bond.

[0087] First, when no data is actually being transmitted, the sender sends a continuous comma sequence, allowing the receiver to identify and prepare for the incoming data frame. At the start of data transmission, each lane first sends a frame header of at least 4 bytes (8 bytes or more is recommended). The frame header serves as a synchronization marker. The frame header is followed by the actual data payload to be transmitted.

[0088] In step S400, the receiving end sets all lanes as slave lanes in the chanel-bond mode and selects the same 4-byte string after the consecutive comma sequences as the bond sequence alignment recognition sequence.

[0089] Configuring the receiver: All receiving lanes on the interface are configured as chanel-bond slave lanes and set to the same alignment sequence (bond sequence), which is taken from a portion of the transmitter's frame header. The receiver begins counting when a valid transition from comma to data (commadet signal changes from high to low) is detected.

[0090] Step S500: When the receiving end detects that the commadet control signal changes from a high level to a low level, the receiving end sends a control sequence to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the transmitting end.

[0091] Byte alignment is then performed. By sending a specific control sequence to bondi (the interface that controls lanes) after a specific clock cycle, the data in all lanes is aligned and output according to the byte order of the sender. The control sequence (five bits of data: "10000," "00000," "00000," "00000," "01110") is used to adjust the synchronization state. This process is completed after approximately six cycles, and the data is then output in the order of the alignment sequence.

[0092] Step S600: The receiving end reselects the bond sequence or modifies the bondi control sequence code to control the arrangement of the parallel output byte order within the Lane.

[0093] By modifying the bond sequence or control sequence, you can adjust the byte output order at the receiver to achieve byte alignment for different needs. By leveraging precise timing control triggered by commadet signals and selecting the bond sequence, you can fine-tune output latency to ensure accurate data synchronization. Figure 7 The figure shows a schematic diagram of the bond sequence change order proposed in an embodiment of the present application. In the figure, the alignment sequence d2-d5 is offset by 2 bytes relative to the TX end. After the RX end undergoes the alignment process, the final byte output order is offset by 2 bytes.

[0094] In one possible implementation, the method further includes:

[0095] The transmitter uses the commadet control signal to trigger the bond control code sequence and selects the bond sequence to adjust the output delay of the receiver.

[0096] Use command to trigger the bond control timing. By selecting the bond sequence, you can fine-tune the RX output delay. Figure 8 The diagram shows the byte order fine-tuning delay proposed in the embodiment of the present application. The bond sequence of RX is one user clock later than that of RX1, and the final aligned output sequence is one clock earlier than that of RX1. If the bond sequence is offset relative to the position of the data at the transmitting end (e.g., 2 bytes), then after the alignment process, the output sequence of the receiving end will also reflect this offset, that is, the final output will be offset by 2 bytes compared to the original transmission. The bond sequence control at the RX end starts one user clock later than RX1 (assuming it is the reference lane), but after alignment, its output can be aligned one clock cycle earlier, reflecting the fine-tuning capability of this mechanism.

[0097] In addition, a single lane is used for bond to achieve low-latency byte-ordered output.

[0098] Figure 9 A schematic diagram of 8-lane JESD204B data channel initialization alignment sequence ILAS data received by the ultra-low latency universal simplex transmission method of an embodiment of the present application is shown. The bond sequence is "KKKR" (K is comma, output X"bc", R is a multi-frame alignment K code, and output X"1c"). The transmission of "10000", "00000", "00000", "00000", and "01110" after the bond control sequence is earlier than the time when any channel outputs "R". After 6 cycles, the padding code X"14131211" in ILAS is synchronously output, and the outputs of different AD channels are also aligned.

[0099] To achieve the stable low-latency performance of this patented JESD204B interface, the addition and subtraction functions and the online frame and multi-frame alignment verification functions must be removed. Maintaining long-term link stability under these conditions requires additional measures. Because 64b / 66b, 64b / 67b, and 128b / 130b encodings must use addition and subtraction during transmission and cannot be hard-aligned between lanes, only the adaptive reset and coarse buffer alignment methods described in this patent are effective and cannot significantly reduce propagation delay.

[0100] In one possible implementation, the ultra-low-latency universal simplex transmission method proposed in this application is applied to high-speed data transmission (X4 mode) over hundreds of optical fibers in a specific project. The transmit and receive delays are controlled within 24 to 25 processing clocks, while the traditional Aurora protocol typically has a latency that varies randomly within 70 to 100 processing clocks. In comparison, the ultra-low-latency universal simplex transmission method proposed in this application significantly improves the real-time and stability of the timing.

[0101] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0102] Custom control protocols and standard protocol applications: Compatibility with custom control protocols provides a high degree of flexibility, allowing data transmission methods to be tailored to specific needs. It is also compatible with widely used standard protocols such as JESD204B and Gigabit Ethernet. JESD204B is a high-performance serial interface standard commonly used for communication between high-speed data converters and logic devices, while Gigabit Ethernet is a high-speed transmission protocol commonly used in network communications. Both require efficient and precise data transmission mechanisms.

[0103] Multi-Lane Data Transmission and Test Methodology: In a multi-lane configuration, data is split and transmitted in parallel across multiple lanes to increase total bandwidth. High-speed optical and LVDS (Low Voltage Differential Signaling) electrical interfaces are utilized, facilitating performance evaluation at different physical layers. The shortest measured transmit / receive latency is 24 USERCLK2 cycles, representing the time required for data to be transmitted and received. USERCLK typically refers to the user clock frequency, which serves as the basis for data transmission synchronization.

[0104] Byte order and latency jitter issues: When the transmit and receive latency is set to 24 clock cycles, there is approximately a 10% probability of byte order errors and latency jitter. This indicates that under this configuration, the system may occasionally fail to accurately reconstruct the original data sequence, or that latency fluctuates between packets. Increasing the latency to 25 clock cycles eliminates the issues, indicating that the system requires additional time to stabilize data processing and ensure data integrity and timing accuracy.

[0105] The relationship between clock frequency and transmission rate: When the high-speed transmission rate is 10 Gbps and the user clock frequency is 250 MHz, the transmit and receive latency is stable at 100 ns. Reducing latency requires increasing the user clock frequency, which directly increases the transmission rate. This is because a higher clock frequency allows for faster data processing, reducing data waiting time in the system and, in turn, lowering latency.

[0106] This application takes into account the common challenges in high-speed data transmission, and achieves support for multiple protocols and performance improvements by adjusting latency and optimizing clock frequency.

[0107] A possible implementation of an ultra-low-latency universal simplex transmission system is provided below. The system is used to execute the various execution steps and corresponding technical effects of the ultra-low-latency universal simplex transmission method shown in the above embodiments and possible implementations. The system includes a controlled slave alignment receiving end and a transmitting end using an unbuffered TX slave synchronous transmission architecture. The method includes:

[0108] The transmitter uses the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels;

[0109] All lanes are configured in unbuffered slave synchronization mode. After power-on reset, a state machine is used to manually control the internal delay, phase initialization, and transmit phase alignment mechanisms within the lanes to eliminate inter-lane skew of transmitted data. Transmitted data contains a continuous comma sequence, which is used by the receiving end to determine the received byte boundary. Each lane sends the data comma sequence and then sends the same byte or byte sequence for lane alignment.

[0110] The receiving end is used to reset based on the continuous comma sequence received by the Lane channel, and return to the initial state when a non-comma sequence is received after the reset;

[0111] Set all lanes as slave lanes in chanel-bond mode, and select the same 4-byte string after the consecutive comma sequence as the bond sequence alignment recognition sequence;

[0112] When the commadet control signal is detected to be converted from high level to low level, a control sequence is sent to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the transmitting end;

[0113] Reselect the bond sequence or modify the bondi control sequence code to control the order of the parallel output bytes within the Lane.

[0114] In a possible embodiment, the receiving end is further configured to: receive a continuous comma sequence through the receiving end, start a reset state machine to count and obtain a comma sequence count value;

[0115] When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state;

[0116] When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

[0117] In a possible embodiment, the receiving end is further configured to:

[0118] The self-state machine of the elastic buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all lanes in the receiving channel become high.

[0119] In a possible embodiment, the clock management component adopts MMCM, PLL or BUFG.

[0120] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An ultra-low-latency universal simplex transmission method based on 8b / 10b encoding, characterized in that: The method is applied to an ultra-low-latency universal simplex transmission system, the system including a controlled slave-aligned receiving end and a transmitting end using a bufferless TX slave synchronous transmission architecture, and the method includes: The transmitter uses the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels; The transmitter configures all lanes in unbuffered slave synchronization mode. After power-on reset, a state machine is used to manually control the internal delay, phase initialization, and transmit phase alignment mechanisms within the channel lanes to eliminate skew between transmitted data lanes. Transmitted data contains continuous comma sequences, which the receiver uses to determine received byte boundaries. Each lane sends the data comma sequence and then sends the same byte or byte sequence for lane alignment. The receiving end resets by receiving a continuous comma sequence based on the Lane channel, and returns to the initial state when a non-comma sequence is received after the reset; The receiving end sets all lanes as slave lanes in chanel-bond mode and selects the same 4-byte string after the consecutive comma sequences as the bond sequence alignment identification sequence; When the receiving end detects that the commadet control signal changes from high level to low level, it sends a control sequence to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the sending end; The receiving end reselects the bond sequence or modifies the bondi control sequence code to control the order of the parallel output bytes within the lane.

2. The ultra-low delay universal simplex transmission method according to claim 1, wherein: The steps of resetting the receiving end by receiving a continuous comma sequence based on a Lane channel and returning to the initial state when receiving a non-comma sequence after the reset include: The receiving end receives a continuous comma sequence and starts the reset state machine to count and obtain the comma sequence count value; When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state; When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

3. The ultra-low delay universal simplex transmission method according to claim 2, wherein: The steps after the state machine is reset and enters the reset state include: The self-state machine using flexible buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all lanes in the receiving channel become high.

4. The ultra-low delay universal simplex transmission method according to claim 1, wherein: The clock management component uses MMCM, PLL or BUFG.

5. An ultra-low latency universal simplex transmission system based on 8b / 10b encoding, characterized in that: The system includes a controlled slave alignment receiving end and a transmitting end adopting a bufferless TX slave synchronous transmission architecture. The transmitter uses the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels; All lanes are configured in unbuffered slave synchronization mode. After power-on reset, a state machine is used to manually control the internal delay, phase initialization, and transmit phase alignment mechanisms within the lanes to eliminate inter-lane skew of transmitted data. Transmitted data contains a continuous comma sequence, which is used by the receiving end to determine the received byte boundary. Each lane sends the data comma sequence and then sends the same byte or byte sequence for lane alignment. The receiving end is used to reset based on the continuous comma sequence received by the Lane channel, and return to the initial state when a non-comma sequence is received after the reset; Set all lanes as slave lanes in chanel-bond mode, and select the same 4-byte string after the consecutive comma sequence as the bond sequence alignment recognition sequence; When the commadet control signal is detected to be converted from high level to low level, a control sequence is sent to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the transmitting end; Reselect the bond sequence or modify the bondi control sequence code to control the order of the parallel output bytes within the Lane.

6. The ultra-low delay universal simplex transmission system according to claim 5, wherein: The receiving end is further configured to: receive a continuous comma sequence through the receiving end, start a reset state machine to count, and obtain a comma sequence count value; When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state; When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

7. The ultra-low delay universal simplex transmission system according to claim 6, wherein: The receiving end is also used to: The self-state machine of the elastic buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all lanes in the receiving channel become high.

8. The ultra-low delay universal simplex transmission system according to claim 5, wherein: The clock management component uses MMCM, PLL or BUFG.

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