Access optimized partial cache avalanche

Abstract

Aspects of the present disclosure relate to systems and methods for improving performance of a processing device for partially cached avalanche. Certain embodiments provide a method for performing a partial cache avalanche procedure, the method comprising: counting, in each cache channel of a set of cache channels, a number of dirty cache lines having dirty bits indicating that the cache line has been modified; selecting at least one cache channel from the group for avalanche based on the number of corresponding dirty cache lines of the at least one cache channel; and performing the partially cached avalanche procedure based on selecting the at least one cache channel for an avalanche from the group.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 806,291, filed on June 10, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated by reference in its entirety, as if fully set forth below and for all applicable purposes. Background Art Technical Field

[0003] Aspects of the present disclosure relate to memory devices, and in particular, to systems and methods for improving the performance of partial cache avalanche procedures.

[0004] Related technologies

[0005] Typically, main memory in a computing system may use random access memory (RAM) devices as a volatile memory source. RAM is particularly useful as a memory due to its density and speed. One of the disadvantages is that RAM may occasionally experience errors due to, for example, neutrons or alpha particles passing through the die, faulty components, inaccurate system timing, etc. This disadvantage may be particularly problematic for computing systems that convey critical data or require data that is nearly error-free.

[0006] For this reason, a computer system may include an error correction device that generates and stores one or more error correction code (ECC) bits corresponding to the data stored in the RAM. Here, when the stored data is read from the main memory, the associated ECC bits are also read out and sent to the error correction device for proper evaluation and, if necessary, error correction. In some RAM devices, the ECC bits are stored "inline" with the corresponding data. In one example, for every 512 bits of payload data stored in the RAM device, there are associated ECC bits stored in the same DRAM in another location (address) different from the payload data.

[0007] However, in order to perform certain memory functions (e.g., partial data writes), the RAM area storing data and its corresponding ECC bits must be initialized to matching values. For example, an application or processor may need to perform a process for initializing the area by writing zeros into the RAM area storing both data and ECC bits. However, such a process may require a relatively large amount of time and power. In one example, this may cause problems for battery-powered RAM devices. As RAM devices are increasingly utilized, there is a need for further improvements to such devices. Summary of the invention

[0008] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desired characteristics. Without limiting the scope of the present disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and especially after reading the section entitled "Detailed Description," it will be understood how the features of the present disclosure provide advantages.

[0009] Certain embodiments provide a method for performing a partial cache avalanche procedure. The method generally includes: counting the number of dirty cache lines having a dirty bit indicating that the cache line has been modified in each cache way in a group of cache ways; selecting at least one cache way from the group for avalanche based on the number of cache lines that meet eviction criteria corresponding to the at least one cache way; and performing the partial cache avalanche procedure based on selecting the at least one cache way from the group for avalanche.

[0010] The following description and the associated drawings set forth in detail certain illustrative features of one or more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings depict certain aspects of the one or more embodiments and therefore are not to be considered limiting of the scope of the present disclosure.

[0012] Figure 1 Example components and interconnections in a system on a chip (SoC) coupled to a memory that may be suitable for implementing various aspects of the present disclosure are illustrated.

[0013] Figure 2 is a schematic diagram illustrating partial cache avalanche in an example cache according to aspects of the present disclosure.

[0014] Figure 3A and Figure 3B An example diagram illustrating a performance-aware partial cache avalanche procedure according to aspects of the present disclosure.

[0015] Figure 4A and Figure 4B The example allocates cache lines that meet non-eviction criteria from a selected way to a non-selected way according to aspects of the present disclosure.

[0016] Figure 5 is a graph of memory access latency for various levels of memory.

[0017] Figure 6 is a flow diagram illustrating example operations for performing a partial cache avalanche procedure in accordance with aspects of the present disclosure.

[0018] Figure 7A processing system is illustrated that may include various components (eg, corresponding to means-plus-function components) configured to perform operations for the techniques disclosed herein.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0020] Aspects of the present disclosure provide methods and apparatus for improving the performance of a processing device to partial buffer avalanche.

[0021] In a device that performs computer processing (e.g., a computer, a smartphone, a system on a chip (SoC), etc.), a cache memory is a supplemental memory system that temporarily stores frequently used instructions and data for faster processing by the device's processor (e.g., a central processing unit (CPU)). Using cache memory can reduce the average time and / or energy used by the processor to access data compared to the processor accessing the data from the device's main memory. In other words, when data is found in cache memory (in what is known as a cache hit), accessing the data is much faster than retrieving the data from main memory. The number of searches that result in a cache hit relative to the total number of searches is known as the cache hit rate.

[0022] Some devices may be configured to perform partial cache avalanche, which generally refers to a mechanism for saving power by selectively applying power to a portion of a shared cache (power gating). Processors based on the Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) architecture are examples of devices that can perform a partial cache avalanche procedure. When a device performs a partial cache avalanche procedure, the avalanched portion of the cache is typically checked for cache lines in which a dirty bit (i.e., a bit indicating whether the corresponding cache line has been updated) is set. That is, in order to capture updated data, each dirty line of the channel being avalanched is written to main memory, and the channel is avalanched (i.e., the channel is power gated).

[0023] In a conventional partial cache avalanche procedure, the selection of the channel being avalanched and the writing of dirty cache lines to main memory is performed without regard to how recent the avalanche cache lines are relative to the other cache channels. Therefore, without regard to the eviction policy (the policy applied to decide which cache entries to remove and which to keep), the number of main memory accesses during an avalanche is typically equal to the number of dirty lines in the avalanche channel. Unfortunately, this typically results in an increase in the number of memory accesses, a potential increase in cache miss rates, and a loss in performance.

[0024] However, aspects of the present disclosure provide techniques that can lead to improvements in partial cache avalanche procedures. For example, by considering the recency of an avalanche cache line relative to other cache ways, the number of memory accesses can be reduced and the cache miss rate can be reduced, resulting in a corresponding improvement in performance.

[0025] Memory System Overview

[0026] The following description provides examples, but does not limit the scope, applicability or implementation scheme set forth in the claims. Without departing from the scope of the present disclosure, the functions and arrangements of the elements discussed may be changed. Each example may ignore, replace or add each procedure or component as appropriate. For example, the method described may be performed in a different order than that described, and various steps may be added, omitted or combined. In addition, the features described for some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functionality, or structure and functionality that are supplemented or substituted for the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims.

[0027] Although certain teachings of the present disclosure are exemplified with dynamic random access memory (DRAM) devices as example memory devices, the teachings are applicable to other fields, such as to other volatile memory devices (e.g., static RAM (SRAM), synchronous SRAM (SDRAM), Rambus DRAM (RDRAM), etc.). In addition, although certain teachings of the present disclosure are exemplified with system on chip (SoC), the teachings are applicable to any suitable computing device that utilizes memory. Therefore, the disclosed teachings should not be interpreted as limited to DRAM devices or SoCs or the illustrated embodiments. The illustrated embodiments are merely vehicles for describing and illustrating examples of the inventive teachings disclosed herein.

[0028] Figure 1Example components and interconnects in a system on chip (SoC) 100 coupled to a volatile memory 124 (e.g., DRAM) that may be suitable for implementing various aspects of the present disclosure are illustrated. The SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. The processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.) so that the processors may operate at a much higher frequency / clock rate than would be possible if the signals were propagated off-chip. The proximity of the cores may also allow for sharing of on-chip memory and resources (e.g., voltage rails), as well as allowing for more coordinated collaboration between the cores.

[0029] Processors 102, 104, 106, 108 may be interconnected to memory controller 114 and other system components (not shown) via an interconnect / bus module 122, which may include an array of reconfigurable logic gates and / or implement a bus architecture (e.g., CoreConnect, Advanced Microcontroller Bus Architecture (AMBA), etc.) Communications may also be provided by advanced interconnects such as a high-performance network-on-chip (NoC).

[0030] The memory controller 114 may include a dedicated hardware module configured to receive various memory transactions from one or more master devices and address and communicate the memory transactions to the memory 124. The multiple master devices may include one or more of the processors 102, 104, 106, 108 and / or applications operating on the processors 102, 104, 106, 108. The memory controller 114 may also manage the maintenance of the memory 124, such as scheduling and / or initiating refresh cycles, and clearing content (e.g., data and / or code) commands as described herein. In some examples, the memory controller 114 may include one or more processors configured to perform the operations disclosed herein. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform various functionalities described throughout the present disclosure. Memory 124 and memory controller 114 may be on-chip components of SoC 100 (eg, on a substrate, die, integrated chip, etc.); however, it should be noted that in some examples, one or more of memory 124 and memory controller 114 may be located off-chip.

[0031] Memory 124 is a computer-readable storage medium having an interface to processors 102, 104, 106, 108 via bus module 122. As discussed, memory 124 can be an on-chip component, or alternatively (as shown) an off-chip component. Memory 124 can provide volatile storage, such as DRAM, for processors 102, 104, 106, 108 and / or other functional aspects of SoC 100. As shown, memory controller 114 includes ECC module 130. ECC module 130 is configured to implement ECC logic for detecting and correcting errors in memory 124, as discussed and known in the art. In some aspects, ECC module 130 is configured to perform inline ECC logic.

[0032] The memory 124 may also include a hierarchy of one or more rows 134 and multiple libraries 132a to 132j ​​(collectively referred to as libraries 132) in each row 134. For example, the memory 124 may include multiple rows, each of which contains multiple internal library structures. In some examples, each library structure may include multiple memory pages or "rows". In general, a row of memory can be accessed at each library at a given time. Each library in the library 132 of a given row 134 can share a bus (not shown) for reading / writing data. The memory controller 114 can support simultaneous operation of different rows 134 and libraries 132 that can be accessed independently. Because each library 132 acts as an independent entity, the library 132 can serve multiple memory requests in parallel, thereby providing library-level parallelism.

[0033] Overview of cache architecture with partial cache avalanche

[0034] Figure 2 is a diagram illustrating an example cache architecture 200 that may be configured with a conventional partial cache avalanche procedure. The cache architecture 200 may be included in the memory controller 114 of the SoC 100, or may be built into any of the CPU 102, the modem processor 104, the GPU 106, or the application processor 108, all of which are Figure 1 2. Cache 200 includes a cache controller 202 and a cache memory 220. Cache memory 220 stores cache lines, where each cache line includes a cache tag (shown at 222), a validity bit (shown at 224), a dirty bit (shown at 226), and data (shown at 228). The cache tag in each cache line indicates which memory location in the main memory the cache line was copied from. The valid bit indicates whether the cache line has been loaded with valid data.

[0035] During operation of the cache, a processor core (e.g., any of the CPU 102, modem processor 104, GPU 106, or application processor 108) issues a memory address 210 of a memory that the processor core needs to access for reading or writing. In the example cache, the cache controller compares the tag portion 212 of the memory address with the cache tag (shown at 222) of the cache line stored in the cache memory. If the cache controller finds that the tag portion matches the cache tag in the cache memory, a cache hit has occurred. However, if the cache controller does not find a cache tag in the cache memory that matches the tag portion, a cache miss has occurred. In the case of a cache hit, the cache controller immediately reads or writes the data of the corresponding cache line. In the case of a processor core issuing a read of a memory location, the cache controller delivers the data of the corresponding cache line to the processor core via the data bus 230. For the case of a cache miss, the cache controller allocates a new cache line in the cache memory and copies the data from the main memory into the new cache line, and then satisfies the request from the processor core from the contents of the new cache line.

[0036] The example cache is a four-channel cache, and therefore each main memory location corresponds to a location in each of the four channels 240, and the data of any particular main memory location can be stored in a corresponding location in each of the four channels. Each of the four cache memory locations in which the data of the main memory location can be stored (i.e., a cache memory location in each channel) can be referred to as a member in a cache memory location set, and each such set has a corresponding set index. Each channel has a corresponding channel mask 270. When a cache miss occurs, the cache controller attempts to allocate a new cache line in a currently unused location in the cache memory. Therefore, in the example four-channel cache, when the cache controller is allocating a new cache line, the cache controller checks up to four locations (one location in each channel) to determine whether any location is unused. If there is no unused location, the cache controller consults the eviction policy 260 to determine which of the four locations can have its current data evicted so that a new cache line can be allocated.

[0037] When a device including the example cache determines to perform a partial cache avalanche, one of the four channels is selected for power gating. The cache controller executes corresponding channel avalanche logic (shown at 280) when avalanching the selected channel. Each of the channel avalanche logic includes executing sequential dirty line search logic 250, which searches the selected channel for cache lines marked as dirty (i.e., cache lines for which the dirty bit 226 is set) and writes those cache lines to their corresponding main memory locations, which are known from the cache tags of the cache lines.

[0038] As previously described, in a conventional partial cache avalanche procedure, the selection of the channel being avalanched and the writing of dirty cache lines to main memory is performed without regard to how recent the avalanched cache line is relative to the other cache channels. Therefore, without regard to the eviction policy (the policy applied to decide which cache entries to remove and which to keep), the number of main memory accesses at the time of avalanche is typically equal to the number of dirty lines in the avalanche channel. Unfortunately, this typically results in an increase in the number of memory accesses, a potential increase in cache miss rates, and a loss of performance.

[0039] Example Technique for Partial Cache Avalanche for Access Optimization

[0040] However, aspects of the present disclosure provide techniques that can lead to improved partial cache avalanche procedures, for example, by considering how recent the avalanched cache line is relative to other cache ways.

[0041] The partial avalanche mechanism described in this article can help optimize the performance of the partial cache avalanche procedure by reducing the number of memory accesses and cache miss rate, resulting in a corresponding improvement in performance.

[0042] The operations performed during the performance-aware partial cache avalanche procedure proposed herein may be referred to herein as sequential channel processing. Figure 3A As shown, a cache architecture 300 configured to perform the access optimized partial cache avalanche procedure proposed herein may include cache line swap logic 350 including sequential search logic, details of which are described below.

[0043] This sequential pass processing can be initiated when certain avalanche criteria are met. If such avalanche criteria are not met, the cache can behave as a regular cache (e.g., without sequential pass processing logic). Depending on the specific implementation, the avalanche criteria can be based on the number of active cores or based on a dedicated request by a core or software for a partial cache avalanche.

[0044] If the avalanche criteria are met, then sequential channel processing logic and additional hardware (e.g. Figure 3A Logic 350) can activate and implement the selected avalanche strategy.

[0045] In some cases, the cache architecture 300 may include logic 380 configured to count the number of dirty cache lines. As illustrated, a dirty cache line may be indicated by a dirty status bit that, when set, indicates that the cache line has been modified. As illustrated, the logic 380 may include a "dirty bit" counter for each channel to count the number of dirty cache lines for a given channel. In some cases, similar counters may be used to count cache lines that meet other criteria, such as least recently used (LRU). In such cases, these other counters (e.g., LRU counters) may be used in combination with the dirty bit counter to determine the best channel to avalanche.

[0046] The techniques described herein can be applied in a memory system regardless of the actual cache eviction policy 360 in each cache way in a set of cache ways. Any suitable deterministic cache eviction policy can be used. For example, a deterministic cache eviction policy can specify that the least recently used (LRU) or least frequently used (LFU) cache line is evicted.

[0047] The cache controller may then select at least one cache way from the group for avalanche based on the number of cache lines corresponding to the at least one cache way that meet the eviction criteria (and perform a partial cache avalanche procedure based on selecting the at least one cache way from the group for avalanche).

[0048] exist Figure 3B In the example shown, for example, because channel 0 has the least number of dirty cache lines, that channel is selected for avalanche. As described above, in some cases, other factors may be considered in conjunction with the number of dirty cache lines, such as the number of LRU cache lines in a given channel. In some cases, if there is a tie in the number of dirty cache lines, such other counters may be used to break the tie and determine which channel is selected for avalanche.

[0049] The logic 350 may then sequentially check the selected avalanche cache way (or ways) for cache lines with a set dirty bit or for a most recently used (MRU) cache line, indicating that such cache line is temporally significant (and has been recently accessed and / or modified). Once such a cache line is found, the cache line may be retained by swapping it with a non-dirty and / or non-MRU cache line from a non-avalanche way in the same set. In other words, a non-dirty and / or non-MRU line from a non-avalanche way may be evicted and replaced with a dirty and / or MRU cache line from an avalanche way.

[0050] This approach can reduce the number of memory (e.g., DDR) writes performed during a partial cache avalanche, thereby reducing the time spent on channel avalanche preparation, and can also improve cache hit rates by retaining temporally important cache lines because recency is taken into account.

[0051] You can refer to Figure 4A and Figure 4B To understand this method. Figure 4A As shown, the channel selected for avalanche (e.g., from Figure 3B Channel 0) may have one or more dirty and / or MRU cache lines 410 (meaning they have been modified and / or accessed relatively recently), while channels not selected for avalanche may have one or more non-dirty and / or non-MRU cache lines 420 (meaning they have not been changed or accessed relatively recently).

[0052] like Figure 4B As illustrated, non-dirty / non-MRU cache lines 420 from non-avalanche channels may be evicted and replaced by dirty / MRU cache lines 410 from avalanche channels. In other words, evicted non-dirty / non-MRU cache lines 420 from non-avalanche channels are assigned to dirty / MRU cache lines 410 from avalanche channels. As described above, this method can reduce the number of memory accesses and reduce cache miss rates by retaining cache lines that are important in time.

[0053] Although the above example considers avalanches of a single channel, in some cases it may be necessary (or desirable) to avalanche more than one channel (e.g., N channels). In such cases, the techniques described above may be performed to select the N channels with the fewest dirty cache lines, and these channels may be excluded from the swap operation from the first channel avalanche.

[0054] The performance-aware partial avalanche procedure described herein can have many benefits. For example, selecting the channel (or channels) with the least dirty cache lines for avalanche can reduce the number of immediate memory (e.g., DDR) transactions during avalanche. An avalanche strategy for evicting available non-dirty cache lines from active channels instead of evicting dirty lines from avalanche channels can avoid immediate transactions. An avalanche strategy for retaining MRU lines (or at least temporally important cache lines) according to an implemented cache eviction strategy can help reduce potential DDR transactions by improving cache hit rates.

[0055] Considering example memory access latencies for different memory levels, potential performance improvements can be seen. Figure 5As illustrated, the latency of memory accesses to DDR memory (510) may average 128 CPU cycles per memory access, the latency of memory accesses to level 3 (L3) cache (520) may average 26 CPU cycles per memory access, the latency of memory accesses to level 2 (L2) cache (530) may average 7 CPU cycles per memory access, and the latency of memory accesses to level 1 (L1) cache (540) may average 2 CPU cycles per memory access. Given these example values, increasing cache hit rates using the performance-aware partial avalanche procedure described herein may help avoid a potential ~5X time penalty for DDR accesses during an avalanche.

[0056] The sequential processing for the performance-aware partial avalanche procedure described herein may take a certain amount of time, for example, to complete the reference Figure 4A and Figure 4B In some cases, if a read or write request (to L3) arrives during this time, sequential processing may be suspended until the request is serviced.

[0057] Aspects of the present disclosure can help reduce power consumption by reducing memory access activity, especially in high data traffic usage scenarios, such as audio / video playback. As described herein, minimizing DDR traffic can help achieve partial cache avalanche power savings. The power savings may be sensitive to the pattern of addresses accessed. Ideally, partial avalanche procedures can be accelerated by improving cache hit rates, thereby reducing immediate and potential DDR traffic, resulting in power savings.

[0058] In some cases, all channels (including the channel being considered for avalanche) can remain visible to reads. If a read request is for an index that has already been processed and results in a cache hit on a cache line in one of the channels that was not selected for partial avalanche, then the index may not need to be processed. On the other hand, if the read request hits the avalanche channel, then the index can be reprocessed.

[0059] In some cases, sequential processing can be suspended when a write request arrives. Therefore, the write request can essentially see the L3 cache with only non-avalanche channels active. In other words, the channel being considered for avalanche may not be visible to the write. If a write is to an already processed index, then because the write request evicts one of the non-avalanche channels, the evicted line can be written back to the DDR (if dirty) or swapped with the avalanche channel line (for example, if the avalanche line is non-dirty, depending on which one is prioritized). Writes to unprocessed indexes can be processed like normal L3 writes, where all channels are visible.

[0060] In some cases, the avalanche strategy can use information about speculative business to initiate sequential processing with the help of the selected avalanche strategy with the help of existing logic (such as address mode detection, random address mode detector and pre-fetch block address). In such cases, it is possible to create an address access pattern that can keep the sequential processing stopped or repeatedly process the same INDEX. In order to avoid such locks, timer-based sequential processing cancellation can be implemented. As an alternative, a limit on the number of scans for sequential processing can be set. In such cases, if the timer expires or the scan limit is met, the avalanche processing can be suspended because this can indicate that the traffic business is high, or the L3 transaction can be suspended to complete the avalanche processing.

[0061] Example Method

[0062] Figure 6 is a flow diagram illustrating example operations 600 for performing a partial cache avalanche procedure in accordance with certain aspects of the present disclosure. For example, Figure 6 The steps of the operation may be performed by a memory controller (e.g., Figure 1 The memory controller 114) or another suitable circuit may be used to perform the above operation.

[0063] Operations 600 begin at step 605 by counting, in each cache way in a set of cache ways, a number of dirty cache lines having a dirty bit indicating that the cache line has been modified.

[0064] Operation 600 may continue at step 610 by selecting at least one cache way from the group for avalanche based on a number of corresponding dirty cache lines of the at least one cache way.

[0065] Operations 600 may continue at step 615 by performing a partial cache avalanche procedure based on selecting at least one cache way from the group for avalanche.

[0066] In certain aspects, the operations 600 include determining that one or more avalanche criteria are satisfied prior to executing the partial cache avalanche procedure.

[0067] In certain aspects, the avalanche criteria is based on at least one of a number of active cores or a request for partial cache avalanche.

[0068] In certain aspects, performing the partial cache avalanche procedure includes replacing cache lines from cache ways of the group that were not selected for avalanche with cache lines of the cache ways selected for avalanche from the group.

[0069] In certain aspects, replacing includes: evicting cache lines of cache ways not selected for avalanche; and assigning the evicted cache lines to cache lines of cache ways selected from the group for avalanche.

[0070] In certain aspects, the evicted cache line comprises at least one of a non-dirty cache line or a non-recently used (non-MRU) cache line; and the cache line selected from the set of cache ways for avalanche comprises at least one of a dirty cache line or a MRU cache line.

[0071] In some aspects, selecting at least one cache way from the set for avalanche includes selecting a cache way having a lowest number of dirty cache lines for avalanche.

[0072] In some aspects, selecting at least one cache way from the set for avalanche includes selecting a plurality of cache ways having a lowest number of dirty cache lines.

[0073] In certain aspects, performing the partial avalanche procedure includes excluding cache lines of a plurality of cache ways that meet eviction criteria from replacement operations.

[0074] Figure 7 700 is illustrated, and the processing system may include a processor configured to perform operations for the techniques disclosed herein (such as in Figure 6 The processing system 700 includes a processor 704 coupled to a computer-readable medium / memory 712 via a bus 706. In some aspects, the computer-readable medium / memory 712 is configured to store programs that, when executed by the processor 704, cause the processor 704 to perform Figure 6 Instructions (e.g., computer executable code) for performing the operations illustrated in or other operations discussed herein for performing various techniques for performing partial cache avalanche.

[0075] In some aspects, the computer-readable medium / memory 712 stores code 714 for counting, in each cache way in a group of cache ways, a number of dirty cache lines having a dirty bit indicating that the cache line has been modified; code 716 for selecting at least one cache way from the group for avalanche based on the number of corresponding dirty cache lines of at least one cache way; and code 717 for performing a partial cache avalanche procedure based on selecting at least one cache way from the group for avalanche.

[0076] In some aspects, the processor 704 has circuitry configured to implement code stored in the computer-readable medium / memory 712. The processor 704 includes circuitry 720 for counting, in each cache way in a group of cache ways, a number of dirty cache lines having a dirty bit indicating that the cache line has been modified; circuitry 722 for selecting at least one cache way from the group for avalanche based on the number of corresponding dirty cache lines of the at least one cache way; and circuitry 724 for performing a partial cache avalanche procedure based on selecting the at least one cache way from the group for avalanche.

[0077] Sample Clauses

[0078] Specific implementation examples are described in the following numbered clauses:

[0079] Item 1: A method for performing a partial cache avalanche procedure, the method comprising: counting the number of dirty cache lines having a dirty bit indicating that the cache line has been modified in each cache way in a group of cache ways; selecting at least one cache way from the group for avalanche based on the number of dirty cache lines corresponding to the at least one cache way; and performing the partial cache avalanche procedure based on selecting the at least one cache way from the group for avalanche.

[0080] Clause 2: The method of clause 1, further comprising determining that one or more avalanche criteria are satisfied prior to executing the partial cache avalanche procedure.

[0081] Clause 3: The method of clause 2, wherein the avalanche criteria is based on at least one of a number of active cores or a request for partial cache avalanche.

[0082] Clause 4: The method of clause 1, wherein performing the partial cache avalanche procedure comprises replacing cache lines from cache ways in the group that are not selected for avalanche with cache lines of the cache ways selected for avalanche from the group.

[0083] Clause 5: The method of clause 4, wherein the replacing comprises: evicting the cache lines of the cache ways not selected for avalanche; and assigning the evicted cache lines to the cache lines of the cache ways selected from the group for avalanche.

[0084] Clause 6: A method according to clause 5, wherein: the evicted cache line includes at least one of a non-dirty cache line or a non-recently used (non-MRU) cache line; and the cache line of the cache channel selected from the group for avalanche includes at least one of a dirty cache line or an MRU cache line.

[0085] Clause 7: The method of clause 1, wherein selecting at least one cache way from the set for avalanche comprises selecting a cache way having a lowest number of dirty cache lines for avalanche.

[0086] Clause 8: The method of clause 1, wherein selecting at least one cache way from the set for avalanche comprises selecting a plurality of cache ways having a lowest number of dirty cache lines.

[0087] Clause 9: An apparatus comprising: a memory including executable instructions; and a processor configured to execute the executable instructions and cause the apparatus to perform the method according to any one of clauses 1 to 8.

[0088] Clause 10: An apparatus comprising means for performing the method according to any one of clauses 1 to 8.

[0089] Clause 11: A non-transitory computer readable medium comprising executable instructions which, when executed by a processor of an apparatus, cause the apparatus to perform the method of any one of clauses 1 to 8.

[0090] Clause 12: A computer program product embodied on a computer readable storage medium, the computer program product comprising code for performing the method according to any one of clauses 1 to 8.

[0091] Additional Information

[0092] The previous description is provided to enable any person skilled in the art to practice the various embodiments described herein. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the universal principles defined herein can be applied to other embodiments. For example, without departing from the scope of the present disclosure, the function and arrangement of the elements discussed may be changed. Each example may ignore, replace or add each procedure or component as appropriate. In addition, the features described for some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functionality, or structure and functionality that are supplemented or substituted for the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims.

[0093] As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0094] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0095] As used herein, the term "determine" encompasses a wide variety of actions. For example, "determine" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), ascertaining, and the like. Furthermore, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Additionally, "determine" may include resolving, selecting, choosing, establishing, and the like.

[0096] The method disclosed herein includes one or more steps or actions for implementing the method. The steps and / or actions of the method can be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions can be modified without departing from the scope of the claims. In addition, the various operations of the method described above can be performed by any appropriate component that can perform the corresponding function. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Typically, in the case of operations illustrated in the accompanying drawings, those operations may have corresponding corresponding components with similar numbers plus functional components.

[0097] The various illustrative logical blocks, modules, and circuits described in conjunction with the present disclosure may be implemented or executed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0098] The processing system can be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus can include any number of interconnecting buses and bridges. The bus can link various circuits together, including processors, machine-readable media, and input / output devices, etc. A user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) can also be coupled to the bus. The bus can also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further. The processor can be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuits that can execute software. Those skilled in the art will recognize how to best implement the functionality of the processing system depending on the specific application and the overall design constraints imposed on the entire system.

[0099] If implemented in software, each function can be stored on or sent through a computer-readable medium as one or more computer-executable instructions or codes. Software should be broadly interpreted as meaning instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or other. Computer-readable media include both computer storage media and communication media, such as any medium that facilitates the transfer of computer programs from one place to another. The processor may be responsible for managing the bus and general processing, including executing software modules stored on a computer-readable storage medium. A computer-readable storage medium may be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative solution, the storage medium may be integral with the processor. By way of example, a computer-readable medium may include a transmission line, a carrier modulated by data, and / or a computer-readable storage medium having instructions stored thereon that is separated from a wireless node, all of which may be accessed by a processor through a bus interface. Alternatively or in addition thereto, a computer-readable medium or any part thereof may be integrated into a processor, such as in the case of having a cache and / or a general register stack. By way of example, examples of machine-readable storage media may include RAM (random access memory), flash memory, ROM (read only memory), PROM (programmable read only memory), EPROM (erasable programmable read only memory), EEPROM (electrically erasable programmable read only memory), registers, magnetic disks, optical disks, hard drives, or any other suitable storage media, or any combination thereof. The machine-readable medium may be embodied in a computer program product.

[0100] A software module may include a single instruction, perhaps multiple instructions, and may be distributed over several different code segments, between different programs, and across multiple storage media. A computer-readable medium may include multiple software modules. A software module includes instructions that, when executed by a device such as a processor, cause a processing system to perform various functions. A software module may include a sending module and a receiving module. Each software module may reside in a single storage device or may be distributed across multiple storage devices. By way of example, when a triggering event occurs, a software module may be loaded from a hard drive into a RAM. During the execution of a software module, a processor may load some of the instructions into a cache to increase access speed. One or more cache lines may then be loaded into a general register stack for execution by the processor. When referring to the functionality of a software module, it will be understood that such functionality is implemented by a processor when executing instructions from the software module.

[0101] The following claims are not intended to be limited to the embodiments shown herein, but should be granted the full scope consistent with the language of the claims. Within the claims, unless otherwise specified, the reference to the singular element is not intended to mean "one and only one", but "one or more". Unless otherwise specified, the term "some" refers to one or more. No claim element should be interpreted according to the provisions of 35 U.S.C. § 112 (f), unless the phrase "member for..." is used to expressly record the element, or in the case of a method claim, the phrase "step for..." is used to record the element. All structural and functional equivalents of the elements of various aspects described throughout the present disclosure that are known or will be known later to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly recorded in the claims.

Claims

1. A method for executing a partial cache avalanche procedure, the method comprising: counting, in each cache way in a set of cache ways, a number of dirty cache lines having a dirty bit indicating that the cache line has been modified; selecting the at least one cache way from the group for avalanche based on a number of corresponding dirty cache lines of the at least one cache way; as well as The partial cache avalanche procedure is performed based on selecting the at least one cache way from the group for avalanche. 2 . The method of claim 1 , further comprising determining that one or more avalanche criteria are satisfied prior to executing the partial cache avalanche procedure. 3 . The method of claim 2 , wherein the avalanche criteria is based on at least one of a number of active cores or a request for partial cache avalanche.

4. The method of claim 1 , wherein executing the partial cache avalanche procedure comprises: Cache lines from cache ways in the group that are not selected for avalanche are replaced with cache lines of the cache ways selected for avalanche from the group.

5. The method of claim 4, wherein the replacing comprises: evicting the cache lines of the cache ways that are not selected for avalanche; as well as The evicted cache line is assigned to the cache line of the cache way selected from the group for avalanche.

6. The method according to claim 5, wherein: The evicted cache line comprises at least one of a non-dirty cache line or a non-recently used (non-MRU) cache line; and The cache line of the cache way selected from the group for avalanche includes at least one of a dirty cache line or a MRU cache line. 7 . The method of claim 1 , wherein selecting at least one cache way from the group for avalanche comprises selecting a cache way having a lowest number of dirty cache lines for avalanche.

8. The method of claim 1, wherein selecting at least one cache way from the group for avalanche comprises selecting a plurality of cache ways having a lowest number of dirty cache lines.

9. An apparatus for executing a partial cache avalanche procedure, the apparatus comprising: a memory including computer executable instructions; and a processor configured to execute the computer executable instructions and cause the apparatus to: counting, in each cache way in a set of cache ways, a number of dirty cache lines having a dirty bit indicating that the cache line has been modified; selecting the at least one cache way from the group for avalanche based on a number of corresponding dirty cache lines of the at least one cache way; as well as The partial cache avalanche procedure is performed based on selecting the at least one cache way from the group for avalanche.

10. The apparatus of claim 9, wherein the processor is further configured to determine that one or more avalanche criteria are satisfied prior to executing the partial cache avalanche procedure.

11. The apparatus of claim 10, wherein the avalanche criteria is based on at least one of a number of active cores or a request for partial cache avalanche.

12. The apparatus of claim 9, wherein the processor being configured to execute the partial cache avalanche procedure comprises the processor being configured to: Cache lines from cache ways in the group that are not selected for avalanche are replaced with cache lines of the cache ways selected for avalanche from the group.

13. The apparatus of claim 12, wherein the processor being configured to replace the cache line of the cache way comprises the processor being configured to: evicting the cache lines of the cache ways not selected for avalanche; and The evicted cache line is assigned to the cache line of the cache way selected from the group for avalanche.

14. The device according to claim 13, wherein: The evicted cache line comprises at least one of a non-dirty cache line or a non-recently used (non-MRU) cache line; and The cache line of the cache way selected from the group for avalanche includes at least one of a dirty cache line or a MRU cache line.

15. The apparatus of claim 9, wherein the processor being configured to select at least one cache way from the group for avalanche comprises the processor being configured to select a cache way having a lowest number of dirty cache lines for avalanche.

16. The apparatus of claim 9, wherein the processor being configured to select at least one cache way from the group for avalanche comprises the processor being configured to select a plurality of cache ways having a lowest number of dirty cache lines.

17. A non-transitory computer readable medium comprising computer executable instructions which, when executed by a processor of a device, cause the device to perform a partial cache avalanche procedure, the partial cache avalanche procedure comprising: counting, in each cache way in a set of cache ways, a number of dirty cache lines having a dirty bit indicating that the cache line has been modified; selecting the at least one cache way from the group for avalanche based on a number of corresponding dirty cache lines of the at least one cache way; as well as The partial cache avalanche procedure is performed based on selecting the at least one cache way from the group for avalanche.

18. The non-transitory computer readable medium of claim 17, wherein the partial cache avalanche procedure further comprises determining that one or more avalanche criteria are satisfied prior to executing the partial cache avalanche procedure.

19. The non-transitory computer readable medium of claim 18, wherein the avalanche criteria is based on at least one of a number of active cores or a request for partial cache avalanche.

20. The non-transitory computer readable medium of claim 17, wherein the partial cache avalanche procedure further comprises: Cache lines from cache ways in the group that are not selected for avalanche are replaced with cache lines of the cache ways selected for avalanche from the group.

21. The non-transitory computer readable medium of claim 20, wherein the replacing comprises: evicting the cache lines of the cache ways that are not selected for avalanche; as well as The evicted cache line is assigned to the cache line of the cache way selected from the group for avalanche.

22. The non-transitory computer readable medium of claim 21, wherein: The evicted cache line comprises at least one of a non-dirty cache line or a non-recently used (non-MRU) cache line; and The cache line of the cache way selected from the group for avalanche includes at least one of a dirty cache line or a MRU cache line.

23. The non-transitory computer readable medium of claim 17, wherein selecting at least one cache way from the group for avalanche comprises selecting a cache way having a lowest number of dirty cache lines for avalanche.

24. The non-transitory computer readable medium of claim 17, wherein selecting at least one cache way from the group for avalanche comprises selecting a plurality of cache ways having a lowest number of dirty cache lines.

25. An apparatus for executing a partial cache avalanche procedure, the apparatus comprising: means for counting, in each cache way of a set of cache ways, a number of dirty cache lines having a dirty bit indicating that the cache line has been modified; means for selecting at least one cache way from the group for avalanche based on a number of corresponding dirty cache lines of the at least one cache way; and Means for executing the partial cache avalanche procedure based on selecting the at least one cache way from the group for avalanche.

26. The apparatus of claim 25, further comprising means for determining that one or more avalanche criteria are satisfied prior to executing the partial cache avalanche procedure.

27. The apparatus of claim 26, wherein the avalanche criteria is based on at least one of a number of active cores or a request for partial cache avalanche.

28. The apparatus according to claim 25, further comprising: Means for replacing cache lines from cache ways in the group that were not selected for avalanche with cache lines of the cache ways selected for avalanche from the group.

29. The apparatus of claim 25, wherein the means for selecting at least one cache way from the set for avalanche comprises means for selecting a cache way having a lowest number of dirty cache lines for avalanche.

30. The apparatus of claim 25, wherein the means for selecting at least one cache way from the set for avalanche comprises means for selecting a plurality of cache ways having a lowest number of dirty cache lines.

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