Array substrate, manufacturing method thereof and display device

Abstract

The invention provides an array substrate, a manufacturing method of the array substrate and a display device. The array substrate comprises a substrate body, a thin film transistor set, a signal shielding structure and a conductive connecting piece. The thin film transistor group comprises a first thin film transistor and a second thin film transistor which are overlapped with each other in a first direction perpendicular to the main surface of the substrate; the second thin film transistor is located on the side, away from the substrate, of the first thin film transistor, the first thin film transistor comprises a first active layer and a first grid electrode, and the second thin film transistor comprises a second active layer and a second grid electrode. The signal shielding structure is located between the first thin film transistor and the second thin film transistor, and the orthographic projection of the first grid electrode on the substrate is located in the orthographic projection range of the signal shielding structure on the substrate. The conductive connecting piece is connected to the first thin film transistor through a via hole, and the via hole does not penetrate through the signal shielding structure and is spaced from the signal shielding structure. The array substrate disclosed by the invention can effectively shield signal crosstalk between adjacent thin film transistors.

Description

Array substrate, manufacturing method thereof, and display device Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate, a manufacturing method thereof, and a display device. Background Art

[0002] Display devices can generally include liquid crystal display devices, light emitting diode (LED) display devices, organic light emitting diode (OLED) display devices, quantum dot light emitting diode (QLED) display devices, etc. Among various display devices, an array substrate with a pixel driving circuit may be included, and the pixel driving circuit generally includes a plurality of thin film transistors and capacitors. With the continuous development of display technology, the resolution requirements for display devices are also increasing. Generally speaking, the resolution can be improved by reducing the sub-pixel size, but this may lead to problems such as signal crosstalk between adjacent thin film transistors. Therefore, how to avoid signal crosstalk while improving the resolution of the display device is a problem that needs to be solved in current display technology.

[0003] For example, micro-light-emitting diode (Micro-LED) display technology has become increasingly popular in recent years. Due to its small chip size, high integration, and self-luminescence, Micro-LEDs offer significant advantages over LCDs and OLEDs in terms of brightness, resolution, contrast, energy consumption, lifespan, response speed, and thermal stability. These performance advantages in contrast, brightness, lifespan, and response speed make Micro-LEDs highly competitive in the near-eye display market. However, near-eye displays require high-resolution screens, so improving the resolution of Micro-LED driver circuit backplanes is currently a primary challenge in implementing this technology in this field.

[0004] Summary of the Invention

[0005] An embodiment of the present disclosure provides an array substrate, comprising: a base substrate; a thin film transistor group, arranged on one side of the base substrate, the thin film transistor group comprising a first thin film transistor and a second thin film transistor, the first thin film transistor and the second thin film transistor overlapping each other in a first direction perpendicular to a main surface of the base substrate, wherein the second thin film transistor is located on a side of the first thin film transistor away from the base substrate, the first thin film transistor comprising a first active layer and a first gate, and the second thin film transistor comprising a second active layer and a second gate; a signal shielding structure, arranged between the first thin film transistor and the second thin film transistor in the first direction, wherein the orthographic projection of the first gate on the base substrate is located within the orthographic projection range of the signal shielding structure on the base substrate; and a conductive connecting member, located on a side of the signal shielding structure away from the first thin film transistor, and connected to the first thin film transistor through a via, wherein the via does not penetrate the signal shielding structure and is spaced apart from the signal shielding structure in a second direction parallel to the main surface of the base substrate.

[0006] In the array substrate provided in an embodiment of the present disclosure, the orthographic projection of at least part of the second gate on the base substrate overlaps with the orthographic projection of the first gate on the base substrate, and the orthographic projection of at least part of the second gate is located within the orthographic projection range of the signal shielding structure.

[0007] In the array substrate provided by the embodiment of the present disclosure, the signal shielding structure is provided on a side of the first gate electrode away from the first active layer and close to the second thin film transistor.

[0008] In the array substrate provided in the embodiment of the present disclosure, the signal shielding structure includes a metal shielding layer, and the metal shielding layer is connected to the DC signal terminal.

[0009] In the array substrate provided by the embodiment of the present disclosure, the DC signal terminal includes a power supply voltage terminal, a ground terminal, and a common voltage terminal.

[0010] In the array substrate provided in the embodiment of the present disclosure, the second gate includes a top gate and a bottom gate connected to each other, the top gate and the bottom gate are located on opposite sides of the second active layer in the first direction, and the bottom gate is closer to the base substrate than the top gate; and the metal shielding layer is located between the bottom gate and the first gate.

[0011] In the array substrate provided by the embodiment of the present disclosure, the second gate and the metal shielding layer are located on opposite sides of the second active layer in the first direction, and the metal shielding layer is also configured to adjust the threshold voltage of the second thin film transistor by selecting the DC signal end to which it is connected.

[0012] In the array substrate provided in the embodiment of the present disclosure, the signal shielding structure further includes a dielectric shielding unit, and the orthographic projection of the second active layer on the base substrate is located within the orthographic projection range of the dielectric shielding unit on the base substrate.

[0013] In the array substrate provided in an embodiment of the present disclosure, the metal shielding layer is arranged on a side of the dielectric shielding unit close to the first thin film transistor, and the metal shielding layer extends beyond the edge of the dielectric shielding unit in a direction parallel to the main surface of the base substrate.

[0014] In the array substrate provided in the embodiment of the present disclosure, the metal shielding layer is arranged on a side of the dielectric shielding unit away from the first thin film transistor, and the orthographic projection of the metal shielding layer on the base substrate overlaps with the orthographic projection of the dielectric shielding unit on the base substrate.

[0015] The array substrate provided in the embodiment of the present disclosure also includes: an interlayer dielectric structure, located between the first thin film transistor and the second thin film transistor in the first direction, wherein the signal shielding structure is embedded in the interlayer dielectric structure or at least includes a portion of the interlayer dielectric structure.

[0016] In the array substrate provided in the embodiment of the present disclosure, the interlayer dielectric structure includes a dielectric main body and a dielectric protrusion; the dielectric main body extends from a first area where the thin film transistor group is located to a second area of ​​the array substrate in a second direction parallel to the base substrate, and the second area is an area outside the first area; the dielectric protrusion is located in the first area and protrudes from the surface of the dielectric main body away from the first thin film transistor toward the second thin film transistor, and the dielectric protrusion serves as a dielectric shielding unit and serves as at least part of the signal shielding structure, wherein the via passes through the dielectric main body.

[0017] In the array substrate provided by the embodiment of the present disclosure, the dielectric main portion and the dielectric protrusion include different materials and have an interface therebetween.

[0018] In the array substrate provided by the embodiment of the present disclosure, the dielectric constant of the dielectric protrusion is smaller than the dielectric constant of the dielectric main body.

[0019] In the array substrate provided by the embodiment of the present disclosure, the dielectric constant of the dielectric protrusion is less than or equal to 3.5.

[0020] In the array substrate provided by the embodiment of the present disclosure, the dielectric main body includes silicon oxide, and the dielectric protrusion includes spin-on-glass.

[0021] In the array substrate provided by the embodiment of the present disclosure, the dielectric main body and the dielectric protrusions include the same material and are integrally formed.

[0022] In the array substrate provided by the embodiment of the present disclosure, the dielectric main body and the dielectric protrusions include spin-on-glass.

[0023] In the array substrate provided in the embodiment of the present disclosure, the signal shielding structure also includes a metal shielding layer, which is embedded in the dielectric main body and connected to the DC signal end through a conductive through-hole, wherein the conductive through-hole is located on the side of the dielectric protrusion in the second direction and extends through a portion of the dielectric main body to connect to the metal shielding layer.

[0024] In the array substrate provided by the embodiment of the present disclosure, an additional metal layer is provided on a side of the dielectric protrusion away from the dielectric main body and close to the second active layer; the second gate includes a top gate located on a side of the second active layer away from the additional metal layer; wherein the additional metal layer is connected to the DC signal terminal and serves as a metal shielding layer of the signal shielding structure; or the additional metal layer is connected to the top gate to serve as a bottom gate of the second thin film transistor.

[0025] The array substrate provided in the embodiment of the present disclosure also includes: a capacitor, which is arranged side by side with the first thin film transistor and the signal shielding structure on the base substrate in a direction parallel to the main surface of the base substrate, and the capacitor includes a first electrode plate and a second electrode plate opposite to each other, wherein the array substrate includes a first metal material layer, an insulating layer and a second metal material layer, and the insulating layer is located between the first metal material layer and the second metal material layer; the first electrode plate and the first gate are located in the first metal material layer, and the second electrode plate is located in the second metal material layer; and the signal shielding structure includes at least one of a metal shielding layer and a dielectric shielding unit, and the dielectric shielding unit is located on the side of the insulating layer away from the first metal material layer.

[0026] In the array substrate provided by the embodiment of the present disclosure, the metal shielding layer and the second metal material layer are in the same layer.

[0027] In the array substrate provided in the embodiment of the present disclosure, it includes a first area and a second area, the thin film transistor group is located in the first area, the capacitor is located in the second area, and the second metal material layer extends continuously from the first area to the second area and is reused as the metal shielding layer and the second electrode plate.

[0028] The array substrate provided in the embodiment of the present disclosure includes a plurality of thin film transistor groups arranged in an array, and each of the thin film transistor groups is configured to be formed in a sub-pixel driving circuit.

[0029] In the array substrate provided in the embodiment of the present disclosure, the thin film transistor group includes a first thin film transistor subgroup and a second thin film transistor subgroup arranged side by side in a direction parallel to the base substrate; the first thin film transistor subgroup includes the first thin film transistor and the second thin film transistor; the second thin film transistor subgroup includes a third thin film transistor and a fourth thin film transistor arranged to overlap in the first direction, and an additional signal shielding structure is arranged between the third thin film transistor and the fourth thin film transistor.

[0030] In the array substrate provided by the embodiment of the present disclosure, the first active layer and the second active layer include different materials.

[0031] In the array substrate provided by the embodiment of the present disclosure, the first active layer includes polysilicon, and the second active layer includes an oxide semiconductor.

[0032] An embodiment of the present disclosure provides a display device, comprising an array substrate as described above; and a light-emitting device, wherein the light-emitting device is connected to a sub-pixel driving circuit including the thin film transistor group, and the sub-pixel driving circuit is configured to drive the light-emitting device to emit light.

[0033] In the display device provided by the embodiment of the present disclosure, the light-emitting device includes an inorganic light-emitting diode chip or an organic light-emitting layer.

[0034] An embodiment of the present disclosure provides a method for manufacturing an array substrate, comprising: providing a base substrate; forming a first thin film transistor on the base substrate, the first thin film transistor including a first active layer and a first gate; forming a signal shielding structure on a side of the first thin film transistor away from the base substrate; and forming a second thin film transistor on a side of the signal shielding structure away from the first thin film transistor, the second thin film transistor including a second active layer and a second gate; and forming a conductive connector, the conductive connector being located on a side of the signal shielding structure away from the first thin film transistor and connected to the first thin film transistor through a via, wherein the via is located outside the signal shielding structure and spaced apart from the signal shielding structure in a direction parallel to the base substrate, wherein the first thin film transistor and the second thin film transistor overlap with each other in a first direction perpendicular to the main surface of the base substrate and constitute a thin film transistor group, the signal shielding structure being located between the first thin film transistor and the second thin film transistor in the first direction, and the orthographic projection of the first gate on the base substrate being located within the orthographic projection range of the signal shielding structure on the base substrate.

[0035] The manufacturing method of the array substrate provided in the embodiment of the present disclosure also includes: forming a first metal material layer on the side of the first active layer away from the base substrate, and the first gate is located in the first metal material layer; forming an insulating layer on the side of the first metal material layer away from the first active layer; and forming an interlayer dielectric structure on the side of the insulating layer away from the first metal material layer; wherein the signal shielding structure includes at least one of the metal shielding layer and a portion of the interlayer dielectric structure.

[0036] In the manufacturing method of the array substrate provided in the embodiment of the present disclosure, the interlayer dielectric structure includes a dielectric main body and a dielectric protrusion, and forming the interlayer dielectric structure includes: forming a first dielectric layer on the insulating layer as the dielectric main body; forming a second dielectric layer on the first dielectric layer; and patterning the second dielectric layer to remove the portion of the second dielectric layer located outside the first area where the thin film transistor group is located, and leaving the portion of the second dielectric layer located in the first area as the dielectric protrusion, wherein the dielectric protrusion serves as at least part of the signal shielding structure.

[0037] In the manufacturing method of the array substrate provided in the embodiment of the present disclosure, the interlayer dielectric structure includes a dielectric main body and a dielectric protrusion, and forming the interlayer dielectric structure includes: forming a planarization dielectric layer on the insulating layer; thinning the thickness of a portion of the planarization dielectric layer to form the dielectric main body having a first thickness and the dielectric protrusion having a second thickness, wherein the second thickness is greater than the first thickness, wherein the dielectric protrusion is located in the area where the thin film transistor group is located and serves as at least part of the signal shielding structure.

[0038] In the method for manufacturing the array substrate provided by the embodiment of the present disclosure, the metal shielding layer is formed before forming the interlayer dielectric structure, and the metal shielding layer is embedded in the dielectric main body.

[0039] In the method for manufacturing the array substrate provided by the embodiment of the present disclosure, after the interlayer dielectric structure is formed, an additional metal layer is formed on a side of the dielectric protrusion away from the dielectric main body.

[0040] In the manufacturing method of the array substrate provided in the embodiment of the present disclosure, the additional metal layer is connected to the DC signal end and serves as the metal shielding layer; or the second gate includes a top gate located on the side of the second active layer away from the additional metal layer, and the additional metal layer is connected to the top gate and serves as the bottom gate of the second thin film transistor.

[0041] In the manufacturing method of the array substrate provided in the embodiment of the present disclosure, forming the signal shielding structure includes: before forming the interlayer dielectric structure, forming a second metal material layer on the side of the insulating layer away from the first metal material layer, the second metal material layer includes the metal shielding layer, and the interlayer dielectric structure covers the second metal material layer.

[0042] The manufacturing method of the array substrate provided in the embodiment of the present disclosure also includes: forming a capacitor, which is arranged side by side with the first thin film transistor and the signal shielding structure, wherein the capacitor includes a first electrode plate and a second electrode plate opposite to each other; wherein the first electrode plate and the second electrode plate are respectively located in the first metal material layer and the second metal material layer.

[0043] In the manufacturing method of the array substrate provided in the embodiment of the present disclosure, forming the metal shielding layer and the second electrode plate includes: patterning the second metal material layer to form the metal shielding layer and the second electrode plate separated from each other; or the second metal material layer continuously extends from the area where the thin film transistor group is located to the area where the capacitor is located, and is reused as the metal shielding layer and the second electrode plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0045] FIG1 shows a schematic cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0046] FIG2 shows a schematic cross-sectional view of an array substrate according to some other embodiments of the present disclosure.

[0047] 3A to 3J are schematic cross-sectional views illustrating a method for manufacturing an array substrate according to some embodiments of the present disclosure.

[0048] 4 to 6 are schematic cross-sectional views of array substrates according to other embodiments of the present disclosure.

[0049] 7A to 7H are schematic cross-sectional views illustrating methods for manufacturing an array substrate according to other embodiments of the present disclosure.

[0050] 8 to 10 are schematic cross-sectional views of array substrates according to other embodiments of the present disclosure.

[0051] 11A to 11C are schematic cross-sectional views illustrating methods for manufacturing an array substrate according to other embodiments of the present disclosure.

[0052] 12 and 13 are schematic cross-sectional views of array substrates according to other embodiments of the present disclosure.

[0053] FIG14 shows a schematic block diagram of an array substrate according to some embodiments of the present disclosure.

[0054] FIG15A shows a schematic block diagram of a display device according to some embodiments of the present disclosure.

[0055] FIG15B shows a schematic diagram of a sub-pixel driving circuit according to some embodiments of the present disclosure.

[0056] FIG16 shows a schematic block diagram of a display device according to some other embodiments of the present disclosure.

[0057] FIG. 17 shows a scanning electron microscope (SEM) image of an array substrate according to some embodiments of the present disclosure.

[0058] FIG18 is a schematic top view of the gate and signal shielding structure of each thin film transistor of a thin film transistor group in an array substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0059] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0061] FIG1A shows a schematic cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0062] Referring to FIG. 1A , in some embodiments, an array substrate 50 includes a base substrate 10 and a plurality of thin film transistors disposed on the base substrate 10 , wherein some of the plurality of thin film transistors may overlap each other in a direction perpendicular to the main surface of the base substrate 10 . For example, the plurality of thin film transistors may include a thin film transistor T1′, a thin film transistor T2′, and a thin film transistor T3′. In some embodiments, thin film transistors T1′ and T3′ may be top-gate thin film transistors, and thin film transistor T2′ may be a dual-gate transistor. For example, thin film transistor T1′ may include a gate 14a and an active layer 12a; thin film transistor T3′ may include a gate 14b and an active layer 12b; and thin film transistor T2′ may include a bottom gate 16a, a top gate 16b, and an active layer 19. The active layers 12a, 12b, and 19 of thin film transistors T1′-T3′ each include a source region, a drain region, and a channel region, wherein the channel region is located between the source and drain regions. In some embodiments, thin film transistors T1' and T3' may be arranged on the same layer, that is, their gates and active layers may be arranged on the same layer. In this article, "arranging on the same layer" of multiple components means that the multiple components are located in the same layer, have the same material, or are patterned from the same material layer. That is, gates 12a and 12b may be formed from the same metal material layer through a patterning process; active layers 14a and 14b may be formed from the same active material layer through a patterning process. Thin film transistor T2' may be arranged on the side of thin film transistor T1' away from base substrate 10, and overlap with thin film transistor T1' in a direction perpendicular to the main surface of base substrate 10. In this article, multiple components overlapping each other in a certain direction means that the orthographic projections of the multiple components on the same reference plane in the direction overlap with each other, where the direction is perpendicular to the reference plane. That is, the thin film transistors T1 ′ and T2 ′ overlap in a direction perpendicular to the base substrate 10 (eg, direction D1 ), meaning that orthographic projections of the thin film transistors T1 ′ and T2 ′ on the base substrate 10 in the direction D1 overlap each other.

[0063] In some embodiments, the array substrate 50 also includes a capacitor C1', and the capacitor C1' includes a first electrode plate and a second electrode plate 16b opposite to each other; for example, the first electrode plate of the capacitor C1' can share the same metal layer with the gate 14b of the thin film transistor T2', that is, at least a portion of the metal layer where the gate 14b is located can be reused as the first electrode plate of the capacitor C1'; the second electrode plate 16b of the capacitor C1' can be set on the same layer as the bottom gate 16a of the thin film transistor T2'.

[0064] In some embodiments, a buffer layer 11 may be disposed between the thin-film transistors T1' and T3' and the base substrate 10. An insulating layer 13, a dielectric layer 15, an insulating layer 17, a buffer layer 18, an insulating layer 20, and an interlayer dielectric layer 23 may also be disposed on the side of the buffer layer 11 away from the base substrate 10. A conductive layer 25 is disposed on the interlayer dielectric layer 23 and includes a plurality of conductive connectors connected to the thin-film transistors and capacitors through vias.

[0065] In some embodiments, one or more planarization dielectric layers and passivation layers as well as a conductive layer 28 are further disposed on the conductive layer 25. For example, the conductive layer 28 may include one or more conductive connectors, and the conductive connectors are electrically connected to the conductive layer 25 through vias in the planarization dielectric layer 26 and the passivation layer 27. One or more passivation layers 29 and a planarization dielectric layer 30 may be disposed on the conductive layer 28, and the conductive layer 28 may have a portion exposed by the openings in the passivation layer 29.

[0066] In some embodiments, the thin film transistors T1' and T2' and / or the thin film transistor T2' and the capacitor C1' are included in the same sub-pixel driving circuit. By stacking the thin film transistors T1' and T2', the lateral occupied area of ​​the sub-pixel driving circuit and the sub-pixel can be reduced, that is, the pixel size is reduced, thereby improving the resolution of the display device. In this article, a plurality of thin film transistors are stacked to refer to the plurality of thin film transistors overlapping each other in a direction perpendicular to the substrate. In some embodiments, the thin film transistor T1' is, for example, a low temperature polysilicon (LTPS) thin film transistor, which can use polysilicon material as the active layer material; the thin film transistor T3' can be an oxide thin film transistor, which uses indium gallium zinc oxide (IGZO) and the like as the active layer material, but the present disclosure is not limited thereto. The thin film transistor T3' is, for example, used as a switching transistor. In some embodiments, compared to using LTPS thin film transistors as switching transistors, using oxide thin film transistors as switching transistors can significantly reduce leakage current, thereby reducing the size of corresponding capacitors, reducing pixel area, and thus improving the resolution of the display device.

[0067] However, in this embodiment, the gate signal lines of thin-film transistors T1' and T2' overlap in direction D1, and signal crosstalk may occur between adjacent gate signal lines. For example, the transition of gate 14a of thin-film transistor T1' may affect and drive the transition of gates 16a and 22 of thin-film transistor T2', thereby affecting the operating state of thin-film transistor T2'.

[0068] In order to solve the problem of signal crosstalk between stacked thin film transistors, various embodiments of the present disclosure provide an array substrate, which includes a thin film transistor group, wherein the thin film transistor group includes a plurality of thin film transistors overlapping each other in a direction perpendicular to the main surface of the substrate; a signal shielding structure is provided between adjacent thin film transistors among the plurality of thin film transistors to shield the signal crosstalk between adjacent thin film transistors, for example, to prevent the jump of the gate signal of one of the adjacent thin film transistors from affecting or driving the jump of the gate signal of the other, and / or to prevent the jump of the gate signal of one of the adjacent thin film transistors from affecting the channel region of the active layer of the other. For example, the thin film transistor group includes a first thin film transistor and a second thin film transistor that are stacked, the second thin film transistor is arranged on a side of the first thin film transistor away from the substrate, and the signal shielding structure is arranged between the first thin film transistor and the second thin film transistor in a direction perpendicular to the main surface of the substrate; for example, the positive projection of the first gate of the first thin film transistor on the substrate can be located within the positive projection range of the signal shielding structure on the substrate, thereby preventing the jump of the gate signal of the first thin film transistor from causing an adverse effect on the gate signal of the second thin film transistor or causing the gate of the second thin film transistor to jump, and / or preventing the jump of the gate signal of the first thin film transistor from affecting the channel region of the active layer of the second thin film transistor.

[0069] This embodiment, by stacking thin-film transistors and providing a signal shielding structure between adjacent thin-film transistors, can prevent signal crosstalk between adjacent thin-film transistors while reducing device size (for example, reducing pixel size to increase resolution), thereby ensuring the normal operation and reliability of the thin-film transistors and meeting the display function of a high-resolution display device. In various embodiments, the signal shielding structure may include at least one of a metal shielding layer and a dielectric shielding unit; the metal shielding layer is connected to the DC signal terminal, and the dielectric shielding unit may include a low-k dielectric material with sufficient thickness, thereby ensuring that the signal shielding structure has good signal shielding capabilities.

[0070] FIG2 shows a schematic cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0071] Referring to FIG. 2 , in some embodiments, an array substrate 500a includes a base substrate 100 and a thin film transistor group TS disposed on the base substrate 100. The thin film transistor group TS may include a plurality of thin film transistors arranged in a stacked manner, the plurality of thin film transistors overlapping each other in a direction perpendicular to the main surface of the base substrate 100, for example, at least partially overlapping. For example, the thin film transistor group TS may include a thin film transistor T1 and a thin film transistor T2. The thin film transistors T1 and T2 overlap each other in a direction perpendicular to the main surface of the base substrate 100 (for example, direction D1). That is, the orthographic projection of the thin film transistor T1 on the base substrate 100 in direction D1 overlaps the orthographic projection of the thin film transistor T2 on the base substrate 100 in direction D1. For example, the thin film transistor T2 may be disposed on a side of the thin film transistor T1 away from the base substrate 100. The thin film transistors T1 and T2 may be referred to as a first thin film transistor and a second thin film transistor, respectively.

[0072] It should be understood that the number of thin film transistors included in the thin film transistor group TS shown in the figure is for illustration only and is not intended to limit the present disclosure. For example, in other embodiments, the thin film transistor group TS may include more than two thin film transistors. Multiple thin film transistors in the thin film transistor group TS may be included in the same sub-pixel driving circuit, and the thin film transistor group TS may include multiple thin film transistor sub-groups arranged side by side in a direction parallel to the main surface of the base substrate 100, each thin film transistor sub-group including two thin film transistors arranged in a stacked manner.

[0073] In some embodiments, a signal shielding structure is provided between adjacent thin film transistors in the thin film transistor group TS to shield signal crosstalk between adjacent thin film transistors, such as electrical signal crosstalk. It should be understood that adjacent thin film transistors refer to thin film transistors that are adjacent to each other in a direction perpendicular to the main surface of the base substrate 100 (for example, direction D1). The figure schematically shows a signal shielding structure S1 provided between the thin film transistors T1 and T2. In other embodiments in which the thin film transistor group TS includes more than two thin film transistors, the array substrate 500a may include a plurality of signal shielding structures S1, and the plurality of signal shielding structures S1 are respectively provided between corresponding two adjacent thin film transistors, that is, a signal shielding structure may be provided between each two adjacent and stacked thin film transistors in the thin film transistor group to shield signal crosstalk between adjacent thin film transistors.

[0074] In some embodiments, as shown in FIG2 , the thin film transistor T1 includes a gate G1, an active layer AL1, and a gate insulating layer located between the gate G1 and the active layer AL1. Herein, the active layer of each thin film transistor includes a source region, a drain region, and a channel region. The source region and the drain region are interchangeable, and the source region and the drain region may be collectively referred to as the source-drain region. For the sake of simplicity, the source-drain region and the channel region of each active layer are not specifically shown in the figure, but it should be understood that the channel region is located between the source region and the drain region and overlaps with the gate in a direction perpendicular to the main surface of the substrate. In some embodiments, the thin film transistor T1 may have a top-gate structure, that is, the gate G1 is disposed on the side of the active layer AL1 away from the substrate 100. In other words, the gate G1 is closer to the thin film transistor T2 than the active layer AL1.

[0075] In some embodiments, the thin film transistor T2 may be a dual-gate transistor and include a gate G2, a gate G3, an active layer AL2, and a gate insulating layer located between each gate G2 and G3 and the active layer AL2. Gates G2 and G3 are connected to each other and are arranged on opposite sides of the active layer AL2 in a direction perpendicular to the main surface of the base substrate 100. In some embodiments, gate G2 is closer to the base substrate 100 than gate G3. Gate G2 and gate G3 may also be referred to as the bottom gate and top gate of the thin film transistor T2, respectively. Each gate of the multiple thin film transistors may be connected to a corresponding gate signal line. For example, each gate may be located on the same layer as the gate signal line, and a portion of the gate signal line may serve as the gate of the thin film transistor.

[0076] In some embodiments, the active layers AL1 and AL2 of thin-film transistors T1 and T2 are referred to as the first active layer and the second active layer, respectively, and the gates G1 and G2 / G3 of thin-film transistors T1 and T2 are referred to as the first gate and the second gate, respectively. In this embodiment, the second gate of thin-film transistor T2 includes a bottom gate G2 and a top gate G3, but the present disclosure is not limited thereto. In other embodiments, the second gate may include only the top gate G3 or only the bottom gate G2.

[0077] In some embodiments, thin film transistor T1 may be a low-temperature polysilicon (LTPS) thin film transistor, using low-temperature polysilicon as the material for active layer AL1, while thin film transistor T2 may be an oxide thin film transistor, using an oxide semiconductor such as IGZO as the material for active layer AL2, but the present disclosure is not limited thereto. Thin film transistors T1 and T2 may each be selected from one of an LTPS thin film transistor and an oxide thin film transistor, and both may be of the same or different types. In some embodiments, thin film transistor T2 is used as a switching transistor in a pixel driver circuit, and its use of an oxide semiconductor such as IGZO can reduce leakage current.

[0078] Continuing with FIG. 2 , a signal shielding structure S1 is disposed between thin-film transistors T1 and T2 in a direction D1 perpendicular to the major surface of substrate 100 to shield signal crosstalk between thin-film transistors T1 and T2, for example, shielding crosstalk between the gate signals of the thin-film transistors T1 and T2. For example, gate G1 of thin-film transistor T1 and gates G2 / G3 of thin-film transistor T2 at least partially overlap in a direction perpendicular to the major surface of substrate 100, and signal shielding structure S1 is disposed at least between the overlapping portion of gates G1 and G2. For example, the orthographic projection of the gate G1 of the thin-film transistor T1 on the substrate 100 may be within the orthographic projection of the signal shielding structure S1 on the substrate 100, thereby preventing the signal transition of the gate G1 of the thin-film transistor T1 from adversely affecting the gates G2 / G3 of the thin-film transistor T2. At least a portion of the orthographic projection of the gates G2 / G3 of the thin-film transistor T2 on the substrate 100 overlaps with the orthographic projection of the gate G1 of the thin-film transistor T1 on the substrate 100, and the orthographic projection of at least a portion of the gates G2 / G3 on the substrate 100 is within the orthographic projection of the signal shielding structure S1 on the substrate 100, thereby preventing the signal transition of the gates G2 / G3 of the thin-film transistor T2 from adversely affecting the gate G1 of the thin-film transistor T1. In some embodiments, the orthographic projections of the gates G2 / G3 of the thin-film transistor T2 on the substrate 100 may all be within the orthographic projection of the signal shielding structure S1 on the substrate 100. Herein, the orthographic projection of a component on the base substrate 100 refers to a projection of the component on the base substrate main surface in a direction perpendicular to the base substrate main surface (eg, direction D1 ).

[0079] In some embodiments, a signal shielding structure S1 is disposed on a side of the gate G1 of the thin-film transistor S1 that is away from the active layer AL1 and closer to the thin-film transistor T2. For example, the signal shielding structure S1 is located between the gate G1 of the thin-film transistor T1 and the bottom gate G2 of the thin-film transistor T2. In some embodiments, the gate G1 is part of a first gate signal line, and the gates G2 / G3 are part of a second gate signal line. The first and second gate signal lines at least partially overlap in a direction perpendicular to the main surface of the substrate 100. Furthermore, the signal shielding structure S1 is disposed at least between the overlapping portions of the first and second gate signal lines in a direction perpendicular to the main surface of the substrate 100. The orthographic projection of the overlapping portions of the first and second gate signal lines onto the main surface of the substrate 100 may be located within the orthographic projection of the signal shielding structure S1 onto the main surface of the substrate 100. For example, the orthographic projection of the first gate signal line on the main surface of the base substrate 100 is within the orthographic projection range of the signal shielding structure S1 on the main surface of the base substrate, and the orthographic projection of at least a portion of the second gate signal line on the base substrate overlaps with the orthographic projection of the first gate signal line on the base substrate, and the orthographic projection of at least a portion of the second gate signal line on the base substrate is within the orthographic projection range of the signal shielding structure S1 on the main surface of the base substrate. The extension directions of the first gate signal line and the second gate signal line can be the same or different.

[0080] In some embodiments, the signal shielding structure S1 may be or include a metal shielding layer MS, and the metal shielding layer MS is connected to a DC signal terminal, which may include a power supply voltage terminal, a ground terminal, a common voltage terminal, etc. For example, the metal shielding layer MS may be grounded, connected to a 0V voltage, or connected to a stable DC power supply voltage terminal such as VDD or VSS. For example, the metal shielding layer 106a is connected to a DC signal layer DS, which is configured to ground the metal shielding layer 106a, connect it to a 0V voltage, or apply a DC voltage signal such as VDD or VSS to the metal shielding layer 106a. By providing a metal shielding layer MS between the thin film transistors T1 and T2 and connecting the metal shielding layer MS to a stable DC signal terminal, signal crosstalk between the thin film transistors T1 and T2 can be shielded. For example, it can prevent the signal jump of the gate signal line where the gate G1 is located from affecting the gates G2 and G3 or even causing the jump of the gates G2 and G3, or prevent the signal jump of the gate signal line where the gates G2 / G3 are located from affecting the gate G1 or even causing the jump of the gate G1, thereby ensuring that the thin film transistors T1 and T2 operate independently and do not interfere with each other, thereby improving the reliability of the thin film transistors T1 and T2.

[0081] In some embodiments, the array substrate 500a may further include a thin film transistor T3 and a capacitor C1. The thin film transistor T3 may include a gate electrode G3, an active layer AL3, and a gate insulating layer located between the gate electrode G3 and the active layer AL3. The capacitor C1 may include an electrode plate M1 and an electrode plate M2 facing each other, and an inter-electrode insulating layer located between the electrode plate M1 and the electrode plate M2.

[0082] For example, the thin film transistor T3 and the capacitor C1 may be stacked and may be located to the side of the thin film transistor group TS in a direction parallel to the main surface of the base substrate 100 (e.g., direction D2). For example, the thin film transistor T3 may be located to the side of the thin film transistor T1 in direction D2; the gate G3 and active layer AL3 of the thin film transistor T3 may be located in the same layer as the gate G1 and active layer AL1 of the thin film transistor T1, respectively. The capacitor C1 may be located side by side with the thin film transistor T1 and the signal shielding structure S1 in a direction parallel to the main surface of the base substrate. For example, the capacitor C1 may be located to the side of the thin film transistor T1 and the metal shielding layer MS in direction D2, and the electrode plates M1 and M2 of the capacitor C1 may be located in the same layer as the gate G1 and the metal shielding layer MS, respectively.

[0083] In some embodiments, the array substrate 500a may include, from bottom to top, a first active material layer, a metal material layer (or a first metal material layer) 103, a metal material layer (or a second metal material layer) 106, a metal material layer (or a third metal material layer) 109, a second active material layer, and a metal material layer 113 (or a fourth metal material layer). The active layers AL1 and AL3 of thin-film transistors T1 and T3 may be located in the first active material layer. The gates G1 and G3 of thin-film transistors T1 and T3, as well as the electrode plate M1 of capacitor C1, may be located in the metal material layer 103. For example, the metal material layer 103 may include a metal layer 103a and a metal layer 103b, separated from each other. At least a portion of the metal layer 103a functions as the gate G1, and at least a portion of the metal layer 103b functions as the gate G3, which may also serve as the electrode plate M1. That is, the gate G3 and the electrode plate M1 may share the same metal layer 103b. However, the present disclosure is not limited to this. The metal shielding layer MS and the electrode plate M2 may be located in the metal material layer 106. For example, the metal material layer 106 may include a metal layer 106a and a metal layer 106b separated from each other, with at least a portion of the metal layer 106a serving as the metal shielding layer MS, and at least a portion of the metal layer 106b serving as the electrode plate M2. In some embodiments, the metal shielding layer MS is disposed in the metal material layer 106, co-located with the electrode plate M2, so that the metal shielding layer can be formed without increasing the number of masks.

[0084] The bottom gate G2, active layer AL2, and top gate G3 of the thin film transistor 109 may be located in the metal material layer 109, the second active material layer, and the metal material layer 113, respectively. That is, at least a portion of the metal material layer 109 serves as the gate G2, at least a portion of the second active material layer serves as the active layer AL2, and at least a portion of the metal material layer 113 serves as the gate G2. It should be understood that active layers of other thin film transistors may be provided in each of the above-mentioned active material layers, and gates or other metal components of other thin film transistors may be provided in each of the above-mentioned metal material layers. The metal layer in which each gate is located may be or include a gate signal line extending in a horizontal direction, and a portion of the gate signal line serves as a gate, that is, the gate and the gate signal line may share the same metal layer.

[0085] In some embodiments, each of the active material layers and metal material layers is embedded in a dielectric / insulating material layer, and adjacent layers of the active material layer and metal material layer are separated by the dielectric / insulating material located therebetween. For example, the dielectric / insulating material includes a buffer layer 101, an insulating layer 102, an insulating layer 105, a dielectric layer 107, a buffer layer 110, an insulating layer 112, and a dielectric layer 115, disposed sequentially from bottom to top on the base substrate 100. The buffer layer 101 may be located between the plurality of thin film transistors T1-T3 and the capacitor C1 and the base substrate 100. For example, the first active material layer is arranged on the side of the buffer layer 101 away from the base substrate 100; and the first active material layer (for example, active layers AL1 and AL3), metal material layer 103, metal material layer 106, metal material layer 109, second active material layer (for example, active layer AL2) and metal material layer 113 are respectively placed in advance in the insulating layer 102, insulating layer 105, dielectric layer 107, buffer layer 110, insulating layer 112 and dielectric layer 115.

[0086] Portions of the insulating layer 102 are located between the first active material layer and the metal material layer 103 and serve as gate insulating layers for thin film transistors T1 and T3. For example, a portion of the insulating layer 102 is located between the active layer AL1 and the gate electrode G1 to serve as the gate insulating layer for thin film transistor T1; another portion of the insulating layer 102 is located between the active layer AL3 and the gate electrode G3 to serve as the gate insulating layer for thin film transistor T3.

[0087] Some portions of the insulating layer 105 are located between the metal material layer 103 and the metal material layer 106. For example, a portion of the insulating layer 105 is located between the metal shield layer MS and the gate G2, separating the metal shield layer MS from the gate G2; another portion of the insulating layer 105 is located between the electrode plate M1 and the electrode plate M2, and serves as an inter-electrode insulating layer of the capacitor C1.

[0088] In some embodiments, dielectric layer 107 serves as an interlayer dielectric structure ILD1, located between thin-film transistors T1 and T2. Metal shield layer MS of signal shield structure S1 is embedded within interlayer dielectric structure ILD1. A portion of dielectric layer 107 is located between metal shield layer MS and bottom gate G2 of thin-film transistor T2, thereby separating metal shield layer MS from gate G2.

[0089] A portion of the buffer layer 110 is located between the bottom gate G2 and the active layer AL2 and serves as the bottom gate insulating layer of the thin film transistor T2; a portion of the insulating layer 112 is located between the top gate G3 and the active layer AL2 and serves as the top gate insulating layer of the thin film transistor T2.

[0090] In some embodiments, the insulating layers 102 / 105, buffer layer 110, and insulating layer 112 may comprise insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, or high-k dielectric materials such as hafnium oxide. Since portions of these layers function as gate insulating layers and / or inter-electrode insulating layers, the use of higher-k dielectric materials can reduce leakage current in corresponding thin-film transistors or increase the capacitance of capacitors. In some embodiments, the interlayer dielectric structure ILD1 (e.g., dielectric layer 107) may comprise dielectric materials such as silicon oxide or spin-on glass (SOG). Low-k dielectric materials may be used for the interlayer dielectric structure ILD1, thereby reducing parasitic capacitance between adjacent metal layers in direction D1. In some embodiments, the dielectric constant of the interlayer dielectric structure ILD1 may be less than or equal to the dielectric constants of the insulating layers 102 / 105, buffer layer 110, and insulating layer 112.

[0091] The dielectric layer 115 is located on the insulating layer 112 and covers the metal material layer 113. In some embodiments, the dielectric layer 115 is a planarization layer and has a flat surface on the side away from the insulating layer 112. In some embodiments, a conductive layer 116 is provided on the dielectric layer 115. The conductive layer 116 includes conductive connectors connected to each thin film transistor, capacitor, and metal shield layer and separated from each other. Each conductive connector is connected to the corresponding thin film transistor, capacitor, and metal shield layer through a via located in one or more insulating material layers (for example, one or more of the insulating layer 112 to the dielectric layer 115). For example, the conductive connectors include source-drain electrode SD1a, source-drain electrode SD2a, conductive connector GC, DC signal layer DS, conductive connectors Ct1 and Ct2. It should be understood that the source-drain electrode can be a source electrode connected to the source region of the active layer or a drain electrode connected to the drain region of the active layer, and the figure only schematically shows some of the source-drain electrodes of the thin film transistor.

[0092] In some embodiments, some conductive connectors (e.g., source / drain electrodes SD1a) are located on a side of the signal shielding structure S1 away from the first thin-film transistor T1 and are connected to the first thin-film transistor T1 through vias. The vias are located outside the signal shielding structure S1 and spaced apart from the signal shielding structure S1 in a direction parallel to the substrate 100. That is, the vias do not penetrate the signal shielding structure S1. The vias extend through insulating material layers such as the dielectric layer 115, the insulating layer 112, the buffer layer 110, the dielectric layer 107, the insulating layer 105, and / or the insulating layer 102, so that the conductive connectors are connected to corresponding components of the thin-film transistor T1.

[0093] In some embodiments, source-drain electrode SD1a is connected to the source-drain region of active layer AL1 via conductive via v1; source-drain electrode SD2a is connected to the source-drain region of active layer AL2 via conductive via v2; conductive connector GC is connected to gate G3 via conductive via v3 and to gate G2 via conductive via v4. In other words, gates G2 and G3 of thin-film transistor T2 are electrically connected to each other via conductive connector GC; conductive connector Ct1 is connected to metal layer 103b via conductive via v6, that is, to gate G3 of thin-film transistor T3 and electrode plate M1 of capacitor C1; conductive connector Ct2 is connected to electrode plate M2 of capacitor C1 via conductive via v7. Each conductive via is a portion of a conductive material layer that fills a corresponding via hole in an insulating / dielectric material layer.

[0094] The DC signal layer DS is connected to the metal shielding layer MS via conductive vias v5, enabling the metal shielding layer MS to provide signal shielding. In some embodiments, the DC signal layer DS can be or be connected to a DC signal terminal such as a power supply voltage terminal, a ground terminal, or a common voltage terminal. For example, the DC signal layer DS can be a power supply voltage signal line such as VDD or VSS, a 0V voltage signal line, or a ground signal line.

[0095] In some embodiments, similar to the embodiment shown in FIG. 1A , other conductive layers, planarization layers, passivation layers, etc. may be further provided on the conductive layer 116 of this embodiment. For the sake of brevity, they are not shown or described again here.

[0096] In this embodiment, a metal shielding layer MS is provided between the stacked thin-film transistors T1 and T2 in the thin-film transistor group TS. This metal shielding layer MS is connected to the DC signal terminal to serve as a signal shielding structure S1. This shields signal crosstalk between the thin-film transistors T1 and T2. For example, this prevents a gate signal transition from one thin-film transistor T1 or T2 from affecting or causing a gate signal transition from the other. In this way, while providing a thin-film transistor group to reduce pixel size, the individual thin-film transistors in the thin-film transistor group can operate stably and independently without interfering with each other, thereby improving the reliability of the array substrate and the display device incorporating it, and achieving stable display performance for a high-resolution display device.

[0097] 3A to 3J are schematic cross-sectional views illustrating structures in various process steps of a method for manufacturing an array substrate 500 a according to some embodiments of the present disclosure.

[0098] Referring to Figure 3A, in some embodiments, a base substrate 100 is provided. The base substrate 100 may be a rigid substrate and, for example, may include materials such as glass; alternatively, the base substrate 100 may be a flexible substrate and may include materials such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), etc., but the present disclosure is not limited to this.

[0099] A buffer layer 101 is formed on a base substrate 100 . The buffer layer 101 may include insulating materials such as silicon oxide and silicon nitride and may be formed on one side of the base substrate 100 , for example, on the main surface of the base substrate 100 , by a deposition process such as chemical vapor deposition (CVD).

[0100] Active layers AL1 and AL3 are formed on the side of the buffer layer 101 away from the substrate 100. In some embodiments, the active layers AL1 and AL3 include a semiconductor material such as polycrystalline silicon, for example, low-temperature polysilicon (LTPS). A method for manufacturing the active layers AL1 and AL3 may include forming an active material layer (e.g., a low-temperature polysilicon layer) on the buffer layer 101, followed by patterning the active material layer to form the active layers AL1 and AL3; the patterning process may include photolithography and etching. The active layers AL1 and AL3 will serve as the active layers of the thin-film transistors T1 and T3, respectively.

[0101] Next, an insulating layer 102 is formed on the side of the buffer layer 101 away from the base substrate 100 to cover the sidewalls of the active layers AL1 and AL3 and their surfaces away from the buffer layer 101. In some embodiments, the insulating layer 102 may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, or high-k dielectric materials such as hafnium oxide, and may be formed using a deposition process such as CVD. Portions of the insulating layer 102 will serve as gate insulating layers for thin-film transistors T1 and T3, respectively.

[0102] Referring to FIG3B , a metal material layer 103 is formed on a side of the insulating layer 102 away from the active layers AL1 and AL3 and the buffer layer 101. The metal material layer 103 may include a metal material such as copper, aluminum, molybdenum, or titanium. The metal material layer 103 may include metal layers 103a and 103b spaced apart from each other. For example, the metal material layer may be formed by a deposition process such as physical vapor deposition (PVD), and then patterned to form the metal layers 103a and 103b. At least portions of the metal layers 103a and 103b will serve as the gates G1 and G3 of the thin-film transistors T1 and T3, respectively, and at least portions of the metal layer 103b will also serve as the electrode plate M1 of the capacitor C1. In some embodiments, the metal layers 103a and 103b may each be or include a gate signal line, with portions of the gate signal lines serving as the gates of the respective thin-film transistors.

[0103] 3C , an insulating layer 105 is formed on the side of the insulating layer 102 away from the buffer layer 101 to cover the sidewalls of the metal material layer 103 and the surface thereof away from the insulating layer 102. The material of the insulating layer 105 can be similar to, the same as, or different from that of the insulating layer 102. For example, the insulating layer 105 can be selected from insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, or high-k dielectric materials such as hafnium oxide, and can be formed by a deposition process such as CVD.

[0104] A metal material layer 106 is formed on the side of the insulating layer 105 away from the metal material layer 103. The material of the metal material layer 106 may be the same as or different from the material of the metal material layer 103. For example, the metal layer 106 may include a metal material such as copper, aluminum, molybdenum, titanium, or a metal oxide material such as indium tin oxide (ITO). It should be understood that, in this document, "metal material layer" or "metal layer" may be or may include any material layer containing metal elements such as metal, metal alloy, metal oxide, etc. In some embodiments, the metal material layer 106 includes a metal layer 106a and a metal layer 106b spaced apart from each other. For example, a metal material layer can be formed on the insulating layer 105 by a deposition process such as PVD, and then the metal material layer is subjected to a patterning process to form metal layers 106a and 106b spaced apart from each other. In some embodiments, metal layer 106a may serve as metal shielding layer MS; metal layer 106b may serve as electrode plate M2 of capacitor C1, and a portion of insulating layer 105 is located between electrode plate M2 and electrode plate M1 to serve as an inter-electrode insulating layer of capacitor C1.

[0105] Referring to FIG. 3D , a dielectric layer 107 is formed on a side of insulating layer 105 away from insulating layer 102 and metal material layer 103 to cover the sidewalls of metal material layer 106 and its surface away from insulating layer 105. Dielectric layer 107 may include a dielectric material such as silicon oxide or silicon nitride, or a low-k material such as SOG, and may be formed by a deposition process such as CVD or a spin-on coating process. In some embodiments, dielectric layer 107 serves as an interlayer dielectric structure ILD1.

[0106] Next, a metal material layer 109 is formed on a side of the dielectric layer 107 away from the insulating layer 105 and the metal material layer 106. At least a portion of the metal material layer 109 will serve as the gate G2 of the thin film transistor. In some embodiments, the metal material layer 109 may be or include a gate signal line, and a portion of the gate signal line serves as the gate G2. The material of the metal material layer 109 can be selected from the same candidate materials as the metal material layer 103a, for example, copper, aluminum, molybdenum, titanium, and other metal materials, and can be formed through deposition and patterning processes.

[0107] Referring to Figure 3E, a buffer layer 110 is formed on the side of the dielectric layer 107 away from the insulating layer 105 to cover the side wall of the metal material layer 109 and the surface of the side away from the dielectric layer 107; the material of the buffer layer 110 can be selected from insulating materials such as silicon oxide and silicon nitride, and the buffer layer 110 can be formed by a deposition process such as CVD.

[0108] Next, an active layer AL2 is formed on a side of the buffer layer 110 away from the metal material layer 109 and the dielectric layer 107. A portion of the buffer layer 110 is located between the active layer AL2 and the gate G2 and serves as a gate insulating layer for the thin film transistor. In some embodiments, the active layer AL2 comprises a material different from that of the active layers AL1 and AL3. For example, the active layer AL2 may comprise an oxide semiconductor material such as indium gallium zinc oxide (IGZO), but the present disclosure is not limited thereto. In other embodiments, the second active material layer in which the active layer AL2 is located and the first active material layer in which the active layers AL1 and AL3 are located may also comprise the same type of material, for example, both may be semiconductor materials such as low-temperature polycrystalline silicon or both may be oxide semiconductor materials such as IGZO.

[0109] Referring to Figure 3F , an insulating layer 112 is formed on the side of the buffer layer 110 away from the dielectric layer 107 and the metal layer 109 to cover the sidewalls of the active layer AL2 and its surface away from the buffer layer 110. Subsequently, a metal layer 113 is formed on the side of the insulating layer 112 away from the buffer layer 110 and the active layer AL2. At least a portion of the metal layer 113 serves as the gate G3 of the thin-film transistor T2. A portion of the insulating layer 112 is located between the gate G3 and the active layer AL2 and serves as the gate insulation layer for the thin-film transistor T2. In some embodiments, the metal layer 113 may be or include a gate signal line, with a portion of the gate signal line serving as the gate G3. The insulating layer 112 may be made of the same candidate materials as the insulating layers 102 / 105 and the buffer layer 110. For example, it may include insulating materials such as silicon oxide and silicon nitride, or high-k dielectric materials such as hafnium oxide. It may be formed using a deposition process such as CVD. The material of the metal material layer 113 can be selected from the same candidate materials as the metal material layers 103 and 109 , for example, copper, aluminum, molybdenum, titanium and other metal materials, and can be formed by deposition processes such as PVD and patterning processes.

[0110] 3G , a dielectric layer 115 is formed on a side of the insulating layer 112 away from the buffer layer 110 to cover the sidewalls of the metal material layer 113 and a surface thereof away from the insulating layer 112. The dielectric layer 115 may include a dielectric material such as silicon oxide or silicon nitride and may be formed, for example, by a deposition process such as CVD or a spin coating process.

[0111] 3H , a patterning process is performed on the plurality of dielectric / insulating layers to form a plurality of vias in the dielectric / insulating layers, exposing corresponding active material layers, metal material layers, etc. For example, a first patterning process is performed on dielectric layer 115 to insulating layer 102 to remove portions of the dielectric / insulating layers and form vias VH1, VH5, VH6, and VH7. The first patterning process may include photolithography and etching processes. For example, a photoresist layer is deposited on dielectric layer 115 and patterned using a photolithography process. The patterned photoresist layer is then used to etch the plurality of dielectric / insulating layers to form a plurality of vias in the layers. For example, via VH1 extends through the dielectric layer 115, the insulating layer 112, the buffer layer 110, the dielectric layer 107, the insulating layer 105 and a portion of the insulating layer 102, and exposes a portion of the active layer AL1; via VH6 extends through the dielectric layer 115, the insulating layer 112, the buffer layer 110, the dielectric layer 107 and a portion of the insulating layer 105, and exposes a portion of the metal layer 103b; via VH5 and via VH7 extend through the dielectric layer 115, the insulating layer 112, the buffer layer 110 and a portion of the dielectric layer 107, respectively, and expose portions of the metal layers 106a and 106b.

[0112] Referring to Figure 3I , a second patterning process is performed on multiple dielectric / insulating layers to form vias VH2, VH3, and VH4. Via VH2 extends through dielectric layer 115 and a portion of insulating layer 112, exposing a portion of active layer AL2; via VH3 extends through a portion of dielectric layer 115, exposing a portion of metal layer 113; and via VH4 extends through dielectric layer 115, insulating layer 112, and a portion of buffer layer 110, exposing a portion of metal layer 109. During the patterning process, the etching process has a high selectivity between the dielectric / insulating material and the active / metal material, and the corresponding active / metal layer serves as an etch stop layer during the etching process. It should be understood that the multiple vias VH1-VH7 described above are formed via two patterning processes, but the present disclosure is not limited thereto. In alternative embodiments, multiple vias may be formed via a single patterning process or two or more patterning processes, and the number of vias is not limited to that shown in the figure.

[0113] Referring to FIG3J , a metal layer 116 is formed on the dielectric layer 115. The metal layer 116 includes a plurality of conductive connectors and extends into the plurality of vias VH1-VH7 to electrically connect to the corresponding active layer or metal layer. The method for manufacturing the metal layer 116 may include, for example, depositing a metal material layer on the dielectric layer 115. The metal material layer extends on a side of the dielectric layer 115 away from the insulating layer 112 and fills the vias VH1-VH7 to connect to the corresponding active layer or metal layer. Thereafter, the metal material layer is patterned to form separate source-drain electrodes SD1a and SD2a, conductive connectors GC, a DC signal layer DS, and conductive connectors Ct1 and Ct2. The source-drain electrode SD1a, the source-drain electrode SD2a, the conductive connector GC, the DC signal layer DS, the conductive connectors Ct1 and Ct2 each include conductive vias v1-v7 located in the corresponding vias VH1-VH7, and are electrically connected to the corresponding active layer or metal layer through these conductive vias.

[0114] 4 shows a schematic cross-sectional view of an array substrate 500b according to some other embodiments of the present disclosure. The structure of the array substrate 500b is similar to that of the array substrate 500a, except that the thin film transistor T2 in the array substrate 500b is not a dual-gate structure and does not include a bottom gate.

[0115] Referring to FIG. 4 , in some embodiments, a thin-film transistor T2 includes a gate G3, an active layer AL2, and a gate insulating layer positioned between the gate G3 and the active layer AL2. The thin-film transistor T2 may have a top-gate structure, i.e., the gate G3 is positioned on the side of the active layer AL2 facing away from the substrate 100. In this embodiment, since the bottom gate G2 shown in FIG. 2 is omitted, the conductive via v4 is correspondingly omitted, and the conductive connector GC is connected to the gate G3 only through the conductive via v3. The metal shielding layer MS and the gate G3 are positioned on opposite sides of the active layer AL2, i.e., the gate G3 is positioned on the side of the active layer AL2 facing away from the metal shielding layer MS. The active layer AL2 is positioned between the gate G3 and the metal shielding layer MS. In some embodiments, dielectric materials such as a buffer layer 110 and a dielectric layer 107 are positioned between the active layer AL2 and the metal shielding layer MS, and no other metallic material layers may be positioned between the metal shielding layer 106a and the active layer AL2. The active layer AL2 at least partially overlaps the metal shielding layer MS in a direction perpendicular to the main surface of the base substrate 100. In some embodiments, the orthographic projection of the active layer AL2 on the base substrate 100 is located within the orthographic projection of the metal shielding layer 106a on the base substrate 100; or, at least the orthographic projection of the channel region of the active layer AL2 on the base substrate 100 is located within the orthographic projection of the metal shielding layer 106a on the base substrate 100.

[0116] Similar to the aforementioned embodiments, the metal shielding layer MS is connected to the DC signal terminal and is configured to shield signal crosstalk between thin-film transistors T1 and T2, for example, shield signal crosstalk between their gates G1 and G3. In some embodiments, the metal shielding layer MS is further configured to control or adjust the threshold voltage of the thin-film transistor T2 by selecting the type of DC signal terminal to which it is connected. For example, when the metal shielding layer MS is connected to a negative voltage, the threshold voltage of the thin-film transistor T2 is positively biased; when the metal shielding layer MS is connected to a positive voltage, the threshold voltage of the thin-film transistor T2 is negatively biased. Arranging the active layer AL2 and the metal shielding layer MS to overlap each other can facilitate the metal shielding layer MS's control over the channel region in the active layer AL2, thereby achieving control over the threshold voltage of the thin-film transistor T2. It should be noted that the metal shielding layer MS is not electrically connected to the gate G3; the conductive connector GC connected to the gate G3 and the DC signal layer DS connected to the metal shielding layer MS are electrically isolated from each other.

[0117] The formation process of the array substrate 500b is similar to the formation process of the array substrate 500a shown in Figures 3A to 3J, except that the step of forming the metal material layer 109 / gate G2 in Figure 3D is omitted, and the via VH4 and the conductive through hole v4 are not formed in the steps of Figures 3I to 3J. The remaining steps are similar to those in the aforementioned embodiment and will not be repeated here.

[0118] 5 shows a schematic cross-sectional view of an array substrate 500c according to some other embodiments of the present disclosure. The array substrate 500c is similar to the array substrate 500b, except that the metal shielding layer MS and the electrode plate M2 of the capacitor C1 share the same metal layer 106'.

[0119] Referring to Figure 5 , in some embodiments, the second metal material layer includes a metal layer 106', and the metal layer 106' extends continuously from the region where the thin-film transistor group TS is located to the region where the capacitor C1 is located. For example, the array substrate 500c includes a first region R1 and a second region R2 arranged side by side in a direction parallel to the main surface of the base substrate 100. The thin-film transistor group TS may be located in the first region R1, and the capacitor C1 may be located in the second region R2. The metal layer 106' may extend continuously from the location in the first region R1 where it overlaps with the thin-film transistors T1 and T2 to the location in the second region R2 where it overlaps with the metal layer 103b, and may serve as both the metal shielding layer MS of the signal shielding structure S1 and the electrode plate M2 of the capacitor C1. In other words, the metal shielding layer MS may be co-located with the second metal material layer. It should be noted that the second region R2 may be any region other than the first region R1 where the thin-film transistor group TS is located. The components located in the second region R2 are not limited to the capacitor C1. The second region R2 may alternatively or additionally include any other suitable type of device.

[0120] In some embodiments, the DC signal layer DS is connected to the metal layer 106' through a conductive through-hole v5. The DC signal layer DS may be or be connected to a DC power supply voltage terminal, such as a power supply voltage VDD, but the present disclosure is not limited thereto. In other words, the metal shielding layer MS and the electrode plate M2 are physically and electrically connected to each other and are connected to the same DC signal terminal through the same conductive through-hole v5. Compared to the array substrate 500b, the conductive connector Ct2 including the conductive through-hole v7 may be omitted in the array substrate 500c (Figure 4). The manufacturing process of the array substrate 500c is similar to that of the array substrate 500b, except that, in the patterning process for forming the metal layers 106a and 106b shown in Figure 3C, the metal material layer is patterned into a continuous metal layer 106' in this embodiment, and the conductive connector Ct2 including the conductive through-hole v7 is not formed in the steps of Figures 3H to 3J. In this way, the mask pattern used in the process of forming the metal layer 106 ′ can be simplified, and the number of via holes formed in the process of FIG. 3H to FIG. 3J can be reduced, thereby simplifying the process.

[0121] Figure 6 shows a schematic cross-sectional view of an array substrate 500d according to other embodiments of the present disclosure. Array substrate 500d is similar to array substrate 500b of the aforementioned embodiment, except that the signal shielding structure of array substrate 500d includes not only a metal shielding layer but also a dielectric shielding unit to further enhance the signal shielding capability of the signal shielding structure.

[0122] Referring to FIG. 6 , in some embodiments, in an array substrate 500d , a signal shielding structure S2 may include a metal shielding layer MS and a dielectric shielding unit DS. The dielectric shielding unit DS may be part of an interlayer dielectric structure ILD2. For example, the interlayer dielectric structure ILD2 is disposed between thin-film transistors T1 and T2. Specifically, the interlayer dielectric structure ILD2 may be located between the insulating layer 105 and the buffer layer 110. The metal shielding layer MS may be embedded in the interlayer dielectric structure ILD2, and a portion of the interlayer dielectric structure ILD2 may serve as the dielectric shielding unit DS. For example, the interlayer dielectric structure ILD2 may include a dielectric layer 107 and a dielectric protrusion 108. The dielectric layer 107 extends parallel to the main surface of the base substrate 100. The metal shielding layer MS is, for example, embedded in the dielectric layer 107. The dielectric protrusion 108 may be located on a side of the dielectric layer 107 away from the thin-film transistor T1. For example, dielectric protrusion 108 protrudes from the surface of dielectric layer 107 away from thin-film transistor T1 toward thin-film transistor T2. Dielectric protrusion 108 serves as a dielectric shielding unit DS, which is part of signal shielding structure S2. For example, dielectric shielding unit DS can shield the gate G1 or the gate signal line to which it is attached from the channel region of active layer AL2 from signal transitions.

[0123] In some embodiments, the dielectric layer 107 can also be referred to as the dielectric body of the interlayer dielectric structure ILD2. In some embodiments, the dielectric layer 107 extends continuously from the first region R1 where the thin-film transistor group TS is located to a region outside the first region R1, such as the second region R2. The dielectric protrusion 108 can be disposed in the first region R1 and does not extend into the second region R2. In some embodiments, the dielectric layer 107 and the dielectric protrusion 108 are made of different materials and have a distinct interface therebetween, but the present disclosure is not limited thereto. The dielectric layer 107 and the dielectric protrusion 108 can also comprise the same material. In some embodiments, at least the dielectric protrusion 108 of the interlayer dielectric structure ILD2 is formed from a planarization material (e.g., SOG) and provides a flat surface on the side facing away from the dielectric layer 107.

[0124] In some embodiments, the buffer layer 110, insulating layer 112, and dielectric layer 115 covering the dielectric protrusion 108 may all be conformal layers, and the area directly above the dielectric protrusion 108 may also have a corresponding protrusion. In some embodiments, the active layer AL2 and gate G3 of the thin-film transistor T2 overlap with the dielectric shielding unit DS in direction D1. For example, the orthographic projection of the active layer AL2 on the main surface of the base substrate 100 is within the orthographic projection of the dielectric shielding unit DS on the main surface of the base substrate 100; the orthographic projection of the gate G3 on the main surface of the base substrate 100 may also be within the orthographic projection of the dielectric shielding unit DS on the main surface of the base substrate 100.

[0125] In some embodiments, because the dielectric shielding unit DS is formed from a planarized material layer and has a flat surface, the buffer layer 110 formed thereon also has a flat surface. Consequently, components such as the active layer AL2 of the thin-film transistor T2 are formed on a flat surface, resulting in stable and reliable performance. In other words, the dielectric shielding unit DS can shield the topography of the underlying structure, allowing the thin-film transistor T2 to be formed on a flat surface, thereby improving the stability and reliability of the thin-film transistor T2.

[0126] In some embodiments, the material of the dielectric shielding unit DS is a low-k dielectric material, such as spin-on glass (SOG) or an organic dielectric material such as a polymer. As used herein, a low-k dielectric material refers to a dielectric material having a dielectric constant less than that of silicon oxide. For example, the dielectric constant of the dielectric shielding unit DS is less than the dielectric constant of the insulating layers 102 / 105 / 112. For example, the dielectric constant of the dielectric protrusion 108 may also be less than the dielectric constant of the dielectric layer 107, but the present disclosure is not limited thereto. In embodiments where the dielectric protrusion 108 and the dielectric layer 107 comprise different materials, the dielectric constant of the dielectric protrusion 108 may be less than or equal to 3.5, less than or equal to 3.1, or 3.0; the dielectric constant of the dielectric layer 107 (i.e., the dielectric body portion) may be, for example, in the range of 3.9 to 4.5. For example, in one example, the material of the dielectric protrusion 108 comprises spin-on glass, and the material of the dielectric body portion 107 comprises silicon oxide. In an embodiment where the dielectric protrusion 108 and the dielectric layer 107 include the same material, the dielectric constants of the dielectric protrusion 108 and the dielectric layer 107 may both be less than or equal to 3.5 or even less than or equal to 3.1 or 3.0. For example, the dielectric protrusion 108 and the dielectric layer 107 may both include a low dielectric constant material such as spin-on glass.

[0127] In some embodiments, the thickness of the dielectric shielding unit DS may be greater than 1 μm and may be greater than the thickness of the dielectric layer 107. By providing a dielectric shielding unit DS having a sufficient thickness and a low dielectric constant between the thin film transistors T1 and T2, the parasitic capacitance between the signal lines (e.g., adjacent gate signal lines) of the adjacent thin film transistors T1 and T2 can be reduced, thereby reducing signal crosstalk between the adjacent thin film transistors T1 and T2, such as gate signal crosstalk.

[0128] In this embodiment, both the metal shielding layer MS and the dielectric shielding unit DS can shield signal crosstalk, and the two together constitute the signal shielding structure S2, thereby achieving double shielding of signal crosstalk between adjacent thin film transistors and further improving the signal shielding capability of the signal shielding structure.

[0129] In some embodiments, because the portions of the buffer layer 110, the insulating layer 112, and the dielectric layer 115 located directly above the dielectric shielding unit DS also have a convex shape, the source-drain electrode SD2a and the conductive connector GC located on these layers can be located at a different level than other components in the metal layer 116. For example, the surface of the source-drain electrode SD2a and the conductive connector GC that is away from the dielectric layer 115 (i.e., the top surface shown in the figure) is located at a greater distance from the main surface of the substrate 100 than the surface of the source-drain electrode SD1a, the DC signal terminal DS, and the conductive connectors Ct1 and Ct2 that is away from the dielectric layer 115 (i.e., the top surface shown in the figure) is located from the main surface of the substrate 100.

[0130] In some embodiments, the dielectric shielding unit DS is disposed in the first region R1 where the thin-film transistor group TS resides, at a location overlapping with the thin-film transistors T1 and T2, and does not extend to other regions (e.g., the second region R2). Furthermore, the plurality of conductive vias v1-v7 are disposed on the sides of the dielectric shielding unit DS in a direction parallel to the main surface of the substrate 100 (e.g., direction D2) and are spaced apart from the dielectric shielding unit DS. This ensures that the addition of the dielectric shielding unit DS does not adversely affect the etching process for forming the vias. In some embodiments, the dielectric shielding unit DS is formed on the side of the dielectric layer 107 and the insulating layer 105 away from the metal material layer 103, rather than replacing the insulating layer 105 with the dielectric shielding unit DS. This ensures that the provision of the dielectric shielding unit DS does not affect the capacitance of the capacitor C1.

[0131] In some embodiments, the dielectric shielding unit DS and the metal shielding layer MS overlap, for example, at least partially overlap, in a direction D1 perpendicular to the main surface of the base substrate 100. In this embodiment, the dielectric shielding unit DS is located on a side of the metal shielding layer MS away from the thin-film transistor T1. The metal shielding layer MS may be located between the dielectric shielding unit DS and the gate G1 of the thin-film transistor T1 and connected to the DC signal layer DS via a conductive via v5. In some embodiments, a portion (or an extension) of the metal shielding layer MS extends laterally beyond the sidewalls / edges of the dielectric shielding unit DS in a direction parallel to the main surface of the base substrate 100 (for example, direction D2), and the extension of the metal shielding layer MS serves to overlap the conductive via v5. In this way, the dielectric shielding unit DS can be avoided during the etching process for forming the via for the conductive via v5, preventing the dielectric shielding unit from affecting the etching process for forming the via.

[0132] 7A to 7G illustrate a method for manufacturing an array substrate 500d according to some embodiments of the present disclosure. The method for manufacturing the array substrate 500d is similar to the aforementioned embodiment, except that the formation process of the interlayer dielectric structure ILD2 includes forming a dielectric layer 107 and also forming dielectric protrusions 108.

[0133] For example, referring to FIG7A , in some embodiments, processes similar to those described above with respect to FIG3A to FIG3D are performed to sequentially form a buffer layer 101, active layers AL1 and AL3, an insulating layer 102, a metal material layer 103, an insulating layer 105, a metal material layer 106, and a dielectric layer 107 on a substrate 100. In some embodiments, the dielectric layer 107 includes a dielectric material such as silicon oxide and can be formed by a deposition process such as CVD.

[0134] Referring to FIG. 7B , a dielectric layer 108 ′ is formed on the side of dielectric layer 107 away from insulating layer 105 . In some embodiments, dielectric layer 107 and dielectric layer 108 ′ may also be referred to as a first dielectric layer and a second dielectric layer. Dielectric layer 108 ′ may be a planarized dielectric layer having a flat surface on the side away from dielectric layer 107 . In some embodiments, dielectric layer 108 ′ may be or include a dielectric material such as SOG and may be formed by a spin-coating process, but the present disclosure is not limited thereto. Dielectric layer 108 ′ may include any dielectric material having a low dielectric constant and providing a flat surface. In some embodiments, the material of dielectric layer 108 ′ is different from the material of insulating layers 102 and 105 , and the dielectric constant of dielectric layer 108 ′ is less than the dielectric constant of insulating layers 102 and 105 . The material of dielectric layer 108 ′ may also be different from the material of dielectric layer 107 , and the dielectric constant of dielectric layer 108 ′ may be less than the dielectric constant of dielectric layer 107 . Alternatively, the material of dielectric layer 108' may be similar to or identical to that of dielectric layer 107, and both may have similar or substantially identical dielectric constants. In some embodiments, the difference in dielectric constant between dielectric layer 108' and dielectric layer 107 is less than the difference in dielectric constant between dielectric layer 108' and insulating layer 102 or 105. Using dielectric materials with higher dielectric constants for insulating layers 102 and 105 can help reduce leakage current in thin-film transistors T1 and T3 and increase the capacitance of capacitor C1. Using dielectric materials with lower dielectric constants for dielectric layers 107 and 108' can subsequently reduce signal crosstalk between adjacent metal layers and improve their signal shielding capabilities.

[0135] 7B and 7C , a patterning process is performed on the dielectric layer 108 ′ to remove portions of the dielectric layer 108 ′ and form the dielectric protrusion 108 . The patterning process may include photolithography and etching processes. For example, a patterned mask layer is formed on the dielectric layer 108 ′. The patterned mask layer is, for example, a patterned photoresist layer formed by a photolithography process. The patterned mask layer covers the area where the dielectric protrusion 108 is to be formed and has an opening to expose other portions of the dielectric layer 108 ′. Next, an etching process is performed on the dielectric layer 108 ′ using the patterned mask layer as an etching mask to remove the portions of the dielectric layer 108 ′ exposed by the mask layer, thereby forming the dielectric protrusion 108 and exposing a portion of the surface of the dielectric layer 107 . For example, the etching process removes the dielectric layer 108 ′ located in the second region R2 and may also remove a portion of the dielectric layer 108 ′ located in the first region R1 . In some embodiments, the dielectric protrusion 108 and the dielectric layer 107 together form an interlayer dielectric structure ILD, and the dielectric protrusion 108 can serve as a dielectric shielding unit DS, and together with the metal shielding layer MS form a signal shielding structure S2.

[0136] In this embodiment, the dielectric protrusions 108 are formed only in the region where the thin film transistor groups TS are located to achieve signal shielding between adjacent thin film transistors, and do not extend to other regions of the array substrate. This ensures that the provision of the dielectric protrusions 108 does not affect the subsequent etching process for forming via holes.

[0137] In some embodiments, a portion of the dielectric layer 108' located directly above the metal shielding layer MS remains to form a dielectric protrusion 108, and another portion of the dielectric layer 108' located directly above the metal shielding layer MS is removed during the etching process, thereby causing a portion of the metal shielding layer MS to extend beyond the edge of the dielectric protrusion 108 in the horizontal direction, so that the portion of the metal shielding layer MS can be used for subsequent overlapping of conductive vias.

[0138] Referring to FIG. 7D , a buffer layer 110 is formed on a side of the interlayer dielectric structure ILD away from the insulating layer 105 and the thin-film transistor T1. The buffer layer 110 may conformally extend along the surfaces of the dielectric layer 107 and the dielectric protrusion 108. Next, an active layer AL2 is formed on a side of the buffer layer 110 away from the dielectric protrusion 108. In some embodiments, the active layer AL2 is formed directly above the dielectric protrusion 108 and may be formed within the region where the dielectric protrusion 108 is located. Because the dielectric protrusion 108 is formed from a planarizing material and has a flat surface, the buffer layer 110 formed thereon also has a flat surface. Therefore, forming the active layer AL2 within the region where the dielectric protrusion 108 is located allows the entire active layer AL2 to be formed on a flat surface, avoiding instability issues that may arise from forming the active layer AL2 on an uneven surface, thereby improving the reliability of the active layer AL2 and the thin-film transistor including it.

[0139] Referring to FIG7E , an insulating layer 112 is formed on a side of the buffer layer 110 remote from the interlayer dielectric structure ILD, covering the sidewalls of the active layer AL2 and its surface remote from the buffer layer 110. The insulating layer 112 may also have a morphology similar to that of the interlayer dielectric structure ILD. Subsequently, a metal material layer 113 is formed on a side of the insulating layer 112 remote from the active layer AL2. At least a portion of the metal material layer 113 serves as the gate G3 of the thin film transistor T2.

[0140] 7F and 7G , a dielectric layer 115 is formed on the side of the insulating layer 112 away from the buffer layer 110 to cover the sidewalls of the metal material layer 113 and its surface away from the insulating layer 112. Subsequently, one or more patterning processes are performed on the multiple dielectric / insulating material layers, such as the dielectric layer, the insulating layer, and the buffer layer, to form a plurality of vias VH1, VH2, VH3, VH5, VH6, and VH7 in these dielectric / insulating material layers. The one or more patterning processes include an etching process and are similar to the processes described with respect to FIG. 3H and FIG. 3I in the aforementioned embodiment, and are not further described here.

[0141] In some embodiments, because the dielectric protrusions 108 are formed only between adjacent thin-film transistors in the first region where the thin-film transistor group is located and do not extend into other regions, during the etching process for forming the vias VH1-VH7, the multiple vias are formed on the sides of or directly above the dielectric protrusions 108 and do not pass through the dielectric protrusions 108. As a result, the number and / or thickness of material layers required to be removed during the etching process for forming the vias in this embodiment can be substantially the same as the number and / or thickness of material layers required to be removed during the etching process for forming the vias in the aforementioned embodiment without the dielectric protrusions 108 ( FIGS. 3H to 3I ). In other words, the provision of the dielectric protrusions 108 does not affect the etching process for forming the vias.

[0142] In this embodiment, a portion (or extension) of the metal shielding layer MS extends laterally beyond the edge of the dielectric shielding unit DS. The via VH5 is formed above the extension of the metal shielding layer MS and exposes a portion of the extension. In other words, the via VH5 avoids the area where the dielectric shielding unit DS is located and does not pass through the dielectric shielding unit DS, thus preventing the dielectric shielding unit DS from interfering with the etching process for forming the via.

[0143] Referring to FIG. 7H , a metal layer 116 is then formed on the dielectric layer 115. The metal layer 116 includes source-drain electrodes SD1a and SD2a, conductive connectors GC, Ct1 and Ct2, and a DC signal layer DS. In some embodiments, because the active layer AL2 and gate G3 of the thin-film transistor T2 are formed above the dielectric protrusion 108, the source-drain electrode SD2a connected to the active layer AL2 and the conductive connector GC connected to the gate G3 are located at a higher level than other portions of the metal layer 116. Herein, the level at which a component is located refers to its height relative to the main surface of the substrate 100 in the direction D1. In other words, the top surfaces of the source-drain electrode SD2a and the conductive connector GC are located farther from the main surface of the substrate 100 than the other portions of the metal layer 116 (e.g., the DC signal layer DS).

[0144] 8 shows a schematic cross-sectional view of an array substrate 500e according to some other embodiments of the present disclosure. The array substrate 500e is similar to the array substrate 500d, except that the positional relationship between the dielectric shielding unit DS and the metal shielding layer MS is different.

[0145] Referring to FIG. 8 , in some embodiments, the metal shielding layer MS is located on a side of the dielectric shielding unit DS that is away from the thin-film transistor T1 and closer to the thin-film transistor T2. For example, the metal shielding layer MS may be located between the dielectric shielding unit DS and the active layer AL2 of the thin-film transistor T2. For example, the metal shielding layer MS is embedded in the buffer layer 110, with a portion of the buffer layer 110 located between the metal shielding layer MS and the active layer AL2, thereby separating the metal shielding layer MS from the active layer AL2. The orthographic projection of the metal shielding layer MS on the main surface of the base substrate 100 overlaps, for example, partially or completely, with the orthographic projection of the dielectric shielding unit DS on the main surface of the base substrate 100.

[0146] In some embodiments, the metal shielding layer MS is located on the surface of the dielectric shielding unit DS on the side near the thin-film transistor T2 (i.e., the top surface shown in the figure) and is in direct contact with the surface of the dielectric shielding unit DS. The metal shielding layer MS is connected to the DC signal layer DS via a conductive via v5. In this embodiment, because the metal shielding layer MS is located above the dielectric shielding unit DS, the influence of the dielectric shielding unit DS does not need to be considered during the etching process for forming the via hole for the conductive via v5. Therefore, the metal shielding layer MS does not need to extend laterally beyond the edge of the dielectric shielding unit DS. In some embodiments, the orthographic projection of the metal shielding layer MS on the main surface of the base substrate 100 may be located within the orthographic projection range of the dielectric shielding unit DS on the main surface of the base substrate 100, but the present disclosure is not limited to this.

[0147] In this embodiment, the metal shielding layer MS is disposed in a different layer from the electrode plate M2 of the capacitor C1. For example, the electrode plate M2 is disposed in the second metal material layer where the metal layer 106b is located, while the metal shielding layer MS can be disposed in the third metal material layer 109'. The third metal material layer 109' can also be referred to as an additional metal layer.

[0148] In this embodiment, the metal shielding layer MS is connected to the DC signal terminal and is not connected to the conductive connector GC, and therefore is not connected to the gate G3. Furthermore, similar to array substrate 500b, the threshold voltage of the thin-film transistor T2 can be controlled or adjusted by selecting the type of DC signal terminal to which the metal shielding layer MS is connected. Furthermore, in this embodiment, the metal shielding layer MS is closer to the active layer AL2, which further facilitates the metal shielding layer MS's control of the threshold voltage of the thin-film transistor T2.

[0149] 9 shows a schematic cross-sectional view of an array substrate 500f according to some other embodiments of the present disclosure. The array substrate 500f is similar to the array substrate 500e, except that the metal material layer 109' is connected to the gate G3 and serves as the bottom gate of the thin film transistor T2.

[0150] Referring to Figure 9, in some embodiments, the metal material layer 109' is connected to the conductive connector GC via a conductive via v5, and is further electrically connected to the gate (i.e., top gate) G3 via the conductive connector GC. At least a portion of the metal material layer 109' serves as the bottom gate G2 of the thin-film transistor T2. For example, the metal material layer 109' may be or include a gate signal line, and a portion of this gate signal line serves as the bottom gate G2 of the thin-film transistor T2. In this embodiment, the signal shielding structure S3 comprises only the dielectric shielding unit DS, without the metal shielding layer. Due to the low dielectric constant and large thickness of the dielectric shielding unit DS, the dielectric shielding unit DS alone can effectively shield signal crosstalk between the thin-film transistors T1 and T2, thus omitting the metal shielding layer. Using the metal material layer 109' as the bottom gate G2 of the thin-film transistor T2 gives the thin-film transistor T2 a dual-gate structure, allowing the gates G2 and G3 to jointly and more stably control the channel region of the active layer AL2.

[0151] 10 shows a schematic cross-sectional view of an array substrate 500g according to some other embodiments of the present disclosure. The array substrate 500g is similar to the array substrate 500d, except that the interlayer dielectric structure ILD3 of the array substrate 500g is integrally formed.

[0152] Referring to FIG. 10 , in some embodiments, the interlayer dielectric structure ILD includes a dielectric main portion 108 a and a dielectric protrusion 108 b. The positions of the dielectric main portion 108 a and the dielectric protrusion 108 b are similar to those of the dielectric layer 107 and the dielectric protrusion 108 in the aforementioned embodiments. For example, the dielectric main portion 108 b extends in a direction parallel to the main surface of the substrate 100 (e.g., direction D2) and may extend from a first region R1 where the thin-film transistor group TS is located to a second region R2 where the capacitor C1 is located. The dielectric protrusion 108 a is located in the first region R1 and between adjacent thin-film transistors T1 and T2 in the thin-film transistor group TS, serving as a dielectric shielding unit DS, at least partially forming a signal shielding structure. The dielectric protrusion 108 a protrudes from the surface of the dielectric main portion 108 b facing away from the insulating layer 105 and the thin-film transistor T1 (i.e., the top surface shown in the figure) toward the thin-film transistor T2.

[0153] In some embodiments, the dielectric body portion 108a and the dielectric protrusion 108b of the interlayer dielectric structure ILD are integrally formed. That is, the dielectric body portion 108a and the dielectric protrusion 108b comprise the same material and have no interface therebetween. In some embodiments, the material of the interlayer dielectric structure ILD is substantially the same as that of the dielectric protrusion 108 in the aforementioned embodiments, such as a dielectric material with a relatively low dielectric constant, such as SOG. In some embodiments, the dielectric constant of the interlayer dielectric structure ILD can be lower than the dielectric constant of the insulating layers 102 / 105 / 112.

[0154] In some embodiments, the dielectric protrusion 108b of the interlayer dielectric structure ILD serves as a dielectric shielding unit DS and together with the metal shielding layer MS forms a signal shielding structure S2 for shielding signal crosstalk between the thin film transistors T1 and T2. In some embodiments, the metal shielding layer MS is embedded in the interlayer dielectric structure ILD. For example, the metal shielding layer MS is embedded in the dielectric main portion 108a and overlaps (e.g., partially overlaps) with the dielectric protrusion 108b in the direction D1. Similar to the aforementioned embodiments, a portion of the metal shielding layer MS extends laterally beyond the edge of the dielectric protrusion 108b in a direction parallel to the main surface of the substrate 100 (e.g., direction D2) to facilitate overlapping of the conductive via v5. In some embodiments, the thickness of the dielectric main portion 108a is greater than the thickness of the metal material layer 106 in which the metal shielding layer MS is located, so that the dielectric main portion 108a covers the surface of the metal material layer 106 away from the insulating layer 105 (i.e., the top surface shown in the figure). Other structural features of the array substrate 500g are similar to those of the array substrate 500d and are not described again here.

[0155] 11A to 11C are schematic cross-sectional views illustrating structures in various process steps of a method for manufacturing an array substrate 500 g according to some embodiments of the present disclosure.

[0156] 11A , process steps similar to those shown in FIG. 3A to FIG. 3C are performed to form a buffer layer 101, active layers AL1 and AL3, an insulating layer 102, a metal material layer 103, an insulating layer 105, and a metal material layer 106 on a substrate 100. Next, a dielectric layer 108″ is formed on a side of the insulating layer 105 away from the insulating layer 102 and the metal material layer 103 to cover the sidewalls of the metal material layer 106 and the surface thereof away from the insulating layer 105. The material and manufacturing method of the dielectric layer 108″ are similar to those of the dielectric layer 108′ formed in the step of FIG. 7B of the aforementioned embodiment. For example, the dielectric layer 108″ may include a dielectric material with a low dielectric constant, such as spin-on glass (SOG), and may be formed by a spin coating process. Compared to the process steps of first forming the dielectric layer 107 and then forming the dielectric layer 108' in the manufacturing method of the array substrate 500d in the aforementioned embodiment, in the present embodiment, the step of forming the dielectric layer 107 is omitted, and the dielectric layer 108" is directly formed to the thickness required for the subsequent dielectric protrusions after forming the metal material layer 106. For example, the thickness of the dielectric layer 108" in the present embodiment may be substantially equal to the sum of the thicknesses of the dielectric layer 107 and the dielectric layer 108' shown in Figure 7B in the aforementioned embodiment.

[0157] 11A to 11B , the dielectric layer 108 ″ is then subjected to a patterning process to remove a portion of the dielectric layer 108 ″ and form an interlayer dielectric structure ILD3 including a dielectric main portion 108 a and a dielectric protrusion 108 b. In some embodiments, the patterning process may include the following process steps: forming a patterned mask layer over the dielectric layer 108 ″, the patterned mask layer may be or include a patterned photoresist layer; the patterned mask layer covers a portion of the dielectric layer 108 ″ located in the first region R1 where the dielectric protrusion 108 b is to be formed (e.g., the first portion), and exposes other portions of the dielectric layer 108 ″ (e.g., the second portion, which may include the dielectric layer 108 ″ located in the second region, and may also include a portion of the dielectric layer 108 ″ located in the first region R1); using the patterned mask layer as The etching mask performs an etching process on the dielectric layer 108″ to remove a portion of the dielectric layer 108″ exposed by the patterned mask layer. The etching process reduces the thickness of the second portion of the dielectric layer 108″ without completely removing the second portion of the dielectric layer 108″, thereby forming a thinner dielectric body portion 108a and a thicker dielectric protrusion 108b. In other words, the thickness of the dielectric protrusion 108b is greater than the thickness of the dielectric body portion 108a. In some embodiments, the amount of dielectric layer 108″ removed, and thus the thickness of the dielectric body portion 108a, can be controlled by controlling the etching time. For example, the thickness of the dielectric body portion 108a is at least greater than the thickness of the metal material layer 106, so that the dielectric body portion 108a can cover the sidewalls of the metal material layer 106 and the surface of the metal material layer 106 on the side away from the insulating layer 105. In some embodiments, the thickness of the dielectric body portion 108a can be approximately equal to the thickness of the dielectric layer 107 in the aforementioned embodiment. The dielectric protrusion 108 b protrudes upward from the top surface of the dielectric body portion 108 a away from the base substrate 100 and the thin film transistor T1 , and serves as a dielectric shielding unit and is subsequently used as a part of a signal shielding structure.

[0158] 11B and 11C , process steps similar to those shown in FIG. 7D to 7H are then performed to form components such as a buffer layer 110, an active layer AL2, an insulating layer 112, a metal material layer 113, a dielectric layer 115, and a metal layer 116 on the interlayer dielectric structure ILD3. The methods for manufacturing these material layers are substantially the same as those in the previous embodiment and are not further described here.

[0159] In this embodiment, array substrate 500g is based on array substrate 500d, except that the interlayer dielectric structure ILD2 including the dielectric layer 107 and the dielectric protrusions 108 is replaced with an integrally formed interlayer dielectric structure ILD3. It should be understood that this embodiment can also be applied to array substrates 500e and 500f, replacing the interlayer dielectric structures in array substrates 500e and 500f with an integrally formed interlayer dielectric structure ILD3.

[0160] In this embodiment, after forming metal layer 106, an interlayer dielectric structure is formed directly using a dielectric shielding material, omitting the step of forming dielectric layer 107 and simplifying the manufacturing process. Furthermore, the interlayer dielectric structure is entirely made of low-k dielectric materials, further enhancing the signal shielding capability of the portion located between thin-film transistors T1 and T2.

[0161] 12 and 13 are schematic cross-sectional views of array substrates 500h and 500i according to other embodiments of the present disclosure.

[0162] Referring to Figures 12 and 13 , array substrates 500h and 500i are similar to array substrates 500d ( Figure 6 ) and 500g ( Figure 10 ), respectively. The difference is that the metal shielding layer MS is omitted in array substrates 500h and 500i, and the conductive via v5 and the portion of the metal layer 116 connected thereto are correspondingly omitted. Array substrates 500h and 500i utilize dielectric protrusions 108 and 108b of interlayer dielectric structures ILD2 and ILD3, respectively, as dielectric shielding units DS. In this embodiment, the signal shielding structure S3 may include only the dielectric shielding unit DS. Because the dielectric shielding unit DS has a low dielectric constant and is sufficiently thick, it alone provides good signal shielding capabilities, thus omitting the metal shielding layer. Furthermore, because the dielectric shielding unit DS is formed from a planarized material, it not only shields the electrical signals of adjacent thin-film transistors but also the topography of the underlying material layer, thereby providing a flat surface for the components formed thereon, thereby ensuring or improving the stability and other device characteristics of the thin-film transistor T2 formed thereon. In some embodiments, the thin film transistor T2 may have good characteristics without providing a bottom gate.

[0163] 14 shows a schematic block diagram of an array substrate 500 according to some embodiments of the present disclosure. The array substrate 500 may be any one of the array substrates 500a-500i described above.

[0164] Referring to FIG. 14 , in some embodiments, an array substrate 500 includes a plurality of sub-pixel driving circuits PC, for example, arranged in an array. Each sub-pixel driving circuit PC may be composed of a plurality of thin-film transistors and capacitors. In some embodiments, thin-film transistors T1 and T2 in the thin-film transistor group TS of the array substrates 500 a - 500 i are included in the same sub-pixel driving circuit PC. In some embodiments, one or more sub-pixel driving circuits PC include thin-film transistors in a stacked arrangement, for example, a thin-film transistor group TS including at least thin-film transistors T1 and T2.

[0165] In some embodiments, the array substrate 500 may include a plurality of thin film transistor groups TS arranged in an array, and each thin film transistor group TS is configured to be formed in a sub-pixel driving circuit. Each thin film transistor group TS may include one or more groups of thin film transistors arranged in a stacked manner. For example, the thin film transistor group TS may include multiple thin film transistor subgroups, and the multiple thin film transistor subgroups may be arranged side by side and spaced apart from each other in a direction parallel to the main surface of the substrate, wherein each thin film transistor subgroup includes multiple thin film transistors stacked in a direction perpendicular to the main surface of the substrate. For example, as shown in Figure 14, the thin film transistor group TS may include a first thin film transistor subgroup consisting of a first thin film transistor T1 and a second thin film transistor T2, and a second thin film transistor subgroup consisting of a third thin film transistor T3A and a fourth thin film transistor T4A. It should be noted that a signal shielding structure is provided between adjacent stacked thin film transistors in each thin film transistor subgroup to shield signal crosstalk between adjacent thin film transistors. For example, an additional signal shielding structure is provided between the third thin-film transistor T3A and the fourth thin-film transistor T4A. The additional signal shielding structure may be any of the aforementioned signal shielding structures. The structural and positional relationship between the third thin-film transistor T3A, the fourth thin-film transistor T4A, and the additional signal shielding structure is similar to that described above with respect to the first thin-film transistor T1, the second thin-film transistor T2, and the signal shielding structure, and will not be further described herein. It should be understood that the number of thin-film transistors included in the thin-film transistor group TS in each sub-pixel driving circuit PC shown in the figures is merely illustrative and is not intended to limit the present disclosure. The number of thin-film transistors included in the thin-film transistor group TS in different sub-pixel driving circuits PC may be the same or different.

[0166] The array substrate 500 of the present disclosure can be applied to various display devices, such as LED display devices, OLED display devices, etc. In these display devices, the sub-pixel driving circuit of the array substrate is used to drive the light-emitting devices to emit light.

[0167] FIG. 15A shows a schematic block diagram of a display device 600 according to some embodiments of the present disclosure.

[0168] Referring to FIG. 15A , in some embodiments, a display device 600 may be a light-emitting diode (LED) display device, such as a micro-LED display device or a sub-millimeter LED (Mini-LED) display device. The display device 600 may include an array substrate 500 and a plurality of light-emitting diode chips LC. The array substrate 500 may be selected from any of the array substrates 500 a to 500 i described in the aforementioned embodiments. The light-emitting diode chips LC may be inorganic light-emitting diode chips, such as micro-LED chips or Mini-LED chips. Each light-emitting diode chip PC may serve as a sub-pixel of the display device 600.

[0169] The array substrate 500 and the plurality of LED chips LC are electrically connected to each other. In this embodiment, the array substrate 500 serves as a driving substrate (or driving backplane) for the display device 600 and is used to drive the plurality of LED chips PC to emit light. For example, the array substrate 500 may include a plurality of sub-pixel driving circuits PC, each of which may be connected to a corresponding LED chip LC to drive the corresponding LED chip LC to emit light.

[0170] In some embodiments, the sub-pixel driving circuit PC includes a plurality of thin film transistors and capacitors, some of which are stacked together as thin film transistor groups, thereby reducing the pixel size and improving the resolution of the display device. On the other hand, in an embodiment of the present disclosure, a signal shielding structure is provided between the stacked thin film transistors to shield the signal crosstalk between adjacent thin film transistors, thereby improving the reliability and performance of the display device, thereby meeting the display function of a high-resolution display device. For example, the sub-pixel driving circuit PC may include the thin film transistor group TS described in the aforementioned embodiment with respect to the array substrate. In some embodiments, the thin film transistor group TS in the array substrates 500a-500i is included in the same sub-pixel driving circuit PC.

[0171] In some embodiments, the array substrate 500 of the display device 600 has a high resolution, for example, greater than 300 pixels per inch (PPI), and can be applied to near-eye display applications such as mobile phones, but the present disclosure is not limited thereto. The display device 600 can be applied to a variety of fields, such as flat panel displays; virtual reality (VR), augmented reality (AR), mixed reality (MR) displays; as well as spatial displays, flexible transparent displays, wearable / implantable optoelectronic devices, optical communications / interconnects, medical detection, smart car lights, and other fields.

[0172] FIG15B shows a schematic diagram of a sub-pixel driving circuit PC of a display device 600 according to some embodiments of the present disclosure.

[0173] Referring to FIG. 15B , in some embodiments, the sub-pixel driving circuit PC employs a combined pulse amplitude modulation (PAM) and pulse width modulation (PWM) operating mode. For example, the PAM mode is used at low currents to reduce power consumption, while the PWM mode is used at high currents to reduce instability in the LED display effect under high current driving conditions.

[0174] For example, the sub-pixel driving circuit PC may include a first reset transistor T1a, a threshold compensation transistor T2a, a driving transistor T3a, a first data writing transistor T4a, a first emission control transistor T5a, a second emission control transistor T6a, a second reset transistor T7a, a first storage capacitor Cst1, and a light-emission signal control sub-circuit 8. The sub-pixel driving circuit PC is configured to drive the light-emitting device LD to emit light. In some embodiments, the light-emitting device LD may be the light-emitting diode chip LC shown in FIG. 15A , but the present disclosure is not limited thereto.

[0175] In some embodiments, each transistor in the pixel driving circuit PC may be a low-temperature polysilicon thin-film transistor or an oxide thin-film transistor. The active layer of the low-temperature polysilicon thin-film transistor is made of a semiconductor material such as low-temperature polysilicon, while the active layer of the oxide thin-film transistor is made of an oxide semiconductor material such as IGZO. Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on an array substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, thereby achieving low-frequency driving, reducing power consumption, and improving display quality.

[0176] Each of the multiple transistors in the pixel driving circuit PC includes a gate, a first electrode, and a second electrode. The first electrode and the second electrode may be a source electrode and a drain electrode, respectively. It should be understood that the source electrode and the drain electrode of the transistor may be interchangeable. That is, the first electrode and the second electrode may also be a drain electrode and a source electrode, respectively.

[0177] In some embodiments, as shown in FIG15B , a first reset transistor T1a is electrically connected to the gate of the driving transistor T3a and is configured to reset the gate of the driving transistor T3a. A second reset transistor T7a is electrically connected to the anode of the light-emitting device LD and is configured to reset the anode of the light-emitting device LD. For example, the gate of the first reset transistor T1a is electrically connected to the reset control line Rst1, the first electrode of the first reset transistor T1 is electrically connected to the initial power supply terminal Vini, and the second electrode of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7a is electrically connected to the reset control line Rst2, the first electrode of the second reset transistor T7a is electrically connected to the initial power supply terminal Vini, and the second electrode of the second reset transistor T7 is electrically connected to the anode of the light-emitting device LD. The cathode of the light-emitting device LD can be connected to a first power supply voltage terminal, such as the power supply voltage VSS.

[0178] The gate of the first data write transistor T4a is connected to the first scan signal line and is configured to receive the first scan signal GA1. The first electrode of the first data write transistor T4a is connected to the data signal line and is configured to receive the first data signal Data1. The second electrode of the first data write transistor T4a is connected to the first electrode of the drive transistor T3a. For example, during the data write and compensation phase, the first data write transistor T4a can be turned on in response to the first scan signal GA1, write the data signal Data1 into the first electrode of the drive transistor T3a, and store the data signal in the storage capacitor Cst1. For example, during the light-emitting phase, a drive current can be generated based on the data signal to drive the light-emitting device LD to emit light.

[0179] The gate of compensation transistor T2a is connected to the second scan signal line and is configured to receive the second scan signal GA2. The first electrode and second electrode of compensation transistor T2a are electrically connected to the second electrode and gate of drive transistor T3a, respectively. Compensation transistor T2a is configured to perform threshold compensation for drive transistor T3a in response to the second scan signal GA2. The first scan signal line and the second scan signal line can be the same or different scan signal lines.

[0180] The first storage capacitor Cst1 includes a first electrode plate and a second electrode plate. The first electrode plate is connected to a second power supply voltage terminal, for example, to a power supply voltage VDD, and the second electrode plate is connected to the gate of the driving transistor T3a. The first storage capacitor Cst1 is configured to store the first data signal Data1 written by the first data write transistor T4a. For example, during the data write and compensation phase, the compensation transistor T2a can be turned on in response to the second scan signal GA2, thereby storing the data signal Data1 written by the first data write transistor T4a in the first storage capacitor Cst1. For example, during both the data write and compensation phases, the compensation transistor T2a can electrically connect the gate and the second electrode of the driving transistor T3a, thereby storing information related to the threshold voltage of the driving transistor T3a in the first storage capacitor Cst1. Subsequently, for example, during the light-emitting phase, the data signal and the threshold voltage-related signal stored in the storage capacitor Cst1 can be used to control the driving transistor T3a, so that the output of the driving transistor T3a is compensated.

[0181] The first emission control transistor T5a is connected to a first electrode and a second power supply voltage terminal (e.g., a power supply voltage VDD) of the driving transistor T3a, and is configured to apply the power supply voltage VDD to the first electrode of the driving transistor T3a in response to a light emission control signal EM. For example, a gate of the first emission control transistor T5a is connected to a light emission control line to receive the light emission control signal EM, a first electrode of the first emission control transistor T5a is connected to the second power supply voltage terminal to receive the power supply voltage VDD, and a second electrode of the first emission control transistor T5a is connected to the first electrode of the driving transistor T3a.

[0182] The second light-emission control transistor T6a is connected to the light-emission signal control sub-circuit 8, the anode of the light-emitting device LD, and the second electrode of the driving transistor T3a, and is configured to apply a driving current to the light-emitting device LD under the control of the light-emission signal control sub-circuit 8 and the driving transistor T3a. For example, the gate of the second light-emission control transistor T6a is connected to the light-emission signal control sub-circuit 8 to receive the light-emission control signal, the first electrode of the second light-emission control transistor T6a is connected to the second electrode of the driving transistor T3a, and the second electrode of the second light-emission control transistor T6a is connected to the anode of the light-emitting device LD.

[0183] In this example, the first node N1 is the connection point of the first storage capacitor Cst1, the first reset transistor T1a, the driving transistor T3a and the threshold compensation transistor T2a, the second node N2 is the connection point of the first light-emitting control transistor T5a, the data writing transistor T4a and the driving transistor T3a, the third node N3 is the connection point of the driving transistor T3a, the threshold compensation transistor T2a and the second light-emitting control transistor T6a, and the fourth node N4 is the connection point of the second light-emitting control transistor T6a, the second reset transistor T7a and the light-emitting device LD.

[0184] In some embodiments, the light-emitting signal control subcircuit 8 includes a first selection transistor T8a, a second selection transistor T9a, a second data writing transistor T10a, and a second storage capacitor Cst2. The second data writing transistor T10a is used to write the second data signal Data2 into the second storage capacitor Cst2 under the control of the third scanning signal GA3. For example, the gate of the second data writing transistor T10a is connected to the third scanning signal line and is configured to receive the third scanning signal GA3; the first electrode of the second data writing transistor T10a is connected to the second data signal line and is configured to receive the second data signal Data2; the second electrode of the second data writing transistor T10a is connected to the first electrode of the second storage capacitor Cst2; the second electrode of the second storage capacitor Cst2 can be connected to the common voltage Vcom, or can be connected to other power supply voltage terminals.

[0185] The first selection transistor T8a and the second selection transistor T9a are respectively connected to the second storage capacitor Cst2 and the second light-emitting control transistor T6a, wherein the first selection transistor T8a is used to turn on or off the connection between the first light-emitting control signal EM1 and the second light-emitting control transistor T6a under the control of the first data sub-signal of the second data signal Data2; the second selection transistor T9a is used to turn on or off the connection between the second light-emitting control signal EM2 and the second light-emitting control transistor T6a under the control of the second data sub-signal of the second data signal Data2.

[0186] For example, the gate of the first selection transistor T8a is connected to the first electrode of the second storage capacitor Cst2; the first electrode of the first selection transistor T8a is connected to the first emission control signal line to be configured to receive the first emission control signal EM1; the second electrode of the first selection transistor T8a is connected to the gate of the second emission control transistor T6a. The gate of the second selection transistor T9a is connected to the first electrode of the second storage capacitor Cst2; the first electrode of the second selection transistor T9a is connected to the second emission control signal line to be configured to receive the second emission control signal EM2; and the second electrode of the second selection transistor T9a is connected to the gate of the second emission control transistor T6a.

[0187] In some embodiments, the light emitting signal control subcircuit 8 is a NOT gate circuit and is configured such that when the first selection transistor T8a is turned on, the second selection transistor T9a is turned off. Alternatively, when the second selection subcircuit T9a is turned on, the first selection transistor T8a is turned off.

[0188] In some embodiments, the sub-pixel driver circuit PC can implement a combined PWM and PAM operating mode to control the light emission of the light-emitting device LD during the light emission process. For example, PWM can be used to control the light emission duration of the light-emitting device LD, while PAM can be used to control the brightness of the light-emitting device LD. For example, the PAM mode can be used at low currents to reduce power consumption, while the PWM mode can be used at high currents to reduce the instability of the LED display effect under high current driving conditions.

[0189] For example, the first data signal Data1 is a PAM signal, while the second data signal Data2 is a PWM signal. The PAM signal is written into the driving transistor T3a via a writing circuit consisting of the first data signal transistor T4a and the compensation transistor T2a, thereby controlling the magnitude of the driving current applied by the driving transistor T3a to the light-emitting device LD, thereby achieving pulse amplitude modulation.

[0190] In some embodiments, the second data signal Data2 is a signal for pulse width modulation. For example, the second data signal Data2 may include a first data sub-signal and a second data sub-signal. The first data sub-signal is used to control the first select transistor T8a to be turned on and the second select transistor T9a to be turned off. The second data sub-signal is used to control the second select transistor T9a to be turned on and the first select transistor T8a to be turned off. The pulse width of the first data sub-signal corresponds to the period during which the first emission control signal EM1 turns on the second emission control transistor T6a, and the pulse width of the second data sub-signal corresponds to the period during which the second emission control signal EM2 turns on the second emission control transistor T6a.

[0191] In some embodiments, the first light-emission control signal EM1 is a first pulse-width modulated signal used to control the first light-emission duration of the light-emitting device LD under the drive of the first data sub-signal. The second light-emission control signal EM2 is a second pulse-width modulated signal used to control the second light-emission duration of the light-emitting device LD under the drive of the second data sub-signal. Therefore, the light-emission duration of the light-emitting device LD is controlled by the light-emission signal control sub-circuit 8, thereby achieving pulse-width modulation.

[0192] In other embodiments, the light signal control subcircuit 8 may be a dimming circuit that implements PAM and PWM. The second data signal Data2 may be a dimming control signal and include a first data sub-signal and a second data sub-signal. The first light control signal EM1 may be a pulse width modulation signal, while the second light control signal EM2 may be a signal for pulse amplitude modulation. The first data sub-signal is used to control the conduction of the first selection transistor T8a and the disconnection of the second selection transistor T9a. The first selection transistor T8a may transmit the first light control signal (i.e., pulse width modulation signal) EM1 to the second light control transistor T6a based on the first data sub-signal, thereby implementing pulse width modulation and thus controlling the light emission duration of the light-emitting device LD. The second data sub-signal is used to control the conduction of the second selection transistor T9a and the disconnection of the first selection transistor T8a. The second selection transistor T9a may transmit the second light control signal EM2 to the second light control transistor T6a based on the second data sub-signal, thereby implementing pulse amplitude modulation and thus controlling the light emission brightness of the light-emitting device LD.

[0193] In some embodiments, the thin film transistors T1 and T2 in the thin film transistor group described with reference to Figures 2 to 13 may be transistors T2a and T4a in the sub-pixel driving circuit, or may be transistors T5a and T10a, respectively, but the present disclosure is not limited thereto.

[0194] In some embodiments, by stacking the thin film transistors in the array substrate, the pixel size can be reduced. In addition, the use of oxide thin film transistors as switching transistors can reduce leakage current, thereby correspondingly reducing the size of the storage capacitor to further reduce the pixel size; in this way, the resolution of the display device can be effectively improved. On the other hand, the sub-pixel driving circuit uses an inverter circuit module composed of transistors T8a to T10a to reduce the number of transistors in the PWM module, thereby also improving the resolution. In some embodiments, the display device 600 is a micro-LED display device, and its resolution can be increased to more than 300PPI. Moreover, providing a signal shielding structure between the stacked thin film transistors can effectively shield the signal crosstalk between adjacent thin film transistors, thereby enabling each thin film transistor to operate reliably and stably, thereby realizing the display function of a high-resolution display device.

[0195] The pixel driving circuit of the present application is described above using 10T2C as an example, but the present disclosure is not limited to this. It should be understood that the present application can adopt any suitable pixel driving circuit based on product requirements, such as 2T1C, 4T1C, 6T1C, 7T1C, or 8T1C pixel driving circuits. The signal shielding structure of the embodiment of the present disclosure can be applied to various pixel driving circuits and arranged between stacked thin film transistors to shield signal crosstalk between adjacent thin film transistors.

[0196] FIG16 shows a schematic block diagram of a display device D according to some other embodiments of the present disclosure.

[0197] In some embodiments, the display device D may be an OLED display device and may be or include any of the above-mentioned array substrates 500a-500i. For example, the display device D may include a plurality of pixel units arranged in an array. For example, each pixel unit may include a sub-pixel driving circuit PC and a light-emitting device, and the sub-pixel driving circuit PC is configured to drive the light-emitting device to emit light. The sub-pixel driving circuit PC may include a plurality of thin-film transistors and capacitors. The plurality of thin-film transistors may include a thin-film transistor group TS, and a signal shielding structure is provided between adjacent thin-film transistors in the thin-film transistor group TS to shield signal crosstalk between adjacent thin-film transistors. The light-emitting device may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.

[0198] In the above embodiments, the application of the array substrate to an LED or OLED display device is used as an example for description, but the present disclosure is not limited thereto. In other embodiments, the array substrate of the present disclosure may also be applied to other types of display devices. It should be understood that the concept of providing a signal shielding structure between stacked thin-film transistors in the embodiments of the present disclosure may be applied to any display device or other type of electronic device including stacked thin-film transistors.

[0199] Figure 17 shows an SEM image of an array substrate according to some embodiments of the present disclosure. Figure 17 corresponds to the array substrate of the embodiment shown in Figure 2, and for the sake of simplicity, Figure 17 mainly shows the gate G1 of the thin film transistor T1, the metal shielding layer MS, the gate G2 of the thin film transistor T2, the active layer AL2 and the gate G3, and the insulating / dielectric material layers between these material layers.

[0200] 2 and 17 , in some embodiments, the insulating layer 105 formed on the metal layer 103a extends along the surface of the metal layer 103a and is, for example, conformal to the metal layer 103a. That is, the insulating layer 105 located on the gate G1 has substantially the same morphology as the gate G1. Consequently, the metal shield layer MS formed on the insulating layer 105 also has substantially the same morphology as the underlying material layer (gate G1).

[0201] For example, gate G1 has a main portion G1a and an end portion G1e. Main portion G1a has a substantially uniform thickness, while end portion G1e is located near the sidewalls / edges of gate G1. For example, gate G1 may have inclined sidewalls, and the thickness of end portion G1e may gradually decrease as it moves away from main portion G1a. Metal shield layer MS is located on the side of gate G1 away from the substrate and includes a first portion MS1, a second portion MS2, and a third portion MS3 that are connected to each other. The first portion MS1 ​​and the second portion MS2 are located on the side of main portion G1a and end portion G1e of gate G1 away from the substrate, respectively, and their orthographic projections on the substrate overlap with the orthographic projections of main portion G1a and end portion G1e of gate G1, respectively. The third portion MS3 extends beyond end portion G1e and the edge of the gate in a direction parallel to the main surface of the substrate.

[0202] In some embodiments, as shown in FIG17 , the metal shielding layer MS can laterally surround the gate G1 and the metal layer 103a on which it resides in a direction parallel to the main surface of the base substrate, and the orthographic projection of the gate G1 on the base substrate can be covered (e.g., completely covered) by the orthographic projection of the metal shielding layer MS on the base substrate. In this way, the metal shielding layer MS can effectively shield the signal from the gate G1 from affecting the upper thin-film transistor T2, thereby effectively preventing signal crosstalk.

[0203] In some embodiments, the gate G2, active layer AL2, gate G1, and other components of the thin-film transistor T2 located on the side of the metal shield layer MS away from the base substrate also have similar morphologies to the underlying material layers. For example, gate G2 comprises a first portion G2a, a second portion G2b, and G2b', and a third portion G2c, all connected to each other. The orthographic projections of the first portion G2a, the second portion G2b, and G2b', and the third portion G2c of gate G2 on the base substrate overlap with the orthographic projections of the first portion MS1, the second portion MS2, and the third portion MS3 of the metal shield layer MS on the base substrate, respectively. In some embodiments, gate G2 may have an asymmetric structure. For example, the second portions G2b and G2b' of gate G2, located opposite the first portion G2a, may have different thicknesses. The thickness of the second portion G2b' may gradually decrease as it moves away from the first portion G2a. The third portion G2c may be located only on the side of the second portion G2b away from the first portion G2a, while the third portion G2c may not be present on the side of the second portion G2b' away from the first portion G2a. However, the present disclosure is not limited thereto.

[0204] In some embodiments, gate G3 also has an asymmetric structure. For example, gate G3 includes a main portion G3a and end portions G3b and G3b' located on opposite sides of gate G3a in a direction parallel to the main surface of the substrate. For example, the main portion G3a and the end portions G3b / G3b' may have different thicknesses, with the thickness of the end portions G3b and G3b' gradually decreasing as they move away from the main portion G3a. End portion G3b may extend beyond the edge of gate G1 in a direction parallel to the main surface of the substrate, while end portion G3b' may be located directly above gate G1 without extending beyond the edge of gate G1. However, the present disclosure is not limited to this.

[0205] In some embodiments, the thickness of the metal shielding layer MS is less than the thickness of the metal layer containing the gates G1, G2, and G3. For example, the thickness of the metal shielding layer MS may be less than or equal to 103 nm. Providing a thinner metal shielding layer MS can avoid or minimize the significant impact of the addition of the metal shielding layer MS on the morphology of the upper structure and can also avoid or minimize the impact on the overall thickness of the array substrate.

[0206] In some embodiments, as shown in FIG17 , among the multiple metal layers shown, the metal shielding layer MS has the largest lateral dimension. For example, the metal shielding layer MS extends laterally beyond the edges of gate G1 (metal layer 103a), gate G2 (metal layer 109), and gate G3 (metal layer 113) in a direction parallel to the main surface of the base substrate. The orthographic projections of gate G1 (metal layer 103a), gate G2 (metal layer 109), and gate G3 (metal layer 113) on the base substrate can all be within the orthographic projection of the metal shielding layer MS on the base substrate, and the orthographic projection area of ​​the metal shielding layer MS on the base substrate can be larger than the orthographic projection areas of gate G1 (metal layer 103a), gate G2 (metal layer 109), and gate G3 (metal layer 113) on the base substrate. This configuration improves the signal shielding capability of the metal shielding layer MS, enabling the metal shielding layer MS to effectively shield signal crosstalk between adjacent thin-film transistors.

[0207] Figure 18 is a schematic top view of the gate and signal shielding structures of each thin-film transistor in a thin-film transistor group in an array substrate according to some embodiments of the present disclosure. It should be understood that the metal layers containing the signal shielding structures S1 / S2 and gates G2 and G3 are shown as transparent in the figure for clarity and ease of description, and do not limit these material layers to transparent materials.

[0208] With reference to Figures 2 to 13 and 18, in some embodiments, the orthographic projections of the metal layer 103a where the gate G1 of the thin-film transistor T1 is located, and the orthographic projections of the metal layer 109 where the gate G2 of the thin-film transistor T2 is located, and the metal layer 113 where the gate G3 is located, on the substrate 100, may all be located within the orthographic projection of the signal shielding structure S1 or S2 on the substrate 100. In some embodiments, the orthographic projection area of ​​the signal shielding structure S1 or S2 on the substrate 100 may be larger than the orthographic projection area of ​​the metal layer 103, the orthographic projection area of ​​the metal layer 109, and the orthographic projection area of ​​the metal layer 113 on the substrate 100. This configuration enables the signal shielding structure to effectively shield signal crosstalk between adjacent thin-film transistors T1 and T2.

[0209] There are a few points to note:

[0210] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0211] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0212] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: substrate substrate; a thin film transistor group, arranged on one side of the base substrate, the thin film transistor group comprising a first thin film transistor and a second thin film transistor, the first thin film transistor and the second thin film transistor overlap each other in a first direction perpendicular to the main surface of the base substrate, wherein the second thin film transistor is located on a side of the first thin film transistor away from the base substrate, the first thin film transistor comprises a first active layer and a first gate, and the second thin film transistor comprises a second active layer and a second gate; a signal shielding structure, arranged between the first thin film transistor and the second thin film transistor in the first direction, wherein the orthographic projection of the first gate on the base substrate is within the orthographic projection range of the signal shielding structure on the base substrate; as well as A conductive connector is located on a side of the signal shielding structure away from the first thin film transistor and is connected to the first thin film transistor through a via, wherein the via does not penetrate the signal shielding structure and is spaced apart from the signal shielding structure in a second direction parallel to the main surface of the substrate.

2. The array substrate according to claim 1, wherein the orthographic projection of at least part of the second gate on the base substrate overlaps with the orthographic projection of the first gate on the base substrate, and the orthographic projection of at least part of the second gate is located within the orthographic projection range of the signal shielding structure. 3 . The array substrate according to claim 1 , wherein the signal shielding structure is disposed on a side of the first gate electrode that is away from the first active layer and close to the second thin film transistor. 4 . The array substrate according to claim 1 , wherein the signal shielding structure comprises a metal shielding layer, and the metal shielding layer is connected to the DC signal terminal. 5 . The array substrate according to claim 4 , wherein the DC signal terminal comprises a power supply voltage terminal, a ground terminal, and a common voltage terminal.

6. The array substrate according to claim 4, wherein The second gate includes a top gate and a bottom gate connected to each other, the top gate and the bottom gate are located at opposite sides of the second active layer in the first direction, and the bottom gate is closer to the base substrate than the top gate; and The metal shielding layer is located between the bottom gate and the first gate.

7. The array substrate according to claim 4, wherein the second gate and the metal shielding layer are located on opposite sides of the second active layer in the first direction, and the metal shielding layer is further configured to adjust the threshold voltage of the second thin film transistor by selecting the DC signal terminal to which it is connected. 8 . The array substrate according to claim 4 , wherein the signal shielding structure further comprises a dielectric shielding unit, and the orthographic projection of the second active layer on the base substrate is located within the orthographic projection range of the dielectric shielding unit on the base substrate.

9. The array substrate according to claim 8, wherein the metal shielding layer is arranged on a side of the dielectric shielding unit close to the first thin film transistor, and the metal shielding layer extends beyond the edge of the dielectric shielding unit in a direction parallel to the main surface of the base substrate.

10. The array substrate according to claim 8, wherein the metal shielding layer is arranged on a side of the dielectric shielding unit away from the first thin film transistor, and an orthographic projection of the metal shielding layer on the base substrate overlaps with an orthographic projection of the dielectric shielding unit on the base substrate.

11. The array substrate according to claim 1, further comprising: An interlayer dielectric structure is located between the first thin film transistor and the second thin film transistor in the first direction, wherein the signal shielding structure is embedded in the interlayer dielectric structure or at least includes a portion of the interlayer dielectric structure.

12. The array substrate according to claim 11, wherein the interlayer dielectric structure comprises a dielectric main body and a dielectric protrusion; The dielectric main body extends from a first area where the thin film transistor group is located to a second area of ​​the array substrate in a second direction parallel to the base substrate, and the second area is an area outside the first area; The dielectric protrusion is located in the first region and protrudes from the surface of the dielectric main body away from the first thin film transistor toward the second thin film transistor. The dielectric protrusion serves as a dielectric shielding unit and is used as at least part of the signal shielding structure. The via hole penetrates through the dielectric body. 13 . The array substrate according to claim 12 , wherein the dielectric main body and the dielectric protrusion comprise different materials and have an interface therebetween. 14 . The array substrate according to claim 13 , wherein a dielectric constant of the dielectric protrusion is smaller than a dielectric constant of the dielectric main body. 15 . The array substrate according to claim 14 , wherein a dielectric constant of the dielectric protrusion is less than or equal to 3.

5. 16 . The array substrate according to claim 14 , wherein the dielectric main body comprises silicon oxide, and the dielectric protrusion comprises spin-on-glass. 17 . The array substrate according to claim 12 , wherein the dielectric main body and the dielectric protrusion comprise the same material and are integrally formed. 18 . The array substrate according to claim 17 , wherein the dielectric body portion and the dielectric protrusion comprise spin-on-glass.

19. The array substrate according to claim 12, wherein the signal shielding structure further comprises a metal shielding layer, wherein the metal shielding layer is embedded in the dielectric main body and connected to the DC signal terminal through a conductive through hole, wherein the conductive through hole is located on the side of the dielectric protrusion in the second direction and extends through a portion of the dielectric main body to connect to the metal shielding layer.

20. The array substrate according to claim 12, wherein an additional metal layer is disposed on a side of the dielectric protrusion away from the dielectric main body and close to the second active layer; the second gate comprises a top gate located on a side of the second active layer away from the additional metal layer; wherein the additional metal layer is connected to the DC signal terminal and serves as a metal shielding layer of the signal shielding structure; or The additional metal layer is connected to the top gate to serve as a bottom gate of the second thin film transistor.

21. The array substrate according to claim 1, further comprising: A capacitor is arranged side by side with the first thin film transistor and the signal shielding structure on the substrate in a direction parallel to the main surface of the substrate, and the capacitor includes a first electrode plate and a second electrode plate opposite to each other, wherein The array substrate comprises a first metal material layer, an insulating layer and a second metal material layer, wherein the insulating layer is located between the first metal material layer and the second metal material layer; The first electrode plate and the first grid are located in the first metal material layer, and the second electrode plate is located in the second metal material layer; as well as The signal shielding structure includes at least one of a metal shielding layer and a dielectric shielding unit, and the dielectric shielding unit is located on a side of the insulating layer away from the first metal material layer. 22 . The array substrate according to claim 21 , wherein the metal shielding layer and the second metal material layer are in the same layer.

23. The array substrate according to claim 19 comprises a first area and a second area, the thin film transistor group is located in the first area, the capacitor is located in the second area, wherein the second metal material layer extends continuously from the first area to the second area and is reused as the metal shielding layer and the second electrode plate. 24 . The array substrate according to claim 1 , comprising a plurality of thin film transistor groups arranged in an array, and each of the thin film transistor groups is configured to be formed in a sub-pixel driving circuit.

25. The array substrate according to claim 24, wherein the thin film transistor group comprises a first thin film transistor subgroup and a second thin film transistor subgroup arranged side by side in a direction parallel to the base substrate; The first thin film transistor subgroup includes the first thin film transistor and the second thin film transistor; The second thin film transistor subgroup includes a third thin film transistor and a fourth thin film transistor that are overlapped in the first direction, and an additional signal shielding structure is disposed between the third thin film transistor and the fourth thin film transistor. 26 . The array substrate according to claim 1 , wherein the first active layer and the second active layer comprise different materials. 27 . The array substrate of claim 26 , wherein the first active layer comprises polysilicon, and the second active layer comprises an oxide semiconductor.

28. A display device, comprising the array substrate according to any one of claims 1 to 20; and A light emitting device is connected to a sub-pixel driving circuit including the thin film transistor group, and the sub-pixel driving circuit is configured to drive the light emitting device to emit light. 29 . The display device according to claim 28 , wherein the light emitting device comprises an inorganic light emitting diode chip or comprises an organic light emitting layer.

30. A method for manufacturing an array substrate, comprising: providing a substrate base plate; Forming a first thin film transistor on the base substrate, wherein the first thin film transistor includes a first active layer and a first gate; forming a signal shielding structure on a side of the first thin film transistor away from the substrate; forming a second thin film transistor on a side of the signal shielding structure away from the first thin film transistor, wherein the second thin film transistor includes a second active layer and a second gate; as well as forming a conductive connecting member, the conductive connecting member being located on a side of the signal shielding structure away from the first thin film transistor and connected to the first thin film transistor through a via hole, wherein the via hole is located outside the signal shielding structure and is spaced apart from the signal shielding structure in a direction parallel to the substrate, The first thin film transistor and the second thin film transistor overlap each other in a first direction perpendicular to the main surface of the substrate and constitute a thin film transistor group, the signal shielding structure is located between the first thin film transistor and the second thin film transistor in the first direction, and the orthographic projection of the first gate on the substrate is located within the orthographic projection range of the signal shielding structure on the substrate.

31. The method for manufacturing an array substrate according to claim 30, further comprising: Forming a first metal material layer on a side of the first active layer away from the base substrate, wherein the first gate is located in the first metal material layer; forming an insulating layer on a side of the first metal material layer away from the first active layer; as well as forming an interlayer dielectric structure on a side of the insulating layer away from the first metal material layer; The signal shielding structure includes at least one of a metal shielding layer and a portion of the interlayer dielectric structure.

32. The method for manufacturing an array substrate according to claim 31, wherein the interlayer dielectric structure comprises a dielectric main body and a dielectric protrusion, and forming the interlayer dielectric structure comprises: forming a first dielectric layer on the insulating layer as the dielectric main body; forming a second dielectric layer on the first dielectric layer; as well as The second dielectric layer is patterned to remove the portion of the second dielectric layer outside the first region where the thin film transistor group is located, and leave the portion of the second dielectric layer located in the first region as the dielectric protrusion, wherein the dielectric protrusion serves as at least part of the signal shielding structure.

33. The method for manufacturing an array substrate according to claim 31, wherein the interlayer dielectric structure comprises a dielectric main body and a dielectric protrusion, and forming the interlayer dielectric structure comprises: forming a planarization dielectric layer on the insulating layer; The thickness of a portion of the planarization dielectric layer is reduced to form the dielectric main body having a first thickness and the dielectric protrusion having a second thickness, wherein the second thickness is greater than the first thickness, wherein the dielectric protrusion is located in the area where the thin film transistor group is located and serves as at least part of the signal shielding structure. 34 . The method for manufacturing an array substrate according to claim 32 or 33 , wherein the metal shielding layer is formed before forming the interlayer dielectric structure, and the metal shielding layer is embedded in the dielectric main body. 35 . The method for manufacturing an array substrate according to claim 32 or 33 , wherein after forming the interlayer dielectric structure, an additional metal layer is formed on a side of the dielectric protrusion away from the dielectric main body.

36. The method for manufacturing an array substrate according to claim 35, wherein The additional metal layer is connected to the DC signal terminal and serves as the metal shielding layer; or The second gate includes a top gate located on a side of the second active layer away from the additional metal layer, the additional metal layer is connected to the top gate and serves as a bottom gate of the second thin film transistor.

37. The method for manufacturing an array substrate according to claim 31, wherein forming the signal shielding structure comprises: Before forming the interlayer dielectric structure, a second metal material layer is formed on a side of the insulating layer away from the first metal material layer, the second metal material layer includes the metal shielding layer, and the interlayer dielectric structure covers the second metal material layer.

38. The method for manufacturing an array substrate according to claim 37, further comprising: forming a capacitor, the capacitor being arranged side by side with the first thin film transistor and the signal shielding structure, wherein the capacitor comprises a first electrode plate and a second electrode plate facing each other; The first electrode plate and the second electrode plate are located in the first metal material layer and the second metal material layer respectively.

39. The method for manufacturing an array substrate according to claim 38, wherein forming the metal shielding layer and the second electrode plate comprises: patterning the second metal material layer to form the metal shielding layer and the second electrode plate separated from each other; or The second metal material layer continuously extends from the area where the thin film transistor group is located to the area where the capacitor is located, and is reused as the metal shielding layer and the second electrode plate.

Images