Data processing device, program, and data processing method

Abstract

The invention discloses a data processing apparatus, a program, and a data processing method. The apparatus includes: a first holding circuit that holds a representative value of each variable group, the variable group being formed by at least two binary variables in an evaluation function of a combinatorial optimization problem, the representative value being a value of one of the at least two binary variables; a first memory storing a first coupling coefficient indicating a magnitude of an interaction between the sets of variables; a second holding circuit that holds a first local domain to be used to specify a first amount of change in the value of the evaluation function caused by a change in the representative value of each variable group; a change amount calculation circuit that calculates a first change amount for each variable group using the first local domain; a selection circuit that accepts a change in the representative value of the one variable group on the basis of the first change amount; a first update circuit that updates a representative value of the first variable group; and a second update circuit that updates the first local domain using a second coupling coefficient read from the first coupling coefficient based on the first identification number of the first variable group.

Description

Technical Field

[0001] The embodiments discussed herein relate to a data processing apparatus, a program, and a data processing method. Background Art

[0002] There is an Ising machine using an Ising type evaluation function as a device for calculating large-scale discrete optimization problems that von Neumann computers are not good at. In the case of using an Ising machine, the combinatorial optimization problem is converted into an Ising model representing the spin behavior of a magnetic material. The Ising machine searches for the state of the Ising model in which the value of the Ising type evaluation function is locally minimized by a Markov Chain Monte Carlo method such as simulated annealing or a replica exchange method (also known as a parallel tempering method, etc.). In the following, the Markov Chain Monte Carlo method will be abbreviated as the MCMC method. The state of the minimum value reaching the local minimum of the evaluation function is regarded as the optimal solution. The state of the Ising model can be represented by a combination of the values ​​of multiple binary variables. As the value of each of the binary variables, 0 or 1 can be used. In view of this, a binary variable can be referred to as a bit.

[0003] For example, the Ising type evaluation function is defined by the following expression (1).

[0004] [Mathematical formula 1]

[0005]

[0006] The first term on the right side is obtained by combining the product of the values ​​of the two binary variables (0 or 1) and the weight value (also called the coupling coefficient) for all combinations of all binary variables of the Ising model without omission or repetition. The binary variables identified by i are represented by x i Indicates that the binary variable with j as the identification number is represented by x j denoted by W, and the coupling coefficient indicating the magnitude of the correlation between binary variables identified by i and j is ij The second term on the right side is obtained by calculating the sum of the products of the bias coefficients of each identification number and the binary variable. The bias coefficient of identification number = i is given by b i express.

[0007] In addition, with x i The change in the value of the evaluation function associated with the change in the value of i ) is represented by the following expression (2).

[0008] [Mathematical formula 2]

[0009]

[0010] In expression (2), when x i When Δx changes from 1 to 0, i becomes -1, and when x i When Δx changes from 0 to 1, i becomes 1. Note that h i is called the local domain and is specified by ΔE i The variable ΔE i is by adding h i Multiply by Δx i The sign (+1 or -1) of

[0011] For example, in ΔE i The Ising machine performs the operation by repeatedly inverting x i The solution is searched by the process of searching for the value of and updating the local domain. Note that the state in which the value of the evaluation function becomes the local maximum can be searched by changing the sign of the evaluation function.

[0012] Since the calculation of ΔE can be performed in parallel i , determine whether to invert x i Multiple treatments of the values ​​of , etc., can therefore be performed on multiple binary variables in parallel.

[0013] There is a conventional process in which the number of binary variables whose values ​​are allowed to change (hereinafter sometimes referred to as conversion) in one trial of the process by the MCMC method is set to 1 (this conventional process will be referred to as single-bit conversion process hereinafter). However, in the single-bit conversion process, when the solution is fitted into a local solution, it is difficult to escape from the local solution, and the search speed may decrease in some cases.

[0014] Therefore, there is a proposed process for determining whether the conversion of multiple bits is possible based on the calculation result of the change amount of the value of the evaluation function when the conversion of multiple bits occurs, and causing the conversion of multiple bits when the conversion is allowed. Hereinafter, such a process will be referred to as a multi-bit conversion process. Through the multi-bit conversion process, it is easy for the solution to escape from the local solution, and the search speed can be improved.

[0015] Japanese Laid-Open Patent Publication Nos. 2020-021209, 2020-064536, and 2021-165965 are disclosed as related technologies. Summary of the invention

[0016] Technical issues

[0017] In conventional multi-bit conversion processing, the configuration for calculating the amount of change in the value of the evaluation function when multiple bits are converted, the configuration for propagating data, etc. become complicated. Therefore, it is difficult to efficiently evaluate the conversion of multiple bits by parallel experiments.

[0018] In one aspect, the embodiments are directed to providing a data processing apparatus, a program, and a data processing method capable of effectively evaluating conversion of a plurality of bits.

[0019] According to one aspect of the present embodiment, a data processing device includes: a first holding circuit that holds a representative value of each of a plurality of variable groups, the variable groups being formed by at least two binary variables of different values ​​or equal values ​​included in an evaluation function of a combinatorial optimization problem, and the representative value being a value of one of the at least two binary variables; a first memory that stores a plurality of first coupling coefficients that indicate the magnitude of interaction between the variable groups in the plurality of variable groups; a second holding circuit that holds a first local domain that is to be used to specify a first change in the value of the evaluation function to be caused by a change in the representative value of each of the plurality of variable groups; a change amount calculation circuit that uses the first local domain to calculate a first change for each of the plurality of variable groups; a selection circuit that accepts a change in the representative value of one of the plurality of variable groups based on the first change calculated for each of the plurality of variable groups; a first update circuit that updates the representative value of the first variable group in the plurality of variable groups whose representative value change is accepted; and

[0020] A second updating circuit updates the first local domain using a second coupling coefficient read from the plurality of first coupling coefficients stored in the first memory based on the first identification number of the first variable group.

[0021] Beneficial Effects of the Invention

[0022] In one aspect, embodiments may efficiently evaluate transitions of multiple bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a diagram showing an example of equivalent spin;

[0024] Figure 2A and Figure 2B is a diagram showing examples of pairs of binary variables selected as equivalent spins;

[0025] Figure 3 is a diagram showing an example of state transition in the case of using different values ​​of equivalent spin;

[0026] Figure 4 is a diagram showing an example of state transition in the case of using equivalent spins of the same value;

[0027] Figure 5 is a diagram showing an example of a matrix indicating items contributing to an inequality constraint and a generated neighborhood list;

[0028] Figure 6 is a diagram showing an example of a parallel experiment using equivalent spins;

[0029] Figure 7 is a diagram showing an example of a data processing apparatus according to the first embodiment;

[0030] Figure 8 is a table showing an example of generating an enable signal;

[0031] Fig. 9 is a flowchart showing the flow of an example of an enable signal generation process;

[0032] Fig.10 is a timing chart showing an example of the overall operation of the data processing apparatus according to the first embodiment;

[0033] Fig.11 is a flowchart showing an example of a processing procedure in the entire data processing apparatus according to the first embodiment;

[0034] Fig.12 is a flowchart showing an example of a processing procedure in a single-bit conversion process;

[0035] Fig.13 is a flowchart showing an example of a processing procedure in an equivalent spin conversion process;

[0036] Fig.14 is a diagram showing an example of a data processing apparatus according to a second embodiment;

[0037] Fig.15 is a diagram for explaining coupling coefficients stored in an updated coupling coefficient memory;

[0038] Fig.16 is a timing chart showing an example of the overall operation of the data processing apparatus according to the second embodiment;

[0039] Fig.17 is a timing chart showing an example of a processing sequence in an update process;

[0040] Fig.18 is a flowchart showing an example of a processing procedure in the entire data processing apparatus according to the second embodiment;

[0041] Fig.19is a flowchart showing an example of a processing procedure in a single-bit conversion process in a data processing device according to the second embodiment;

[0042] Fig. 20 is a diagram showing an example of a data processing apparatus according to a third embodiment;

[0043] Fig.21 is a timing chart showing an example of the overall operation of the data processing apparatus according to the third embodiment; and

[0044] Fig. 22 is a diagram showing an example of hardware of a computer as an example of a data processing device. DETAILED DESCRIPTION

[0045] In the following description, modes for carrying out the embodiments will be described with reference to the drawings.

[0046] The data processing device of each embodiment described below processes a variable group including two or more binary variables of different values ​​or equal values ​​included in the evaluation function of the combinatorial optimization problem as a binary variable corresponding to one spin. Therefore, the above variable group will be referred to as equivalent spin hereinafter.

[0047] In addition, in the following description, equivalent spins of two or more binary variables including different values ​​will sometimes be referred to as different value equivalent spins, and equivalent spins of two or more binary variables including the same value will sometimes be referred to as the same value equivalent spins. By treating such a group of binary variables as equivalent spins, it becomes possible to perform parallel experiments similar to the single-bit conversion process described below.

[0048] Note that in the following description, equivalent spin will be described assuming that spin includes two binary variables, but the equivalent spin may include three or more binary variables.

[0049] Figure 1 is a diagram showing an example of equivalent spin.

[0050] Figure 1 The equivalent spin is shown as two binary variables indicated by the identifiers i1 and i2. i In the example described below, the value of the equivalent spin is represented by Expression (3).

[0051] [Mathematical formula 3]

[0052]

[0053] In other words, the value of the equivalent spin is represented by the value of one of the two binary variables included in the equivalent spin. Therefore, the value of Expression (3) can also be referred to as a representative value of a variable group including two binary variables.

[0054] In addition, in the following description, the variable that specifies the amount of change in the value of the evaluation function caused by the change in the value of the equivalent spin will be referred to as the equivalent local domain. In the following example, the value of the equivalent local domain of the equivalent spin of different values ​​is represented by expression (4), and the value of the equivalent local domain of the equivalent spin of the same value is represented by expression (5).

[0055] [Formula 4]

[0056]

[0057] [Mathematical formula 5]

[0058]

[0059] In expressions (4) and (5), the variable having the identification number i1 assigned to h accompanying the hat is an equivalent local domain that specifies the amount of change in the value of the evaluation function caused by a change in the value of one of the two binary variables included in the equivalent spin. The variable having the identification number i2 assigned to h accompanying the hat is an equivalent local domain that specifies the amount of change in the value of the evaluation function caused by a change in the value of the other of the two binary variables included in the equivalent spin.

[0060] Furthermore, in the following description, a coupling coefficient indicating the magnitude of interaction between a plurality of equivalent spins (hereinafter referred to as an equivalent coupling coefficient) is represented by Expression (6).

[0061] [Mathematical formula 6]

[0062]

[0063] In expression (6), the coupling coefficient having the identification number i1j1 assigned to W indicates the magnitude of the interaction of the first binary variable included in the equivalent spin of the identification number i to the first binary variable included in the equivalent spin of the identification number j. The coupling coefficient having the identification number i1j2 assigned to W indicates the magnitude of the interaction of the first binary variable included in the equivalent spin of the identification number i to the second binary variable included in the equivalent spin of the identification number j. The coupling coefficient having the identification number i2j1 assigned to W indicates the magnitude of the interaction of the second binary variable included in the equivalent spin of the identification number i to the first binary variable included in the equivalent spin of the identification number j. The coupling coefficient having the identification number i2j2 assigned to W indicates the magnitude of the interaction of the second binary variable included in the equivalent spin of the identification number i to the second binary variable included in the equivalent spin of the identification number j.

[0064] In expressions (4) and (5), the two equivalent local domains on the right side can be expressed by the following expressions (7) and (8), respectively.

[0065] [Formula 7]

[0066]

[0067] [Mathematical formula 8]

[0068]

[0069] In expressions (7) and (8), D represents the set of identification numbers of all binary variables. The variable with identification number i1 assigned to h is a local domain that specifies the amount of change in the evaluation function value caused by the change in the value of the binary variable with identification number i1. The variable with identification number i2 assigned to h is a local domain that specifies the amount of change in the evaluation function value caused by the change in the value of the binary variable with identification number i2. The equivalent local domains in expressions (7) and (8) are the same as the local domains in the case where the coupling coefficient between the two binary variables included in the equivalent spin is set to 0.

[0070] Regardless of how the values ​​of the two binary variables included in the equivalent spin change, the value of the equivalent local domain of the equivalent spin of different values ​​or the same value does not change, but changes when the value of the equivalent spin having an equivalent coupling coefficient that is not 0 relative to the equivalent spin changes. The initial value of the equivalent local domain of the equivalent spin is calculated according to Expression (7) and Expression (8). The value of the equivalent local domain of the equivalent spin when the value of the equivalent spin changes can be updated by differential calculation.

[0071] The amount of change in the value of the equivalent spin of different values ​​can be expressed by the following expression (9).

[0072] [Mathematical formula 9]

[0073]

[0074] The amount of change in the value of the evaluation function caused by the change in the value of the different-value equivalent spin can be expressed by the following expression (10).

[0075] [Formula 10]

[0076]

[0077] As in Expression (10), the amount of change in the value of the evaluation function caused by the change in the value of the equivalent spin can be calculated by the product of the equivalent local domain of the equivalent spin and the amount of change in the value of the equivalent spin.

[0078] When the different-value equivalent spins change, the equivalent local domain can be updated according to the following expression (11).

[0079] [Mathematical formula 11]

[0080]

[0081] The amount of change in the value of equivalent spin of the same value can be expressed by the following expression (12).

[0082] [Mathematical formula 12]

[0083]

[0084] The amount of change in the value of the evaluation function caused by the change in the value of the equivalent spin of the same value can be expressed by the following Expression (13).

[0085] [Mathematical formula 13]

[0086]

[0087] As in Expression (13), the amount of change in the value of the evaluation function caused by the change in the value of the equivalent spin can be calculated by the product of the equivalent local domain of the equivalent spin and the amount of change in the value of the equivalent spin.

[0088] When the value of the equivalent spin of the same value changes, the equivalent local domain can be updated according to the following expression (14).

[0089] [Formula 14]

[0090]

[0091] Figure 2A and Figure 2B is a diagram showing examples of pairs of binary variables selected as equivalent spins.

[0092] Figure 2A A first example of the selection of equivalent spins is shown, and Figure 2B A second example of selection of equivalent spins is shown. In the first example of selection, equivalent spin 1 formed by x1 and x2, equivalent spin 2 formed by x1 and x6, equivalent spin 3 formed by x4 and x5, and equivalent spin 4 formed by x6 and x7 are obtained. In the second example of selection, equivalent spin 5 formed by x2 and x3, equivalent spin 6 formed by x3 and x4, equivalent spin 7 formed by x5 and x9, and equivalent spin 8 formed by x7 and x8 are obtained.

[0093] In the data processing device of each embodiment described below, some binary variables among all binary variables are selected as equivalent spins, such as Figure 2A and 2B As shown. In addition, the data processing device can change the binary variable to be selected as the equivalent spin from the first example of the selection example to the second example of the selection during the solution search. Note that all binary variables can be selected so as to belong to one of the equivalent spins.

[0094] For example, consider the following points to determine whether to use different values ​​of equivalent spin or the same value of equivalent spin.

[0095] Figure 3 : is a diagram showing an example of state transition in the case of using different values ​​of equivalent spin. The vertical axis indicates the value of the evaluation function, and the horizontal axis indicates the state of the equivalent spin. Note that in this example, it is assumed that a state with an equivalent spin in which the evaluation function becomes smaller is searched as a solution.

[0096] In combinatorial optimization problems with inequality constraints such as the knapsack problem, it is effective to set groups of binary variables connected by inequality constraints to equivalent spins. Note that the knapsack problem is a problem in which, when multiple items with given value and weight (or capacity) are put into a knapsack with a weight limit (or capacity limit), a method of putting the item with the maximum net profit is calculated.

[0097] For example, Figure 3 As shown, two binary variables represented by identification numbers i1 and i2 can be used as a binary variable pair indicating whether two items close in weight to each other are put into a backpack. In the following description, it is assumed that when the value of the binary variable is 1, the binary variable indicates that the corresponding item is selected and put into the backpack, and when the value of the binary variable is 0, the binary variable indicates that the corresponding item is not selected and is not put into the backpack.

[0098] In the case of transitioning from the state where the values ​​of the above two binary variables are 1 and 0 to the state where the values ​​of both binary variables are 1, Figure 3 In the example, the value of the evaluation function is large. This state transition may be a state transition in which both items enter the backpack, resulting in not meeting the weight limit and violating the inequality constraint.

[0099] In such a case, it is preferred to Figure 3 The two binary variables in are set to different value equivalent spins. This is because, when the values ​​of the different value equivalent spins are reversed, the values ​​of the two binary variables are changed to (1, 0) or (0, 1), and the state transition that increases the value of the evaluation function as described above is avoided.

[0100] Figure 4 : is a diagram showing an example of state transition in the case of using equivalent spins of the same value. The vertical axis indicates the value of the evaluation function, and the horizontal axis indicates the state of the equivalent spin.

[0101] Depending on the method of formulating the evaluation function, such as the manner of determining the signs of coefficients of constraint terms of inequality constraints included in the evaluation function, it is possible to preferably adopt equivalent spins of the same value even in a combinatorial optimization problem having inequality constraints.

[0102] like Figure 4 As shown, in the case of a transition from a state where the values ​​of both binary variables are 1 to a state where one of the values ​​of the two binary variables is 1 and the other is 0, Figure 4 In the example above, the value of the evaluation function is large.

[0103] In such a case, it is preferred to Figure 4 The two binary variables in are set to the same value equivalent spin. This is because, when the values ​​of the same value equivalent spin are reversed, the values ​​of the two binary variables are changed to (1, 1) or (0, 0), and the state transition that increases the value of the evaluation function as described above is avoided.

[0104] In the case where there are multiple inequality constraints, binary variable groups with many commonly contributing inequality constraints may preferably be set as equivalent pairs. As an example of a method of generating a neighborhood list indicating a state variable with many commonly contributing inequality constraints, there is a method described in the following document.

[0105] (Literature) S. Umetani, "Exploiting variable associations to configure efficient local search algorithms in large-scale binary integer programs", European Journal of Operational Research 263 (2017) 72-81.

[0106] Figure 5 is a diagram showing an example of a matrix indicating terms contributing to an inequality constraint and the generated neighbor list.

[0107] Figure 5 An example is shown in which there are six inequality constraints for ten terms. Figure 5 The matrix on the left indicates whether each of the ten terms contributes to each of the six inequality constraints. When the jth term contributes to the ith inequality constraint, the matrix element a ij The value of is 1, and when the jth term does not contribute to the i-th inequality constraint, the matrix element a ij The value of is 0. Figure 5 In the example of , the first term contributes to the second, third, and fifth inequality constraints.

[0108] The number of inequality constraints that jointly contribute to the first term is two for the second, seventh, eighth, and tenth terms, and one for the third to sixth terms.

[0109] In this case, the binary variables corresponding to the second, seventh, eighth, and tenth items are defined in the neighborhood list as the neighbors of the binary variable corresponding to the first item. Figure 5 In the example of , binary variables corresponding to the first to tenth items are denoted by x1 to x10.

[0110] As described above, converting the combinatorial optimization problem into the Ising model using equivalent spins enables multi-bit conversion by parallel trials similar to the single-bit conversion process. Note that the problem converted into the Ising model is almost the same as the problem called quadratic unconstrained binary optimization (QUBO), and is mutually convertible, and therefore, in the following description, these problems will not be distinguished from each other.

[0111] Figure 6 is a diagram showing an example of a parallel experiment using equivalent spins. Figure 6 An example of a parallel experiment using M equivalent spins is shown.

[0112] For example, a parallel experiment is performed using the storage circuits 10a1, 10a2, ..., and 10aM, the variation calculation circuits 10b1, 10b2, ..., and 10bM, and the selection circuit 10c.

[0113] Each of the storage circuits 10a1 to 10aM stores an equivalent coupling coefficient between one of the M equivalent spins and the other equivalent spins. For example, the storage circuit 10a1 stores an equivalent coupling coefficient between an equivalent spin including two binary variables represented by identification numbers 11 and 12 and the other equivalent spins. Since the equivalent coupling coefficients do not depend on the state, they can be calculated in advance.

[0114] Each of the variation calculation circuits 10b1 to 10bM calculates the variation of the value of the evaluation function caused by the variation of the corresponding values ​​of the M equivalent spins. As shown in Expression (10) or Expression (13), the variation calculation is performed by calculating the product of the variation of the equivalent local domain and the value of the equivalent spin. In the case of using different value equivalent spins, the equivalent local domain represented by Expression (4) is used. In the case of using the same value equivalent spin, the equivalent local domain represented by Expression (5) is used.

[0115] The selection circuit 10c selects one of the M equivalent spins based on the M changes and outputs the identification number j of the selected equivalent spin. When the equivalent local domain is updated with the change in the value of the selected equivalent spin, j is used to read the equivalent coupling coefficient from the storage circuits 10a1 to 10aM.

[0116] When the value of the equivalent spin of identification number j changes, the equivalent local domain is updated according to the following expression (15).

[0117] [Mathematical formula 15]

[0118]

[0119] In Expression (15), when using equivalent spins of different values, the equivalent coupling coefficient is expressed by the above Expression (6). When using equivalent spins of two binary variables each including the same value, the equivalent coupling coefficient is expressed by the following Expression (16).

[0120] [Formula 16]

[0121]

[0122] Note that even if equivalent spins of different values ​​and equivalent spins of the same value coexist, only the initial values ​​and equivalent coupling coefficients of the equivalent local domains are different, and the processing details of the parallel experiments are the same as above.

[0123] The initial values ​​of equivalent local domains of different values ​​of equivalent spin are expressed by the following expression (17).

[0124] [Mathematical formula 17]

[0125]

[0126] The initial value of the equivalent local domain of equivalent spin of the same value is expressed by the following expression (18).

[0127] [Mathematical formula 18]

[0128]

[0129] The equivalent coupling coefficient between equivalent spins of different values ​​and equivalent spins of the same value is expressed by the following expressions (19) and (20).

[0130] [Mathematical formula 19]

[0131]

[0132] [Mathematical formula 20]

[0133]

[0134] Expression (19) represents the equivalent coupling coefficient in the case where j is the identification number of equivalent spins of different values. Expression (20) represents the equivalent coupling coefficient in the case where j is the identification number of equivalent spins of the same value.

[0135] When i is an identification number of equivalent spins of different values, an upper symbol is used between an upper symbol - and a lower symbol +. When i is an identification number of equivalent spins of the same value, a lower symbol is used between an upper symbol - and a lower symbol +.

[0136] Next, a data processing apparatus according to a first embodiment is described.

[0137] (First Embodiment)

[0138] As described below, the data processing device of the first embodiment includes a function of performing a single-bit conversion process and a function of performing a conversion process using equivalent spin as described above (this conversion process will be referred to as equivalent spin conversion process hereinafter). Both functions are switchable.

[0139] Figure 7 is a diagram showing an example of a data processing apparatus according to the first embodiment.

[0140] The data processing device 20 includes an equivalent spin conversion circuit unit 20 a that performs an equivalent spin conversion process and a single-bit conversion circuit unit 20 b that performs a single-bit conversion process.

[0141] The equivalent spin conversion circuit unit 20a includes an equivalent coupling coefficient memory 21, an equivalent spin update circuit 22, an equivalent spin hold circuit 23, an equivalent local domain update circuit 24, an equivalent local domain hold circuit 25, a ΔE calculation circuit 26, and a ΔE hold circuit 27. In addition, the equivalent spin conversion circuit unit 20a includes an enable processing circuit 28 and a conversion equivalent spin selection circuit 29.

[0142] The single-bit conversion circuit unit 20b includes a coupling coefficient memory 30, a binary variable update circuit 31, a binary variable holding circuit 32, a local domain update circuit 33, a local domain holding circuit 34, a ΔE calculation circuit 35, a ΔE holding circuit 36 ​​and a conversion binary variable selection circuit 37.

[0143] Furthermore, the data processing device 20 includes an equivalent spin decoder circuit 38, a selection circuit 39, an equivalent spin enable determination circuit 40, and an initial equivalent local domain calculation circuit 41. These are used for matching between the single-bit conversion process and the equivalent spin conversion process.

[0144] Furthermore, the data processing device 20 includes a ΔE selection circuit 42 , an E update hold circuit 43 , a comparison circuit 44 , a minimum value update hold circuit 45 , and a control circuit 46 .

[0145] In the following description, the corresponding elements are explained.

[0146] The equivalent coupling coefficient memory 21 stores M×M equivalent coupling coefficients indicating the magnitude of the interaction between each of a plurality of (hereinafter referred to as M) equivalent spins. The equivalent coupling coefficient is represented by the above expression (6), expression (16), expression (19), or expression (20). The equivalent coupling coefficient memory 21 corresponds to Figure 6 The equivalent coupling coefficient memory 21 may be formed by, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a volatile storage device as an electronic circuit such as a register, etc. The equivalent coupling coefficient memory 21 may be a non-volatile storage device as an electronic circuit such as a flash memory, or a storage device such as a hard disk drive (HDD). The storage device used as the equivalent coupling coefficient memory 21 may be selected from the storage devices described above according to the number of equivalent spins (=M), the number of bits of the equivalent coupling coefficient, etc.

[0147] The equivalent spin update circuit 22 updates the value of the equivalent spin whose value (as a representative value of one of two or more binary variables constituting the equivalent spin) is allowed to be changed among the M equivalent spins. The equivalent spin update circuit 22 performs the update by inverting (flipping) the value of the equivalent spin specified by the identification number output from the conversion equivalent spin selection circuit 29 from 1 to 0 or from 0 to 1 among the values ​​of the M equivalent spins held in the equivalent spin holding circuit 23.

[0148] The equivalent spin holding circuit 23 includes a holding circuit such as a register, for example, and holds the values ​​of M equivalent spins. In addition, the equivalent spin holding circuit 23 outputs the amount of change in the value of the equivalent spin to be used when updating the equivalent local domain and calculating the amount of change in the evaluation function.

[0149] The equivalent local domain update circuit 24 updates the equivalent local domain held in the equivalent local domain holding circuit 25 using the equivalent coupling coefficient read from the equivalent coupling coefficient memory 21 based on the identification number output from the conversion equivalent spin selection circuit 29. In order to update the equivalent local domain according to the above expression (15), the equivalent local domain update circuit 24 can be implemented, for example, with a multiplier and an adder.

[0150] The equivalent local domain holding circuit 25 includes a holding circuit such as a register, and holds M equivalent local domains. The equivalent local domains of different value equivalent spins are represented by the above expression (4), and the equivalent local domains of the same value equivalent spins are represented by the above expression (5).

[0151] The ΔE calculation circuit 26 calculates the amount of change in the value of the evaluation function for each of the M equivalent spins using the equivalent local domain held in the equivalent local domain holding circuit 25. The ΔE calculation circuit 26 corresponds to Figure 6 The ΔE calculation circuit 26 can be implemented by a multiplier, for example, to calculate the change amount according to the above expression (13).

[0152] The ΔE holding circuit 27 includes a holding circuit such as, for example, a register, and holds the amount of change in the value of the evaluation function that has been calculated for the corresponding M equivalent spins.

[0153] Based on an enable signal described later, the enable processing circuit 28 invalidates processing to be performed by the conversion equivalent spin selection circuit 29 described next, for an equivalent spin whose value is not allowed to change.

[0154] The conversion equivalent spin selection circuit 29 accepts a change in the value of one of the M equivalent spins based on the amount of change in the value of the evaluation function calculated for the corresponding M equivalent spins (excluding those invalid equivalent spins). The conversion equivalent spin selection circuit 29 determines the equivalent spin for which the change in value is to be accepted according to the MCMC method. In addition, the conversion equivalent spin selection circuit 29 outputs the identification number of the determined equivalent spin and the amount of change in the value of the evaluation function caused by the change in the value of the equivalent spin.

[0155] For example, in the case where the larger value between the amount of change in the value of the evaluation function caused by the change in the value of a certain equivalent spin and 0 is less than a threshold value obtained based on the value of the random number and the temperature parameter, the conversion equivalent spin selection circuit 29 allows the change in the value of the equivalent spin. For example, -log(rand)×T is used as the threshold. rand represents a uniform random number in the range of 0 to 1, and T represents the value of the temperature parameter. In the case where the change in the value of a plurality of equivalent spins is allowed, the conversion equivalent spin selection circuit 29 can select an equivalent spin randomly or according to a predetermined rule, and output the identification number of the selected equivalent spin.

[0156] The conversion equivalent spin selection circuit 29 can select an equivalent spin for which the allowed value changes based on the M changes in the value of the evaluation function and the threshold. Such a selection method is sometimes called a non-rejection method. In this method, the conversion equivalent spin selection circuit 29 calculates M max function values ​​for the corresponding M changes to output a larger value between 0 and the change, for example. The conversion equivalent spin selection circuit 29 converts Tlog(-log(rand i )) is added to each of the M max function values. Here, rand i represents a uniform random number in the range of 0 to 1 that has been generated for each equivalent spin. Then, the conversion equivalent spin selection circuit 29 outputs the identification number of the equivalent spin to provide a minimum addition result when the value varies among the M equivalent spins.

[0157] The coupling coefficient memory 30 stores N×N coupling coefficients indicating the magnitude of the interaction between the respective binary variables of the plurality of (hereinafter referred to as N) binary variables included in the evaluation function. The coupling coefficient memory 30 may be formed of, for example, a DRAM, an SRAM, a volatile storage device as an electronic circuit such as a register, etc. The coupling coefficient memory 30 may be a nonvolatile storage device as an electronic circuit such as a flash memory, or a storage device such as an HDD.

[0158] The binary variable updating circuit 31 updates the value of the binary variable whose value change is accepted. The binary variable updating circuit 31 updates the values ​​of the N binary variables held in the binary variable holding circuit 32 by flipping the value of the binary variable specified by the identification number output from the conversion binary variable selecting circuit 37.

[0159] The binary variable holding circuit 32 includes a holding circuit such as a register, for example, and holds the values ​​of N binary variables. In addition, the binary variable holding circuit 32 outputs the variation of the value of the binary variable to be used when updating the local domain and calculating the variation in the evaluation function.

[0160] The local domain updating circuit 33 updates the local domain using one of the plurality of coupling coefficients read from the coupling coefficient memory 30 based on the identification number output from the conversion binary variable selection circuit 37. ij Δx j Add to h indicated in expression (2) i To perform such an update, the local domain update circuit 33 can be implemented, for example, with a multiplier and an adder.

[0161] The local region holding circuit 34 includes a holding circuit such as, for example, a register, and holds N local regions.

[0162] The ΔE calculation circuit 35 calculates the amount of change in the value of the evaluation function for each of the N binary variables using the local domain held in the local domain holding circuit 34. The ΔE calculation circuit 35 may be implemented with a multiplier, for example, to calculate the amount of change according to the above expression (2).

[0163] The ΔE holding circuit 36 ​​includes a holding circuit such as, for example, a register, and holds the amount of change in the value of the evaluation function that has been calculated for the corresponding N binary variables.

[0164] The conversion binary variable selection circuit 37 accepts a change in the value of one of the N binary variables based on the amount of change in the value of the evaluation function calculated for the corresponding N binary variables. The conversion binary variable selection circuit 37 determines the binary variable for which a change in value is to be accepted according to the MCMC method. In addition, the conversion binary variable selection circuit 37 outputs the identification number of the determined binary variable and the amount of change in the value of the evaluation function caused by the change in the value of the binary variable.

[0165] For example, in the case where the larger value between the amount of change in the value of the evaluation function caused by the change in the value of a certain binary variable and 0 is less than a threshold value obtained based on the value of the random number and the temperature parameter, the conversion binary variable selection circuit 37 allows the change in the value of the binary variable. In the case where the change in the values ​​of a plurality of binary variables is allowed, the conversion binary variable selection circuit 37 may select one binary variable randomly or according to a predetermined rule, and output the identification number of the selected binary variable. Alternatively, the conversion binary variable selection circuit 37 may be a circuit that determines a binary variable whose value change is to be accepted by the no-rejection method as described above.

[0166] The equivalent spin decoder circuit 38 generates and outputs identification numbers of two binary variables included in the equivalent spin of the identification number based on the identification number output from the conversion equivalent spin selection circuit 29. The equivalent spin decoder circuit 38 can be implemented with a holding circuit, a memory, or the like that holds information indicating the correspondence relationship between, for example, the identification number of the equivalent spin and the identification number of the binary variable.

[0167] In the case of performing a single-bit conversion process, the selection circuit 39 selects and outputs the identification number of the binary variable output by the conversion binary variable selection circuit 37. In the case of performing a conversion process using equivalent spin, the selection circuit 39 selects and outputs the identification numbers of the two binary variables output by the equivalent spin decoder circuit 38. The selection circuit 39 performs the above selection under the control of the control circuit 46, for example.

[0168] The equivalent spin enable determination circuit 40 generates an enable signal indicating whether to allow the value of each equivalent spin to change based on the identification number of the binary variable output from the conversion binary variable selection circuit 37 or the equivalent spin decoding circuit 38. An example of the enable signal generation process will be described later (see Figure 8 and Fig. 9 ).

[0169] When the single-bit conversion process is switched to the equivalent spin conversion process, the initial equivalent local domain calculation circuit 41 calculates the initial value of the equivalent local domain indicated by expression (17) or expression (18) using, for example, the binary variable, the coupling coefficient, and the value of the local domain. For example, the initial equivalent local domain calculation circuit 41 can be implemented with an adder and a multiplier.

[0170] In the case of performing a single-bit conversion process, the ΔE selection circuit 42 selects and outputs the amount of change in the value of the evaluation function output by the conversion binary variable selection circuit 37. In the case of performing a conversion process using an equivalent spin, the ΔE selection circuit 42 selects and outputs the amount of change in the value of the evaluation function output by the conversion equivalent spin selection circuit 29. The ΔE selection circuit 42 performs the above selection under the control of the control circuit 46, for example.

[0171] The E update hold circuit 43 includes a hold circuit such as a register, and holds the value of the evaluation function. The E update hold circuit 43 acquires the change amount selected by the ΔE selection circuit 42, updates the value of the evaluation function with the change amount, and outputs the updated value.

[0172] The comparison circuit 44 compares the value of the evaluation function held in the E update hold circuit 43 with the minimum value of the evaluation function held in the minimum value update hold circuit 45 .

[0173] The minimum value update hold circuit 45 includes a holding circuit such as a register, and holds the minimum value of the evaluation function obtained so far. In the case where the comparison circuit 44 outputs a comparison result indicating that the value of the evaluation function held in the E update hold circuit 43 is less than the minimum value obtained so far, the minimum value update hold circuit 45 updates the minimum value with the value of the evaluation function. In addition, the minimum value update hold circuit 45 holds the values ​​of the N binary variables when the minimum value is obtained. For example, the values ​​of the N binary variables held when a predetermined end condition is satisfied are then output as a solution to the combinatorial optimization problem.

[0174] The control circuit 46 controls the various components of the data processing device 20. The control circuit 46 performs control to switch between the single-bit conversion process and the equivalent spin conversion process. For example, in the single-bit conversion process, in the case where a change in the binary variable value is not accepted within a predetermined period of time, there is a possibility that the solution is fitted into a local solution, and therefore, the control circuit 46 performs switching so as to perform the equivalent spin conversion process.

[0175] The control circuit 46 can obtain the evaluation function information input from the outside, and store the N×N coupling coefficients included in the evaluation function information into the coupling coefficient memory 30. In addition, the control circuit 46 can calculate the equivalent coupling coefficient represented by the above expression (6), expression (16), expression (19) or expression (20) based on the N×N coupling coefficients, and store the equivalent coupling coefficient into the equivalent coupling coefficient memory 21. In addition, the control circuit 46 can determine the initial values ​​of the N binary variables, and make the binary variable holding circuit 32 hold the initial values. In addition, the control circuit 46 can generate M equivalent spins, determine their initial values, and make the equivalent spin holding circuit 23 hold the determined initial values.

[0176] Additionally, control circuit 46 may generate a threshold value to be used when conversion equivalent spin selection circuit 29 or conversion binary variable selection circuit 37 determines an equivalent spin or binary variable for which a change in value is to be accepted.

[0177] Each of the circuits in the data processing device 20 described above may be formed of an electronic circuit such as, for example, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0178] (Example of Enable Signal Generation Processing)

[0179] Next, an example of enable signal generation processing is described.

[0180] Figure 8 is a table showing an example of generating an enable signal.

[0181] like Figure 8 As shown, the equivalent spin enable determination circuit 40 generates an enable signal for each equivalent spin. Figure 8 , a first binary variable and a second binary variable included in the equivalent spin are shown. In addition, the type of the equivalent spin (indicating different value equivalent spins or the same value equivalent spins) is shown.

[0182] The enable signal (En) for equivalent spins of different values ​​is obtained by exclusive OR of the values ​​of the binary variables of identification numbers i1 and i2. i ). By performing exclusive NOR on the values ​​of the binary variables with subscript identifiers i1 and i2, an enable signal (En) of equivalent spin with the same value is obtained. i ).

[0183] The equivalent spin enable determination circuit 40 holds the enable signal information as table data in a memory (not shown), for example, Figure 8 shown.

[0184] In the case where the identification number of the binary variable output by the conversion binary variable selection circuit 37 is an identification number indicating the binary variable included in the equivalent spin, the equivalent spin enable determination circuit 40 inverts the value of the enable signal for the equivalent spin.

[0185] The equivalent spin enable determination circuit 40 performs a process of inverting the value of the enable signal of the equivalent spin according to the identification numbers of the two binary variables output by the equivalent spin decoder circuit 38. For example, the inversion process is performed as follows.

[0186] Assume there are equivalent spins Y0 with the same values including binary variables X0 and X1, equivalent spins Y1 with different values including binary variables X0 and X1, equivalent spins Y2 with different values including binary variables X1 and X2, and equivalent spins Y3 with different values including binary variables X2 and X3. Additionally, assume the enable signals for Y0 to Y3 are En0 to En3. When (X0, X1, X2, X3) = (0, 1, 1, 1) is regarded as the initial value, the initial values of the enable signals for the corresponding equivalent spins are (En0, En1, En2, En3) = (0, 1, 0, 0).

[0187] When the value of Y1 changes, the states of the binary variables are converted to (X0, X1, X2, X3) = (1, 0, 1, 1). At this time, the equivalent spin enable determination circuit 40 sets the enable signals to (En0, En1, En2, En3) = (0, 1, 1, 0).

[0188] In the process of inverting the value of the enable signal for the equivalent spin, when one of the two binary variables included in a certain equivalent spin is included in another equivalent spin, the value of the enable signal for the other equivalent spin is inverted. In the above example, the value of the enable signal (En2) of Y2 is inverted, and Y2 includes one of X0 and X1 included in Y1 (X1).

[0189] Furthermore, in the process of inverting the value of the enable signal for the equivalent spin, when the value of one of the two equivalent spins including the same two binary variables and only different in the equivalent spin type is inverted, the value of any enable signal is not inverted. In the above example, Y0 and Y1 include X0 and X1 and are only different in type. The values of the enable signals (En0 and En1) for the two equivalent spins remain 0 and 1 and are not inverted. Note that the value of the enable signal (En3 of Y3 in the above example) for the equivalent spin that does not include any of the two binary variables included in the equivalent spin whose allowed value changes is also not inverted.

[0190] Through the enable signal generation process as described above, appropriate enable signals are obtained.

[0191] Fig. 9 It is a flowchart showing an example of the enable signal generation process.

[0192] The processing in steps S10 to S14 is executed in the initialization process for the data processing device 20.

[0193] Step S10: Start the loop processing for M equivalent spins. When i < M + 1 is satisfied, the loop processing is executed, starting from i = 1.

[0194] Step S11: Determine the type of the equivalent spin of identification number i. For example, the control circuit 46 determines whether the equivalent spin of identification number i is a different-value equivalent spin or a same-value equivalent spin based on the pre-generated corresponding equivalent spin and the information about its type.

[0195] Step S12: When the equivalent spin is determined to be a different-value equivalent spin, obtain the initial value of En through the exclusive OR of the values of the binary variables of identification numbers i1 and i2 included in the equivalent spin of identification number i. i of the initial value.

[0196] Step S13: When the equivalent spin is determined to be a same-value equivalent spin, obtain the initial value of En through the exclusive NOR of the values of the binary variables of identification numbers i1 and i2. i of the initial value.

[0197] The processes in Steps S12 and S13 are performed by the control circuit 46, for example, by performing a logical operation of exclusive OR or exclusive NOR on the initial values of the binary variables of identification numbers i1 and i2. As Figure 8 shown, the obtained initial value of En i is stored as table data in a memory (not shown) in, for example, the equivalent spin enable determination circuit 40.

[0198] Step S14: After the process in Step S12 or S13, if i < M, then i is incremented by 1, and the process starting from Step S11 is repeated.

[0199] While the data processing device 20 searches for a solution, the processes in Steps S15 to S25 are performed.

[0200] Step S15: The equivalent spin enable determination circuit 40 determines whether to flip the value of the binary variable based on the output of the conversion binary variable selection circuit 37. When the conversion binary variable selection circuit 37 outputs the identification number of the binary variable for which the value change is allowed, for example, the equivalent spin enable determination circuit 40 determines to flip the value of the binary variable. If it is determined to flip the value of the binary variable, the equivalent spin enable determination circuit 40 performs the process in Step S16, and if it is determined not to flip the value of the binary variable, it performs the process in Step S20.

[0201] Step S16: Start the loop process of M equivalent spins. When i < M + 1 is satisfied, the loop process is performed, starting from i = 1.

[0202] Step S17: The equivalent spin enable determination circuit 40 determines whether the binary variable to be flipped is included in one of the M equivalent spins. For example, the equivalent spin enable determination circuit 40 may perform the above determination based on the identification number of the binary variable output by the conversion binary variable selection circuit 37 and the table data as shown in Figure 8 If the equivalent spin enable determination circuit 40 determines that the binary variable to be flipped is included in one of the M equivalent spins, the equivalent spin enable determination circuit 40 performs the process in step S18. If the equivalent spin enable determination circuit 40 determines that the binary variable to be flipped is not included in any of the M equivalent spins, the equivalent spin enable determination circuit 40 performs the process in step S19.

[0203] Step S18: The equivalent spin enable determination circuit 40 reverses the value of En i .

[0204] Step S19: After the process of step S17 or step S18, if i < M, i is incremented by 1, and the process starting from step S17 is repeated.

[0205] Step S20: The equivalent spin enable determination circuit 40 determines whether to flip the value of the equivalent spin based on the output of the equivalent spin decoder circuit 38. For example, when the equivalent spin decoder circuit 38 outputs the identification numbers of two binary variables included in the equivalent spin for which the allowed value change, the equivalent spin enable determination circuit 40 determines to flip the value of the equivalent spin. If it is determined to flip the value of the equivalent spin, the equivalent spin enable determination circuit 40 performs the process in step S21, and if it is determined not to flip the value of the equivalent spin, the process in step S25 is performed.

[0206] Step S21: Start the loop process of the M equivalent spins. When i < M + 1 is satisfied, the loop process is executed, starting from i = 1.

[0207] Step S22: The equivalent spin enable determination circuit 40 determines whether one of the two binary variables included in the equivalent spin to be flipped is included in another equivalent spin. For example, the equivalent spin enable determination circuit 40 may be based on the identification numbers of the two binary variables output by the equivalent spin decoder circuit 38 and as shown in Figure 8The above determination is performed using the table data shown. When the equivalent spin enable determination circuit 40 determines that one of the two binary variables included in the equivalent spin to be flipped is included in the other equivalent spin, the equivalent spin enable determination circuit 40 performs the process in step S23. When the equivalent spin enable determination circuit 40 determines that any one of the two binary variables included in the equivalent spin to be flipped is not included in the other equivalent spin, the equivalent spin enable determination circuit 40 performs the process in step S24.

[0208] Step S23: The equivalent spin enable determination circuit 40 inverts the value of En. i value.

[0209] Step S24: After the process in step S22 or step S23, if i < M, i is incremented by 1, and the process starting from step S22 is repeated.

[0210] Step S25: The control circuit 46 determines whether a predetermined termination condition for the process of searching for a solution is satisfied. If it is determined that the predetermined termination condition is satisfied, the process of searching for a solution ends. If it is determined that the predetermined termination condition is not satisfied, the process starting from step S15 is repeated.

[0211] Note that Fig. 9 the order of the processes shown is an example, and the order of the processes can be changed as appropriate.

[0212] (Example of the overall operation of the data processing device 20)

[0213] Fig.10 is a timing diagram showing an example of the overall operation of the data processing device according to the first embodiment.

[0214] Fig.10 An example in which the single-bit conversion process or the equivalent spin conversion process is performed with up to eight copies is shown. The single-bit conversion process is repeated T times per unit process, and the equivalent spin conversion process is repeated Tp times per unit process. The eight copies are Ising models, each represented by the same evaluation function. The same equivalent spin is used for the eight copies. The process for each copy can be performed by pipeline processing in the data processing device 20 as shown. Figure 7 shown.

[0215] From time sequence t1 to time sequence t2, the single-bit conversion process is performed. When the single-bit conversion process is completed for the Tth time (time sequence t2), between time sequences t2 and t3, the initialization process for the local domain and the equivalent local domain is performed. During the initialization process for the local domain and the equivalent local domain, the repeated processes of the single-bit conversion process and the equivalent spin conversion process are stopped.

[0216] When the initialization process for the local domain and the equivalent local domain is completed (timing t3), Fig.10 In the example of , the equivalent spin conversion process is performed on the replicas of replica numbers 2 and 5 (from timing t3 to timing t4). On the other hand, for the replicas of replica numbers 0, 1, 3, 4, 6, and 7 for which the equivalent spin conversion process has not yet been performed, the single-bit conversion process is performed in parallel with the equivalent spin conversion process for the replicas of replica numbers 2 and 5.

[0217] Assume that in the equivalent spin conversion process, the value of the equivalent spin of the replica of replica number 2 or replica number 5 is allowed to change. At this time, the values ​​of the two binary variables included in the equivalent spin of the replica of replica number 2 or replica number 5 held in the binary variable holding circuit 32 are also updated. In addition, the N local domains of each of the replicas of replica number 2 or replica number 5 held in the local domain holding circuit 34 are also updated twice in accordance with the update of the values ​​of the two binary variables. The above-mentioned process of updating the replica of replica number 2 or replica number 5 is performed during a time equivalent to one repetition of the single-bit conversion process.

[0218] When the equivalent spin conversion process has been repeated Tp times (timing t4) and the change in the value of the equivalent spin of the replica number 2 or 5, etc. is reflected to the side of the single-bit conversion process (timing t5), the initialization process for the local domain and the equivalent local domain is performed again.

[0219] When the initialization process for the local domain and the equivalent local domain is completed (timing t6), Fig.10 In the example of , equivalent spin conversion processing is performed on the replicas of replica numbers 0, 3, and 7, while single-bit conversion processing is performed on the replicas of replica numbers 1, 2, 4, 5, and 6.

[0220] Fig.11 is a flowchart showing an example of a processing procedure in the entire data processing apparatus according to the first embodiment.

[0221] Step S30: Initialization processing is performed under the control of the control circuit 46. In the initialization processing, generation of initial values ​​of N binary variables, calculation of initial values ​​of the evaluation function, initial values ​​of the local domain, and the like are performed.

[0222] Step S31: The control circuit 46 generates M equivalent spins. Figure 3 As described, when searching for a solution to the knapsack problem, the control circuit 46 may set two binary variables corresponding to two terms having weights close to each other to an equivalent spin. Figure 5 As described, control circuit 46 may preferably set groups of binary variables having many inequality constraints that contribute in common as equivalent pairs.

[0223] In addition, in the process of step S31, the control circuit 46 performs equivalent coupling coefficient calculation, Fig. 9 The enable signal initial value calculation shown in FIG.

[0224] Step S32: The control circuit 46 performs data / operation setting. For example, in the processing of step S32, the control circuit 46 sets the initial values ​​of N binary variables in the binary variable holding circuit 32, sets the initial values ​​of N local domains in the local domain holding circuit 34, and sets the initial values ​​of the evaluation function in the E update holding circuit 43 and the minimum value update holding circuit 45. In addition, the control circuit 46 sets the initial values ​​of M equivalent spins in the equivalent spin holding circuit 23, and stores M×M equivalent coupling coefficients in the equivalent coupling coefficient memory 21. In addition, the control circuit 46 sets the initial values ​​of M equivalent spins in the equivalent spin enable determination circuit 40 as shown in FIG. Figure 8 Table data related to the enable signal is shown.

[0225] In addition, the control circuit 46 sets operating conditions such as, for example, a solution search termination condition as an operating setting. In the case where the simulated annealing method is implemented as an MCMC method, for example, a start value and an end value of a temperature parameter, a value by which the temperature parameter is to be multiplied for each predetermined temperature change cycle, etc. are set. In the case where the replica exchange method is implemented as an MCMC method, for example, setting of a value of the temperature parameter for each replica, setting of a replica exchange cycle, etc. are performed.

[0226] Step S33: Single-bit conversion processing is performed under the control of the control circuit 46. An example of the procedure in the single-bit conversion processing will be described later (see Fig.12 ).

[0227] Step S34: The control circuit 46 determines whether to end the single-bit conversion process. For example, in the case where the single-bit conversion process has been repeated a predetermined number of times, the control circuit 46 determines to end the single-bit conversion process. In the case where it is determined that the single-bit conversion process is to be ended, the process in step S35 is performed. In the case where it is determined that the single-bit conversion process is not to be ended, the process in step S33 is repeated.

[0228] Step S35: The control circuit 46 determines whether to perform an equivalent spin conversion process. For example, in a single-bit conversion process, in the case where a change in the binary variable value is not accepted within a predetermined period of time, there is a possibility that the solution is fitted into a local solution, and therefore, the control circuit 46 determines to perform an equivalent spin conversion process. In the case where it is determined that the equivalent spin conversion process is to be performed, the process in step S36 is performed. In the case where it is determined that the equivalent spin conversion process is not to be performed, the process in step S40 is performed.

[0229] Step S36 : The control circuit 46 performs matching processing to match the values ​​of the M equivalent spins held in the equivalent spin holding circuit 23 with the values ​​of the N binary variables held in the binary variable holding circuit 32 .

[0230] Step S37: The initial equivalent local domain calculation circuit 41 calculates the initial value of the equivalent local domain represented by expression (17) or expression (18) using, for example, binary variables, coupling coefficients, and the value of the local domain. The calculated initial value of the equivalent local domain is held in the equivalent local domain holding circuit 25.

[0231] Step S38: The equivalent spin conversion process is performed under the control of the control circuit 46. An example of the process in the equivalent spin conversion process will be described later (see Fig.13 ).

[0232] Step S39: The control circuit 46 determines whether to end the equivalent spin conversion process. For example, in the case where the equivalent spin conversion process has been repeated a predetermined number of times, the control circuit 46 determines to end the equivalent spin conversion process. In the case where it is determined that the equivalent spin conversion process is to be ended, the process in step S40 is performed. In the case where it is determined that the equivalent spin conversion process is not to be ended, the process in step S38 is repeated.

[0233] Note that in the case where the simulated annealing method is implemented as the MCMC method, the control circuit 46 reduces the value of the above-mentioned temperature parameter according to a predetermined temperature parameter change schedule while repeating the single-bit conversion process or the equivalent spin conversion process. Therefore, the threshold value to be used by the conversion equivalent spin selection circuit 29 and the conversion binary variable selection circuit 37 is updated.

[0234] In the case where the replica exchange method is implemented as an MCMC method, a single-bit conversion process or an equivalent spin conversion process is repeated for each of a plurality of replicas in which corresponding different temperature parameter values ​​are set. The control circuit 46 performs a replica exchange each time the process has been repeated a predetermined number of times. For example, the control circuit 46 randomly selects two replicas from a plurality of replicas. Then, the control circuit 46 performs a temperature parameter value exchange between the two selected replicas with a predetermined exchange probability based on the difference in the value of the evaluation function or the difference in the temperature parameter value between the replicas. Instead of the temperature parameter value exchange, the control circuit 46 may perform an exchange of the values ​​of N binary variables or the values ​​of M equivalent spins between the two selected replicas.

[0235] Step S40: The control circuit 46 determines whether a predetermined solution search termination condition is satisfied. In the case where it is determined that the solution search termination condition is satisfied, the processing in step S41 is performed. In the case where it is determined that the solution search termination condition is not satisfied, the processing starting from step S33 is repeated.

[0236] Step S41: Under the control of the control circuit 46, the search result of the solution search is output. After that, the search process ends. In the process of step S41, when the termination condition is met, for example, the values ​​of the N binary variables held in the minimum value update holding circuit 45 are output as the solution of the combinatorial optimization problem. The control circuit 46 can cause a display device (not shown) to display the solution, or can cause a communication circuit (not shown) to send the solution to an external device.

[0237] (Processing process in single-bit conversion processing)

[0238] Fig.12 is a flowchart showing an example of a processing procedure in a single-bit conversion process.

[0239] Step S50 : The ΔE calculation circuit 35 calculates the amount of change in the value of the evaluation function for each of the N binary variables using the local region held in the local region holding circuit 34 .

[0240] Step S51: The conversion binary variable selection circuit 37 determines whether the value of each of the N binary variables can be changed (conversion acceptance possibility), for example, based on the amount of change in the value of the evaluation function calculated for the corresponding N binary variables.

[0241] Step S52: In the case where changes in the values ​​of a plurality of binary variables are allowed, the conversion binary variable selection circuit 37 selects one binary variable randomly or according to a predetermined rule.

[0242] Step S53: The control circuit 46 determines whether the value of the binary variable can be inverted based on the output from the conversion binary variable selection circuit 37. In the case where it is determined that it can be inverted, the processing in step S54 is performed. In the case where it is determined that it cannot be inverted, the repetition of the single-bit conversion processing ends.

[0243] Step S54 : The binary variable updating circuit 31 updates the value of the binary variable selected by the conversion binary variable selecting circuit 37 .

[0244] Step S55 : The E update hold circuit 43 updates the value of the evaluation function using the change amount of the evaluation function output by the conversion binary variable selection circuit 37 .

[0245] Step S56 : The local domain updating circuit 33 updates the N local domains using one coupling coefficient among the plurality of coupling coefficients read from the coupling coefficient memory 30 based on the identification number output from the conversion binary variable selecting circuit 37 .

[0246] Step S57: According to Fig. 9 In the process shown, the equivalent spin enable determination circuit 40 updates the enable signal.

[0247] Thus, the repetition of the single-bit conversion process ends.

[0248] (Processing process in equivalent spin conversion processing)

[0249] Fig.13 is a flowchart showing an example of a processing procedure in an equivalent spin conversion process.

[0250] Step S60 : The ΔE calculation circuit 26 calculates the amount of change in the value of the evaluation function for each of the M equivalent spins using the equivalent local region held in the equivalent local region holding circuit 25 .

[0251] Step S61: The conversion equivalent spin selection circuit 29 determines whether the value of each of the equivalent spins having 1 as an enable signal can be changed (conversion acceptance possibility), for example, based on the amount of change in the value of the evaluation function calculated for the corresponding M equivalent spins. Note that for the equivalent spins having 0 as an enable signal, the determination on the conversion acceptance possibility is not performed.

[0252] Step S62: In the case where the values ​​of a plurality of equivalent spins are allowed to vary, the conversion equivalent spin selection circuit 29 may select an equivalent spin randomly or according to a predetermined rule.

[0253] Step S63: The control circuit 46 determines whether the value of the equivalent spin can be flipped based on the output from the conversion equivalent spin selection circuit 29. If it is determined that it can be flipped, the processing in step S64 is performed. If it is determined that it cannot be flipped, the repetition of the equivalent spin conversion processing ends.

[0254] Step S64 : The equivalent spin update circuit 22 updates the value of the equivalent spin selected by the conversion equivalent spin selection circuit 29 .

[0255] Step S65 : The E update hold circuit 43 updates the value of the evaluation function using the amount of change of the evaluation function output by the conversion equivalent spin selection circuit 29 .

[0256] Step S66 : The binary variable updating circuit 31 updates the values ​​of the two binary variables included in the equivalent spin selected by the conversion equivalent spin selecting circuit 29 .

[0257] Step S67: The local domain update circuit 33 updates the N local domains twice using one of the plurality of coupling coefficients read from the coupling coefficient memory 30 based on the two identification numbers output from the equivalent spin decoder circuit 38. In addition, the equivalent local domain update circuit 24 updates the M equivalent local domains using one of the plurality of equivalent coupling coefficients read from the equivalent coupling coefficient memory 21 based on the identification number output from the conversion equivalent spin selection circuit 29.

[0258] Step S68: According to Fig. 9 In the process shown, the equivalent spin enable determination circuit 40 updates the enable signal.

[0259] Thus, the repetition of the equivalent spin conversion process ends.

[0260] Notice, Figures 11 to 13 The order of processing shown is an example, and the order of processing may be changed as appropriate.

[0261] As described above, the equivalent spin holding circuit 23 of the data processing device 20 holds a representative value (value of equivalent spin) which is one value of two or more binary variables of each variable group in a plurality of variable groups (equivalent spins), each variable group being formed by two binary variables of different values ​​or the same value included in the evaluation function. In addition, the equivalent coupling coefficient memory 21 stores a plurality of equivalent coupling coefficients indicating the magnitude of the interaction between the respective equivalent spins. At the same time, the equivalent local domain holding circuit 25 holds an equivalent local domain for specifying a first change amount of the value of the evaluation function caused by a change in the value of each of the plurality of equivalent spins. The ΔE calculation circuit 26 calculates a first change amount for each of the plurality of equivalent spins using the equivalent local domain. In addition, the conversion equivalent spin selection circuit 29 accepts a change in the value of one of the plurality of spins based on the above-mentioned change amount calculated for the corresponding equivalent spin of the plurality of equivalent spins. The equivalent spin update circuit 22 updates the value of the equivalent spin of the plurality of equivalent spins for which a change in value is accepted. Furthermore, the equivalent local domain updating circuit 24 updates the equivalent local domain using the equivalent coupling coefficient read out based on the identification number of the equivalent spin for which a change in value has been accepted, among the plurality of equivalent coupling coefficients stored in the equivalent coupling coefficient memory 21 .

[0262] With such a data processing device 20, an equivalent spin formed by two binary variables can be processed as one binary variable, and therefore, a double-bit conversion process can be performed by parallel experiments as in a single-bit conversion process (a change in the value of the equivalent spin corresponds to a double-bit conversion). Therefore, a double-bit conversion can be efficiently evaluated by parallel experiments. In addition, since parallel experiments can be performed, search efficiency is improved, and problem solving performance is enhanced.

[0263] In addition, the data processing device 20 includes a single-bit conversion circuit unit 20b and a control circuit 46, and the single-bit conversion circuit unit 20b accepts the change in the value of one of the multiple binary variables based on the change in the value of the evaluation function caused by the change in the value of each binary variable of the evaluation function including the above-mentioned multiple variable groups. The control circuit 46 switches between the equivalent spin conversion processing of the equivalent spin conversion circuit unit 20a and the single-bit conversion processing of the single-bit conversion circuit unit 20b. Therefore, when the solution is fitted into the local solution in the single-bit conversion processing, a flexible search can be effectively performed according to the situation, such as switching to the equivalent spin conversion processing.

[0264] In addition, the data processing device 20 further includes an equivalent spin decoder circuit 38, which outputs an identification number for specifying two binary variables included in the equivalent spin specified by the identification number based on the identification number output from the conversion equivalent spin selection circuit 29. Then, the single-bit conversion circuit unit 20b updates the values ​​of the two binary variables corresponding to these identification numbers. Therefore, the change in the value of the equivalent spin in the equivalent spin conversion circuit unit 20a can be reflected in the binary variable processed by the single-bit conversion circuit unit 20b.

[0265] In addition, the data processing device 20 includes an equivalent spin enable determination circuit 40 as described above. The equivalent spin enable determination circuit 40 generates an enable signal indicating whether to allow a change in the value of a plurality of equivalent spins. In the case where the single-bit conversion circuit unit 20b accepts a change in the value of a certain binary variable among a plurality of binary variables, the equivalent spin enable determination circuit 40 inverts the value of the enable signal associated with the equivalent spin including the binary variable among the plurality of equivalent spins. Therefore, the binary variable processed by the equivalent spin conversion circuit unit 20a can be matched with the equivalent spin of a different value or the same value processed by the unit conversion circuit unit 20b.

[0266] In addition, the data processing device 20 includes an initial equivalent local domain calculation circuit 41. The initial equivalent local domain calculation circuit 41 calculates the initial value of the equivalent local domain using the multiple binary variables and the multiple coupling coefficients obtained by the processing performed by the single-bit conversion circuit unit 20b and the value of the local domain. Therefore, an equivalent spin conversion process reflecting the result of the single-bit conversion process becomes possible.

[0267] Note that the data processing device 20 may process conversion processing of three or more bits using equivalent spins each including three or more binary variables. In this case, the mathematical formula for calculating the equivalent coupling coefficient and the equivalent local domain changes as appropriate.

[0268] For example, the data processing device 20 first calculates the equivalent coupling coefficient and the equivalent local domain of the equivalent spin formed by two binary variables of different values ​​or the same value among the three binary variables. After that, the data processing device 20 regards the equivalent spin as a binary variable and calculates the equivalent coupling coefficient and the equivalent local domain with other binary variables to obtain the equivalent spin formed by the three binary variables.

[0269] Such a data processing apparatus 20 can be expected to be used as a technique for obtaining an accurate solution at high speed when solving various problems in modern society that can be converted into combinatorial optimization problems.

[0270] (Second Embodiment)

[0271] Fig.14 1 is a diagram showing an example of a data processing device according to the second embodiment. Fig.14 In, with Figure 7 Elements identical to those of the data processing device 20 shown are replaced by Figure 7 Note that in Fig.14 Not shown Figure 7 The ΔE selection circuit 42, the E update and hold circuit 43, the comparison circuit 44 and the minimum value update and hold circuit 45 are shown.

[0272] The data processing device 50 according to the second embodiment has a function of causing the values ​​of the equivalent spin and the equivalent local field to reflect a change in the value of the binary variable every time a change in the value of the binary variable occurs during a single-bit conversion process.

[0273] In the data processing device 50 of the second embodiment, an equivalent spin conversion circuit unit 50 a is different from the equivalent spin conversion circuit unit 20 a of the data processing device 20 of the first embodiment.

[0274] The equivalent spin conversion circuit unit 50 a includes the equivalent coupling coefficient memory 21 , a storage unit 51 including update coupling coefficient memories 51 a and 51 b , and a binary variable pair update holding circuit 52 .

[0275] The update coupling coefficient memories 51a and 51b store a plurality of coupling coefficients associated with binary variables included in M ​​equivalent spins among N×N coupling coefficients.

[0276] Fig.15 It is a diagram for explaining the coupling coefficient stored in the updated coupling coefficient memory.

[0277] The updated coupling coefficient memory 51a stores a coupling coefficient indicating the magnitude of the interaction between the binary variable with identification number i1 among the N binary variables and other binary variables. The updated coupling coefficient memory 51b stores a coupling coefficient indicating the magnitude of the interaction between the binary variable with identification number i2 among the N binary variables and other binary variables.

[0278] These coupling coefficients are used when updating the equivalent local domain according to the change in the value of the binary variable caused during the single-bit conversion process.

[0279] The binary variable pair update and hold circuit 52 holds every two binary variables (each binary variable pair) included in the corresponding M equivalent spins. In addition, the binary variable pair update and hold circuit 52 updates the value of the binary variable corresponding to one or two identification numbers output from the selection circuit 39 among the held binary variables. In addition, the binary variable pair update and hold circuit 52 outputs the amount of change caused by the value of the binary variable during the single-bit conversion process.

[0280] The equivalent local domain updating circuit 53 updates the equivalent local domain according to the change in the value of the equivalent spin, similarly to the equivalent local domain updating circuit 24 of the data processing device 20 of the first embodiment.

[0281] In addition, the equivalent local domain update circuit 53 updates the equivalent local domain according to the change in the value of the binary variable due to the single-bit conversion process. The equivalent local domain update circuit 53 updates the equivalent local domain held in the equivalent local domain holding circuit 25 using the coupling coefficient read from the update coupling coefficient memories 51a and 51b based on the identification number of the binary variable selected by the selection circuit 39 at the time of the single-bit conversion process. In the case where the identification number selected at this time is j, the equivalent local domain is updated based on the following expression (21).

[0282] [Mathematical formula 21]

[0283]

[0284] The equivalent spin enable determination circuit 54 performs the following operations based on one or two identification numbers output from the selection circuit 39, similarly to the equivalent spin enable determination circuit 40 of the data processing device 20 of the first embodiment. Fig. 9 Processing shown.

[0285] (Example of Overall Operation of Data Processing Device 50)

[0286] Fig.16 is a timing chart showing an example of the overall operation of the data processing device according to the second embodiment.

[0287] Fig.16An example is shown in which a single-bit conversion process or an equivalent spin conversion process is performed with a maximum of eight copies. Each of the single-bit conversion process and the equivalent spin conversion process is repeated T times per unit process. Fig.14 The pipeline processing in the data processing device 50 is shown to perform the processing for each copy.

[0288] From timing t10 ​​to timing t11, the single-bit conversion process is performed. On the equivalent spin conversion process side, the values ​​of the binary variables included in the equivalent spin and M equivalent local domains are updated according to the changes in the values ​​of the binary variables caused by the single-bit conversion process. However, the equivalent spin conversion process has not actually been performed.

[0289] When the single-bit conversion process is completed for the Tth time (timing t11), the initialization process for the local domain and the equivalent local domain is not performed, but the next unit process is performed (from timing t11 to timing t12).

[0290] exist Fig.16 In the example of , from timing t11 to timing t12, the equivalent spin conversion process is performed on the replicas of replica numbers 2 and 5. On the other hand, for the replicas of replica numbers 0, 1, 3, 4, 6, and 7 for which the equivalent spin conversion process has not been performed, the single-bit conversion process is performed in parallel with the equivalent spin conversion process for the replicas of replica numbers 2 and 5.

[0291] When the value of the equivalent spin of the replica number 2 or 5 is allowed to change in the equivalent spin conversion process, the values ​​of the two binary variables included in the equivalent spin of the replica number 2 or 5 held in the binary variable holding circuit 32 are also updated. The updating of the values ​​of the two binary variables of the replica number 2 or 5 can be performed during one repetition of the single-bit conversion process. Similarly, the values ​​of the two binary variables included in the equivalent spin of the replica number 2 or 5 held in the binary variable pair update holding circuit 52 are also updated.

[0292] Among the binary variables of the replica numbers 0, 1, 3, 4, 6 and 7 held in the binary variable pair update holding circuit 52, those whose values ​​have been changed due to the single-bit conversion process are updated. In addition, at the same time as the updating, the equivalent local domain is also updated.

[0293] exist Fig.16 In the example of , as the next unit processing (timing t12 and later), equivalent spin conversion processing is performed on replica numbers 0, 3 and 7, while single-bit conversion processing is performed on replica numbers 1, 2, 4, 5 and 6.

[0294] Fig.17 is a timing chart showing an example of the processing sequence in the update process. Note that Fig.17 A first-in-first-out (FIFO) is shown for adjusting processing timing.

[0295] A test (e.g., determination on the possibility of conversion acceptance) in the single-bit conversion process is performed (timing t20), and in the case where there is a binary variable for which a change in value is allowed, the value of the binary variable and the N local domains are updated (timing t21). At this time, on the equivalent spin conversion process side, the values ​​of the binary variables included in the equivalent spin and the M equivalent local domains are also updated according to the change in the value of the binary variable caused by the single-bit conversion process.

[0296] In the case where there is an equivalent spin for which the allowed value changes in the test (timing t22) in the equivalent spin conversion process, the value of the equivalent spin and the M equivalent local domains are updated (timing t23 to timing t24). At this time, on the single-bit conversion processing side, the values ​​of the two binary variables included in the equivalent spin and the N local domains are also updated (from timing t23 to timing t25).

[0297] Fig.18 is a flowchart showing an example of a processing procedure in the entire data processing apparatus according to the second embodiment.

[0298] The processing in steps S70 to S72 is the same as Fig.11 The processes in steps S30 to S32 shown are the same.

[0299] Step S73: Single-bit conversion processing is performed under the control of the control circuit 46. An example of the procedure in the single-bit conversion processing will be described later (see Fig.19 ).

[0300] Step S74: The control circuit 46 determines whether to end the single-bit conversion process. For example, in the case where the single-bit conversion process has been repeated a predetermined number of times, the control circuit 46 determines to end the single-bit conversion process. In the case where it is determined that the single-bit conversion process is to be ended, the process in step S75 is performed. In the case where it is determined that the single-bit conversion process is not to be ended, the process in step S73 is repeated.

[0301] Step S75: The control circuit 46 determines whether to perform the equivalent spin conversion process. In the case where it is determined that the equivalent spin conversion process is to be performed, the process in step S76 is performed. In the case where it is determined that the equivalent spin conversion process is not to be performed, the process in step S78 is performed.

[0302] The processing in steps S76 to S79 ​​is the same as Fig.11 The processing in steps S38 to S41 shown is the same.

[0303] (Processing process in single-bit conversion processing)

[0304] Fig.19 is a flowchart showing an example of a processing procedure in a single-bit conversion process in the data processing device according to the second embodiment.

[0305] The processing in steps S80 to S86 is the same as Fig.12 The processing in steps S50 to S56 shown is the same.

[0306] Step S87: Binary variable pair update The holding circuit 52 updates the value of the binary variable whose value has changed during the single-bit conversion process, among the binary variables included in the held equivalent spin.

[0307] Step S88: The equivalent local domain updating circuit 53 updates the equivalent local domain according to the change in the value of the binary variable due to the single-bit conversion process.

[0308] Step S89: The equivalent spin enable determination circuit 54 updates the enable signal according to the change in the value of the binary variable caused in the process of step S87. Thus, the repetition of the single-bit conversion process ends.

[0309] Notice, Figure 18 to Figure 19 The order of processing shown is an example, and the order of processing may be changed as appropriate.

[0310] By using the data processing device 50 of the second embodiment as described above, an effect similar to that of the data processing device 20 of the first embodiment can be achieved. In addition, the equivalent spin conversion circuit unit 50a includes update coupling coefficient memories 51a and 51b, which store multiple coupling coefficients related to the binary variables included in the equivalent spin. When the single-bit conversion circuit unit 20b accepts a change in the value of a certain binary variable among the multiple binary variables, the equivalent local domain update circuit 53 then uses the change in the value of the binary variable and one coupling coefficient related to the binary variable among the multiple coupling coefficients to update the equivalent local domain. Therefore, when the single-bit conversion process is switched to the equivalent spin conversion process, the initialization process for the equivalent local domain becomes unnecessary.

[0311] (Third Embodiment)

[0312] Fig. 20 : is a diagram showing an example of a data processing device according to a third embodiment. Fig. 20 In, with Fig.14 Elements identical to those of the data processing device 50 shown are represented by Fig.14 Note that in Fig. 20 Not shown Figure 7 The E update hold circuit 43, the comparison circuit 44 and the minimum value update hold circuit 45 are shown.

[0313] The data processing device 60 according to the third embodiment is integrated Fig.14 The equivalence shown is obtained from some of the circuits of the spin conversion circuit unit 50a and some of the circuits of the single-bit conversion circuit unit 20b.

[0314] The data processing device 60 includes a storage unit 61 including an equivalent coupling coefficient memory 21, a coupling coefficient memory 30, and update coupling coefficient memories 51a and 51b, an equivalent spin / binary variable update circuit 62, and an equivalent spin / binary variable holding circuit 63. In addition, the data processing device 60 includes an equivalent local domain / local domain update circuit 64, an equivalent local domain / local domain holding circuit 65, a ΔE calculation circuit 66, a ΔE holding circuit 67, and a conversion equivalent spin / binary variable selection circuit 68.

[0315] The equivalent spin / binary variable updating circuit 62 is implemented by Fig.14 The equivalent spin update circuit 22 and the binary variable update circuit 31 shown are integrated.

[0316] The equivalent spin / binary variable holding circuit 63 is Fig.14 The equivalent spin holding circuit 23 shown is a combination of the binary variable holding circuit 32. That is, the equivalent spin / binary variable holding circuit 63 holds the values ​​of M equivalent spins and the values ​​of N binary variables.

[0317] The equivalent local domain / local domain update circuit 64 is implemented by Fig.14 The equivalent local domain update circuit 53 and the local domain update circuit 33 shown are integrated.

[0318] The equivalent local domain / local domain holding circuit 65 is Fig.14 The equivalent local domain holding circuit 25 shown is a combination of the local domain holding circuit 34. That is, the equivalent local domain / local domain holding circuit 65 holds M equivalent local domains and N local domains.

[0319] The ΔE calculation circuit 66 is a circuit that calculates Fig.14 The ΔE calculation circuits 26 and 35 shown are integrated.

[0320] ΔE holding circuit 67 is Fig.14 The ΔE holding circuit 67 is a combination of the ΔE holding circuits 27 and 36. That is, the ΔE holding circuit 67 holds the amount of change in the evaluation function caused by the change in the values ​​of the corresponding M equivalent spins, and the amount of change in the value of the evaluation function caused by the change in the values ​​of the corresponding N binary variables.

[0321] The conversion equivalent spin / binary variable selection circuit 68 is achieved by Fig.14 The conversion equivalent spin selection circuit 29 and the conversion binary variable selection circuit 37 shown are integrated.

[0322] (Example of Overall Operation of Data Processing Device 60)

[0323] Fig.21 is a timing chart showing an example of the overall operation of the data processing apparatus according to the third embodiment.

[0324] In the data processing device 60 of the third embodiment, the update process in the single-bit conversion process and the update process in the equivalent spin conversion process are performed in a time-division manner. Fig.16 As shown in the timing diagram, Fig.21 Up to eight copies in the FPGA perform a single-bit conversion process or an equivalent spin conversion process.

[0325] exist Fig.21 In the example of , in the first unit process, a single-bit conversion process is performed on all replicas. In the second unit process, an equivalent spin conversion process is performed on replica numbers 2 and 5, and a single-bit conversion process is performed on the other replicas. In the third unit process, an equivalent spin conversion process is performed on replica numbers 0, 3, and 7, and a single-bit conversion process is performed on the other replicas. "S" indicates a process related to a single-bit conversion process, and "P" indicates a process related to an equivalent spin.

[0326] In the first unit process, a test in the single-bit conversion process (e.g., determination on the possibility of conversion acceptance) is performed (timing t30), and in the case where there is a binary variable for which a change in value is allowed, the value of the binary variable and the N local domains are updated (from timing t31 to timing t32). In addition, on the equivalent spin conversion process side, the values ​​of the binary variables included in the equivalent spin and the M equivalent local domains are also updated according to the change in the value of the binary variable caused by the single-bit conversion process (from timing t32 to timing t33). Note that the black period represents an idle period.

[0327] In the second unit process, the update process accompanied by the change of the value of the binary variable in the single-bit conversion process is performed in the same manner as in the first unit process. In the case where there is an equivalent spin for which the allowed value changes in the test (timing t34) in the equivalent spin conversion process, the value of the equivalent spin and the M equivalent local domains are updated (timing t35 to timing t36). In addition, on the single-bit conversion process side, the values ​​of the two binary variables included in the equivalent spin and the N local domains are also updated (from timing t36 to timing t37).

[0328] By using the data processing device 60 of the third embodiment as described above, effects similar to those of the data processing device 50 of the second embodiment can be achieved. In addition, by integrating a circuit that performs a single-bit conversion process and a circuit that performs an equivalent spin conversion process, the amount of circuits (e.g., the number of arithmetic units) can be reduced.

[0329] Note that circuit integration as described above can be employed in the data processing device 20 of the first embodiment.

[0330] Note that the processing details of each of the above embodiments (e.g., Fig. 9 , Figures 11 to 13 , Fig.18 and Fig.19 ) can be implemented by software that causes a data processing device to execute a program.

[0331] The program can be recorded in a computer-readable recording medium. For example, a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. can be used as a recording medium. Examples of magnetic disks include floppy disks (FD) and HDDs. Examples of optical disks include compact disks (CDs), recordable (R) / rewritable (RW) CDs, digital versatile disks (DVDs), and DVD-R / RWs. Programs are sometimes recorded in portable recording media and distributed. In this case, the program can be copied from the portable recording medium to another recording medium before execution.

[0332] Fig. 22 is a diagram illustrating an example of hardware of a computer as an example of a data processing device.

[0333] The computer 70 includes a processor 71, a random access memory (RAM) 72, an HDD 73, a graphics processing unit (GPU) 74, an input interface 75, a medium reader 76, and a communication interface 77. The above-mentioned units are coupled to a bus.

[0334] The processor 71 loads at least a part of the program and data stored in the HDD 73 into the RAM 72, and executes the program. Note that, for example, the processor 71 may include a plurality of processor cores. In addition, the computer 70 may include a plurality of processors. Note that a collection of a plurality of processors (multiprocessors) may be referred to as a "processor". As the processor 71, a central processing unit (CPU), a GPU, a digital signal processor (DSP), etc. may be used.

[0335] The RAM 72 is a volatile semiconductor memory that temporarily stores programs to be executed by the processor 71 and data to be used by the processor 71 for arithmetic operations. Note that the computer 70 may include a memory of a different type from the RAM 72, or may include a plurality of memories.

[0336] The HDD 73 is a non-volatile storage device that stores software programs and data such as an operating system (OS), middleware, and application software. The programs include, for example, a program for causing the computer 70 to perform a process of searching for a solution to a combinatorial optimization problem as described above. Note that the computer 70 may include some other types of storage devices, such as a flash memory and a solid-state drive (SSD), or may include a plurality of non-volatile storage devices.

[0337] The GPU 74 outputs an image (e.g., an image representing a calculation result of a combinatorial optimization problem, etc.) to a display 74a coupled to the computer 70 according to a command from the processor 71. As the display 74a, a cathode ray tube (CRT) display, a liquid crystal display (LCD), a plasma display panel (PDP), an organic electroluminescence (OEL) display, etc. can be used.

[0338] The input interface 75 acquires an input signal from an input device 75a coupled to the computer 70, and outputs the acquired input signal to the processor 71. A pointing device (such as a mouse, a touch panel, a touch pad, or a trackball), a keyboard, a remote controller, a button switch, etc. can be used as the input device 75a. In addition, various types of input devices can be coupled to the computer 70.

[0339] The medium reader 76 is a reading device that reads the program and data recorded in the recording medium 76a. For example, a magnetic disk, an optical disk, a magneto-optical disk (MO), a semiconductor memory, etc. can be used as the recording medium 76a. Examples of magnetic disks include FD and HDD. Examples of optical disks include CD and DVD.

[0340] The medium reader 76 copies the program or data read from the recording medium 76a to another recording medium such as the RAM 72 or the HDD 73, for example. The read program is executed by the processor 71, for example. Note that the recording medium 76a may be a portable recording medium and is sometimes used for distribution of programs or data. In addition, the recording medium 76a and the HDD 73 are sometimes referred to as computer-readable recording media.

[0341] The communication interface 77 is an interface connected to a network 77a and communicates with another information processing device via the network 77a. The communication interface 77 may be a wired communication interface coupled to a communication device such as a switch through a cable, or may be a wireless communication interface coupled to a base station through a wireless link.

[0342] Although one aspect of the data processing apparatus, the program, and the data processing method according to the embodiments has been described based on the embodiments, this is only an example and is not limited to the above description.

[0343] For example, in the above description, it is assumed that the value of the state variable is 0 or 1, but by appropriately converting the mathematical formula, a variable having a value of -1 or +1 can also be used as the state variable.

[0344] 1. A data processing device, comprising:

[0345] a first holding circuit that holds a representative value of each of a plurality of variable groups, the variable groups being formed of at least two binary variables of different values ​​or equal values ​​included in an evaluation function of a combinatorial optimization problem, and the representative value being a value of one of the at least two binary variables;

[0346] a first memory storing a plurality of first coupling coefficients indicating magnitudes of interactions between the variable groups in the plurality of variable groups;

[0347] a second holding circuit that holds a first local domain to be used to specify a first amount of change in a value of the evaluation function to be caused by a change in the representative value of each of the plurality of variable groups;

[0348] a variation calculation circuit for calculating the first variation for each of the plurality of variable groups using the first local domain;

[0349] a selection circuit that accepts a change in the representative value of one of the plurality of variable groups based on the first change amount calculated for each of the plurality of variable groups;

[0350] a first updating circuit that updates the representative value of a first variable group among the plurality of variable groups, the change in the representative value of which is accepted; and

[0351] A second updating circuit updates the first local domain using a second coupling coefficient read from the plurality of first coupling coefficients stored in the first memory based on a first identification number of the first variable group.

[0352] 2. The data processing device according to solution 1 further comprises:

[0353] a first circuit unit, the first circuit unit comprising the first holding circuit, the first memory, the second holding circuit, the variation calculation circuit, the selection circuit, the first updating circuit, and the second updating circuit;

[0354] a second circuit unit that accepts a change in the value of one of the plurality of binary variables based on a second amount of change in the value of the evaluation function to be caused by a change in the value of each of the plurality of binary variables of the evaluation function including the plurality of variable groups; and

[0355] A control circuit switches between the processing of the first circuit unit and the processing of the second circuit unit.

[0356] 3. The data processing device according to solution 2 further comprises:

[0357] a decoder circuit that outputs at least two second identification numbers specifying the at least two binary variables included in the first variable group based on the first identification number,

[0358] The second circuit unit updates the values ​​of the at least two binary variables corresponding to the at least two second identification numbers.

[0359] 4. The data processing device according to solution 2 further comprises:

[0360] an enable determination circuit that generates an enable signal indicating whether to allow a change in the representative values ​​of the plurality of variable groups,

[0361] When the second circuit unit accepts a change in the value of a first binary variable among the plurality of binary variables, the enable determination circuit inverts the value of the enable signal associated with a second variable group among the plurality of variable groups including the first binary variable.

[0362] 5. The data processing device according to claim 2, wherein:

[0363] The second circuit unit comprises:

[0364] a third holding circuit that holds a value of each of the plurality of binary variables of the evaluation function;

[0365] a second memory storing a plurality of third coupling coefficients indicating magnitudes of interactions between respective ones of the plurality of binary variables; and

[0366] a fourth holding circuit that holds a second local domain to be used for specifying the second variation, and

[0367] The data processing device further includes an initial value calculation circuit that calculates an initial value of the first local domain using the second local domain, the plurality of third coupling coefficients, and the values ​​of the plurality of binary variables obtained in the processing of the second circuit unit.

[0368] 6. The data processing device according to claim 2, wherein:

[0369] The second circuit unit comprises:

[0370] a third holding circuit that holds a value of each of the plurality of binary variables of the evaluation function;

[0371] a second memory storing a plurality of third coupling coefficients indicating magnitudes of interactions between respective ones of the plurality of binary variables; and

[0372] a fourth holding circuit that holds a second local domain to be used for specifying the second variation amount,

[0373] The first circuit unit further includes:

[0374] a third memory storing a plurality of fourth coupling coefficients associated with binary variables included in the plurality of variable groups among the plurality of third coupling coefficients, and

[0375] When the second circuit unit accepts a change in the value of a first binary variable among the plurality of binary variables, the second update circuit updates the first local domain using an amount of change in the value of the first binary variable and a fourth coupling coefficient among the plurality of fourth coupling coefficients associated with the first binary variable.

[0376] 7. The data processing device according to item 2, wherein a part of the first circuit unit and a part of the second circuit unit are integrated.

[0377] 8. A data processing program that causes a computer to execute the following processing:

[0378] maintaining a representative value of each of a plurality of variable groups, the variable group being formed of at least two binary variables of different values ​​or equal values ​​included in an evaluation function of a combinatorial optimization problem, and the representative value being a value of one of the at least two binary variables;

[0379] storing a plurality of first coupling coefficients indicating magnitudes of interactions between the variable groups in the plurality of variable groups;

[0380] maintaining a first local domain to be used to specify a first amount of change in a value of the evaluation function to be caused by a change in the representative value of each of the plurality of variable groups;

[0381] Calculate the first variation for each variable group in the plurality of variable groups using the first local domain;

[0382] accepting a change in the representative value of one of the plurality of variable groups based on the first change amount calculated for each of the plurality of variable groups;

[0383] updating the representative value of a first variable group among the plurality of variable groups, in which a change in the representative value is accepted; and

[0384] The first local domain is updated using a second coupling coefficient read from the plurality of first coupling coefficients stored in the first memory based on a first identification number of the first variable group.

[0385] 9. A data processing method, comprising:

[0386] maintaining a representative value of each of a plurality of variable groups, the variable group being formed of at least two binary variables of different values ​​or equal values ​​included in an evaluation function of a combinatorial optimization problem, and the representative value being a value of one of the at least two binary variables;

[0387] storing a plurality of first coupling coefficients indicating magnitudes of interactions between the variable groups in the plurality of variable groups;

[0388] maintaining a first local domain to be used to specify a first amount of change in a value of the evaluation function to be caused by a change in the representative value of each of the plurality of variable groups;

[0389] Calculate the first variation for each variable group in the plurality of variable groups using the first local domain;

[0390] accepting a change in the representative value of one of the plurality of variable groups based on the first change amount calculated for each of the plurality of variable groups;

[0391] updating the representative value of a first variable group among the plurality of variable groups, in which a change in the representative value is accepted; and

[0392] The first local domain is updated using a second coupling coefficient read from the plurality of first coupling coefficients stored in the first memory based on a first identification number of the first variable group.

Claims

1. A data processing device, comprising: a first holding circuit that holds a representative value of each of a plurality of variable groups, the variable groups being formed of at least two binary variables of different values ​​or equal values ​​included in an evaluation function of a combinatorial optimization problem, and the representative value being a value of one of the at least two binary variables; a first memory storing a plurality of first coupling coefficients indicating magnitudes of interactions between the variable groups in the plurality of variable groups; a second holding circuit that holds a first local domain to be used to specify a first amount of change in a value of the evaluation function to be caused by a change in the representative value of each of the plurality of variable groups; a variation calculation circuit for calculating the first variation for each of the plurality of variable groups using the first local domain; a selection circuit that accepts a change in the representative value of one of the plurality of variable groups based on the first change amount calculated for each of the plurality of variable groups; a first updating circuit that updates the representative value of a first variable group among the plurality of variable groups, the change in the representative value of which is accepted; as well as A second updating circuit updates the first local domain using a second coupling coefficient read from the plurality of first coupling coefficients stored in the first memory based on a first identification number of the first variable group.

2. The data processing device according to claim 1, further comprising: a first circuit unit, the first circuit unit comprising the first holding circuit, the first memory, the second holding circuit, the variation calculation circuit, the selection circuit, the first updating circuit, and the second updating circuit; a second circuit unit that receives a change in the value of one of the plurality of binary variables based on a second amount of change in the value of the evaluation function to be caused by a change in the value of each of the plurality of binary variables of the evaluation function comprising the plurality of variable groups; as well as A control circuit switches between the processing of the first circuit unit and the processing of the second circuit unit.

3. The data processing device according to claim 2, further comprising: a decoder circuit that outputs at least two second identification numbers specifying the at least two binary variables included in the first variable group based on the first identification number, The second circuit unit updates the values ​​of the at least two binary variables corresponding to the at least two second identification numbers.

4. The data processing device according to claim 2, further comprising: an enable determination circuit that generates an enable signal indicating whether to allow a change in the representative values ​​of the plurality of variable groups, When the second circuit unit accepts a change in the value of a first binary variable among the plurality of binary variables, the enable determination circuit inverts the value of the enable signal associated with a second variable group among the plurality of variable groups including the first binary variable.

5. The data processing device according to claim 2, wherein: The second circuit unit comprises: a third holding circuit that holds a value of each of the plurality of binary variables of the evaluation function; a second memory storing a plurality of third coupling coefficients indicating magnitudes of interactions between respective ones of the plurality of binary variables; and a fourth holding circuit that holds a second local domain to be used for specifying the second variation, and The data processing device further includes an initial value calculation circuit that calculates an initial value of the first local domain using the second local domain, the plurality of third coupling coefficients, and values ​​of the plurality of binary variables obtained by the processing of the second circuit unit.

6. The data processing device according to claim 2, wherein: The second circuit unit comprises: a third holding circuit that holds a value of each of the plurality of binary variables of the evaluation function; a second memory storing a plurality of third coupling coefficients indicating magnitudes of interactions between respective ones of the plurality of binary variables; and a fourth holding circuit that holds a second local domain to be used for specifying the second variation amount, The first circuit unit further includes: a third memory storing a plurality of fourth coupling coefficients associated with binary variables included in the plurality of variable groups among the plurality of third coupling coefficients, and When the second circuit unit accepts a change in the value of a first binary variable among the plurality of binary variables, the second update circuit updates the first local domain using an amount of change in the value of the first binary variable and a fourth coupling coefficient among the plurality of fourth coupling coefficients associated with the first binary variable.

7. The data processing device according to claim 2, wherein: A portion of the first circuit unit and a portion of the second circuit unit are integrated.

8. A computer-readable recording medium storing a data processing program, wherein the data processing program causes a computer to execute the following processing: maintaining a representative value of each of a plurality of variable groups, the variable group being formed of at least two binary variables of different values ​​or equal values ​​included in an evaluation function of a combinatorial optimization problem, and the representative value being a value of one of the at least two binary variables; storing a plurality of first coupling coefficients indicating magnitudes of interactions between the variable groups in the plurality of variable groups; maintaining a first local domain to be used to specify a first amount of change in a value of the evaluation function to be caused by a change in the representative value of each of the plurality of variable groups; Calculate the first variation for each variable group in the plurality of variable groups using the first local domain; accepting a change in the representative value of one of the plurality of variable groups based on the first change amount calculated for each of the plurality of variable groups; updating the representative value of a first variable group among the plurality of variable groups, in which a change in the representative value is accepted; as well as The first local domain is updated using a second coupling coefficient read from the plurality of first coupling coefficients stored in the first memory based on a first identification number of the first variable group.

9. A data processing method, comprising: maintaining a representative value of each of a plurality of variable groups, the variable group being formed of at least two binary variables of different values ​​or equal values ​​included in an evaluation function of a combinatorial optimization problem, and the representative value being a value of one of the at least two binary variables; storing a plurality of first coupling coefficients indicating magnitudes of interactions between the variable groups in the plurality of variable groups; maintaining a first local domain to be used to specify a first amount of change in a value of the evaluation function to be caused by a change in the representative value of each of the plurality of variable groups; Calculate the first variation for each variable group in the plurality of variable groups using the first local domain; accepting a change in the representative value of one of the plurality of variable groups based on the first change amount calculated for each of the plurality of variable groups; updating the representative value of a first variable group among the plurality of variable groups, in which a change in the representative value is accepted; as well as The first local domain is updated using a second coupling coefficient read from the plurality of first coupling coefficients stored in the first memory based on a first identification number of the first variable group.

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