Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a gate drive circuit and multiple rows of pixel circuits, the gate drive circuit comprises multiple levels of gate drive units, and the gate drive units provide gate drive signals for the pixel circuits; the gate driving unit comprises an input module which is at least connected with a first node and a second node; the power-on control module is at least connected with a first signal end, a first clock end, a first node, a second node and a third node; the node control module is at least connected with the second node and the fourth node; the first output module is connected between the first power supply end and the shift output end, and the control end of the first output module is connected with the third node; the second output module is connected between the second power supply end and the shift output end, and the control end of the second output module is connected with the fourth node; in the power-on stage, the first output module is turned off, the second output module is turned on, and the second power signal controls the pixel circuit to be turned off. The power-on splash screen problem can be solved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In a display panel, a driving circuit arranged in a non-display area is an indispensable circuit structure, which is used to realize the display, touch and other functions of the display panel.

[0003] The driving circuit is usually composed of a multi-stage driving unit, and the driving chip provides an electrical signal to the driving circuit through a signal line to enable the driving circuit to operate normally.

[0004] However, some existing display panels have abnormal output problems of driving circuits during the power-on phase, resulting in screen flickering and affecting display effects. Summary of the invention

[0005] The present invention provides a display panel and a display device to solve the screen flashing problem existing in the current display panel power-on initialization process.

[0006] According to one aspect of the present invention, a display panel is provided, comprising: a gate driving circuit and a plurality of rows of pixel circuits, wherein the gate driving circuit comprises a multi-stage gate driving unit, and the gate driving unit is used to provide a gate driving signal to the pixel circuit; the gate driving unit comprises:

[0007] An input module, connected at least to a first node and a second node, and configured to control a potential of the first node and a potential of the second node;

[0008] a power-on control module, connected at least to a first signal terminal, a first clock terminal, the first node, the second node, and a third node, and configured to control a potential of the second node and a potential of the third node in response to signals of the first signal terminal, the first clock terminal, and the first node;

[0009] a node control module, connected to at least the second node and a fourth node, and configured to control the potential of the fourth node in response to the potential of the second node;

[0010] A first output module, connected between the first power supply terminal and the shift output terminal, wherein the control terminal of the first output module is connected to the third node, and is used to control the on-off between the first power supply terminal and the shift output terminal in response to the potential of the third node;

[0011] A second output module is connected between the second power supply terminal and the shift output terminal, and a control terminal of the second output module is connected to the fourth node, and is used to control the connection between the second power supply terminal and the shift output terminal in response to the potential of the fourth node;

[0012] The working process of the gate driving unit includes: a power-on stage;

[0013] In the power-on stage, the first output module is turned off, and the power-on control module controls the second output module to turn on through the node control module, so that the shift output end outputs the second power signal provided by the second power end, and the second power signal controls the pixel circuit to turn off.

[0014] According to another aspect of the present invention, a display device is provided, comprising: the display panel as described above.

[0015] In the present invention, a power-on control module is added to the gate driving unit, and the power-on control module is used to control the potential of the second node and the potential of the third node. The node control module controls the potential of the fourth node in response to the potential of the second node; the first output module switches the on-off state between the first power supply terminal and the shift output terminal in response to the potential of the third node, and the second output module switches the on-off state between the second power supply terminal and the shift output terminal in response to the potential of the fourth node. In the present invention, in the power-on stage, the power-on control module controls to turn off the first output module and turn on the second output module, and the second power supply signal provided by the second power supply terminal is transmitted to the shift output terminal, and the corresponding transistor in the corresponding pixel circuit is controlled to turn off. Therefore, a short circuit between multiple signal terminals will not occur in the pixel circuit, and the problem of large current burning the pixel circuit and the screen flashing during the power-on initialization process is avoided, thereby improving the display effect of the display panel.

[0016] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of a gate driving circuit provided by an embodiment of the present invention;

[0020] Figure 3 is a schematic diagram of another gate driving circuit provided by an embodiment of the present invention;

[0021] Figure 4 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0022] Figure 5 is a schematic diagram of a gate driving unit provided by an embodiment of the present invention;

[0023] Figure 6 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention;

[0024] Figure 7 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention;

[0025] Figure 8 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention;

[0026] Fig. 9 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention;

[0027] Fig.10 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention;

[0028] Fig.11 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention;

[0029] Fig.12 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention;

[0030] Fig.13 yes Fig.12 A timing diagram of the gate driving unit shown;

[0031] Fig.14 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention, Figure 2 is a schematic diagram of a gate driving circuit provided by an embodiment of the present invention, Figure 3 is a schematic diagram of another gate driving circuit provided by an embodiment of the present invention, Figure 4 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figures 1 to 4 As shown, the display panel 100 includes: a gate driving circuit 110 and a plurality of rows of pixel circuits 120, the gate driving circuit 110 includes a multi-stage gate driving unit 111, and the gate driving unit 111 is used to provide a gate driving signal to the pixel circuit 120. One gate driving unit 111 can be electrically connected to a row of pixel circuits 120 to provide a gate driving signal to the row of pixel circuits 120. Those skilled in the art can design a gate driving unit to provide a gate driving signal to multiple rows of pixel circuits at the same time in other embodiments according to product requirements.

[0035] Specifically, the display panel 100 includes a first area 101 and a second area 102. Optionally, the first area 101 of the display panel 100 is a display area of ​​the display panel 100, and the second area 102 of the display panel 100 is a non-display area of ​​the display panel 100.

[0036] The first area 101 is used for display, and the first area 101 includes a plurality of pixel circuits 120, and the pixel circuits 120 are electrically connected to the light-emitting element 130. Optionally, the pixel circuits 120 in the first area 101 are arranged in an array, and a plurality of pixel circuits 120 are arranged along the first direction F1 to form a row of pixel circuits 120, and a plurality of pixel circuits 120 are arranged along the second direction F2 to form a column of pixel circuits 120, and the first direction F1 and the second direction F2 intersect. However, the arrangement of the pixel circuits 120 in the first area 101 can also be other arrangements, not limited to the array arrangement. The light-emitting element 130 electrically connected to the pixel circuit 120 can be an organic light-emitting display unit; however, in other embodiments, the light-emitting element can also be other types of light-emitting elements, such as a micro light-emitting diode display unit, which is not specifically limited.

[0037] The second area 102 includes a circuit structure for driving the pixel circuit 120 in the first area 101. Specifically, the second area 102 includes a gate driving circuit 110. The gate driving circuit 110 includes a multi-level gate driving unit 111. The gate driving circuit 110 is used to drive the pixel circuit 120 in the first area 101 to work, thereby making the light-emitting element 130 display. The first-level gate driving unit 111 can drive one or more rows of pixel circuits 120 in the first area 101 to work. Specifically, the output terminal GOUT of the first-level gate driving unit 111 is connected to one or more rows of pixel circuits 120 for driving the pixel circuit 120.

[0038] The gate driving circuit 110 includes a multi-stage gate driving unit 111, and the gate driving unit 111 includes an input terminal IN and an output terminal GOUT. The output terminal GOUT of the i-th stage gate driving unit 111 is optionally connected to the input terminal IN of the (i+m)-th stage gate driving unit 111, where i and m are both positive integers, i≥1, m≥1.

[0039] refer to Figure 2As shown, m=1 can be selected, that is, the gate driving units 111 of multiple stages in the gate driving circuit 110 are cascaded. Specifically, the output terminal GOUT of the gate driving unit 111 of one stage is connected to the corresponding row or rows of pixel circuits 120, and is also connected to the input terminal IN of the next stage gate driving unit 111. Exemplarily, the gate driving circuit 110 includes at least the (i-3)th stage gate driving unit 111a, the (i-2)th stage gate driving unit 111b, the (i-1)th stage gate driving unit 111c, the (i)th stage gate driving unit 111d, the (i+1)th stage gate driving unit 111e, the (i+2)th stage gate driving unit 111f and the (i+3)th stage gate driving unit 111g. The connection relationship is as follows: the output terminal GOUT(i-3) of the (i-3)-th level gate driving unit 111a is connected to the corresponding row or rows of pixel circuits 120, and is also connected to the input terminal IN(i-2) of the (i-2)-th level gate driving unit 111b; sequentially, the output terminal GOUT(i-2) of the (i-2)-th level gate driving unit 111b is connected to the corresponding row or rows of pixel circuits 120, and is also connected to the input terminal IN(i-1) of the (i-1)-th level gate driving unit 111c; sequentially, the output terminal GOUT(i-1) of the (i-1)-th level gate driving unit 111c is connected to the corresponding row or rows of pixel circuits 120, and is also connected to the input terminal IN(i) of the (i)-th level gate driving unit 111d; and so on.

[0040] In other embodiments, m may be greater than 1. Figure 3 As shown, m=3 can be selected. Exemplarily, the connection relationship of the gate driving circuit 110 is as follows: the output terminal GOUT(i-3) of the (i-3)-th gate driving unit 111a is connected to the corresponding row or rows of pixel circuits 120, and is also connected to the input terminal IN(i) of the (i)-th gate driving unit 111d; sequentially, the output terminal GOUT(i-2) of the (i-2)-th gate driving unit 111b is connected to the corresponding row or rows of pixel circuits 120, and is also connected to the input terminal IN(i) of the (i+1)-th gate driving unit 111e. Terminal IN(i+1); sequentially, the output terminal GOUT(i-1) of the (i-1)-th level gate driving unit 111c is connected to the corresponding row or rows of pixel circuits 120, and is also connected to the input terminal IN(i+2) of the (i+2)-th level gate driving unit 111f; the output terminal GOUT(i) of the (i)-th level gate driving unit 111d is connected to the corresponding row or rows of pixel circuits 120, and is also connected to the input terminal IN(i+3) of the (i+3)-th level gate driving unit 111g; and so on.

[0041] It can be understood that the signals at the input ends of the first to mth gate driving units can come from the driver chip, or can come from the output ends of the m dummy gate driving units arranged before the first gate driving unit. The signals at the output ends of the last m-stage gate driving units can be transmitted to the driver chip, or can be transmitted to the input ends of the m dummy gate driving units arranged after the last-stage gate driving unit.

[0042] In the present invention, the gate driving circuit 110 is not limited to the adjacent gate driving units 111 being cascaded, but may be cascaded every m gate driving units 111, where m may be equal to 2, 4, 6 or other, and the cascade relationship is specifically set according to the needs. Figure 2 and Figure 3 The cascade terminal and the output terminal of the gate driving unit 111 are the same terminal, but in other embodiments of the present invention, the cascade terminal and the output terminal of the gate driving unit 111 can be independent ports. The output terminal of the gate driving unit 111 is a shift output terminal.

[0043] The pixel circuit 120 in the display panel 100 may be arranged in various ways, and the pixel circuit 120 may be a "7T1C" structure, an "8T1C" structure, an "8T2C" structure, or other structures. The types of transistors in the pixel circuit 120 may be various, and may be an N-type transistor or a P-type transistor. Based on the various arrangements of the pixel circuit and the transistors therein, those skilled in the art may adjust the pixel circuit and the transistors therein to be adaptable according to the needs.

[0044] refer to Figure 4 As shown, in this embodiment, the pixel circuit 120 is illustrated with an "8T1C" structure. The pixel circuit 120 is electrically connected to the light-emitting element 130. The optional pixel circuit 120 includes a driving transistor M23, a first reset transistor M21, a threshold compensation transistor M22 and a light-emitting element 130; the first terminal ND3 of the driving transistor M23 is coupled to the light-emitting element 130; the first reset transistor M21 is connected between the first reset signal terminal VREF1 and the gate ND1 of the driving transistor M23; the threshold compensation transistor M22 is connected between the gate ND1 of the driving transistor M23 and the first terminal ND3 of the driving transistor M23; the shift output terminal GOUT of the gate driving unit 111 is connected to the gate of the first reset transistor M21 or the gate of the threshold compensation transistor M22.

[0045] It should be noted that the primary gate driving unit 111 can be connected to the gate of the first reset transistor M21 in one pixel circuit 120 and to the gate of the threshold compensation transistor M22. Alternatively, the primary gate driving unit 111 can be connected to the gate of the first reset transistor M21 in one row of pixel circuits 120 and to the gate of the threshold compensation transistor M22 in another row of pixel circuits 120.

[0046] The pixel circuit 120 also includes a first dimming transistor M24, a second dimming transistor M25, a data writing transistor M26, a second reset transistor M27, a bias adjustment transistor M28 and a storage capacitor Cst. The optional pixel circuit 120 is an LTPO pixel circuit. Specifically, the optional driving transistor M23, the first dimming transistor M24, the second dimming transistor M25, the data writing transistor M26, the second reset transistor M27 and the bias adjustment transistor M28 are all P-type transistors, and the exemplary P-type transistors are low temperature polysilicon (LTPS) transistors, which have the advantages of high switching speed, high carrier mobility and low power. The optional first reset transistor M21 and the threshold compensation transistor M22 are both N-type transistors, and the exemplary N-type transistors are indium gallium zinc oxide (IGZO) transistors.

[0047] The display panel 100 includes a plurality of signal lines, and the signal lines are configured to provide a voltage signal and / or a current signal to the pixel circuit 120, thereby realizing the pixel circuit 120 driving the light emitting element 130. In this embodiment, the gate of the first reset transistor M21 in the optional pixel circuit 120 is connected to the shift output terminal GOUT of the first-stage gate driving unit 111 through the signal line SL1, and the gate of the threshold compensation transistor M22 in the pixel circuit 120 is connected to the shift output terminal GOUT of the other-stage gate driving unit 111 through the signal line SL2.

[0048] The working process of the display panel 100 includes a power-on phase. In the power-on phase, the pixel circuit 120 should be turned off to prevent the pixel circuit 120 from being burned by a large current during the power-on initialization process.

[0049] However, in reality, Figure 4In the LTPO pixel circuit shown, during the power-on stage of the display panel, the gate driving unit 111 may drive the first reset transistor M21 and the threshold compensation transistor M22 in the pixel circuit 120 to be abnormally turned on. In this case, the electrical signal provided by the first reset signal line to the first reset signal terminal VREF1 will turn on the driving transistor M23. Based on this situation, if the electrical signal provided by the dimming control signal line to the dimming control terminal EM makes the first dimming transistor M24 and the second dimming transistor M25 unable to be turned off normally, or the electrical signal provided by the SL4 signal line makes the second reset transistor M27 and the bias adjustment transistor M28 unable to be turned off normally, then the first reset transistor M21, the threshold compensation transistor M22, the driving transistor M23 and the bias adjustment transistor M28 are turned on, which will cause the VREF1 signal terminal and the DVH signal terminal in the pixel circuit 120 to be short-circuited, the first reset transistor M21, the threshold compensation transistor M22, the driving transistor M23 and the first dimming transistor M24 are turned on, which will cause the VREF1 signal terminal and the PVDD signal terminal in the pixel circuit 120 to be short-circuited, and the first reset transistor M21, the threshold compensation transistor M22, the second dimming transistor M25 and the second reset transistor M27 are turned on, which will cause the VREF1 signal terminal and the VREF2 signal terminal in the pixel circuit 120 to be short-circuited, so that a large current will burn the pixel circuit 120 or the display panel 100 will flash during the power-on initialization process.

[0050] In order to solve the problem of large current burning pixel circuits or screen flickering due to abnormal driving of pixel circuits by a gate driving unit during power-on initialization of a display panel, an embodiment of the present invention provides a gate driving unit.

[0051] Figure 5 is a schematic diagram of a gate driving unit provided by an embodiment of the present invention, such as Figure 5As shown, the gate driving unit 111 includes: an input module 201, which is at least connected to the first node N1 and the second node N2, and is used to control the potential of the first node N1 and the potential of the second node N2; a power-on control module 202, which is at least connected to the first signal terminal ES1, the first clock terminal CK1, the first node N1, the second node N2 and the third node N3, and is used to respond to the signal of the first signal terminal ES1, the first clock terminal CK1 and the first node N1, Control the potential of the second node N2 and the potential of the third node N3; a node control module 203, which is at least connected to the second node N2 and the fourth node N4, and is used to respond to the potential of the second node N2, Control the potential of the fourth node N4; a first output module 204, which is connected between the first power supply terminal VG1 and the shift output terminal GOUT, and the first output module 20 The control end of the gate driving unit 111 is connected to the third node N3, and is used to control the on-off between the first power supply terminal VG1 and the shift output terminal GOUT in response to the potential of the third node N3; the second output module 205 is connected between the second power supply terminal VG2 and the shift output terminal GOUT, and the control end of the second output module 205 is connected to the fourth node N4, and is used to control the on-off between the second power supply terminal VG2 and the shift output terminal GOUT in response to the potential of the fourth node N4; the working process of the gate driving unit 111 includes: a power-on stage; in the power-on stage, the first output module 204 is turned off, and the power-on control module 202 controls the second output module 205 to turn on through the node control module 203, so that the shift output terminal GOUT outputs the second power supply signal provided by the second power supply terminal VG2, and the second power supply signal controls the pixel circuit to turn off.

[0052] In this embodiment, the gate driving unit 111 includes an input module 201 and a power-on control module 202. The input module 201 is at least connected to the first node N1 and the second node N2, and the power-on control module 202 is at least connected to the first signal terminal ES1, the first clock terminal CK1, the first node N1, the second node N2 and the third node N3. The input module 201 receives one or more input signals, and controls the potential of the first node N1 and the potential of the second node N2 based on the input signal, so that the potential of the first node N1 may jump to a high or low level, or the potential of the second node N2 may jump to a high or low level. The first signal terminal ES1 provides a first control signal, and the first control signal may be a fixed potential electrical signal. The first clock terminal CK1 provides a first clock signal, and the first clock signal may jump to a high or low level. The power-on control module 202 controls the potential of the second node N2 and the potential of the third node N3 based on the first control signal, the first clock signal and the potential of the first node N1, so that the potential of the second node N2 may jump to a high or low level, and the potential of the third node N3 may jump to a high or low level.

[0053] The node control module 203 connects the second node N2 and the fourth node N4, and controls the potential of the fourth node N4 based on the potential of the second node N2, so that the potential of the fourth node N4 may jump between high and low levels.

[0054] The control end of the first output module 204 is connected to the third node N3, and the first output module 204 is connected between the first power supply terminal VG1 and the shift output terminal GOUT. The potential of the third node N3 changes from high to low, which controls the on-off state of the first output module 204 to change. If the potential of the third node N3 controls the first output module 204 to turn on, the transmission path between the first power supply terminal VG1 and the shift output terminal GOUT is turned on, and the first power supply signal provided by the first power supply terminal VG1 can be written into the shift output terminal GOUT. If the potential of the third node N3 controls the first output module 204 to turn off, the transmission path between the first power supply terminal VG1 and the shift output terminal GOUT is disconnected.

[0055] The control end of the second output module 205 is connected to the fourth node N4, and the second output module 205 is connected between the second power supply terminal VG2 and the shift output terminal GOUT. The potential of the fourth node N4 changes from high to low, which controls the on-off state of the second output module 204 to change. If the potential of the fourth node N4 controls the second output module 205 to turn on, the transmission path between the second power supply terminal VG2 and the shift output terminal GOUT is turned on, and the second power supply signal provided by the second power supply terminal VG2 can be written to the shift output terminal GOUT. If the potential of the fourth node N4 controls the second output module 205 to turn off, the transmission path between the second power supply terminal VG2 and the shift output terminal GOUT is disconnected.

[0056] The working process of the gate driving unit 111 includes: a power-on stage.

[0057] During the power-on stage, the power-on control module 202 adjusts the potential of the third node N3 so that the potential of the third node N3 controls the first output module 204 to turn off, and the transmission path between the first power supply terminal VG1 and the shift output terminal GOUT is disconnected, and the first power supply signal provided by the first power supply terminal VG1 will not be written to the shift output terminal GOUT; at the same time, the power-on control module 202 also adjusts the potential of the second node N2, and the node control module 203 adjusts the potential of the fourth node N4 in response to the potential of the second node N2, so that the potential of the fourth node N4 controls the second output module 205 to turn on, and the transmission path between the second power supply terminal VG2 and the shift output terminal GOUT is turned on, and the second power supply signal provided by the second power supply terminal VG2 is written to the shift output terminal GOUT.

[0058] In this embodiment, the second power signal provided by the second power terminal VG2 is a fixed voltage signal, the first power signal provided by the first power terminal VG1 is a fixed voltage signal, and the second power signal is different from the first power signal.

[0059] Combination Figure 4 and Figure 5 As shown, the shift output terminal GOUT of the gate driving unit 111 is connected to the gate of the first reset transistor M21 or the gate of the threshold compensation transistor M22 in the pixel circuit 120. The first reset transistor M21 and the threshold compensation transistor M22 are both N-type transistors. Accordingly, the second power supply signal provided by the second power supply terminal VG2 is a low level, which can control the first reset transistor M21 and the threshold compensation transistor M22 to be turned off. The first power supply signal provided by the first power supply terminal VG1 is a high level, which can control the first reset transistor M21 and the threshold compensation transistor M22 to be turned on.

[0060] In the power-on stage, the power-on control module 202 adjusts the potential of the third node N3 and the potential of the fourth node N4, so that the first output module 204 is turned off and the second output module 205 is turned on, and the shift output terminal GOUT outputs the second power signal, so that the first reset transistor M21 and the threshold compensation transistor M22 in the corresponding pixel circuit 120 can be controlled to be turned off, and the driving transistor M23 in the corresponding pixel circuit 120 is turned off. Since the first reset transistor M21, the threshold compensation transistor M22 and the driving transistor M23 are all turned off, the transmission path between the VREF1 signal terminal and the DVH signal terminal in the pixel circuit 120 is disconnected, the transmission path between the VREF1 signal terminal and the PVDD signal terminal is disconnected, and the transmission path between the VREF1 signal terminal and the VREF2 signal terminal is disconnected, so that the VREF1 signal terminal will not be short-circuited with other signal terminals in the pixel circuit 120, avoiding the problem of large current burning the pixel circuit and power-on flashing.

[0061] In the present invention, a power-on control module is added to the gate driving unit, and the power-on control module is used to control the potential of the second node and the potential of the third node. The node control module controls the potential of the fourth node in response to the potential of the second node; the first output module switches the on-off state between the first power supply terminal and the shift output terminal in response to the potential of the third node, and the second output module switches the on-off state between the second power supply terminal and the shift output terminal in response to the potential of the fourth node. In the present invention, in the power-on stage, the power-on control module controls to turn off the first output module and turn on the second output module, and the second power supply signal provided by the second power supply terminal is transmitted to the shift output terminal, and the corresponding transistor in the corresponding pixel circuit is controlled to turn off. Therefore, a short circuit between multiple signal terminals will not occur in the pixel circuit, and the problem of large current burning the pixel circuit and the screen flashing during the power-on initialization process is avoided, thereby improving the display effect of the display panel.

[0062] Figure 6 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention, Figure 7 FIG. 1 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention. Figure 6 or Figure 7 As shown, the optional power-on control module 202 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a first capacitor C1; the gate of the first transistor M1 is connected to the first initialization terminal RST1, and the first transistor M1 is connected between the first signal terminal ES1 and the second node N2; the gate of the second transistor M2 is connected to the second initialization terminal RST2, the first end of the second transistor M2 is connected to the first clock terminal CK1 and the second end is connected to the first end N1a of the third transistor M3; the gate of the third transistor M3 is connected to the first node N1, the second end of the third transistor M3 is connected to the second end N1b of the first capacitor C1, and the first end of the first capacitor C1 is connected to the first node N1; the fourth transistor M4 is connected between the second end N1b of the first capacitor C1 and the third node N3; in the power-on stage, the first transistor M1 is turned on and the second transistor M2 is turned off.

[0063] Optionally, the gate of the fourth transistor M4 is connected to the first end of the second transistor M2; or, the gate of the fourth transistor M4 is connected to the second end of the second transistor M2. Figure 6 As shown, the gate of the optional fourth transistor M4 is connected to the second end of the second transistor M2, that is, the gate of the fourth transistor M4 and the second end of the second transistor M2 are commonly connected to the first end N1a of the third transistor M3. Figure 7 As shown, the gate of the optional fourth transistor M4 is connected to the first end of the second transistor M2, that is, the gate of the fourth transistor M4 and the first end of the second transistor M2 are commonly connected to the first clock terminal CK1.

[0064] Optionally, the first transistor and the second transistor are both NMOS or PMOS. Figure 6As shown, the optional first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all P-type transistors. However, it is not limited to this. In other embodiments, at least one of the first transistor, the second transistor, the third transistor and the fourth transistor can be designed as an N-type transistor according to the requirements. In this embodiment, the electrical signal provided by the first initialization terminal RST1 is a low level, which can control the first transistor M1 to turn on, so that the first control signal of the first signal terminal ES1 is written into the second node N2; the electrical signal provided by the first initialization terminal RST1 is a high level, which can control the first transistor M1 to turn off. The electrical signal provided by the second initialization terminal RST2 is a low level, which can control the second transistor M2 to turn on; the electrical signal provided by the second initialization terminal RST2 is a high level, which can control the second transistor M2 to turn off. In other embodiments, if the first transistor and the second transistor are both NMOS, then in the power-on stage, the electrical signal provided by the first initialization terminal is a high level to control the first transistor to turn on, and the electrical signal provided by the second initialization terminal is a low level to control the second transistor to turn off.

[0065] In the power-on stage, the electric signal provided by the first initialization terminal RST1 is at a low level to control the first transistor M1 to turn on, then the first control signal of the first signal terminal ES1 is written into the second node N2, and the second output module 205 is controlled to turn on through the node control module 203. At the same time, the electric signal provided by the second initialization terminal RST2 is at a high level to control the second transistor M2 to turn off, then the first clock signal will not be written into the node N1b and the third node N3.

[0066] In the power-on stage, the first clock signal is at a low level. Assuming that the second transistor M2 is turned on in the power-on stage, the first clock signal will be written into the node N1b, and the first clock signal will control the fourth transistor M4 to turn on, then the low level of the first clock signal is also written into the third node N3 through the node N1b, so that the potential of the third node N3 is at a low level, then the first output module 204 is turned on in the power-on stage, so that the first power signal is transmitted to the pixel circuit 120, and then the corresponding transistor in the pixel circuit 120 is controlled to turn on, and a short circuit between multiple signal terminals is likely to occur in the pixel circuit 120.

[0067] Based on this, in this embodiment, in the power-on stage, the electrical signal provided by the second initialization terminal RST2 controls the second transistor M2 to turn off, and the transmission path between the first clock terminal CK1 and the node N1b is turned off. Regardless of whether the fourth transistor M4 is turned on or off, the transmission path between the first clock terminal CK1 and the third node N3 is turned off, so the first clock signal provided by the first clock terminal CK1 will not affect the potential of the third node N3, and the first output module 204 maintains the off state. The signal output by the gate driving unit 111 is the second power signal, which controls the corresponding transistors in the pixel circuit 120 to turn off, avoiding the short circuit between multiple signal terminals in the pixel circuit 120, and preventing the large current from burning the pixel circuit during the power-on initialization process and the problem of screen flashing when powered on.

[0068] Similarly, if Figure 7 As shown, in the power-on stage, the electric signal provided by the second initialization terminal RST2 controls the second transistor M2 to turn off, so that the transmission path between the first clock terminal CK1 and the third node N3 is turned off, the first output module 204 maintains the off state, and the gate driving unit 111 outputs the second power signal to control the corresponding transistor in the pixel circuit 120 to turn off. The problem of large current burning the pixel circuit and power-on flashing during the power-on initialization process will not occur, thereby improving the display effect of the display panel.

[0069] Figure 8 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention, Fig. 9 FIG. 1 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention. Figure 8 or Fig. 9 As shown, the optional power-on control module 202 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a first capacitor C1; the gate of the first transistor M1 is connected to the first initialization terminal RST1, and the first transistor M1 is connected between the first signal terminal ES1 and the second node N2; the gate of the second transistor M2 is connected to the second initialization terminal RST2, the first end of the second transistor M2 is connected to the second end N1b of the first capacitor C1, and the first end of the first capacitor C1 is connected to the first node N1; the gate of the third transistor M3 is connected to the first node N1, and the first end N1a of the third transistor M3 is connected to the first clock terminal CK1; the gate of the fourth transistor M4 is connected to the first clock terminal CK1, and the first end of the fourth transistor M4 is connected to the third node N3; in the power-on stage, the first transistor M1 is turned on and the second transistor M2 is turned off.

[0070] Optionally, the second end of the second transistor M2 is connected to the second end of the third transistor M3, and the second end of the fourth transistor M4 is connected to the second end N1b of the first capacitor C2; or, the second end of the second transistor M2 is connected to the second end of the fourth transistor M4, and the second end of the third transistor M3 is connected to the second end N1b of the first capacitor C1. Figure 8 As shown, the second end of the second transistor M2 is optionally connected to the second end of the third transistor M3, and the second end of the fourth transistor M4 is connected to the second end N1b of the first capacitor C2. Fig. 9 As shown, the second end of the optional second transistor M2 is connected to the second end of the fourth transistor M4, and the second end of the third transistor M3 is connected to the second end N1b of the first capacitor C1.

[0071] Optionally, the first transistor and the second transistor are both NMOS or PMOS. Figure 8 As shown, the optional first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all P-type transistors. However, it is not limited to this. In other embodiments, at least one of the first transistor, the second transistor, the third transistor and the fourth transistor can be designed as an N-type transistor according to the requirements. In this embodiment, the electrical signal provided by the first initialization terminal RST1 is a low level, which can control the first transistor M1 to turn on, so that the first control signal of the first signal terminal ES1 is written into the second node N2; the electrical signal provided by the first initialization terminal RST1 is a high level, which can control the first transistor M1 to turn off. The electrical signal provided by the second initialization terminal RST2 is a low level, which can control the second transistor M2 to turn on; the electrical signal provided by the second initialization terminal RST2 is a high level, which can control the second transistor M2 to turn off.

[0072] In the power-on stage, the electrical signal provided by the first initialization terminal RST1 is at a low level to control the first transistor M1 to turn on, then the first control signal of the first signal terminal ES1 is written into the second node N2, and the node control module 203 controls the second output module 205 to turn on.

[0073] In the power-on stage, the electric signal provided by the second initialization terminal RST2 is at a high level to control the second transistor M2 to turn off, and the transmission path between the first clock terminal CK1 and the node N1b is cut off. Regardless of whether the fourth transistor M4 is turned on or off, the transmission path between the first clock terminal CK1 and the third node N3 is cut off. Therefore, the first clock signal provided by the first clock terminal CK1 will not affect the potential of the third node N3, and the first output module 204 maintains the off state. Similarly, if Fig. 9 As shown, in the power-on stage, the electrical signal provided by the second initialization terminal RST2 controls the second transistor M2 to turn off, so that the transmission path between the first clock terminal CK1 and the third node N3 is turned off, and the first output module 204 maintains the off state.

[0074] It can be seen from this that the gate driving unit 111 outputs a second power supply signal to control the corresponding transistor in the pixel circuit 120 to turn off, thereby avoiding a short circuit between multiple signal terminals in the pixel circuit 120, preventing the pixel circuit from being burned by a large current during the power-on initialization process and preventing the screen from flashing during power-on, thereby improving the display effect of the display panel.

[0075] Optionally, one of the first transistor and the second transistor is NMOS and the other is PMOS; the first initialization terminal is multiplexed as the second initialization terminal. In this embodiment, the first transistor and the second transistor are of different types, and the first initialization terminal can be multiplexed as the second initialization terminal, which can reduce the number of signal lines corresponding to the gate drive unit, thereby facilitating the realization of a narrow frame.

[0076] If the first transistor is a PMOS and the second transistor is an NMOS, then in the power-on phase, the electrical signal provided by the first initialization terminal is a low level to control the first transistor to turn on and the second transistor to turn off.

[0077] If the first transistor is an NMOS and the second transistor is a PMOS, then in the power-on phase, the electrical signal provided by the first initialization terminal is a high level to control the first transistor to turn on and the second transistor to turn off.

[0078] Here with Figure 6 The structure of the power-on control module shown is used as an example for explanation. Fig.10 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention, and Figure 6 The difference is that Fig.10 The second transistor M2 may be an N-type transistor, and the first initialization terminal RST1 is connected to the gate of the first transistor M1 and to the gate of the second transistor M2. Fig.10 As shown, the first transistor M1 is a PMOS and the second transistor M2 is an NMOS. In the power-on stage, the electrical signal provided by the first initialization terminal RST1 is at a low level, which can control the first transistor M1 to turn on and the second transistor M2 to turn off. Then, the first control signal of the first signal terminal ES1 is written into the second node N2 and controls the second output module 205 to turn on through the node control module 203, and the transmission path between the first clock terminal CK1 and the third node N3 is turned off to keep the first output module 204 in the off state. This can avoid the problem of large current burning the pixel circuit and the screen flashing during the power-on initialization process.

[0079] Fig.11 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention, wherein Fig.11 The structure of the power-on control module shown in FIG. Figure 6 The structure of the power-on control module is the same as shown. Fig.11As shown, the optional first output module 204 includes a fifth transistor M5 and a second capacitor C2; the gate of the fifth transistor M5 is connected to the third node N3, and the fifth transistor M5 is connected between the first power supply terminal VG1 and the shift output terminal GOUT; the second capacitor C2 is connected between the third node N3 and the first power supply terminal VG1.

[0080] In this embodiment, when the potential of the third node N3 is at the on-level, the fifth transistor M5 is controlled to be turned on, and the first power supply signal provided by the first power supply terminal VG1 is written into the shift output terminal GOUT. When the potential of the third node N3 is at the off-level, the fifth transistor M5 is controlled to be turned off. The fifth transistor M5 can be optionally a PMOS, then the on-level of the third node N3 is a low level and the off-level is a high level; in other embodiments, the fifth transistor can also be designed as an NMOS according to requirements. Specifically, in the power-on stage, the power-on control module 202 controls the third node N3 to be a high level to drive the fifth transistor M5 to be turned off.

[0081] The optional second output module 205 includes a sixth transistor M6 and a third capacitor C3; the gate of the sixth transistor M6 is connected to the fourth node N4, and the sixth transistor M6 is connected between the second power supply terminal VG2 and the shift output terminal GOUT; the third capacitor C3 is connected between the fourth node N4 and the shift output terminal GOUT.

[0082] In this embodiment, when the potential of the fourth node N4 is at the on-level, the sixth transistor M6 is controlled to be turned on, and the second power supply signal provided by the second power supply terminal VG2 is written into the shift output terminal GOUT. When the potential of the fourth node N4 is at the off-level, the sixth transistor M6 is controlled to be turned off. The sixth transistor M6 can be optionally a PMOS, then the on-level of the fourth node N4 is a low level and the off-level is a high level; in other embodiments, the sixth transistor can also be designed as an NMOS according to requirements. Specifically, in the power-on stage, the fourth node N4 is at a low level to drive the sixth transistor M6 to be turned off.

[0083] The sixth transistor M6 can be PMOS, and the first signal terminal ES1 can be a low voltage; or the sixth transistor can be NMOS, and the first signal terminal can be a high voltage. It can be understood that when the first transistor M1 is turned on, the first control signal provided by the first signal terminal ES1 will be written into the fourth node N4 through the node control module 203. In the power-on stage, the fourth node N4 needs to be at a conduction level to drive the sixth transistor M6 to turn on. Therefore, the first control signal provided by the first signal terminal ES1 should be a conduction level to drive the sixth transistor M6 to turn on. In this way, the sixth transistor M6 can be controlled to turn on in the power-on stage, so that the shift output terminal GOUT of the gate driving unit 111 outputs the second power supply signal, thereby controlling the corresponding transistor in the pixel circuit to turn off.

[0084] In this embodiment, when the sixth transistor M6 is a PMOS, the first control signal provided by the first signal terminal ES1 is a low voltage. In the power-on stage, the low voltage signal provided by the first signal terminal ES1 is written into the fourth node N4 to control the sixth transistor M6 to turn on.

[0085] In other embodiments, if the sixth transistor is an NMOS and the first control signal provided by the first signal terminal is a high voltage, then in the power-on phase, the high voltage signal provided by the first signal terminal will be written into the fourth node to control the sixth transistor to turn on.

[0086] The optional input module 201 includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10; the gate of the seventh transistor M7 is connected to the second clock terminal CK2, and the seventh transistor M7 is connected between the second power supply terminal VG2 and the input terminal N6 of the eighth transistor M8; the gate of the eighth transistor M8 is connected to the second power supply terminal VG2, and the eighth transistor M8 is connected between the output terminal N6 of the seventh transistor M7 and the first node N1; the gate of the ninth transistor M9 is connected to the second node N2, and the ninth transistor M9 is connected between the second clock terminal CK2 and the input terminal N6 of the eighth transistor M8; the gate of the tenth transistor M10 is connected to the second clock terminal CK2, and the tenth transistor M10 is connected between the second signal terminal STV and the second node N2.

[0087] In this embodiment, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are all PMOS, and in the power-on stage, the first clock signal and the second clock signal are both low level. In the driving operation stage after the power-on stage, the first clock signal undergoes a high-low level jump, and the second clock signal undergoes a high-low level jump.

[0088] In the power-on stage, the potential of the second node N2 is controlled by the power-on control module 202. Specifically, in the power-on stage, the first transistor M1 in the power-on control module 202 is turned on, and the first control signal provided by the first signal terminal ES1 is written into the second node N2.

[0089] In the driving operation phase after the power-on phase, the potential of the second node N2 is controlled by the input module 201. Specifically, in the driving operation phase, the first transistor M1 in the power-on control module 202 is turned off, the transmission path between the first signal terminal ES1 and the second node N2 is disconnected, the second clock signal provided by the second clock terminal CK2 undergoes a high-low level jump, the second clock signal controls the on-off state of the tenth transistor M10 to switch, and when the tenth transistor M10 is turned on, the trigger control signal provided by the second signal terminal STV is written into the second node N2.

[0090] In other embodiments, the ninth transistor may be a dual-gate transistor.

[0091] The optional node control module 203 includes: an eleventh transistor M11 and a twelfth transistor M12; the gate of the eleventh transistor M11 is connected to the second power supply terminal VG2, and the eleventh transistor M11 is connected between the second node N2 and the fourth node N4; the gate of the twelfth transistor M12 is connected to the second node N2, and the twelfth transistor M12 is connected between the first power supply terminal VG1 and the third node N3.

[0092] The eleventh transistor M11 and the twelfth transistor M12 can be both PMOS. Figure 4 In the LTPO pixel circuit 120 shown, the threshold compensation transistor M22 is an NMOS, the second power supply signal is a low voltage, and the first power supply signal is a high voltage, so the eleventh transistor M11 remains turned on.

[0093] In this embodiment, in the power-on stage, the potential of the second node N2 is controlled by the power-on control module 202. Specifically, in the power-on stage, the first transistor M1 in the power-on control module 202 is turned on, the first control signal provided by the first signal terminal ES1 is written into the second node N2, the level of the second node N2 is a low voltage, so as to control the sixth transistor M6 to be turned on, and the twelfth transistor M12 can also be controlled to be turned on, the high level provided by the first power supply terminal VG1 can control the fifth transistor M5 to be turned off, so that the first output module 204 maintains the off state, and the low level provided by the second power supply terminal VG2 is written into the shift output terminal GOUT.

[0094] In the driving operation phase after the power-on phase, the potential of the second node N2 is controlled by the input module 201 .

[0095] Fig.12 is a schematic diagram of another gate driving unit provided by an embodiment of the present invention, wherein Fig.12 The structure of the power-on control module shown in FIG. Figure 6 The structure of the power-on control module is the same as that of Fig.11 The difference is that Fig.12 The optional tenth transistor M10 includes a first sub-transistor M10A and a second sub-transistor M10B; the gate of the first sub-transistor M10A and the gate of the second sub-transistor M10B are both connected to the second clock terminal CK2, the first sub-transistor M10A is connected between the second signal terminal STV and the second node N2, the second sub-transistor M10B is connected between the second signal terminal STV and the first sub-node N2b, and the first sub-node N2b is coupled to the fourth node N4.

[0096] and Fig.11 The difference is that Fig.12The eleventh transistor M11 may also be optionally composed of a third sub-transistor M11A and a fourth sub-transistor M11B; the gate of the third sub-transistor M11A and the gate of the fourth sub-transistor M11B are both connected to the second power supply terminal VG2, the third sub-transistor M11A is connected between the second node N2 and the fourth node N4, the fourth sub-transistor M11B is connected between the first sub-node N2b and the fifth node N5, the first sub-node N2b is coupled to the second signal terminal STV, and the fifth node N5 is coupled to the fourth node N4.

[0097] and Fig.11 The difference is that Fig.12 The optional node control module 203 also includes: a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15 and a fourth capacitor C4; the gate of the thirteenth transistor M13 is connected to the input terminal N6 of the eighth transistor M8, and the thirteenth transistor M13 is connected between the first power supply terminal VG1 and the first terminal N7 of the fourth capacitor C4; the gate of the fourteenth transistor M14 is connected to the second terminal N5 of the fourth capacitor C4, the fourteenth transistor M14 is connected between the first clock terminal CK1 and the first terminal N7 of the fourth capacitor C4, and the second terminal of the fourth capacitor C4 is connected to the fifth node N5; the gate and input terminal of the fifteenth transistor M15 are both connected to the fifth node N5, and the output terminal of the fifteenth transistor M15 is connected to the fourth node N4.

[0098] Optionally, in the power-on phase, the first clock signal provided by the first clock terminal CK1 and the second clock signal provided by the second clock terminal CK2 are the same fixed voltage signal.

[0099] In this embodiment, the first transistor M1 to the fifteenth transistor M15 can be PMOS, and accordingly, in the power-on stage, the first clock signal provided by the first clock terminal CK1 and the second clock signal provided by the second clock terminal CK2 are both low-level signals. It can be understood that if the type of transistor in the gate driving unit changes, the signal of each signal terminal can be adaptively adjusted. Figure 4 In the LTPO pixel circuit 120 shown, the threshold compensation transistor M22 is an NMOS, the second power supply signal provided by the second power supply terminal VG2 is optionally a low voltage, and the first power supply signal provided by the first power supply terminal VG1 is a high voltage.

[0100] It should be noted that, under the condition of ensuring the normal operation of the gate driving unit 111, the types of each transistor can be reasonably designed. In addition, the structure of the gate driving unit 111 in the present invention is not limited to Fig.11 and Fig.12 As shown, relevant practitioners can reasonably design the structure of the gate drive unit according to needs.

[0101] Here with Fig.12The timing sequence is described by taking the gate driving unit 111 as an example. Fig.13 yes Fig.12 A timing diagram of the gate driving unit is shown.

[0102] Combination Fig.12 and Fig.13 As shown, the working process of the gate driving unit 111 at least includes a power-on stage T10, a first stage T11, a second stage T12 and a third stage T13, wherein the first stage T11 is an input stage, the second stage T12 is a first output stage, and the third stage T13 is a second output stage.

[0103] Among them, the first power supply signal provided by the optional first power supply terminal VG1 is a high voltage, the second power supply signal provided by the second power supply terminal VG2 is a low voltage, the trigger control signal provided by the second signal terminal STV will undergo a high-low level jump, the first clock signal provided by the first clock terminal CK1 is a low level in the power-on stage T10, the second clock signal provided by the second clock terminal CK2 is a low level in the power-on stage T10, the first clock signal will undergo a high-low level jump after the power-on stage T10, and the second clock signal will undergo a high-low level jump after the power-on stage T10.

[0104] The working process of the gate driving unit 111 is as follows:

[0105] In the power-on stage T10, the first initialization terminal RST1 provides a low-level signal to turn on the first transistor M1 and the third sub-transistor M11A, and the low-level signal provided by the first signal terminal ES1 is sequentially written into the second node N2 and the fourth node N4, the sixth transistor M6 is turned on, and the low-level signal provided by the second power supply terminal VG2 is transmitted to the shift output terminal GOUT; the second initialization terminal RST2 provides a high-level signal to turn off the second transistor M2 and the fourth transistor M4; the potential of the second node N2 is low, so that the twelfth transistor M12 is turned on, and the high-level signal provided by the first power supply terminal VG1 is written into the third node N3, and the fifth transistor M5 is turned off.

[0106] In the first stage T11, the first initialization terminal RST1 provides a high-level signal to turn off the first transistor M1; the second initialization terminal RST2 provides a low-level signal to turn on the second transistor M2; the second clock signal provided by the second clock terminal CK2 is low-level, the seventh transistor M7 is turned on, the eighth transistor M8 is turned on, the low-level signal provided by the second power supply terminal VG2 is written into the first node N1, and the third transistor M3 is turned on; the first clock signal provided by the first clock terminal CK1 is high-level, and the fourth transistor M4 is turned off; the tenth transistor M10 is turned on, the eleventh transistor M11 is turned on, the high-level signal provided by the second signal terminal STV is written into the second node N2 and the fourth node N4, the twelfth transistor M12 is turned off, and the third node maintains a high level; the fifth transistor M5 is turned off and the sixth transistor M6 is turned off; the shift output terminal GOUT outputs a low level.

[0107] In the second stage T12, the second clock signal provided by the second clock terminal CK2 undergoes a high-low level jump, so that the second node N2 is maintained at a high level, the eleventh transistor M11 is turned on, and the twelfth transistor M12 is turned off, then the fourth node N4 is maintained at a high level, and the sixth transistor M6 remains turned off; the second clock signal provided by the second clock terminal CK2 undergoes a high-low level jump, so that the first node N1 is maintained at a low level; the first clock signal provided by the first clock terminal CK1 undergoes a high-low level jump; when the first clock terminal CK1 provides a low level signal, the fourth transistor M4 is turned on, and the low level signal provided by the first clock terminal CK1 is written into the third node N3; when the first clock terminal CK1 provides a high level signal, the fourth transistor M4 is turned off, and the third node N3 maintains a low level; the fifth transistor M5 is turned on, and the high level signal provided by the first power supply terminal VG1 is written into the shift output terminal GOUT.

[0108] In the third stage T13, the second signal terminal STV provides a low-level signal, and the second clock signal provided by the second clock terminal CK2 undergoes a high-low level jump, so that the second node N2 is maintained at a low level, the eleventh transistor M11 is turned on, the fourth node N4 is maintained at a low level, and the sixth transistor M6 is turned on; the second node N2 is a low level, so that the twelfth transistor M12 is turned on, the high-level signal provided by the first power supply terminal VG1 is written into the third node N3, and the fifth transistor M5 is turned off; the low-level signal provided by the second power supply terminal VG2 is written into the shift output terminal GOUT.

[0109] In this embodiment, in the power-on stage T10, the electric signal provided by the second initialization terminal RST2 controls the second transistor M2 to turn off, and the transmission path between the first clock terminal CK1 and the third node N3 is turned off. The electric signal provided by the first initialization terminal RST1 controls the first transistor M1 to turn on, and the low-level signal of the first signal terminal ES1 is written into the second node N2 and the fourth node N4, and the low level of the second node N2 turns on the twelfth transistor M12, and the high-level signal provided by the first power supply terminal VG1 is written into the third node N3, and the first output module 204 maintains the off state; the low level of the fourth node N4 turns on the sixth transistor M6, and the gate driving unit 111 outputs the second power supply signal to control the corresponding transistor in the pixel circuit 120 to turn off. The problem of large current burning the pixel circuit and the screen flashing during power-on initialization will not occur, thereby improving the display effect of the display panel.

[0110] Based on the same inventive concept, an embodiment of the present invention provides a display device, Fig.14 is a schematic diagram of a display device provided by an embodiment of the present invention, such as Fig.14 As shown, the display device includes the display panel described in any embodiment of the present invention.

[0111] The display device can be applied to a liquid crystal display device, an organic light-emitting display device, or a micro light-emitting diode display device, without specific limitation. The display device can also be a car display product, a mobile display product or others, and has display and touch functions.

[0112] like Fig.14 The optional display device shown is a smart phone 1, and the smart phone 1 includes a display panel, and the display panel is the display panel described in any embodiment of the present invention.

[0113] The display device provided in the embodiment of the present invention has the functional modules and beneficial effects corresponding to the gate drive circuit described in any of the above embodiments. The display device can be applied to terminal devices such as smart phones 1, vehicle displays, tablet computers, notebook computers, super mobile personal computers, netbooks, smart wearable devices, augmented reality (AR) / virtual reality (VR) devices, etc.

[0114] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0115] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A gate driving circuit and a plurality of rows of pixel circuits, wherein the gate driving circuit comprises a multi-stage gate driving unit, and the gate driving unit is used to provide a gate driving signal to the pixel circuit; The gate driving unit comprises: An input module, connected at least to a first node and a second node, and configured to control a potential of the first node and a potential of the second node; a power-on control module, connected at least to a first signal terminal, a first clock terminal, the first node, the second node, and a third node, and configured to control a potential of the second node and a potential of the third node in response to signals of the first signal terminal, the first clock terminal, and the first node; a node control module, connected to at least the second node and a fourth node, and configured to control the potential of the fourth node in response to the potential of the second node; A first output module, connected between the first power supply terminal and the shift output terminal, wherein the control terminal of the first output module is connected to the third node, and is used to control the on-off between the first power supply terminal and the shift output terminal in response to the potential of the third node; A second output module is connected between the second power supply terminal and the shift output terminal, and a control terminal of the second output module is connected to the fourth node, and is used to control the connection between the second power supply terminal and the shift output terminal in response to the potential of the fourth node; The working process of the gate driving unit includes: a power-on stage; In the power-on stage, the first output module is turned off, and the power-on control module controls the second output module to turn on through the node control module, so that the shift output end outputs the second power signal provided by the second power end, and the second power signal controls the pixel circuit to turn off.

2. The display panel according to claim 1, characterized in that: The power-on control module includes: a first transistor, a second transistor, a third transistor, a fourth transistor and a first capacitor; The gate of the first transistor is connected to the first initialization terminal, and the first transistor is connected between the first signal terminal and the second node; The gate of the second transistor is connected to the second initialization terminal, the first terminal of the second transistor is connected to the first clock terminal, and the second terminal of the second transistor is connected to the first terminal of the third transistor; The gate of the third transistor is connected to the first node, the second end of the third transistor is connected to the second end of the first capacitor, and the first end of the first capacitor is connected to the first node; The fourth transistor is connected between the second end of the first capacitor and the third node; In the power-on phase, the first transistor is turned on and the second transistor is turned off.

3. The display panel according to claim 2, characterized in that: The gate of the fourth transistor is connected to the first end of the second transistor; or the gate of the fourth transistor is connected to the second end of the second transistor.

4. The display panel according to claim 1, characterized in that: The power-on control module includes: a first transistor, a second transistor, a third transistor, a fourth transistor and a first capacitor; The gate of the first transistor is connected to the first initialization terminal, and the first transistor is connected between the first signal terminal and the second node; The gate of the second transistor is connected to the second initialization end, the first end of the second transistor is connected to the second end of the first capacitor, and the first end of the first capacitor is connected to the first node; The gate of the third transistor is connected to the first node, and the first terminal of the third transistor is connected to the first clock terminal; The gate of the fourth transistor is connected to the first clock terminal, and the first terminal of the fourth transistor is connected to the third node; In the power-on phase, the first transistor is turned on and the second transistor is turned off.

5. The display panel according to claim 4, characterized in that: The second end of the second transistor is connected to the second end of the third transistor, and the second end of the fourth transistor is connected to the second end of the first capacitor; Alternatively, the second end of the second transistor is connected to the second end of the fourth transistor, and the second end of the third transistor is connected to the second end of the first capacitor.

6. The display panel according to claim 2 or 4, characterized in that: The first transistor and the second transistor are both NMOS or PMOS.

7. The display panel according to claim 2 or 4, characterized in that: One of the first transistor and the second transistor is an NMOS and the other is a PMOS; The first initialization end is multiplexed as the second initialization end.

8. The display panel according to claim 1, characterized in that: The first output module includes a fifth transistor and a second capacitor; The gate of the fifth transistor is connected to the third node, and the fifth transistor is connected between the first power supply terminal and the shift output terminal; The second capacitor is connected between the third node and the first power supply terminal.

9. The display panel according to claim 1, characterized in that: The second output module includes a sixth transistor and a third capacitor; The gate of the sixth transistor is connected to the fourth node, and the sixth transistor is connected between the second power supply terminal and the shift output terminal; The third capacitor is connected between the fourth node and the shift output terminal.

10. The display panel according to claim 9, characterized in that: The sixth transistor is a PMOS, and the first signal terminal is a low voltage; Alternatively, the sixth transistor is an NMOS, and the first signal terminal is a high voltage.

11. The display panel according to claim 1, characterized in that: The input module includes: a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The gate of the seventh transistor is connected to the second clock terminal, and the seventh transistor is connected between the second power supply terminal and the input terminal of the eighth transistor; The gate of the eighth transistor is connected to the second power supply terminal, and the eighth transistor is connected between the output terminal of the seventh transistor and the first node; The gate of the ninth transistor is connected to the second node, and the ninth transistor is connected between the second clock terminal and the input terminal of the eighth transistor; A gate of the tenth transistor is connected to the second clock terminal, and the tenth transistor is connected between the second signal terminal and the second node.

12. The display panel according to claim 11, characterized in that: The ninth transistor is a dual-gate transistor.

13. The display panel according to claim 11, characterized in that: In the power-on phase, the first clock signal provided by the first clock terminal and the second clock signal provided by the second clock terminal are the same fixed voltage signal.

14. The display panel according to claim 11, characterized in that: The tenth transistor includes a first sub-transistor and a second sub-transistor; The gate of the first sub-transistor and the gate of the second sub-transistor are both connected to the second clock terminal, the first sub-transistor is connected between the second signal terminal and the second node, the second sub-transistor is connected between the second signal terminal and the first sub-node, and the first sub-node is coupled to the fourth node.

15. The display panel according to claim 11, characterized in that: The node control module includes: an eleventh transistor and a twelfth transistor; The gate of the eleventh transistor is connected to the second power supply terminal, and the eleventh transistor is connected between the second node and the fourth node; A gate of the twelfth transistor is connected to the second node, and the twelfth transistor is connected between the first power supply terminal and the third node.

16. The display panel according to claim 15, characterized in that: The eleventh transistor includes a third sub-transistor and a fourth sub-transistor; The gate of the third sub-transistor and the gate of the fourth sub-transistor are both connected to the second power supply terminal, the third sub-transistor is connected between the second node and the fourth node, the fourth sub-transistor is connected between the first sub-node and the fifth node, the first sub-node is coupled to the second signal terminal, and the fifth node is coupled to the fourth node.

17. The display panel according to claim 16, characterized in that: The node control module further includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a fourth capacitor; The gate of the thirteenth transistor is connected to the input terminal of the eighth transistor, and the thirteenth transistor is connected between the first power supply terminal and the first terminal of the fourth capacitor; The gate of the fourteenth transistor is connected to the second end of the fourth capacitor, the fourteenth transistor is connected between the first clock end and the first end of the fourth capacitor, and the second end of the fourth capacitor is connected to the fifth node; A gate and an input terminal of the fifteenth transistor are both connected to the fifth node, and an output terminal of the fifteenth transistor is connected to the fourth node.

18. The display panel according to claim 1, characterized in that: The pixel circuit includes a driving transistor, a first reset transistor, a threshold compensation transistor and a light emitting element; The first terminal of the driving transistor is coupled to the light emitting element; The first reset transistor is connected between the first reset signal terminal and the gate of the driving transistor; The threshold compensation transistor is connected between the gate of the driving transistor and the first terminal of the driving transistor; The shift output terminal of the gate driving unit is connected to the gate of the first reset transistor or the gate of the threshold compensation transistor.

19. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 18.

Images