Semiconductor package and method of forming same

Abstract

A semiconductor package includes a package assembly including an interconnect structure on a first side of a substrate; a metal pad on the interconnection structure; a semiconductor die connected to the second side of the substrate; a dielectric material surrounding the package component; a passivation layer extending over the package component and over the dielectric material; a first buffer layer over the passivation layer, where the first buffer layer extends over the package component and over the dielectric material, where a width of the first buffer layer is greater than a width of the package component and less than a width of the passivation layer; and a conductive connector passing through the passivation layer and the first buffer layer to physically contact the metal pad. The embodiment of the invention also discloses a method for forming the semiconductor package.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor packages and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density comes from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the demand for smaller and more creative manufacturing technologies for semiconductor dies has emerged. An example of such a packaging system is the system on integrated circuit (SoIC) technology. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor package is provided, comprising: a package component, including an interconnect structure located on a first side of a substrate; a plurality of metal pads located on the interconnect structure; a semiconductor die connected to a second side of the substrate; a dielectric material surrounding the package component; a passivation layer extending over the package component and over the dielectric material; a first buffer layer located over the passivation layer, wherein the first buffer layer extends over the package component and over the dielectric material, wherein a width of the first buffer layer is greater than a width of the package component and less than a width of the passivation layer; and a plurality of conductive connectors passing through the passivation layer and the first buffer layer to physically contact the plurality of metal pads.

[0004] According to another aspect of an embodiment of the present application, a semiconductor package is provided, comprising: a first integrated circuit die, comprising a plurality of conductive pads; a gap filling material, covering the side walls of the first integrated circuit die; a first polymer layer, extending above the first integrated circuit die and the top surface of the gap filling material, wherein the first polymer layer physically contacts the plurality of conductive pads, wherein the side walls of the first polymer layer are recessed from the side walls of the gap filling material; and a plurality of conductive components, extending through the first polymer layer to physically contact the plurality of conductive pads.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor package is provided, comprising: connecting a semiconductor die to a package component, wherein the package component includes a metal pad; sealing the package component with an insulating material; depositing a passivation layer on the surface of the package component and the insulating material; patterning the passivation layer to expose the metal pad; depositing a buffer layer over the patterned passivation layer; patterning the buffer layer to expose the metal pad and expose the surface of the passivation layer over the insulating material, wherein a portion of the patterned buffer layer extends from the metal pad to the exposed surface of the passivation layer; and forming a conductive connector on the metal pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 shows a cross-sectional view of a package assembly according to some embodiments;

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 ,and Fig.14 shows a cross-sectional view of an intermediate stage in the formation of a package according to some embodiments;

[0009] Fig.15 shows a cross-sectional view of a package according to some embodiments;

[0010] Fig.16 , Fig.17 ,and Fig.18 shows a cross-sectional view of a package having a buffer layer according to some embodiments;

[0011] Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 ,and Fig. 27 A cross-sectional view of a package having multiple buffer layers in accordance with some embodiments is shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] A semiconductor package and a method for forming the same are provided. According to some embodiments of the present invention, the semiconductor package includes one or more package components and a conductive connector formed on a buffer layer above the one or more package components. The buffer layer may cover the package component and extend beyond the edge of the package component. By forming a buffer layer that extends beyond the package component, stress within the semiconductor package may be reduced. In some cases, the characteristics of the sidewalls of the buffer layer may be controlled to improve stress reduction. In addition, multiple buffer layers may be formed to improve stress reduction. The techniques described herein may be applied to various packaging technologies, such as system on integrated circuit (SoIC) technology, etc.

[0015] The embodiments discussed herein are intended to provide examples of the subject matter of the present disclosure that can be made or used, and those of ordinary skill in the art will readily appreciate the modifications that may be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being implemented in a particular order, other method embodiments may also be implemented in any logical order.

[0016] exist Figure 1In the embodiment of the present invention, the first package component 40 is formed or provided in a wafer (not shown separately), for example. According to some embodiments, the first package component 40 may be a separate device die (e.g., an integrated circuit die), a package having one or more device dies packaged therein, a system-on-chip (SoC) die including multiple integrated circuits integrated as a system, etc. The device die of the first package component 40 may be or may include a logic die, a memory die, an input-output (I / O) die, an integrated passive device (IPD), etc., or a combination thereof. For example, the logic device die of the first package component 40 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die of the first package component 40 may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc. The device die of the first package component 40 may include a semiconductor substrate and an interconnect structure.

[0017] According to some embodiments, the first package component 40 may include a substrate 42. The substrate 42 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 42 may be a wafer, such as a silicon wafer. Other substrates, such as a silicon on insulator (SOI) substrate, a multilayer substrate, or a gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 42 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof. In some embodiments, a plurality of first package components 40 may be formed on the same substrate 42 and then separated into individual first package components 40 using a singulation process (e.g., a sawing process, a dicing process, etc.).

[0018] Additionally, in some embodiments, integrated circuit devices (not separately shown) may be formed on the front surface of substrate 42. The integrated circuit devices may include active devices (e.g., NMOS and PMOS transistors, diodes, etc.), passive devices (e.g., resistors, capacitors, etc.), etc. Additionally, through substrate vias (TSVs) 46 may be formed that extend partially through substrate 42.

[0019] In some embodiments, an interconnect structure 49 is formed over the front side of the substrate 42. The interconnect structure 49 includes conductive features 48 (e.g., metal lines, metal vias, metal pads, etc.) formed in one or more dielectric layers 44. The conductive features 48 of the interconnect structure 49 may be electrically connected to the integrated circuit device and / or the TSV 46. As shown, the interconnect structure 49 may include a multilayer conductive feature 48 formed in a plurality of dielectric layers 44. The conductive features 48 may be formed using a damascene process, a dual damascene process, or other suitable techniques. The conductive features 48 may include, for example, copper, aluminum, tungsten, ruthenium, cobalt, alloys thereof, combinations thereof, and the like. The dielectric layer 44 may include a dielectric material, such as a polymer, silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc., combinations thereof, and / or multilayers thereof, or may be formed of these dielectric materials. Other materials are possible. In some cases, the dielectric layer 44 may be an intermetallic dielectric (IMD) layer. Figure 1 The interconnect structure 49 shown in FIG. 4 is an example, and the interconnect structure 49 may include other numbers of layers, or may have a different configuration than that shown. In some embodiments, the interconnect structure 49 may include a seal ring (not shown).

[0020] According to some embodiments, a passivation layer 54 may be formed over interconnect structure 49. In some embodiments, passivation layer 54 may be formed by a non-low-k dielectric material having a dielectric constant equal to or greater than that of silicon oxide. Passivation layer 54 may be formed of or include an inorganic dielectric material, which may include a material selected from, but not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, and the like, combinations thereof, and / or multilayers thereof. Other materials are possible.

[0021] According to some embodiments, metal pads 50 may be formed on passivation layer 54. Metal pads 50 are formed on passivation layer 54 and may have portions extending through passivation layer 54 to physically and electrically contact conductive features 48 of interconnect structure 49. Metal pads 50 may help facilitate external electrical connections to the integrated circuits of first package assembly 40 during functional use and / or facilitate external electrical connections during, for example, wafer acceptance testing (e.g., circuit probe testing) of first package assembly 40. Some metal pads 50 may be connected to TSVs 46 through interconnect structure 49. Some metal pads 50 may be connected to integrated circuit devices at the surface of substrate 42 through interconnect structure 49.

[0022] As an example of forming a metal pad 50, a passivation layer 54 can be patterned using photolithography and etching techniques to expose an interconnect structure 49. The patterned passivation layer 54 exposes the topmost conductive component 48 of the interconnect structure 49. A seed layer (not shown) can be deposited above the passivation layer 54 and on the exposed conductive component 48. In some embodiments, the seed layer is a metal layer, which can be a single layer, or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, sputtering, evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), etc. A photoresist (not shown) is then formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metal pad 50. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating. The conductive material may include a metal, such as aluminum copper, copper, aluminum, nickel, tungsten, etc., or an alloy thereof. Other conductive materials are possible. The photoresist is then removed, as well as the portion of the seed layer on which the conductive material is not formed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, an acceptable etching process, such as a wet etching process or a dry etching process, is used to remove the exposed portion of the seed layer. The remaining portion of the seed layer and the conductive material forms a metal pad 50.

[0023] In some embodiments, a dielectric layer 58 may be deposited over the passivation layer 54 and the metal pad 50. The dielectric layer 58 may, for example, protect the metal pad 50 from oxidation. In some embodiments, the dielectric layer 58 is an anti-reflective coating (ARC) and includes an oxide or a nitride, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or any suitable material. In other embodiments, the dielectric layer 58 may include one or more materials, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low-k dielectric materials, etc. The dielectric layer 58 may be formed using a suitable process, such as spin coating, flowable chemical vapor deposition (FCVD), PECVD, low pressure chemical vapor deposition (LPCVD), etc. Other materials or deposition techniques are possible. In some embodiments, an optional planarization process (e.g., chemical mechanical polishing (CMP), grinding, etc.) is performed on the dielectric layer 58 so that the top surface of the dielectric layer 58 is substantially flat.

[0024] exist Figure 2In some embodiments, one or more first package components 40 are connected to the first carrier 20. Then, the package 100 is formed on the first carrier 20, such as Figure 2 Each package area 100 is separated from an adjacent package area 100 by a scribe area 21. The structure is then singulated along the scribe areas 21 to form separate, individual packages 100 (see Fig.15 ). Figure 2 A single first package component 40 in each package region 100 is shown, but in other embodiments, package region 100 may include more than one first package component 40 and / or other package components.

[0025] The first carrier 20 may include a base carrier 22 and one or more dielectric bonding layers 24. In some embodiments, the base carrier 22 may be a wafer and may be a material similar to the substrate 42 of the first package component 40. In this way, during the process, warpage caused by the mismatch of the coefficient of thermal expansion (CTE) between the first carrier 20 and the first package component 40 may be reduced. For example, in some embodiments, the base carrier 22 may be formed of or include silicon. Other embodiments may use other materials, such as laminates, ceramics, glass, silicate glass, organic cores, etc., or combinations thereof. According to some embodiments, the entire base carrier 22 is formed of a uniform material, without other materials different from the uniform material therein. In some embodiments, the entire base carrier 22 may be formed of silicon (doped or undoped), and there are no metal areas, dielectric areas, etc. therein.

[0026] Before connecting the first package component 40 to the first carrier 20, a dielectric bonding layer 24 may be deposited on the base carrier 22. The dielectric bonding layer 24 may include one or more layers, which include one or more materials, such as: oxide-based materials, such as silicon oxide (SiO), PSG, BSG, BPSG, fluorine-doped silicate glass (FSG), etc.; nitride-based materials, such as silicon nitride (SiN), etc.; oxynitride-based materials, such as silicon oxynitride (SiON), etc.; or other materials, such as silicon oxycarbide (SiOC), silicon carbonitride (SiCN), etc. The dielectric bonding layer 24 may be formed using spin coating, FCVD, PECVD, LPCVD, atomic layer deposition (ALD), etc., or a combination thereof. For example, in some embodiments, the dielectric bonding layer 24 may include a lowermost layer (e.g., close to the substrate carrier 22) including an oxide, one or more intermediate layers including a nitride and / or an oxynitride, and an uppermost layer (e.g., away from the substrate carrier 22) including an oxynitride (e.g., having a lower nitrogen-to-oxygen ratio than the intermediate layers). Although not separately shown, the alignment mark may be formed in the dielectric bonding layer 24 (e.g., the uppermost layer) using any suitable method.

[0027] In some embodiments, first package component 40 is connected to first carrier 20 using a direct bonding process such as fusion bonding or dielectric-to-dielectric bonding. According to some embodiments, bonding of first package component 40 to first carrier 20 includes pre-treating dielectric bonding layer 24 and / or dielectric layer 58 with a process gas including oxygen (O2) and / or nitrogen (N2), performing a pre-bonding process to bond dielectric bonding layer 24 and dielectric layer 58 together, and performing an annealing process after the pre-bonding process to strengthen the bonding.

[0028] According to some embodiments, during the pre-bonding process, the first package component 40 forms a physical contact with the first carrier 20, wherein a pressing force is applied to press the first package component 40 against the first carrier 20. The pre-bonding process can be performed at room temperature (e.g., in a range of about 20°C to about 25°C), but higher temperatures can also be used. An annealing process is performed after the pre-bonding process to bond the dielectric bonding layer 24 and the dielectric layer 58 together. According to some embodiments, the annealing process is performed at a temperature in a range of 200°C to 350°C. The annealing duration can be in a range of 30 minutes to 60 minutes.

[0029] exist Figure 3 In some embodiments, a gap filling material 32 is deposited over the first package component 40 and the first carrier 20. The gap filling material 32 can seal, protect, and / or insulate the first package component 40. In some embodiments, the gap filling material 32 may include an optional liner layer and a body layer (not shown separately). For example, the liner layer may be a conformal layer extending along the top surface and sidewalls of the first package component 40 and along the top surface of the dielectric bonding layer 24. The liner layer may also be referred to as a sealing ring, and in some embodiments, is used as an etch stop layer in subsequent steps. The liner layer may be formed of a dielectric material such as silicon nitride, silicon oxide, or a combination thereof. The liner layer may be deposited using a suitable conformal deposition process such as ALD, CVD, or the like. The body layer of the gap filling material 32 may be formed by a molding compound, an epoxy resin, a resin, a nitride such as silicon nitride, an oxide such as silicon oxide, an insulating material, or the like, or a combination thereof. The bulk layer may be deposited using a suitable process such as compression molding, spin coating, FCVD, PECVD, LPCVD, ALD, or the like.

[0030] In some embodiments, a planarization process, such as a CMP process and / or a grinding process, is then performed to remove portions of the gap filler material 32. The planarization process may remove the gap filler material 32, thereby exposing the first package component 40, such as Figure 3 In addition, the planarization process may remove a portion of the substrate 42 of the first package component 40, thereby exposing the TSV 46 of the first package component 40, as shown in FIG. Figure 3 After the planarization process is performed, the surfaces of gap fill material 32 , substrate 42 , and / or TSV 46 may be level or coplanar (within process variations).

[0031] exist Figure 4 In the embodiment of the present invention, a dielectric bonding layer 34 and a bonding pad 35 are formed over the back side of the first package component 40 (e.g., the upper surface of the substrate 42 as shown). In some embodiments, the dielectric bonding layer 34 is first deposited over the first package component 40 and the gap filling material 32 using any suitable method such as ALD, CVD, etc. The dielectric bonding layer 34 is patterned using suitable photolithography and etching techniques to form an opening (not shown separately) that can expose the TSV 46 and / or the surface of the substrate 42. According to some embodiments, the opening is then filled with a conductive material to form a bonding pad 35. The conductive material can be similar to those previously described for the metal pad 50 and can be formed using similar techniques. In this way, the bonding pad 35 can physically and electrically contact the TSV 46. In some embodiments, a planarization process (e.g., CMP or grinding) is performed so that the surfaces of the dielectric bonding layer 34 and the bonding pad 35 can be approximately horizontal or coplanar.

[0032] exist Figure 5 In some embodiments, a second package component 70 is connected to the first package component 40. The second package component 70 may include, for example, an active package component 70A and a dummy package component 70B. The active package component 70A may include a functional component such as an integrated circuit. A dummy package component 70B may be included, for example, to provide structural integrity and / or heat dissipation.

[0033] In some embodiments, active package component 70A and / or dummy package component 70B may be connected using a direct bonding process, such as a dielectric-to-dielectric bonding process and / or a metal-to-metal bonding process (e.g., a fusion bonding process, a hybrid bonding process, etc.). Figure 5 The connection of one active package component 70A and one dummy package component 70B to each first package component 40 is shown, but in other embodiments, any suitable number or type of second package components 70 may be connected to each first package component 40. For example, in other embodiments, no dummy package component 70B may be connected, or multiple active package components 70A of multiple types may be connected.

[0034] In some embodiments, the active package assembly 70A may be a separate device die (e.g., an integrated circuit die), a package having one or more device dies packaged therein, a system-on-chip (SoC) die including multiple integrated circuits (or device dies) integrated as a system, etc. The device die of the active package assembly 70A may include a logic die, a memory die, an input-output (I / O) die, an integrated passive device (IPD), etc., or a combination thereof. For example, the logic device die of the active package assembly 70A may include a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die of the active package assembly 70A may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc. The device die of the active package assembly 70A may include a semiconductor substrate and an interconnect structure. According to some embodiments, the first package assembly 40 is a SoC die, and the active package assembly 70A includes a memory die, such as a SRAM die.

[0035] According to some embodiments (not shown separately), the active package component 70A may include some features similar to those described above for the first package component 40. For example, the active package component 70A may include a semiconductor substrate, an integrated circuit device, and a plurality of dielectric layers formed above the semiconductor substrate and the integrated circuit device. The integrated circuit device may include active devices, passive devices, etc. According to some embodiments, the dummy package component 70B does not include a functional integrated circuit, and / or is electrically disconnected from the first package component 40 and / or the active package component 70A. Each of the second package components 70 may include a dielectric bonding layer 76 that is subsequently bonded to the dielectric bonding layer 34. The active package component 70A may also include a bonding pad 77 formed within the dielectric bonding layer 76. In some embodiments, the dummy package component 70B may also include a dummy bonding pad (not shown).

[0036] According to some embodiments, the dielectric bonding layer 76 is directly bonded to the dielectric bonding layer 34 using dielectric-to-dielectric bonding. Similarly, the bonding pad 77 is directly bonded to the bonding pad 35 using metal-to-metal bonding. In some embodiments, the bonding may include a pre-bonding process and an annealing process. During the pre-bonding process, a small pressing force may be applied to press the second package component 70 against the first package component 40. The pre-bonding process may be implemented at a low temperature, such as room temperature (e.g., a temperature in the range of about 20°C to about 25°C). After the pre-bonding process, the dielectric bonding layer 76 and the dielectric bonding layer 34 are bonded to each other. Then, the bonding strength may be improved in a subsequent annealing step, in which the dielectric bonding layer 76 and the dielectric bonding layer 34 are annealed at a high temperature, such as at a temperature in the range of about 200°C to about 350°C. In this way, the dielectric bonding layer 76 and the dielectric bonding layer 34 are bonded to each other by dielectric-to-dielectric bonding. Additionally, the annealing step bonds the bonding pad 77 of the second package component 70 (eg, active package component 70A) to the bonding pad 35 by metal-to-metal bonding.

[0037] exist Figure 6 In some embodiments, a gap fill material 82 is deposited over the second package component 70 and the dielectric bonding layer 34. The gap fill material 82 can seal the second package component 70. The gap fill material 82 can be similar to the previous embodiment for Figure 3 Gap filler material 82 may be formed using gap filler material 32 as described above and may be formed using similar techniques. For example, gap filler material 82 may include an optional liner layer and a body layer (not separately shown). In some cases, gap filler material 82 may include a different material than gap filler material 32. In some embodiments, a planarization process (e.g., CMP, grinding, etc.) may be performed to remove portions of gap filler material 82. The planarization process may remove gap filler material 82, thereby exposing second package component 70, such as Figure 6 After the planarization process is performed, the surfaces of the gap fill material 82 and the second package component 70 may be level or coplanar (within process variations).

[0038] exist Figure 7In some embodiments, a second carrier 90 is connected. The second carrier 90 may include a substrate carrier 92, and one or more dielectric bonding layers 94. In some embodiments, the substrate carrier 92 and the dielectric bonding layer 94 may be similar to the substrate carrier 22 and the dielectric bonding layer 24 of the first carrier 20 described previously. For example, the substrate carrier 92 may be a material similar to the substrate carrier 22 to reduce warpage caused by CTE mismatch. Before connecting the second carrier 90, one or more dielectric bonding layers 94 are deposited on the substrate carrier 92, and one or more dielectric bonding layers 86 are deposited over the second package component 70 and the gap filling material 82. The second carrier 90 may be connected using dielectric-to-dielectric bonding. For example, according to some embodiments, the bonding of the second carrier includes: pre-treating the dielectric bonding layers 86 and 94 in a process gas including oxygen (O2) and / or nitrogen (N2), performing a pre-bonding process to bond the dielectric bonding layers 86 and 94 together, and performing an annealing process after the pre-bonding process to strengthen the bonding.

[0039] exist Figure 8 In some embodiments, the structure is flipped and the first carrier 20 is removed. The first carrier 20 may be removed using any suitable method, such as using a planarization process and / or an etching process. The planarization process may be a CMP process, a grinding process, etc., or a combination thereof. The etching process may be a wet etching process, a dry etching process, or a combination thereof. Figure 8 As shown in , removal of the first carrier 20 exposes the dielectric layer 58 and the gap-fill material 32. In some embodiments, after removal of the first carrier 20, the surfaces of the dielectric layer 58 and the gap-fill material 32 are level or coplanar (within process variations).

[0040] exist Fig. 9 In some embodiments, a first passivation layer 60 and a second passivation layer 62 are deposited. In some embodiments, the first passivation layer 60 includes a dielectric material, such as silicon oxide (SiO), PSG, BSG, BPSG, FSG, USG, silicon oxynitride (SiON), silicon oxycarbide (SiOC), etc. In some embodiments, the second passivation layer 62 includes a dielectric material different from the dielectric material of the first passivation layer 60, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), etc. For example, in some embodiments, the first passivation layer 60 is USG and the second passivation layer 62 is silicon nitride, although other materials are possible. The first passivation layer 60 and the second passivation layer 62 can be deposited using a suitable technique such as spin coating, FCVD, CVD, PECVD, etc. In some embodiments, an optional planarization process (e.g., CMP, grinding, etc.) is performed on the second passivation layer 62 so that the top surface of the second passivation layer 62 is approximately planar.

[0041] exist Fig.10 In some embodiments, an opening 63 is formed in the first passivation layer 60, the second passivation layer 62, and the dielectric layer 58 to expose the metal pad 50. The opening 63 can be formed using suitable photolithography and etching techniques. For example, a photoresist can be applied above the top surface of the second passivation layer 62 and patterned. The patterned photoresist is then used as an etching mask to etch portions of the first passivation layer 60, the second passivation layer 62, and the dielectric layer 58 to form the opening 63. The etching can include one or more dry etching processes and / or wet etching processes. As stated above, the surface of the metal pad 50 is exposed through the opening 63.

[0042] exist Fig.11 In some embodiments, a buffer layer 64 is deposited over the structure and within the opening 63. For example, the buffer layer 64 may fill the opening 63 and may cover the top surface of the second passivation layer 62. The buffer layer 64 may include a polymer material, such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. The polymer may be photosensitive or non-photosensitive. The buffer layer 64 may be deposited using a suitable process, such as spin coating, lamination, etc. In some cases, a curing process (e.g., heat treatment) may be performed on the buffer layer 64. In some embodiments, the buffer layer 64 may be deposited to a thickness on the second passivation layer 62 in the range of about 3 μm to about 10 μm. Other materials or thicknesses thereof are possible. In other embodiments, a second buffer layer is formed over the buffer layer 64, and the following is directed to Figure 19-Figure 27 Some exemplary embodiments are described.

[0043] exist Fig.12 In some embodiments, buffer layer 64 is patterned. Buffer layer 64 is patterned to form opening 65 exposing metal pad 50. After forming opening 65, a portion of buffer layer 64 may remain on the sidewalls of first passivation layer 60 and second passivation layer 62 (e.g., on the sidewalls of opening 63). A portion of buffer layer 64 may also remain on the top surface of metal pad 50.

[0044] The buffer layer 64 is also patterned to form an opening 67 near the edge of the encapsulation area 100 where the second passivation layer 62 is exposed. In some embodiments, the opening 67 overlaps the scribe line area 21, so that forming the opening 67 includes removing the buffer layer 64 from the scribe line area 21. By removing the buffer layer 64 from the scribe line area 21, the material of the buffer layer 64 does not interfere with the subsequent singulation process (see Fig.14). In this way, the singulation process can be improved. In addition, in some embodiments, the position and / or profile of the sidewalls of opening 67 can be controlled to reduce stress within package 100, as described in more detail below. For example, in some cases, having buffer layer 64 protrude laterally beyond first package component 40 can reduce stress due to CTE mismatch and reduce delamination.

[0045] When the buffer layer 64 is photosensitive, its patterning may include performing a light exposure process on the buffer layer 64, such as exposing the buffer layer 64 to light corresponding to a subsequently performed pattern. The buffer layer 64 may then be developed using an appropriate technique to form openings 65 and 67. In some embodiments, the characteristics of the openings 65 and 67, such as the sidewall slope, may be controlled by controlling the parameters of the exposure. According to an alternative embodiment in which the buffer layer 64 is non-photosensitive, the patterning of the buffer layer 64 may include, for example, applying a photoresist over the buffer layer 64 and patterning it, and etching the buffer layer 64 using the patterned photoresist as an etching mask.

[0046] exist Fig.13 In some embodiments, an under bump metallization (UBM) 66 is formed in the opening 65. In some embodiments, the UBM 66 is not formed in the opening 67. Fig.13 As shown in . UBM 66 is formed in opening 65 and is electrically connected to metal pad 50. As an example for forming UBM 66, a seed layer (not shown separately) is formed over the exposed surface of metal pad 50 and buffer layer 64. In some embodiments, the seed layer is a metal layer, which can be a single layer, or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD. Then a photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to UBM 66. Patterning forms an opening through the photoresist to expose the seed layer. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process. The remaining portion of the seed layer and the conductive material forms UBM 66. In other embodiments, UBM 66 may include a liner layer, such as an adhesive layer. In other embodiments, UBM 66 may have a top surface that is flush with the top surface of buffer layer 64.

[0047] exist Fig.14 In some embodiments, a conductive connector 68 is formed on the UBM 66, and the package 100 is singulated into individual packages 100. The conductive connector 68 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 68 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 68 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 68 includes a metal column (e.g., a copper column) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal cover layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, some or all of UBMs 66 are formed as part of conductive connectors 68 .

[0048] According to some embodiments, after forming conductive connectors 68, a singulation process is performed along scribe regions 21 to separate adjacent package regions 100. In this manner, individual packages 100 are formed. Fig.15 FIG. 1 shows a singulated package 100 according to some embodiments. The singulation process may include a sawing process, a dicing process, an etching process, etc. Fig.14 As shown in , after the singulation process is performed, the sidewalls of the buffer layer 64 are laterally recessed from the sidewalls of the corresponding package 100. In some embodiments, the sidewalls of the package 100 can be substantially coplanar and can be vertical or at a non-zero angle to the vertical direction. For example, the sidewalls of the second passivation layer 62, the first passivation layer 60, the gap filling material 32, the dielectric bonding layer 34, the gap filling material 82, and / or the second carrier 90 can have substantially coplanar surfaces (e.g., within process variations).

[0049] Fig.16 , Fig.17 ,and Fig.18 An enlarged view of a portion of package 100 is shown in accordance with some embodiments. Figure 16-Figure 18 The package 100 shown in FIG. 1 may be similar to Fig.15 and may be formed using similar techniques. Figure 16-Figure 18The enlarged view of FIG. 1 shows the buffer layer 64 near the sidewall of the package 100 and may show a structure similar to FIG. Fig.15 The area 101 is represented in FIG. Figure 16-Figure 18 The embodiments shown in are intended as non-limiting examples, and package 100 and / or buffer layer 64 may be formed to have different characteristics than those shown using the techniques described herein. As previously described, in some embodiments, buffer layer 64 is formed to extend beyond the sidewalls of first package component 40. For example, buffer layer 64 may be formed such that the distance between opposite sides of buffer layer 64 (e.g., Fig.15 ) is greater than the distance between opposite sides of the first package component 40 (eg, as shown in FIG. Fig.15 ) and is less than the distance between opposite sides of the package 100 (e.g., as shown in FIG. Fig.15 ). In some embodiments, the width of buffer layer 64 can be greater than the width of first package component 40 and less than the width of second passivation layer 62. In some embodiments, buffer layer 64 can partially overlap gap fill material 32 (e.g., extend over a portion of gap fill material 32).

[0050] In some cases, as described herein, forming the buffer layer 64 so that it protrudes beyond the edge of the first package component 40 can reduce stress within the package 100. For example, using the techniques described herein, stress or warping caused by the CTE mismatch between the buffer layer 64 and the first package component 40 can be reduced. In some cases, using the techniques described herein, the stress within the package due to the CTE mismatch can be reduced by as much as 10%, but other results are possible. In this way, the thermal performance of the package can be improved. In addition, undesirable effects such as warping, peeling, delamination, etc. can be reduced, which can improve device yield and reliability. Accordingly, Figure 16-Figure 18 A non-limiting example of an embodiment is shown in which stress within the package 100 may be reduced by forming the buffer layer 64 to extend beyond the sidewalls of the first package component 40 .

[0051] refer to Fig.16 , according to some embodiments, a portion of package 100 is shown. As mentioned above, Fig.16 The package 100 may be similar to Fig.15 The package 100 shown in FIG. 1 may be formed using similar techniques. For example, a buffer layer 64 may be deposited over the second passivation layer 62 and then patterned to form an opening 67 over the scribe area 21 (see FIG. 2 ). Fig.13). Scribe line regions 21 are then removed during a singulation process that forms the sidewalls of package 100. In some embodiments, the sidewalls of package 100 may have an angle A1 in a range of about 75° to about 90°, although other angles are possible.

[0052] exist Fig.16 , the vertical edge of the sidewall of the first package component 40 is denoted as component edge 72, and the vertical edge of the upper sidewall of the package 100 is denoted as package edge 74. Package edge 74 may correspond to the upper sidewall of a layer below buffer layer 64, such as the upper sidewall of second passivation layer 62. In some embodiments, a lateral width W1 between component edge 72 and package edge 74 is in a range of about 20 μm to about 40 μm, although other widths are possible.

[0053] like Fig.16 As shown in , buffer layer 64 can have a thickness T1 in the range of about 3 μm to about 10 μm, although other thicknesses are possible. In some embodiments, the sidewalls of buffer layer 64 can have an angle A2 in the range of about 60° to about 90°, although other angles are possible. The bottom edge of the sidewall of buffer layer 64 is represented as point P1, and the top edge of the sidewall of buffer layer 64 is represented as point P2. In some embodiments, the lateral distance D2 between point P1 and point P2 is in the range of about 5 μm to about 20 μm, although other distances are possible.

[0054] exist Fig.16 In the embodiment shown in , point P1 is laterally located between component edge 72 and package edge 74, and point P2 is on the opposite side of component edge 72 from point P1. In other words, point P1 is located above gap fill material 32, and point P2 is located above first package component 40. In some cases, stress in package 100 can be reduced by extending the sidewalls of buffer layer 64 above component edge 72. In some embodiments, point P1 is a lateral distance D1 from package edge 74, which is in a range of about 0.1 μm to about 5 μm. In some embodiments, distance D1 is between about 1% and about 70% of width W1. Other distances are possible.

[0055] The properties of the sidewalls of buffer layer 64 can be controlled based on the composition and configuration of the package to appropriately reduce stress in the package. For example, the sidewall angle A2 (e.g., sidewall slope), distances D1 and D2, and / or the locations of points P1 and P2 can be controlled to provide reduced stress for a particular package design. Fig.17 and Fig.18 Other buffer layers 64 with other sidewall properties according to some embodiments are shown. In some embodiments, the properties of the sidewalls of the buffer layer 64 can be controlled by controlling the formation of the opening 67 (see Fig.16For example, when the buffer layer 64 is photosensitive, the sidewall characteristics can be controlled by controlling the pattern, energy, and / or focus of the exposure process. In some cases, the sidewall characteristics can also be controlled by controlling the temperature or duration of the curing process or controlling the parameters of the development process.

[0056] Fig.17 Shows something like Fig.16 , except that point P2 of buffer layer 64 is substantially aligned with component edge 72. Fig.17 As shown in FIG. 8 , point P1 of buffer layer 64 is located between component edge 72 and package edge 74 . Fig.18 Shows something like Fig.16 , except that point P2 of buffer layer 64 is substantially aligned with component edge 72. Fig.17 As shown in FIG. 8 , point P1 of buffer layer 64 is located between component edge 72 and package edge 74 . Fig.18 Shows something like Fig.16 , except that point P2 of buffer layer 64 is located above gap fill material 32. In other words, points P1 and P2 are both located between component edge 72 and package edge 74.

[0057] Figures 19 to 27 An enlarged view of a portion of package 200 is shown in accordance with some embodiments. Figure 19-Figure 27 The package 200 shown in FIG. Figure 15-18 The package 100 described above differs in that a second buffer layer 80 is formed over the buffer layer 64. In some cases, forming the second buffer layer 80 can further reduce stress within the package 200, thereby improving yield, reliability, and / or thermal performance. The properties of both the buffer layer 64 and the second buffer layer 80 can be independently controlled to reduce stress according to the specific structure of the package 200. Figure 19-Figure 27 A zoomed-in view of the Fig.15 The area 101 is represented in FIG. Figure 19-Figure 27 The embodiments shown in are intended as non-limiting examples, and the package 200, the buffer layer 64, and / or the second buffer layer 80 may be formed to have different characteristics than those shown using the techniques described herein.

[0058] The second buffer layer 80 can be a material similar to or different from the material of the underlying buffer layer 64. The second buffer layer 80 can be a material such as those previously described for the buffer layer 64 and can be formed using similar techniques. For example, in some embodiments, the second buffer layer 80 can be a photosensitive polymer material such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), etc. In some embodiments, after the buffer layer 64 is patterned, the second buffer layer 80 is deposited over the buffer layer 64, such as Fig.12 . The second buffer layer 80 may be deposited to a thickness in the range of about 3 μm to about 10 μm, although other thicknesses are possible. The second buffer layer 80 is then patterned using a suitable technique to expose the metal pad 50 and to expose the scribe line region 21. The sidewall characteristics of the second buffer layer 80 may be controlled by controlling the patterning process parameters, such as those previously described for the buffer layer 64.

[0059] refer to Fig.19 , according to some embodiments, a portion of the package 200 is shown. The bottom edge of the sidewall of the second buffer layer 80 is indicated as point P3, and the top edge of the sidewall of the second buffer layer 80 is indicated as point P4. Fig.19 The buffer layer 64 shown in FIG. Fig.16 For example, point P1 of buffer layer 64 is laterally located between component edge 72 and package edge 74 (e.g., located above gap fill material 32), and point P2 of buffer layer 64 is located above first package component 40. Fig.19 , points P3 and P4 of the second buffer layer 80 are both located above the first package component 40. The sidewall of the second buffer layer 80 may be recessed a distance D3 from the sidewall of the buffer layer 64. In some embodiments, the distance D3 between point P3 of the second buffer layer 80 and point P2 of the buffer layer 64 is in the range of about 0 μm to about 10 μm. Other distances are possible.

[0060] Fig. 20 A package 200 is shown, which is similar to Fig.19 The package shown in FIG. 1 is different in that the buffer layer 64 is similar to Fig.17 For example, point P2 of buffer layer 64 is substantially aligned with component edge 72, and point P1 of buffer layer 64 is located between component edge 72 and package edge 74. Points P3 and P4 of second buffer layer 80 are located above first package component 40, similar to Fig.19 Package 200. Fig.21 A package 200 is shown, which is similar to Fig.19 The package shown in FIG. 1 is different in that the buffer layer 64 is similar to Fig.18For example, points P1 and P2 of buffer layer 64 are located between component edge 72 and package edge 74 (eg, above gap fill material 32 ), and points P3 and P4 of second buffer layer 80 are located above first package component 40 .

[0061] Figure 22 to Figure 27 FIG. 2 shows an exemplary package 200 according to some embodiments, wherein the second buffer layer 80 covers the buffer layer 64. For example, the sidewall of the second buffer layer 80 is closer to the package edge 74 than the sidewall of the buffer layer 64. Fig. 22 , a portion of package 200 is shown, according to some embodiments. Fig. 22 The buffer layer 64 shown in FIG. Fig.16 For example, point P1 of buffer layer 64 is laterally located between component edge 72 and package edge 74 (e.g., located above gap fill material 32), and point P2 of buffer layer 64 is located above first package component 40. Fig. 22 , points P3 and P4 of the second buffer layer 80 are both laterally located between the component edge 72 and the package edge 74 (e.g., located above the gap fill material 32). The sidewall of the buffer layer 64 may be recessed a distance D4 from the sidewall of the second buffer layer 80. In some embodiments, the distance D4 between point P3 of the second buffer layer 80 and point P1 of the buffer layer 64 is in a range of about 0 μm to about 10 μm. In some embodiments, point P3 is a lateral distance from the package edge 74 that is in a range of about 0.1 μm to about 5 μm. Other distances are possible. Point P4 of the second buffer layer 80 may be substantially aligned with point P1, or may be laterally offset from point P1.

[0062] Fig.23 A package 200 is shown, which is similar to Fig. 22 The package shown in FIG. 1 is different in that the buffer layer 64 is similar to Fig.19 For example, point P2 of buffer layer 64 is substantially aligned with component edge 72, and point P1 of buffer layer 64 is located between component edge 72 and package edge 74. Points P3 and P4 of second buffer layer 80 are located laterally between component edge 72 and package edge 74 (e.g., above gap fill material 32), similar to Fig. 22 Package 200. Fig.24 A package 200 is shown, which is similar to Fig.19 The package shown in FIG. 1 is different in that the buffer layer 64 is similar to Fig.21For example, points P1 and P2 of buffer layer 64 and points P3 and P4 of second buffer layer 80 are located between component edge 72 and package edge 74 (e.g., above gap fill material 32). Point P4 of second buffer layer 80 may be substantially aligned with point P1 or point P2, or may be laterally offset from point P1 and / or point P2.

[0063] According to some embodiments, Fig.25 , Fig.26 ,and Fig. 27 In FIG. 4 , points P1 and P2 of buffer layer 64 are located above first package component 40 . In other embodiments, point P1 may be substantially aligned with component edge 72 . Fig.25 , point P3 of second buffer layer 80 is located between component edge 72 and package edge 74 (e.g., above gap fill material 32), and point P4 is substantially aligned with component edge 72. In other embodiments, point P4 may be laterally offset from component edge 72. Fig.26 In FIG. 1 , point P3 is laterally located between component edge 72 and package edge 74 , and point P4 is on the opposite side of component edge 72 from point P3 . In other words, point P3 is located above gap fill material 32 , while point P4 is located above first package component 40 . Fig. 27 , points P3 and P4 of second buffer layer 80 are located between component edge 72 and package edge 74 (eg, located above gap fill material 32 ).

[0064] Embodiments of the present invention have some advantageous features. A buffer layer is formed below a conductive connector of a semiconductor package, wherein the semiconductor package includes a package component surrounded by a gap filling material. By extending the buffer layer above the gap filling material, the stress within the semiconductor package can be reduced. For example, in some cases, the coefficient of thermal expansion (CTE) mismatch between the buffer layer and the package component may cause warping, stress, peeling, or delamination. Extending the buffer layer through the edge of the package component as described herein can reduce the stress caused by the CTE mismatch. The sidewall position and profile of the buffer layer can be controlled to minimize stress for a specific package design. In addition, multiple buffer layers can be deposited, which can further reduce the stress within the semiconductor package. In this way, the thermal performance, yield, and reliability of the semiconductor package can be improved.

[0065] In an embodiment of the present invention, a semiconductor package includes: a package component including an interconnect structure located on a first side of a substrate; a metal pad located on the interconnect structure; a semiconductor die connected to a second side of the substrate; a dielectric material surrounding the package component; a passivation layer extending over the package component and over the dielectric material; a first buffer layer located over the passivation layer, wherein the first buffer layer extends over the package component and over the dielectric material, wherein the width of the first buffer layer is greater than the width of the package component and less than the width of the passivation layer; and a conductive connector passing through the passivation layer and the first buffer layer to physically contact the metal pad. In one embodiment, the first buffer layer physically contacts the metal pad. In one embodiment, the top surface of the dielectric material and the package component is planar. In one embodiment, the first buffer layer includes one of polyimide, polybenzoxazole (PBO), or benzocyclobutene (BCB). In one embodiment, a portion of the first buffer layer above the dielectric material is inclined. In one embodiment, the semiconductor package includes: a second buffer layer located on the first buffer layer, wherein the conductive connector passes through the second buffer layer. In one embodiment, the second buffer layer has a width greater than the width of the first buffer layer and less than the width of the passivation layer. In one embodiment, the second buffer layer has a width less than the width of the package assembly. In one embodiment, the first buffer layer has a thickness in the range of 3 μm to 10 μm.

[0066] In an embodiment of the present invention, a semiconductor package includes: a first integrated circuit die including a conductive pad; a gap filling material covering a sidewall of the first integrated circuit die; a first polymer layer extending above a top surface of the first integrated circuit die and the gap filling material, wherein the first polymer layer physically contacts the conductive pad, wherein the sidewall of the first polymer layer is recessed from the sidewall of the gap filling material; and a conductive component extending through the first polymer layer to physically contact the conductive pad. In one embodiment, the sidewall of the first polymer layer is recessed from the sidewall of the gap filling material at a distance in the range of 0.1 μm to 5 μm. In one embodiment, the sidewall of the first polymer layer is inclined at an angle less than 90°. In one embodiment, the semiconductor package includes: a second polymer layer located on the first polymer layer, wherein the conductive component extends through the second polymer layer. In one embodiment, the bottom edge of the sidewall of the first polymer layer is located above the gap filling material. In one embodiment, the top edge of the sidewall of the first polymer layer is located above the first integrated circuit die. In one embodiment, the top edge of the sidewall of the first polymer layer is located above the gap filling material.

[0067] In an embodiment of the present invention, a method for forming a semiconductor package includes: connecting a semiconductor die to a package assembly, wherein the package assembly includes a metal pad; sealing the package assembly with an insulating material; depositing a passivation layer on the surface of the package assembly and the insulating material; patterning the passivation layer to expose the metal pad; depositing a buffer layer over the patterned passivation layer; patterning the buffer layer to expose the metal pad and expose the surface of the passivation layer over the insulating material, wherein a portion of the patterned buffer layer extends from the metal pad to the exposed surface of the passivation layer; and forming a conductive connector on the metal pad. In one embodiment, the method includes: performing a singulation process on the exposed surface of the passivation layer to remove portions of the passivation layer and the insulating material. In one embodiment, patterning the buffer layer includes exposing the buffer layer to light and developing the buffer layer. In one embodiment, an inclined surface of the buffer layer extends over a sidewall of the package assembly.

[0068] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: a package assembly including an interconnect structure on a first side of a substrate; a plurality of metal pads located on the interconnect structure; a semiconductor die coupled to the second side of the substrate; a dielectric material surrounding the package component; a passivation layer extending over the package assembly and over the dielectric material; a first buffer layer located above the passivation layer, wherein the first buffer layer extends above the package component and above the dielectric material, wherein a width of the first buffer layer is greater than a width of the package component and less than a width of the passivation layer; and A plurality of conductive connectors pass through the passivation layer and the first buffer layer to physically contact the plurality of metal pads.

2. The semiconductor package according to claim 1, wherein: The first buffer layer physically contacts the plurality of metal pads.

3. The semiconductor package according to claim 1, wherein: The top surfaces of the dielectric material and the package assembly are planar.

4. The semiconductor package according to claim 1, further comprising: The second buffer layer is located on the first buffer layer, wherein the plurality of conductive connectors pass through the second buffer layer.

5. The semiconductor package according to claim 4, wherein: The second buffer layer has a width greater than the width of the first buffer layer and smaller than the width of the passivation layer.

6. A semiconductor package, comprising: a first integrated circuit die comprising a plurality of conductive pads; a gap-fill material covering sidewalls of the first integrated circuit die; a first polymer layer extending over a top surface of the first integrated circuit die and the gap-fill material, wherein the first polymer layer physically contacts the plurality of conductive pads, wherein sidewalls of the first polymer layer are recessed from sidewalls of the gap-fill material; and A plurality of conductive features extend through the first polymer layer to physically contact the plurality of conductive pads.

7. The semiconductor package according to claim 6, wherein: The sidewalls of the first polymer layer are inclined at an angle less than 90°.

8. The semiconductor package according to claim 6, further comprising: A second polymer layer is disposed on the first polymer layer, wherein the plurality of conductive features extend through the second polymer layer.

9. The semiconductor package according to claim 6, wherein: A bottom edge of the sidewall of the first polymer layer is located above the gap-fill material.

10. A method of forming a semiconductor package, comprising: connecting a semiconductor die to a package assembly, wherein the package assembly includes a metal pad; sealing the package assembly with an insulating material; Depositing a passivation layer on the surface of the packaging component and the insulating material; patterning the passivation layer to expose the metal pad; depositing a buffer layer over the patterned passivation layer; patterning the buffer layer to expose the metal pad and to expose a surface of the passivation layer above the insulating material, wherein a portion of the patterned buffer layer extends from the metal pad to the exposed surface of the passivation layer; and A conductive connector is formed on the metal pad.

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