Semiconductor package with multiple types of conductive elements

Abstract

The invention discloses a semiconductor package. The semiconductor package includes: a package substrate having a front surface and a back surface, where the package substrate includes: a plurality of groups of front conductive patterns; multiple groups of back conductive patterns; and a plurality of groups of interconnection structures electrically coupling the group of front conductive patterns and the group of back conductive patterns, respectively, wherein the packaging substrate at least comprises a first thermal property area and a second thermal property area, and the first thermal property area and the second thermal property area have different thermal properties; the plurality of groups of conductive elements are attached to the front surface and the back surface of the packaging substrate and are connected with the plurality of groups of front surface conductive patterns and the plurality of groups of back surface conductive patterns, and the plurality of groups of conductive elements comprise a group of first type conductive elements mounted in a first thermal property area of the packaging substrate; and a set of second type conductive elements mounted in a second thermal performance region of the package substrate.

Description

Technical Field

[0001] The present application relates generally to semiconductor technology and, more particularly, to semiconductor packages having multiple types of conductive elements. Background Art

[0002] The interconnect wires inside a semiconductor chip are very thin, with a width on the order of a few micrometers or less. The formation of such wires makes it possible to manufacture semiconductor chips containing millions or more interconnected components. However, at some point, a connection needs to be made between the chip and the outside world, which makes it difficult to accommodate such small wire tolerances.

[0003] In order to connect a semiconductor chip to an external device or system, a printed circuit board (PCB), an intermediate layer or other similar substrate is widely used to mount the chip, thereby forming a semiconductor package with a larger size. The leads on the PCB are much thicker than the leads on the chip, usually measured in millimeters. It is impractical to connect the chip leads directly to the PCB leads. Therefore, an intermediate structure is needed that can handle this range of lead width changes.

[0004] One example of such a structure is a ball grid array (BGA). BGA packaging technology is a surface mount technology used for integrated circuits, often used to permanently fix devices such as microprocessors. The BGA package is an array on the bottom of the package substrate where solder balls are used as input / output (I / O) terminals of the circuit and connected to the PCB.

[0005] Solder balls have the functions of signal conduction, electrical connection and heat conduction. In existing BGA packages, the solder balls on the package substrate are usually the same. The larger the solder ball, the stronger the heat conduction ability. However, at the same time, the larger the solder ball, the larger the substrate area occupied, which conflicts with the high density and high pin output of BGA.

[0006] Therefore, it is necessary to further improve semiconductor packaging. Summary of the invention

[0007] An object of the present application is to provide a semiconductor package structure with improved heat dissipation efficiency.

[0008] According to one aspect of the present application, a semiconductor package is provided. The semiconductor package comprises: a package substrate having a front side and a back side, wherein the package substrate comprises: a plurality of front conductive patterns formed on the front side; a plurality of back conductive patterns formed on the back side; and a plurality of interconnect structures electrically coupling the plurality of front conductive patterns with the plurality of back conductive patterns, respectively; wherein the package substrate comprises at least a first thermal performance region and a second thermal performance region, wherein the first thermal performance region and the second thermal performance region have different thermal performances; a plurality of conductive elements attached to the front side and the back side of the package substrate and connected to the plurality of front conductive patterns and the plurality of back conductive patterns, wherein the plurality of conductive elements comprises: a group of first type conductive elements mounted on the first thermal performance region of the package substrate, connected to a portion of the front conductive patterns and the back conductive patterns; and a group of second type conductive elements mounted on the second thermal performance region of the package substrate, connected to a portion of the front conductive patterns and the back conductive patterns.

[0009] It should be understood that both the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. In addition, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings cited herein form part of the specification. The features shown in the drawings illustrate only some embodiments of the present application, not all embodiments of the present application, unless the detailed description explicitly indicates otherwise, and the reader of this specification should not be implied to the contrary.

[0011] Figures 1 to 3 A semiconductor package according to an embodiment of the present application is shown. Figure 1 is a cross-sectional view of the package. Figure 2 is a front view of the packaging substrate, Figure 3 is a back view of the packaging substrate.

[0012] Figure 4 and Figure 5 A semiconductor package according to another embodiment of the present application is shown. Figure 4 is a cross-sectional view of the packaging substrate. Figure 5 is a back view of the packaging substrate.

[0013] Figure 6 A package substrate of a semiconductor package according to another embodiment of the present application is shown.

[0014] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0015] The following detailed description of the exemplary embodiments of the present application refers to the drawings that form a part of this specification. The drawings illustrate specific exemplary embodiments in which the present application can be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable a person skilled in the art to practice the present application. A person skilled in the art may further utilize other embodiments of the present application and make logical, mechanical and other changes without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret this specification in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0016] In this application, the use of the singular includes the plural unless expressly stated otherwise. In this application, the use of "or" means "and / or" unless otherwise stated. Furthermore, the use of the term "comprising" is not limiting. In addition, terms such as "element" or "component" encompass elements and components comprising one unit and elements and components comprising more than one subunit unless specifically stated otherwise. In addition, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0017] As used herein, for ease of description, spatially relative terms such as "under," "below," "above," "above," "up," "upper," "lower," "left," "right," "vertical," "horizontal," "side," etc. may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features), as illustrated in the drawings. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected or coupled to the other element, or there may be intermediate elements.

[0018] The inventor of the present application has found that due to the increase in integration, many semiconductor packages will install multiple semiconductor chips on the same substrate, or install electronic component packages with multiple circuit function parts integrated on the same substrate. These different semiconductor chips or circuit function parts often have different power consumption, which leads to different heat dissipation capabilities required. When the semiconductor chip and the package generate heat, most of the heat is transferred to the outside of the semiconductor package through the package substrate where they are located, but the package structure is usually made of low thermal conductivity materials such as epoxy resin and filler. Therefore, when the semiconductor chip generates a lot of heat due to long-term operation, the package structure may not be able to conduct the heat in time, causing the heat to be accumulated in the chip or substrate. At the same time, the heat accumulated in the semiconductor package may cause the substrate to deform due to heat, and the substrate may have different compositions in different regions (for example, usually copper interconnect structures, and polymers such as epoxy resin or similar insulating materials). These different material compositions make the semiconductor package have different thermal stress distributions when the substrate is running.

[0019] In order to solve at least one of the above problems, the inventors of the present application have proposed an array of multiple types of conductive elements for interconnecting electronic components or electronic component packages with a package substrate. For example, conductive elements with a copper core or similar materials with higher thermal conductivity, and conductive elements such as solder balls made mainly of materials with lower thermal expansion coefficients (such as resin cores) can be used. These high thermal conductivity conductive elements can establish a thermal path with improved heat dissipation capabilities for the semiconductor package, while the solder balls with lower thermal expansion coefficients can reduce the impact of thermal stress on the solder ball solder joints, thereby significantly reducing the risk of solder joint failure of the semiconductor package due to heat accumulation.

[0020] Figures 1 to 3 A semiconductor package 100 according to an embodiment of the present application is shown. Figure 1 is a cross-sectional view of the semiconductor package 100, Figure 2 is a front view of a package substrate of the semiconductor package 100, Figure 3 is a rear view of the package substrate of the semiconductor package 100 .

[0021] like Figure 1 As shown, the semiconductor package 100 includes a package substrate 125 having a front side 119 and a back side 129. The package substrate 125 may include one or more insulating layers, which may be interlaced with one or more conductive layers. It is understood that the package substrate 125 may include any number of conductive layers and insulating layers interlaced with each other. The insulating layer may include ceramic, plastic, glass or other suitable insulating materials. The conductive layer and other internal conductive structures (such as through holes) form an interconnect structure 130 embedded in the package substrate 125. For example, the interconnect structure 130 may be made of copper.

[0022] The package substrate 125 also includes a group of front conductive patterns 110, such as contact pads, formed on the front side 119, and a group of back conductive patterns 120, such as contact pads, formed on the back side 129. The front and back conductive patterns may be end surfaces of a group of interconnect structures 130 embedded in the insulating layer of the package substrate 125, respectively, which are exposed from the front side 119 or the back side 129, respectively. The group of interconnect structures 130 may electrically couple the group of front conductive patterns 110 with the group of back conductive patterns 120, respectively. As described above, in some embodiments, the interconnect structures 130 may include conductive wiring or vias to guide signals through the insulating layer.

[0023] At least one electronic component 115 is mounted on the front side 119 of the packaging substrate 125. The electronic component can be in the form of a semiconductor chip or multiple semiconductor chips. In some embodiments, the at least one electronic component 115 may include one or more digital chips, analog chips, or mixed signal chips, such as application specific integrated circuit ("ASIC") chips, sensor chips, wireless and radio frequency (RF) chips, memory chips, logic chips, or voltage regulator chips. In some other embodiments, the at least one electronic component 115 may also include one or more passive electrical components, such as resistors, capacitors, inductors, etc. Figure 1 In the illustrated embodiment, the electronic component 115 is a semiconductor chip having a plurality of input / output ports, each of which needs to be electrically coupled to an external device to transmit signals or power.

[0024] The semiconductor package 100 further includes a group of front solder balls 210 and a group of back solder balls 220. As front conductive elements and back conductive elements, the front solder balls 210 and the back solder balls 220 are electrically connected to the group of front conductive patterns 110 and the group of back conductive patterns 120, respectively. The electronic component 115 is electrically connected to the group of front conductive patterns 110 through the group of front solder balls 210 to establish an electrical connection with the package substrate 125.

[0025] Specifically, the front and back solder balls 210 and 220 may be distributed on the package substrate 125 in the form of spherical shapes or similar structures. Figure 1 It can be seen that because there is more space on the packaging substrate 125, especially when the interconnect structure 130 can provide support for the redistribution of wiring, the first spacing between two adjacent solder balls of the front solder balls 210 can be increased to the second spacing between two adjacent solder balls of the back solder balls 220. Accordingly, the size of the back solder balls 220 may be larger than the size of the front solder balls 210. In other words, the solder ball layout on the back side 129 is more expanded than the solder ball layout on the front side 119. The larger solder ball layout is conducive to better heat dissipation. In some embodiments, the number of solder balls in the front solder balls 210 may be equal to the number of solder balls in the back solder balls 220, such as Figures 1 to 3 In one variation, the number of solder balls in the front solder balls 210 and the number of solder balls in the back solder balls 220 may be different, for example, two or more solder balls in the front solder balls 210 may be coupled to one solder ball in the back solder balls 220, or two or more solder balls in the back solder balls 220 may be coupled to one solder ball in the front solder balls 210.

[0026] The front solder balls 210 include at least two types of solder balls, namely, a plurality of first type solder balls 111 and a plurality of second type solder balls 112. Similarly, the back solder balls 220 also include at least two types of solder balls, namely, a plurality of first type solder balls 121 and a plurality of second type solder balls 122. In the illustrated embodiment, the first type solder balls 111, 121 may include a copper core and a solder coating covering the outside of the copper core, while the second type solder balls 112, 122 may be conductive solder balls including a resin core and a solder coated on the outside of the resin core. In some other embodiments, the first type solder balls 111, 121 may be made of other solders with better thermal conductivity. Compared with the second type solder balls 112, 122, the first type solder balls 111, 121 may have higher thermal conductivity and electrical conductivity, thereby achieving better heat dissipation and lower resistance. In some embodiments, the first type solder balls 111, 121 are preferably located in areas of the electronic component 115 that consume more power and generate more heat than other areas because heat needs to be dissipated through the first type solder balls 111, 121. Figure 1 In the figure, the first type solder balls 111 and 121 are attached in the first thermal performance region 101 of the packaging substrate 125; compared with other thermal performance regions of the packaging substrate 125, such as the second thermal performance region 102, the first thermal performance region 101 needs to provide better thermal conductivity to help heat be drawn from the electronic component 115 to the outside of the semiconductor package 100.

[0027] In some embodiments, the electronic component 115 is a semiconductor chip, which may have different circuit function parts, such as a logic circuit part, a power circuit part, a control circuit part or a storage circuit part. Among them, because of the need to perform complex operations such as logical operations, the logic circuit part usually has a higher power consumption; and the power circuit part usually has a relatively high power consumption due to power supply requirements; while the control circuit or storage circuit has a relatively low power consumption. Therefore, the first type of solder balls 111 and / or 121 can be set in the area of ​​the electronic component 115 corresponding to the logic circuit part and the power circuit part, that is, the first thermal performance area 101 of the package substrate 125 corresponds to the area where the logic circuit and / or the power circuit are attached; and the second type of solder balls 112 and / or 122 can be set in the area of ​​the electronic component 115 corresponding to the control circuit or the storage circuit, that is, the second thermal performance area 102 of the package substrate 125 corresponds to the area where the control circuit or the storage circuit is attached.

[0028] In some other embodiments, the first type solder balls 111, 121 are preferably located in areas of the electronic component 115 that require better heat dissipation than other areas. For example, the first type solder balls 111, 121 are at least located in the central area of ​​the package substrate 125, which may be provided with electronic components with higher power consumption, and therefore will generate more heat when working than other areas of the package substrate 125. In addition, as mentioned above, the first type solder balls 121 on the back side of the package substrate 125 can further improve the thermal conductivity of the semiconductor package 100, especially for areas that require better heat dissipation. In some preferred embodiments, the first type conductive elements can be attached in pairs to the front and back sides of the package substrate 125, so that the entire thermal conduction path from the electronic component 115 to the outside of the semiconductor package 100 is composed of a material with higher thermal conductivity (usually the interconnect structure 130 can be composed of copper or similar high thermal conductivity materials). It is understood that the "paired" mentioned herein refers to the front and back conductive elements connected to the same interconnect structure, but since the number of front conductive elements or back conductive elements connected to the same interconnect structure may be different, "paired" does not require a one-to-one correspondence between the front conductive elements and the back conductive elements. In addition, it should be noted that, although preferably all conductive elements in the first thermal performance region can be first-type solder balls, in some embodiments, a portion of the conductive elements installed in the first thermal performance region can be first-type solder balls, which can at least partially improve the thermal conductivity; and the remaining conductive elements installed in the first thermal performance region can be other types of solder balls, such as pure tin solder balls. Preferably, at least 50% of the conductive elements in the first thermal performance region can be first-type solder balls, or more preferably, at least 80% of the conductive elements can be first-type solder balls.

[0029] While thermal conductivity may be a factor to consider when mounting multiple types of solder balls on the package substrate 125, other issues caused by heat accumulation also need to be considered. As previously mentioned, at least one of the groups of front solder balls 210 and the group of back solder balls 220 may further include one or more second-type solder balls that are at least partially made of a material with a greater thermal expansion coefficient than the first-type solder balls, or at least made of a material that is close to the base material (e.g., resin) of the package substrate 125. For example, in Figure 1 In the embodiment shown in , each group of solder balls in the group of front solder balls 210 and the group of back solder balls 220 includes a plurality of second type solder balls 112 and / or 122. The second type solder balls 112 and 122 each include a resin core coated with solder. This type of solder ball can provide mechanical support and compensate for mechanical stress generated, for example, due to thermal expansion within the semiconductor package 100, because the resin core can significantly compensate for the mechanical stress. In some embodiments, the second type solder balls are arranged, for example, in an area of ​​the package substrate 125 where the density of the interconnect structure 130 is higher than in other areas, because a denser interconnect structure may generate greater mechanical stress that needs to be compensated. For example, as Figure 2 and Figure 3 As shown, the second type solder balls 122 of the group of back solder balls 220 can be arranged around the first type solder balls 121 of the group of back solder balls 220. In other embodiments, the second type solder balls can also be arranged in an area on the package substrate 125 that connects the circuit functional parts with lower power consumption. In one embodiment, the second type solder balls 112 of the group of front solder balls 210 are arranged at the corners of the electronic component 115 to compensate for the thermal expansion mismatch between the electronic component 115 and the package substrate 125. In addition, the second type solder balls 112 at the corners of the electronic component 115 can maintain an appropriate distance between the electronic component 115 and the package substrate 125 after the reflow process of the solder balls, thereby allowing the packaging material to pass through and avoiding the generation of voids or cavities in the sealant layer. In some embodiments, the second type solder balls 112 may be located in an area below the electronic component 115 that may generate the greatest mechanical stress during the use of the semiconductor package 100. In addition, the front or back solder balls may also include other types of solder balls, such as pure tin solder balls, which may be formed at other locations of the package substrate 125, such as being attached to areas other than the first thermal performance region and the second thermal performance region to implement, for example, a BGA structure. It is understood that in some embodiments, other types of solder balls, such as pure tin solder balls, may also be attached to the first thermal performance region and the second thermal performance region, but do not completely replace the first type of solder balls or the second type of solder balls. For example, in Figure 1 In the illustrated embodiment, the second thermal performance region 102 includes a portion of pure tin solder balls 113 and 123. Figure 1In the illustrated embodiment, only the first thermal performance region 101 and the second thermal performance region 102 are shown, but in some other embodiments, the packaging substrate 125 may also include other thermal performance regions, which have thermal properties and thermal performance requirements different from those of the first thermal performance region 101 and the second thermal performance region 102.

[0030] In some preferred embodiments, for example Figures 1 to 3 In the embodiment shown in , each of the back solder balls 220 is coupled to at least one of the front solder balls 210 through at least one pair of front and back conductive patterns 110, 120 and an interconnect structure 130. Figure 1 In an embodiment, each first type solder ball 121 of the group of back solder balls 220 is aligned with one first type solder ball 111 of the group of front solder balls 210 in a direction perpendicular to the front or back side 119, 129 of the package substrate 125. Accordingly, the interconnection path 150 connecting each first type solder ball 121 of the group of back solder balls 220 with one first type solder ball 111 of the group of front solder balls 210 is substantially perpendicular to the package substrate 125. In this way, the interconnection path 150 connecting the first type solder ball 121 of the back solder balls 220 with the first type solder ball 111 of the front solder balls 210 has a shorter total lead length or through-hole length and preferably has a larger width than other interconnection paths 160 connecting the second type or other type solder balls of the group of back solder balls 220 with one solder ball of the front solder balls 210, or connecting the second type or other type solder balls of the group of front solder balls 210 with one solder ball of the back solder balls 220. The interconnection path 150 has correspondingly better thermal and electrical conductivity, which may be helpful for heat dissipation in areas of the electronic component 115 that generate more heat during operation. It is understood that in some alternative embodiments, due to the routing of the interconnect structure 130 in the packaging substrate 125 or other considerations, the interconnection path 150 connecting each first type solder ball 121 of the back solder ball 220 with one first type solder ball 111 of the front solder ball 210 may not be perpendicular to the packaging substrate 125. Nevertheless, the use of the first type solder balls 111 and 121 still has better thermal conductivity on both sides of the packaging substrate 125.

[0031] The semiconductor package 100 may further include at least one sealant layer 116, which at least partially extends over the substrate 125 and covers the at least one electronic component 115. The sealant layer 116 may provide protection for the electronic component 115. In some embodiments, a shielding layer (not shown) may be further formed on the sealant layer 116 to achieve the purpose of electromagnetic interference shielding.

[0032] In some embodiments, the electronic components packaged in the semiconductor package may be other components, such as a chiplet or other similar smaller packages.

[0033] Figure 4 and Figure 5 FIG. 4 shows a semiconductor package 400 according to another embodiment of the present application. Figure 4 and Figure 5 As shown, the electronic component 415 is mounted on the front side of the package substrate 425 of the semiconductor package 400 in the form of a chiplet. The chiplet may include a plurality of circuit function modules as shown in the figure, such as a system chip (SoC), a high bandwidth memory (HBM), and a central processing unit (CPU) module. These circuit function modules are packaged in the semiconductor package 400 as respective circuit function parts of the semiconductor package 400.

[0034] Depending on which thermal functional part of the electronic component 415 is connected to the conductive element, different types of conductive elements can be installed on the front and back of the packaging substrate 425. It can be understood that the thermal functional part of the electronic component 415 mainly depends on the circuit function therein, such as the logic circuit part, the power circuit part, the control circuit part or the storage circuit part. Among them, because of the need to perform complex operations such as logical operations, the logic circuit part usually has a higher power consumption; and the power circuit part usually has a relatively high power consumption due to power supply requirements; and the control circuit or storage circuit has a relatively low power consumption. Correspondingly, the circuit functional part with higher power consumption usually has higher heat dissipation requirements, while the circuit functional part with lower power consumption usually has lower heat dissipation requirements.

[0035] For example, a group of front conductive elements, such as solder balls 410, are mounted on the front side of the package substrate 425. The front solder balls 410 include a plurality of first type solder balls 411 below the logic circuit functional area 401 below the central area of ​​the package substrate 425, and are respectively connected to first type solder balls 421 belonging to a group of back solder balls 420 to provide better thermal conductivity and electrical conductivity. The first type solder balls 411 and 421 may include a copper core and solder coated on the outside of the copper core. Other thermal performance areas 402 on the package substrate 425 may be mounted with second type solder balls 412 and 422, which include a resin core and solder coated on the outside of the resin core, in a manner similar to Figures 1 to 3 The semiconductor package 100 is not described in detail here. It is understood that other types of solder balls, such as pure tin solder balls 413 and 423, may also be partially disposed in the region 402 and / or other regions.

[0036] Figure 6A package substrate 600 for semiconductor packaging of another embodiment of the present application is shown. The package substrate 600 can be used to mount various electronic components, and can be further attached to other substrates or devices to transfer the electronic components thereon to these other substrates or devices. In some embodiments, the front side 619 of the package substrate 600 is used to mount electronic components, and the back side 629 of the package substrate 600 is used to attach the package substrate 600 to other substrates or devices.

[0037] like Figure 6 As shown, the package substrate 600 includes multiple areas, which have different thermal properties. For example, the first thermal performance area 601 located in the middle of the package substrate 600 is mainly used to install electronic components with higher heat dissipation requirements, such as logic circuit chips; the second thermal performance area 602 adjacent to the first thermal performance area 601 can be used to install other electronic components, which may generate less heat than the logic circuit chip during operation, such as a power chip; the third thermal performance area 603 located at the outermost side of the package substrate 600 can be used to install other electronic components, such as control chips or passive devices (such as switching devices or connectors). Generally speaking, compared with the third thermal performance area 603, the second thermal performance area 602 can have a higher density of conductive interconnection structure (such as a redistribution layer), wherein the conductive interconnection structure is usually composed of a metal material or an alloy material, which has a higher thermal expansion rate than other dielectric materials (such as resin materials) in the package substrate, so it is easy to produce a larger deformation after being heated.

[0038] For the first thermal performance region 601 with higher heat dissipation requirements, conductive elements with better thermal conductivity and electrical conductivity, such as conductive pillars or copper core solder balls, can be provided on both the front and back sides of the package substrate 600. Figure 6 The copper core solder balls 611 and 621 are shown. Preferably, copper core solder balls or other conductive elements with better thermal conductivity and electrical conductivity can be used in the first thermal performance region 601, and a certain proportion of conductive elements with better thermal conductivity and electrical conductivity can also be used in the region 601, for example, more than 30%, more than 40%, more than 50%, more than 60%, more than 70%, more than 80% or more than 90%. Optionally, for the first thermal performance region 601, conductive elements with better thermal conductivity and electrical conductivity can be set only on one of the front side or the back side of the package substrate 600.

[0039] For the second thermal performance region 602, since there is usually a higher density of conductive interconnect structures therein (for example, compared to the third thermal performance region 603), resin core solder balls 612 and 622, or other solder balls or conductive elements with a reduced metal percentage, can be used on the front and / or back of the package substrate 600 in this region. Such conductive elements have a relatively low thermal expansion coefficient compared to metal solder balls, so the shear stress generated in the package substrate 600 due to temperature changes can be reduced, and the shear stress can be avoided to cause the fracture of the solder ball solder joints. Preferably, solder balls or conductive elements with a reduced metal percentage can be used in the second thermal performance region 602, and a certain percentage of solder balls or conductive elements with a reduced metal percentage can also be used in this region 602, for example, a percentage of more than 30%, more than 40%, more than 50%, more than 60%, more than 70%, more than 80% or more than 90%.

[0040] For the third thermal performance region 603, the electronic components mounted thereon generally have lower heat dissipation requirements, and the density of the conductive interconnection structure contained therein is also relatively low, so conventional conductive components can be used in this region, such as Figure 6 The pure tin solder balls 613 or 623 are shown. The pure tin solder balls can increase the contact area between the solder balls and the chip and between the solder balls and other substrates, thereby increasing the soldering strength and preventing the solder joints from breaking due to external forces.

[0041] Although the semiconductor package of the present application is described in conjunction with the corresponding drawings, it will be understood by those skilled in the art that modifications and adaptations may be made to the semiconductor package without departing from the scope of the present invention.

[0042] The discussion herein includes many illustrative figures showing various parts of semiconductor packages. For clarity of illustration, these figures do not show all aspects of each example semiconductor package. Any example semiconductor package provided herein may share any or all features with any or all other semiconductor packages provided herein.

[0043] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. In addition, other embodiments will be apparent to those skilled in the art by considering the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that the present application and the examples herein be considered merely exemplary, with the true scope and spirit of the invention being indicated by the list of the appended exemplary claims.

Claims

1. A semiconductor package, characterized in that: include: A packaging substrate having a front side and a back side, wherein the packaging substrate comprises: A plurality of front conductive patterns formed on the front surface; A plurality of groups of back-side conductive patterns formed on the back side; and a plurality of interconnect structures electrically coupling the group of front conductive patterns with the group of back conductive patterns; Wherein, the packaging substrate comprises at least a first thermal performance region and a second thermal performance region, and the first thermal performance region and the second thermal performance region have different thermal properties; A plurality of groups of conductive elements are attached to the front and back sides of the packaging substrate and are connected to the plurality of groups of front conductive patterns and the plurality of groups of back conductive patterns, wherein the plurality of groups of conductive elements include: a group of first type conductive elements mounted on a first thermal performance region of the package substrate, connected to a portion of the front conductive pattern and the back conductive pattern; and A group of second type conductive elements mounted on the second thermal performance region of the package substrate are connected to a portion of the front conductive pattern and the back conductive pattern.

2. The semiconductor package according to claim 1, wherein: The first type conductive element includes a conductive copper pillar, or includes a conductive solder ball having a copper core and solder covering the outside of the copper core.

3. The semiconductor package according to claim 1, wherein: The first type conductive elements are attached in pairs to the front and back sides of the package substrate.

4. The semiconductor package according to claim 1, wherein: The second type conductive element includes a conductive solder ball having a resin core and solder coated outside the resin core.

5. The semiconductor package according to claim 1, wherein: The plurality of groups of conductive elements further include pure tin solder balls attached to regions of the package substrate outside the first thermal performance region and the second thermal performance region.

6. The semiconductor package according to claim 1, wherein: The first thermal performance area of ​​the packaging substrate is used to mount a first electronic component, and the second thermal performance area of ​​the packaging substrate is used to mount a second electronic component, wherein the power consumption of the first electronic component is higher than that of the second electronic component.

7. The semiconductor package according to claim 6, wherein: The first electronic component includes a logic circuit electronic component or a power circuit electronic component, and the second electronic component includes a control circuit electronic component.

8. The semiconductor package according to claim 5, wherein: The first thermal performance area of ​​the packaging substrate is used to install a first electronic component, the second thermal performance area of ​​the packaging substrate is used to install a second electronic component, and the area outside the first thermal performance area and the second thermal performance area of ​​the packaging substrate is used to install other electronic components, wherein The heat dissipation requirement of the first electronic component is higher than the heat dissipation requirement of electronic components other than the first electronic component.

9. The semiconductor package according to claim 1, wherein: The density of the interconnection structure in the second thermal performance region of the package substrate is higher than the density of the interconnection structure in the region outside the second thermal performance region of the package substrate.

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