Semiconductor package with multiple types of solder balls

Abstract

The invention discloses a semiconductor package. The semiconductor package includes a package substrate having a front surface and a back surface, the package substrate including: a set of front conductive patterns formed on the front surface; a group of back surface conductive patterns formed on the back surface; and a set of interconnection structures electrically coupling the set of front conductive patterns and the set of back conductive patterns, respectively; at least one electronic component mounted on the front surface of the package substrate and electrically coupled to the set of front conductive patterns through a set of front solder balls; the group of back solder balls are electrically connected with the group of back conductive patterns respectively; wherein the group of front solder balls comprises one or more first type solder balls and one or more second type solder balls, and the group of back solder balls comprises one or more first type solder balls and one or more second type solder balls; and the first type of solder balls in the group of front solder balls are electrically coupled with the first type of solder balls in the group of back solder balls.

Description

Technical Field

[0001] The present application relates generally to semiconductor technology and, more particularly, to semiconductor packages having multiple types of solder balls. Background Art

[0002] The interconnect wires inside a semiconductor chip are very thin, with a width on the order of a few micrometers or less. The formation of such wires makes it possible to manufacture semiconductor chips containing millions or more interconnected components. However, at some point, a connection needs to be made between the chip and the outside world, which makes it difficult to accommodate such small wire tolerances.

[0003] In order to connect a semiconductor chip to an external device or system, a printed circuit board (PCB), an intermediate layer or other similar substrate is widely used to mount the chip, thereby forming a semiconductor package with a larger size. The leads on the PCB are much thicker than the leads on the chip, usually measured in millimeters. It is impractical to connect the chip leads directly to the PCB leads. Therefore, an intermediate structure is needed that can handle this range of lead width changes.

[0004] One example of such a structure is a ball grid array (BGA). BGA packaging technology is a surface mount technology used for integrated circuits, often used to permanently fix devices such as microprocessors. The BGA package is an array on the bottom of the package substrate where solder balls are used as input / output (I / O) terminals of the circuit and connected to the PCB.

[0005] Solder balls have the functions of signal conduction, electrical connection and heat conduction. In existing BGA packages, the solder balls on the back of the package substrate are usually the same. The larger the solder ball, the stronger the heat conduction ability. However, at the same time, the larger the solder ball, the larger the substrate area occupied, which conflicts with the high density and high pin output of BGA.

[0006] Therefore, it is necessary to further improve semiconductor packaging. Summary of the invention

[0007] An object of the present application is to provide a packaging structure with improved heat dissipation efficiency.

[0008] According to one aspect of the present application, a semiconductor package is provided. The semiconductor package comprises: a package substrate having a front side and a back side, wherein the package substrate comprises: a group of front side conductive patterns formed on the front side; a group of back side conductive patterns formed on the back side; and a group of interconnect structures electrically coupling the group of front side conductive patterns with the group of back side conductive patterns respectively; at least one electronic component mounted on the front side of the package substrate and electrically coupled with the group of front side conductive patterns through a group of front side solder balls; a group of back side solder balls electrically connected with the group of back side conductive patterns respectively; wherein the group of front side solder balls comprises one or more first type solder balls and one or more second type solder balls, and the group of back side solder balls comprises one or more first type solder balls and one or more second type solder balls; and wherein the first type solder balls in the group of front side solder balls are electrically coupled with the first type solder balls in the group of back side solder balls.

[0009] It should be understood that both the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. In addition, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings cited herein form part of the specification. The features shown in the drawings illustrate only some embodiments of the present application, not all embodiments of the present application, unless the detailed description explicitly indicates otherwise, and the reader of this specification should not be implied to the contrary.

[0011] Figures 1 to 3 A semiconductor package according to an embodiment of the present application is shown. Figure 1 is a cross-sectional view of the package. Figure 2 is a front view of the packaging substrate, Figure 3 is a back view of the packaging substrate.

[0012] Figure 4 and Figure 5 A semiconductor package according to another embodiment of the present application is shown. Figure 4 is a cross-sectional view of the packaging substrate. Figure 5 is a back view of the packaging substrate.

[0013] Figure 6 and Figure 7 A semiconductor package according to another embodiment of the present application is shown. Figure 6 is a cross-sectional view of the packaging substrate. Figure 7 is a back view of the packaging substrate.

[0014] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0015] The following detailed description of the exemplary embodiments of the present application refers to the drawings that form a part of this specification. The drawings illustrate specific exemplary embodiments in which the present application can be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable a person skilled in the art to practice the present application. A person skilled in the art may further utilize other embodiments of the present application and make logical, mechanical and other changes without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret this specification in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0016] In this application, the use of the singular includes the plural unless expressly stated otherwise. In this application, the use of "or" means "and / or" unless otherwise stated. In addition, the use of the term "including" and other forms such as "includes" and "included" are not limiting. In addition, unless specifically stated otherwise, terms such as "element" or "component" encompass elements and components that include one unit and elements and components that include more than one subunit. In addition, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0017] As used herein, for ease of description, spatially relative terms such as "under," "below," "above," "above," "up," "upper," "lower," "left," "right," "vertical," "horizontal," "side," etc. may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features), as illustrated in the drawings. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected or coupled to the other element, or there may be intermediate elements.

[0018] The inventors of the present application have found that due to the mismatch in thermal expansion coefficients between the semiconductor chip, the packaging adhesive, the packaging substrate, and other structures of the semiconductor package, interlayer thermal stress and thermal deformation may occur inside the semiconductor package under the continuous heat load conditions generated by the semiconductor chip. The peeling stress and shear stress on the interface of the internal structure of the semiconductor package may cause delamination and warping of the packaging structure, and may even cause the failure of the semiconductor package. For example, in some cases, the solder balls on the four corners of the semiconductor package are easily broken when they are dropped or collided.

[0019] For packages using smaller solder balls, the above phenomenon may be less likely to occur. However, if smaller solder balls are used, it is not conducive to the heat dissipation of the semiconductor chip to the external space through the packaging structure. As the size of electronic products continues to shrink or more components are integrated, it becomes important to form a smaller semiconductor packaging structure with more functions. However, as the volume of semiconductor packages decreases and the power increases, the heat per unit volume of the chip increases dramatically. If the temperature is too high, it may also induce failure, breakdown, junction temperature failure, and metallization failure. When the semiconductor chip generates heat, most of the heat is transferred to the outside of the semiconductor package through the packaging structure. However, the packaging structure is usually made of low thermal conductivity materials such as epoxy resin and filler. Therefore, when the semiconductor chip generates a lot of heat due to long-term operation, the packaging structure may not be able to conduct the heat in time, causing the heat to be accumulated in the chip.

[0020] In order to solve at least one of the above problems, the inventors of the present application have proposed a multi-type solder ball array for interconnecting a semiconductor chip with a packaging substrate and / or a packaging substrate with an external device. For example, solder balls with a copper core or similar higher thermal conductivity material, as well as solder balls made of lower thermal conductivity solder (e.g., tin) can be used. In some cases, high thermal conductivity solder balls can be formed on the packaging substrate, which can establish a thermal conductive path with improved heat dissipation capability for the semiconductor package, thereby significantly reducing the risk of semiconductor package failure.

[0021] Figures 1 to 3 A semiconductor package 100 according to an embodiment of the present application is shown. Figure 1 is a cross-sectional view of the semiconductor package 100, Figure 2 is a front view of a package substrate of the semiconductor package 100, Figure 3 is a rear view of the package substrate of the semiconductor package 100 .

[0022] like Figure 1As shown, semiconductor package 100 includes a package substrate 125 having a front side 119 and a back side 129. Package substrate 125 may include one or more insulating layers, which may be interlaced with one or more conductive layers. It is understood that package substrate 125 may include any number of conductive layers and insulating layers interlaced with each other. The insulating layer may include ceramic, plastic, glass or other suitable insulating materials. The conductive layer and other internal conductive structures (such as through holes) form an interconnect 130 embedded in package substrate 125. For example, interconnect 130 may be made of copper.

[0023] The package substrate 125 also includes a group of front conductive patterns 110, such as contact pads, formed on the front side 119, and a group of back conductive patterns 120, such as contact pads, formed on the back side 129. The front and back conductive patterns may be end surfaces of a group of interconnects 130 embedded in the insulating layer of the package substrate 125, respectively, which are exposed from the front side 119 or the back side 129, respectively. The group of interconnects 130 may electrically couple the group of front conductive patterns 110 with the group of back conductive patterns 120, respectively. As described above, in some embodiments, the interconnects 130 may include conductive wiring or vias to guide signals through the insulating layer.

[0024] At least one electronic component 115 is mounted on the front side 119 of the packaging substrate 125. The electronic component can be in the form of a semiconductor chip or multiple semiconductor chips. In some embodiments, the at least one electronic component 115 may include one or more digital chips, analog chips, or mixed signal chips, such as application specific integrated circuit ("ASIC") chips, sensor chips, wireless and radio frequency (RF) chips, memory chips, logic chips, or voltage regulator chips. In some other embodiments, the at least one electronic component 115 may also include one or more passive electrical components, such as resistors, capacitors, inductors, etc. Figure 1 In the illustrated embodiment, the electronic component 115 is a semiconductor chip having a plurality of input / output ports, each of which needs to be electrically coupled to an external device to transmit signals or power.

[0025] The semiconductor package 100 further includes a group of front solder balls 210 and a group of back solder balls 220, which are respectively electrically connected to the group of front conductive patterns 110 and the group of back conductive patterns 120. The electronic component 115 is electrically connected to the group of front conductive patterns 110 through the group of front solder balls 210 to establish an electrical connection with the package substrate 125.

[0026] Specifically, the front and back solder balls 210 and 220 may be distributed on the package substrate 125 in the form of spherical shapes or similar structures. Figure 1It can be seen that because there is more space on the packaging substrate 125, especially when the interconnect 130 can provide support for the redistribution of wiring, the first spacing between two adjacent solder balls of the front solder balls 210 can be increased to the second spacing between two adjacent solder balls of the back solder balls 220. Accordingly, the size of the back solder balls 220 may be larger than the size of the front solder balls 210. In other words, the solder ball layout on the back side 129 is more expanded than the solder ball layout on the front side 119. The larger solder ball layout is conducive to better heat dissipation. In some embodiments, the number of solder balls in the front solder balls 210 may be equal to the number of solder balls in the back solder balls 220, such as Figures 1 to 3 In one variant, for example, Figure 4 and 5 In the embodiment shown, the number of solder balls in the front solder balls 410 and the number of solder balls in the back solder balls 420 may be different, for example, because two or more solder balls in one set may be coupled to one solder ball in another set.

[0027] The front solder balls 210 include at least two types of solder balls, namely, a plurality of first type solder balls 111 and a plurality of second type solder balls 112. Similarly, the back solder balls 220 include at least two types of solder balls, namely, a plurality of first type solder balls 121 and a plurality of second type solder balls 122. In the illustrated embodiment, the first type solder balls 111, 121 may include a copper core and a solder coating covering the outside of the copper core, while the second type solder balls 112, 122 may be made entirely of solder (e.g., tin). In some other embodiments, the first type solder balls 111, 121 may be made of other solders with better thermal conductivity. Compared with the second type solder balls 112, 122, the first type solder balls 111, 121 may have higher thermal conductivity and electrical conductivity, thereby achieving better heat dissipation and lower resistance. In some embodiments, the first type solder balls 111, 121 are preferably located in areas of the electronic component 115 that consume more power and generate more heat than other areas, because heat needs to be conducted through the first type solder balls 111, 121. In some other embodiments, the first type solder balls 111, 121 are preferably located in areas of the electronic component 115 that need better heat dissipation than other areas. For example, the first type solder balls 111, 121 are at least located in the central area of ​​the package substrate 125, which may have a longer heat dissipation path than other areas (e.g., peripheral areas) of the package substrate 125. In addition, as previously described, the first type solder balls 121 on the back of the package substrate 125 can further improve the thermal conductivity of the semiconductor package 100, especially for areas that need better heat dissipation.

[0028] While thermal conductivity may be a factor to consider when mounting multiple types of solder balls on the package substrate 125, other factors or characteristics may also be considered. In some embodiments, at least one of the groups of front solder balls 210 and the group of back solder balls 220 may further include one or more third type solder balls, which are at least partially made of a material having a smaller thermal expansion coefficient than the first type solder balls and the second type solder balls. For example, in Figure 1 In the embodiment shown in , each group of solder balls in the group of front solder balls 210 and the group of back solder balls 220 includes a plurality of third type solder balls 113, 123. The third type solder balls 113 and 123 each include a resin core coated with solder. This type of solder ball can provide mechanical support and compensate for mechanical stress within the semiconductor package 100, for example, due to thermal expansion, because the resin core can significantly compensate for the mechanical stress. In some embodiments, the third type solder balls are, for example, arranged in an area of ​​the package substrate 125 where the density of the interconnects 130 is higher than in other areas, because denser interconnects need to compensate for greater mechanical stress. For example, as Figure 2 and Figure 3 As shown, the third type solder balls 123 of the group of back solder balls 220 can be arranged around the first type solder balls 121 of the group of back solder balls 220. Correspondingly, the second type solder balls 122 can be arranged at the corners around the first type solder balls 121 and the third type solder balls 123. In one embodiment, the third type solder balls 113 of the group of front solder balls 210 are arranged at the corners of the electronic component 115 to compensate for the thermal expansion mismatch between the electronic component 115 and the packaging substrate 125. In addition, the third type solder balls 113 at the corners of the electronic component 115 can maintain an appropriate distance between the electronic component 115 and the packaging substrate 125 after the reflow process of the solder balls, thereby allowing the packaging material to pass through and avoiding the generation of voids or cavities in the sealant layer. In some embodiments, the third type solder balls may be located in an area below the electronic component 115, which may generate the greatest mechanical stress during the use of the semiconductor package 100. In addition, the second type solder balls 112 , 122 in the front or back solder balls may be formed at other locations of the package substrate 125 to implement, for example, a BGA structure.

[0029] exist Figures 1 to 3 In the embodiment shown in , each of the back solder balls 220 is coupled to at least one of the front solder balls 210 through at least one pair of front and back conductive patterns 110, 120 and interconnects 130. Figure 1In an embodiment, each first type solder ball 121 of the group of back solder balls 220 is aligned with one first type solder ball 111 of the group of front solder balls 210 in a direction perpendicular to the front or back side 119, 129 of the package substrate 125. Accordingly, the interconnection path 150 connecting each first type solder ball 121 of the group of back solder balls 220 with one first type solder ball 111 of the group of front solder balls 210 is substantially perpendicular to the package substrate 125. In this way, the interconnection path 150 connecting the first type solder ball 121 of the back solder balls 220 with the first type solder ball 111 of the front solder balls 210 has a shorter total lead length or through-hole length and preferably has a larger width than other interconnection paths 160 connecting the second type or third type solder ball of the group of back solder balls 220 with one solder ball of the front solder balls 210, or connecting the second type or third type solder ball of the group of front solder balls 210 with one solder ball of the back solder balls 220. The interconnection path 150 has correspondingly better thermal and electrical conductivity, which may be helpful for heat dissipation of the electronic component 115 that generates more heat during operation. It is understood that in some alternative embodiments, due to the routing of the interconnection 130 in the package substrate 125 or other considerations, the interconnection path 150 connecting each first type solder ball 121 of the back solder ball 220 and one first type solder ball 111 of the front solder ball 210 may not be perpendicular to the package substrate 125. Nevertheless, the use of the first type solder balls 111 and 121 still has better thermal conductivity on both sides of the package substrate 125.

[0030] The semiconductor package 100 may further include at least one sealant layer 116, which at least partially extends over the substrate 125 and covers the at least one electronic component 115. The sealant layer 116 may provide protection for the electronic component 115. In some embodiments, a shielding layer (not shown) may be further formed on the sealant layer 116 to achieve the purpose of electromagnetic interference shielding.

[0031] Figure 4 and Figure 5 FIG. 4 shows a semiconductor package 400 according to another embodiment of the present application. Figure 4 and Figure 5 As shown, three electronic components 415 are packaged in the semiconductor package 400. Specifically, the electronic component 415 includes a plurality of semiconductor chips, namely, a control chip, a logic circuit chip, and a power chip.

[0032] In this embodiment, a group of front solder balls 410 are mounted on the front side of a packaging substrate 425. The group of front solder balls 410 includes a plurality of first type solder balls 411 for electrical and thermal conduction below the logic circuit chip below the central area of ​​the packaging substrate 425, which are respectively connected to first type solder balls 421 in a group of back solder balls 420 mounted on the back side of the packaging substrate 425. The group of front solder balls 410 also includes a plurality of first type solder balls 411 below the power chip for large current transmission, which are respectively connected to second type and third type solder balls 422 and 423 in the back solder balls 420. The group of front solder balls 410 also includes a plurality of second type solder balls 412 below the control chip for weak current transmission, which are respectively connected to second type and third type solder balls 422 and 423 in the group of back solder balls 420. Figure 4 As shown, the interconnection path 450 connecting each first type solder ball 421 of the back solder balls 420 with the corresponding first type solder ball 411 of the front solder balls 410 is substantially perpendicular to the front side 419 or the back side 429 of the package substrate 425, and thus may be shorter than another interconnection path 460 connecting the second type or third type solder balls 422, 423 of the back solder balls 420 with the solder balls of the front solder balls 410. Figure 5 As shown, the first type solder balls 421 of the back solder balls 420 are surrounded by the second type solder balls 422 and the third type solder balls 423 of the back solder balls 420, and these solder balls are distributed at intervals. The second type solder balls 422 can be formed at other positions of the package substrate 425 to realize a BGA structure.

[0033] In some embodiments, the electronic components packaged in the semiconductor package may be other components, such as a chiplet or other similar smaller packages.

[0034] Figure 6 and Figure 7 FIG. 6 shows a semiconductor package 600 according to another embodiment of the present application. Figure 6 and Figure 7 As shown, the electronic component 615 is mounted in the form of a chiplet on the front side of the package substrate 625 of the semiconductor package 600. The chiplet may include multiple modules as shown in the figure, such as a system chip (SoC), a high bandwidth memory (HBM), and a CPU module.

[0035] and Figure 4 and Figure 5Similar to the illustrated embodiment, different types of solder balls may be installed on the front and back sides of the package substrate 625 according to different modules of the electronic component 615. Specifically, a group of front solder balls 610 are installed on the front side of the package substrate 625. The front solder balls 610 include a plurality of first type solder balls 611 below the CPU in the central area of ​​the electronic component 615 (Chiplet), which are respectively connected to first type solder balls 621 belonging to a group of back solder balls 620 to provide better thermal conductivity and electrical conductivity. The first type solder balls 611 and 621 may include a copper core and a solder coated on the outside of the copper core. Other types of solder balls may be installed on the package substrate 625, such as a second type solder ball made of tin, and a third type solder ball including a resin core and a solder coated on the outside of the resin core, in a manner similar to that of the embodiment shown in FIG. Figures 1 to 3 The semiconductor package 100 is shown and will not be described in detail herein.

[0036] Although the semiconductor package of the present application is described in conjunction with the corresponding drawings, it will be understood by those skilled in the art that modifications and adaptations may be made to the semiconductor package without departing from the scope of the present invention.

[0037] The discussion herein includes many illustrative figures showing various parts of semiconductor packages. For clarity of illustration, these figures do not show all aspects of each example semiconductor package. Any example semiconductor package provided herein may share any or all features with any or all other semiconductor packages provided herein.

[0038] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. In addition, other embodiments will be apparent to those skilled in the art by considering the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that the present application and the examples herein be considered merely exemplary, with the true scope and spirit of the invention being indicated by the list of the appended exemplary claims.

Claims

1. A semiconductor package, characterized in that: include: A packaging substrate having a front side and a back side, wherein the packaging substrate comprises: a set of front conductive patterns formed on the front surface; a set of back-side conductive patterns formed on the back side; and a set of interconnect structures electrically coupling the set of front conductive patterns and the set of back conductive patterns, respectively; at least one electronic component mounted on the front side of the package substrate and electrically coupled to the set of front side conductive patterns via a set of front side solder balls; a group of back solder balls, which are electrically connected to the group of back conductive patterns respectively; wherein the group of front solder balls includes one or more first type solder balls and one or more second type solder balls, and the group of back solder balls includes one or more first type solder balls and one or more second type solder balls; and The first type of solder balls in the group of front solder balls are electrically coupled to the first type of solder balls in the group of back solder balls.

2. The semiconductor package according to claim 1, wherein: The first type of solder balls have higher thermal and electrical conductivity than the second type of solder balls.

3. The semiconductor package according to claim 2, wherein: The first type solder ball includes a metal core and solder covering the outside of the metal core.

4. The semiconductor package according to claim 1, wherein: When viewed from a direction perpendicular to the front surface of the packaging substrate, each of the first type solder balls in the group of back solder balls is vertically aligned with one of the first type solder balls in the group of front solder balls.

5. The semiconductor package according to claim 4, wherein: Each first type solder ball in the group of backside solder balls is electrically coupled to one first type solder ball in the group of frontside solder balls through an interconnection path substantially perpendicular to the package substrate.

6. The semiconductor package according to claim 1, wherein: Each first type solder ball in the group of back solder balls is electrically coupled to a first type solder ball in the group of front solder balls through an interconnection path having a length equal to or shorter than other interconnection paths, wherein the other interconnection paths electrically couple a second type solder ball in the group of front solder balls to a solder ball in the group of back solder balls, or electrically couple a second type solder ball in the group of back solder balls to a solder ball in the group of front solder balls, respectively.

7. The semiconductor package according to claim 1, wherein: Each first type solder ball in the group of back solder balls is electrically coupled to a first type solder ball in the group of front solder balls through an interconnection path with electrical conductivity and thermal conductivity equal to or higher than other interconnection paths, wherein the other interconnection paths electrically couple a second type solder ball in the group of front solder balls to a solder ball in the group of back solder balls, or electrically couple a second type solder ball in the group of back solder balls to a solder ball in the group of front solder balls, respectively.

8. The semiconductor package according to claim 1, wherein: The group of front side solder balls further includes one or more third type solder balls having a thermal expansion coefficient smaller than that of the first type solder balls and the second type solder balls.

9. The semiconductor package according to claim 8, wherein: The one or more third type solder balls in the group of front side solder balls are located outside the one or more second type solder balls in the group of front side solder balls.

10. The semiconductor package according to claim 8, wherein: The one or more third type solder balls are located in a region below the electronic component where maximum mechanical stress is generated during use of the semiconductor package.

11. The semiconductor package according to claim 1, wherein: The set of backside solder balls also includes one or more third type solder balls having a smaller thermal expansion coefficient than the first type solder balls and the second type solder balls.

12. The semiconductor package according to claim 11, wherein: The one or more third type solder balls in the group of back side solder balls are located outside the one or more first type solder balls in the group of back side solder balls.

13. The semiconductor package according to claim 1, wherein: The one or more first type solder balls in the group of front side solder balls are located in an area below the electronic component that generates more power consumption than other areas of the electronic component.

14. The semiconductor package according to claim 1, wherein: The electronic component is a semiconductor chip.

15. The semiconductor package according to claim 1, wherein: The electronic component is a semiconductor package including at least two semiconductor chips.

16. The semiconductor package according to claim 15, wherein: The semiconductor package is a chiplet package.

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