Semiconductor package with multiple types of conductive elements

Abstract

The invention discloses a semiconductor package. The semiconductor package includes: a package substrate having a front surface and a back surface, the package substrate including: a plurality of groups of front conductive patterns formed on the front surface; the plurality of groups of interconnection structures are electrically coupled with the plurality of groups of front conductive patterns respectively; a plurality of electronic elements mounted on the front surface of the package substrate and electrically coupled to the plurality of groups of front conductive patterns through a plurality of groups of front conductive elements, respectively; the plurality of groups of conductive elements at least comprise a group of first type of conductive elements and a group of second type of conductive elements, the group of first type of conductive elements is connected with a first electronic element in the plurality of electronic elements, and the group of second type of conductive elements is connected with a second electronic element in the plurality of electronic elements; and the thermal conductivity of the first type conductive element is higher than that of the second type conductive element, and the power consumption of the first electronic element is higher than that of the second electronic element.

Description

Technical Field

[0001] The present application relates generally to semiconductor technology and, more particularly, to semiconductor packages having multiple types of conductive elements. Background Art

[0002] The interconnect wires inside a semiconductor chip are very thin, with a width on the order of a few micrometers or less. The formation of such wires makes it possible to manufacture semiconductor chips containing millions or more interconnected components. However, at some point, a connection needs to be made between the chip and the outside world, which makes it difficult to accommodate such small wire tolerances.

[0003] In order to connect semiconductor chips to external devices or systems, printed circuit boards (PCBs), interposers or other similar substrates are widely used to mount the chips, thereby forming semiconductor packages with larger dimensions. The leads on the PCB are much thicker than the leads on the chip, usually measured in millimeters. It is impractical to connect the chip leads directly to the PCB leads. Therefore, an intermediate structure is needed that can handle this range of lead width variations.

[0004] One example of such a structure is a ball grid array (BGA). BGA packaging technology is a surface mount technology used for integrated circuits, often used to permanently fix devices such as microprocessors. The BGA package is an array on the bottom of the package substrate where solder balls are used as input / output (I / O) terminals of the circuit and connected to the PCB.

[0005] Solder balls have the functions of signal conduction, electrical connection and heat conduction. In existing BGA packages, the solder balls on the package substrate are usually the same. The larger the solder ball, the stronger the heat conduction ability. However, at the same time, the larger the solder ball, the larger the substrate area occupied, which conflicts with the high density and high pin output of BGA.

[0006] Therefore, it is necessary to further improve semiconductor packaging. Summary of the invention

[0007] An object of the present application is to provide a semiconductor package structure with improved heat dissipation efficiency.

[0008] According to one aspect of the present application, a semiconductor package is provided. The semiconductor package comprises: a package substrate having a front side and a back side, wherein the package substrate comprises: a plurality of groups of front conductive patterns formed on the front side; and a plurality of groups of interconnect structures electrically coupled to the plurality of groups of front conductive patterns respectively; a plurality of electronic components mounted on the front side of the package substrate and electrically coupled to the plurality of groups of front conductive patterns respectively through a plurality of groups of front conductive elements; wherein the plurality of groups of front conductive elements comprises at least a group of first type conductive elements and a group of second type conductive elements, wherein the first type conductive elements are connected to a first electronic component among the plurality of electronic components, and the second type conductive elements are connected to a second electronic component among the plurality of electronic components; and wherein the thermal conductivity of the first type conductive elements is higher than that of the second type conductive elements, and the power consumption of the first electronic components is higher than that of the second electronic components.

[0009] According to another aspect of the present application, a semiconductor package is also provided. The semiconductor package comprises: a package substrate having a front side and a back side, wherein the package substrate comprises: a plurality of front conductive patterns formed on the front side; and a plurality of interconnect structures electrically coupled to the plurality of front conductive patterns respectively; an electronic component package mounted on the front side of the package substrate and electrically coupled to the plurality of front conductive patterns respectively through a plurality of front conductive elements; wherein the electronic component package comprises a plurality of circuit function parts, wherein the plurality of front conductive elements at least comprise a first type conductive element and a second type conductive element, wherein the first type conductive element is connected to a first circuit function part among the plurality of circuit function parts, and the second type conductive element is connected to a second circuit function part among the plurality of circuit function parts; and wherein the thermal conductivity of the first type conductive element is higher than that of the second type conductive element, and the power consumption of the first circuit function part is higher than that of the second circuit function part.

[0010] It should be understood that both the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. In addition, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings cited herein form part of the specification. The features shown in the drawings illustrate only some embodiments of the present application, not all embodiments of the present application, unless the detailed description explicitly indicates otherwise, and the reader of this specification should not be implied to the contrary.

[0012] Figures 1 to 3A semiconductor package according to an embodiment of the present application is shown. Figure 1 is a cross-sectional view of the package. Figure 2 is a front view of the packaging substrate, Figure 3 is a back view of the packaging substrate.

[0013] Figure 4 and Figure 5 A semiconductor package according to another embodiment of the present application is shown. Figure 4 is a cross-sectional view of the packaging substrate. Figure 5 is a back view of the packaging substrate.

[0014] Figure 6 and Figure 7 A semiconductor package according to another embodiment of the present application is shown. Figure 6 is a cross-sectional view of the packaging substrate. Figure 7 is a back view of the packaging substrate.

[0015] Figure 8 A semiconductor package according to another embodiment of the present application is shown.

[0016] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0017] The following detailed description of the exemplary embodiments of the present application refers to the drawings that form a part of this specification. The drawings illustrate specific exemplary embodiments in which the present application can be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable a person skilled in the art to practice the present application. A person skilled in the art may further utilize other embodiments of the present application and make logical, mechanical and other changes without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret this specification in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0018] In this application, the use of the singular includes the plural unless expressly stated otherwise. In this application, the use of "or" means "and / or" unless otherwise stated. Furthermore, the use of the term "comprising" is not limiting. In addition, terms such as "element" or "component" encompass elements and components comprising one unit and elements and components comprising more than one subunit unless specifically stated otherwise. In addition, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0019] As used herein, for ease of description, spatially relative terms such as "under," "below," "above," "above," "up," "upper," "lower," "left," "right," "vertical," "horizontal," "side," etc. may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features), as illustrated in the drawings. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected or coupled to the other element, or there may be intermediate elements.

[0020] The inventors of the present application have found that due to the increase in integration, many semiconductor packages will install multiple semiconductor chips on the same substrate, or install electronic component packages integrating multiple circuit functional parts on the same substrate. These different semiconductor chips or circuit functional parts often have different power consumption, which results in different heat dissipation capabilities required. When semiconductor chips and packages generate heat, most of the heat is transferred to the outside of the semiconductor package through the packaging substrate in which they are located, but the packaging structure is usually made of low thermal conductivity materials such as epoxy resin and filler. Therefore, when the semiconductor chip generates a large amount of heat due to long-term operation, the packaging structure may not be able to conduct the heat in time, resulting in heat accumulation in the chip.

[0021] In order to solve at least one of the above problems, the inventors of the present application have proposed an array of multiple types of conductive elements for interconnecting electronic components or electronic component packages with a package substrate. For example, solder balls with a copper core or similar higher thermal conductivity material, as well as solder balls made of lower thermal conductivity solder (such as tin) can be used. These high thermal conductivity conductive elements can establish a thermal path with improved heat dissipation capabilities for the semiconductor package, thereby significantly reducing the risk of failure of the semiconductor package due to heat accumulation.

[0022] Figures 1 to 3 A semiconductor package 100 according to an embodiment of the present application is shown. Figure 1 is a cross-sectional view of the semiconductor package 100, Figure 2 is a front view of a package substrate of the semiconductor package 100, Figure 3 is a rear view of the package substrate of the semiconductor package 100 .

[0023] like Figure 1As shown, the semiconductor package 100 includes a package substrate 125 having a front side 119 and a back side 129. The package substrate 125 may include one or more insulating layers, which may be interlaced with one or more conductive layers. It is understood that the package substrate 125 may include any number of conductive layers and insulating layers interlaced with each other. The insulating layer may include ceramic, plastic, glass or other suitable insulating materials. The conductive layer and other internal conductive structures (such as through holes) form an interconnect structure 130 embedded in the package substrate 125. For example, the interconnect structure 130 may be made of copper.

[0024] The package substrate 125 also includes a group of front conductive patterns 110, such as contact pads, formed on the front side 119, and a group of back conductive patterns 120, such as contact pads, formed on the back side 129. The front and back conductive patterns may be end surfaces of a group of interconnect structures 130 embedded in the insulating layer of the package substrate 125, respectively, which are exposed from the front side 119 or the back side 129, respectively. The group of interconnect structures 130 may electrically couple the group of front conductive patterns 110 with the group of back conductive patterns 120, respectively. As described above, in some embodiments, the interconnect structures 130 may include conductive wiring or vias to guide signals through the insulating layer.

[0025] At least one electronic component 115 is mounted on the front side 119 of the packaging substrate 125. The electronic component can be in the form of a semiconductor chip or multiple semiconductor chips. In some embodiments, the at least one electronic component 115 may include one or more digital chips, analog chips, or mixed signal chips, such as application specific integrated circuit ("ASIC") chips, sensor chips, wireless and radio frequency (RF) chips, memory chips, logic chips, or voltage regulator chips. In some other embodiments, the at least one electronic component 115 may also include one or more passive electrical components, such as resistors, capacitors, inductors, etc. Figure 1 In the illustrated embodiment, the electronic component 115 is a semiconductor chip having a plurality of input / output ports, each of which needs to be electrically coupled to an external device to transmit signals or power.

[0026] The semiconductor package 100 further includes a group of front solder balls 210 and a group of back solder balls 220. As front conductive elements and back conductive elements, the front solder balls 210 and the back solder balls 220 are electrically connected to the group of front conductive patterns 110 and the group of back conductive patterns 120, respectively. The electronic component 115 is electrically connected to the group of front conductive patterns 110 through the group of front solder balls 210 to establish an electrical connection with the package substrate 125.

[0027] Specifically, the front and back solder balls 210 and 220 may be distributed on the package substrate 125 in the form of spherical shapes or similar structures. Figure 1It can be seen that because there is more space on the packaging substrate 125, especially when the interconnect structure 130 can provide support for the redistribution of wiring, the first spacing between two adjacent solder balls of the front solder balls 210 can be increased to the second spacing between two adjacent solder balls of the back solder balls 220. Accordingly, the size of the back solder balls 220 may be larger than the size of the front solder balls 210. In other words, the solder ball layout on the back side 129 is more expanded than the solder ball layout on the front side 119. The larger solder ball layout is conducive to better heat dissipation. In some embodiments, the number of solder balls in the front solder balls 210 may be equal to the number of solder balls in the back solder balls 220, such as Figures 1 to 3 In one variant, for example, Figure 4 and 5 In the embodiment shown in FIG. 5 , the number of solder balls in the front solder balls 410 and the number of solder balls in the back solder balls 420 may be different, for example, because two or more solder balls in the set may be coupled to another solder ball.

[0028] The front solder balls 210 include at least two types of solder balls, namely, a plurality of first type solder balls 111 and a plurality of second type solder balls 112. Similarly, the back solder balls 220 include at least two types of solder balls, namely, a plurality of first type solder balls 121 and a plurality of second type solder balls 122. In the illustrated embodiment, the first type solder balls 111, 121 may include a copper core and a solder coating covering the outside of the copper core, while the second type solder balls 112, 122 may be made entirely of solder (e.g., tin). In some other embodiments, the first type solder balls 111, 121 may be made of other solders with better thermal conductivity. Compared with the second type solder balls 112, 122, the first type solder balls 111, 121 may have higher thermal conductivity and electrical conductivity, thereby achieving better thermal conductivity and lower resistance. In some embodiments, the first type solder balls 111 and 121 are preferably located in the area of ​​the electronic component 115 that consumes more power and generates more heat than other areas, because heat needs to be conducted through the first type solder balls 111 and 121. In some embodiments, the electronic component 115 is a semiconductor chip, which may have different circuit function parts, such as a logic circuit part, a power circuit part, a control circuit part, or a storage circuit part. Among them, because complex operations such as logical operations need to be performed, the logic circuit part usually has a higher power consumption; and the power circuit part usually has a relatively high power consumption due to power supply requirements; while the control circuit or storage circuit has a relatively low power consumption. Therefore, the first type solder balls 111 and / or 121 can be set in the area of ​​the electronic component 115 corresponding to the logic circuit part and the power circuit part, and the second type solder balls 112 and / or 122 can be set in the area of ​​the electronic component 115 corresponding to the control circuit or the storage circuit. In some other embodiments, the first type solder balls 111 and 121 are preferably located in the area of ​​the electronic component 115 that needs better heat dissipation than other areas. For example, the first type solder balls 111, 121 are at least located in the central region of the package substrate 125, and the central region may have a longer heat dissipation path than other regions (e.g., peripheral regions) of the package substrate 125. In addition, as mentioned above, the first type solder balls 121 on the back side of the package substrate 125 can further improve the thermal conductivity of the semiconductor package 100, especially for regions that require better heat dissipation.

[0029] While thermal conductivity may be a factor to consider when mounting multiple types of solder balls on the package substrate 125, other factors or characteristics may also be considered. In some embodiments, at least one of the group of front solder balls 210 and the group of back solder balls 220 may further include one or more third type solder balls that are at least partially made of a material with a smaller thermal expansion coefficient than the first type solder balls and the second type solder balls, or at least close to the base material (e.g., resin) of the package substrate 125. For example, in Figure 1In the embodiment shown in , each group of solder balls in the group of front solder balls 210 and the group of back solder balls 220 includes a plurality of third type solder balls 113, 123. The third type solder balls 113 and 123 each include a resin core coated with solder. This type of solder ball can provide mechanical support and compensate for mechanical stress generated, for example, due to thermal expansion within the semiconductor package 100, because the resin core can significantly compensate for the mechanical stress. In some embodiments, the third type solder balls are, for example, arranged in an area of ​​the package substrate 125 where the density of the interconnect structure 130 is higher than in other areas, because a denser interconnect structure may generate greater mechanical stress that needs to be compensated. For example, as Figure 2 and Figure 3 As shown, the third type solder balls 123 of the group of back solder balls 220 can be arranged around the first type solder balls 121 of the group of back solder balls 220. Correspondingly, the second type solder balls 122 can be arranged at the corners around the first type solder balls 121 and the third type solder balls 123. In other embodiments, the third type solder balls can also be arranged in the area of ​​the package substrate 125 that connects the circuit functional parts with lower power consumption. In one embodiment, the third type solder balls 113 of the group of front solder balls 210 are arranged at the corners of the electronic component 115 to compensate for the thermal expansion mismatch between the electronic component 115 and the package substrate 125. In addition, the third type solder balls 113 at the corners of the electronic component 115 can maintain an appropriate distance between the electronic component 115 and the package substrate 125 after the reflow process of the solder balls, thereby allowing the packaging material to pass through and avoiding the generation of voids or cavities in the sealant layer. In some embodiments, the third type solder balls may be located in an area below the electronic component 115, which may generate the greatest mechanical stress during the use of the semiconductor package 100. In addition, the second type solder balls 112 , 122 in the front or back solder balls may be formed at other locations of the package substrate 125 to implement, for example, a BGA structure.

[0030] In some preferred embodiments, for example Figures 1 to 3 In the embodiment shown in , each of the back solder balls 220 is coupled to at least one of the front solder balls 210 through at least one pair of front and back conductive patterns 110, 120 and an interconnect structure 130. Figure 1In an embodiment of the present invention, each first type solder ball 121 of the group of back solder balls 220 is aligned with one first type solder ball 111 of the group of front solder balls 210 in a direction perpendicular to the front or back surface 119, 129 of the package substrate 125. Accordingly, the interconnection path 150 connecting each first type solder ball 121 of the group of back solder balls 220 with one first type solder ball 111 of the group of front solder balls 210 is substantially perpendicular to the package substrate 125. In this way, the interconnection path 150 connecting the first type solder ball 121 of the back solder balls 220 with the first type solder ball 111 of the front solder balls 210 has a shorter total lead length or through-hole length and preferably has a larger width than other interconnection paths 160 connecting the second type or third type solder ball of the group of back solder balls 220 with one solder ball of the front solder balls 210, or connecting the second type or third type solder ball of the group of front solder balls 210 with one solder ball of the back solder balls 220. The interconnection path 150 has correspondingly better thermal and electrical conductivity, which may be helpful for heat dissipation in areas of the electronic component 115 that generate more heat during operation. It is understood that in some alternative embodiments, due to the routing of the interconnect structure 130 in the packaging substrate 125 or other considerations, the interconnection path 150 connecting each first type solder ball 121 of the back solder ball 220 with one first type solder ball 111 of the front solder ball 210 may not be perpendicular to the packaging substrate 125. Nevertheless, the use of the first type solder balls 111 and 121 still has better thermal conductivity on both sides of the packaging substrate 125.

[0031] The semiconductor package 100 may further include at least one sealant layer 116, which at least partially extends over the substrate 125 and covers the at least one electronic component 115. The sealant layer 116 may provide protection for the electronic component 115. In some embodiments, a shielding layer (not shown) may be further formed on the sealant layer 116 to achieve the purpose of electromagnetic interference shielding.

[0032] Figure 4 and Figure 5 FIG. 4 shows a semiconductor package 400 according to another embodiment of the present application. Figure 4 and Figure 5 As shown, three electronic components 415 are packaged in the semiconductor package 400. Specifically, the electronic components 415 include a plurality of electronic components, which are, for example, semiconductor chips, such as a control chip, a logic circuit chip, and a power chip.

[0033] In this embodiment, a group of front solder balls 410 is mounted on the front side of a package substrate 425. The group of front solder balls 410 includes a plurality of first type solder balls 411 for electrical and thermal conduction under the logic circuit chip under the central area of ​​the package substrate 425, which are respectively connected to the first type solder balls 421 in a group of back solder balls 420 mounted on the back side of the package substrate 425. The group of front solder balls 410 also includes a plurality of first type solder balls 411 under the power chip for large current transmission, which are respectively connected to the second type and third type solder balls 422 and 423 in the back solder balls 420. The group of front solder balls 410 also includes a plurality of second type solder balls 412 under the control chip for weak current transmission, which are respectively connected to the second type and third type solder balls 422 and 423 in the group of back solder balls 420. It can be understood that compared with the control circuit chip connected to the second type solder ball 412, the logic circuit chip and the power circuit chip connected to the first type solder ball 411 have significantly higher power consumption. Therefore, the first type solder ball 411 with higher thermal conductivity can better assist the logic circuit chip and the power circuit chip to dissipate heat through the packaging substrate 425.

[0034] like Figure 4 As shown, the interconnection path 450 connecting each first type solder ball 421 in the back solder balls 420 with the corresponding first type solder ball 411 in the front solder balls 410 is substantially perpendicular to the front side 419 or the back side 429 of the package substrate 425, and thus may be shorter than another interconnection path 460 connecting the second type or third type solder balls 422, 423 in the back solder balls 420 with the solder balls in the front solder balls 410. Figure 5 As shown, the first type solder balls 421 in the back solder balls 420 are surrounded by the second type solder balls 422 and the third type solder balls 423 in the back solder balls 420, and these solder balls are distributed at intervals. The second type solder balls 422 can be formed at other positions of the package substrate 425 to realize a BGA structure.

[0035] In some embodiments, the electronic components packaged in the semiconductor package may be other components, such as a chiplet or other similar smaller packages.

[0036] Figure 6 and Figure 7 FIG. 6 shows a semiconductor package 600 according to another embodiment of the present application. Figure 6 and Figure 7As shown, the electronic component 615 is mounted on the front side of the package substrate 625 of the semiconductor package 600 in the form of a chiplet. The chiplet may include a plurality of circuit function modules as shown in the figure, such as a system chip (SoC), a high bandwidth memory (HBM), and a central processing unit (CPU) module. These circuit function modules are packaged in the semiconductor package 600 as respective circuit function parts of the semiconductor package 600.

[0037] and Figure 4 and Figure 5 Similar to the illustrated embodiment, different types of conductive elements may be mounted on the front and back sides of the packaging substrate 625, depending on which circuit functional portion of the electronic component 615 is connected to the conductive element. For example, a group of front conductive elements, such as solder balls 610, are mounted on the front side of the packaging substrate 625. The front solder balls 610 include a plurality of first type solder balls 611 below the logic circuit functional area below the central area of ​​the packaging substrate 625, which are respectively connected to first type solder balls 621 belonging to a group of back solder balls 620 to provide better thermal conductivity and electrical conductivity. The first type solder balls 611 and 621 may include a copper core and a solder coated on the outside of the copper core. Other types of solder balls may be mounted on the packaging substrate 625, such as a second type solder ball 622 made of tin, and a third type solder ball 623 including a resin core and a solder coated on the outside of the resin core, in a manner similar to that of the embodiment shown in FIG. Figures 1 to 3 The semiconductor package 100 is shown and will not be described in detail herein.

[0038] Figure 8 FIG. 8 shows a semiconductor package 800 according to another embodiment of the present application. Figure 8 As shown, three electronic components 815 are packaged in the same semiconductor package 800. Specifically, the three electronic components 815 include a logic circuit chip, a control chip, and a power chip. In this embodiment, the front conductive element 810 is mounted on the front side 819 of the package substrate 825, and is used to mount the electronic components 815 on the front side 819 respectively; the back conductive element 820 is mounted on the back side of the package substrate 825, and is used to attach the package substrate 825 to other substrates or devices.

[0039] In some examples, the front conductive element 810 can use multiple different types of elements to connect different electronic components 815 to the package substrate 825, specifically, to the respective interconnection paths 850 in the package substrate 825. Specifically, the front conductive element 810 includes a first type solder ball 811 under the power chip, a second type solder ball 812 under the control chip, and a plurality of conductive pillars 813 under the logic circuit chip in the central area of ​​the package substrate 825. It can be seen that compared with Figure 4 and Figure 5In the semiconductor package 400 shown, the front conductive element 810 includes more types of conductive elements, especially for the logic circuit chip, a conductive column 813 is specially provided to connect it to the package substrate 825. The conductive column 813 can be, for example, a copper column or a similar conductive structure made of a high thermal conductivity material. The conductive column 813 is used because the input / output pin density of the logic circuit chip is high and the heat generated during operation is relatively large. The use of the conductive column 813 to connect the chip pin and the package substrate can enhance the bonding strength between the pin and the package substrate 825 by strengthening the welding process, and avoid the breakage of the solder joint caused by external force.

[0040] Understandably, similar to Figure 4 and Figure 5 The semiconductor package 400 shown in FIG. Figure 8 In the embodiment, the plurality of first-type solder balls 811 under the power chip can be used for large current transmission, and can be solder balls including a copper core and a solder coating covering the outside of the copper core, or other solder balls with better thermal conductivity and electrical conductivity; while the second-type solder balls 812 can be made entirely of solder (such as tin), or a resin core or a similar structure can be further provided inside the solder, or other solder balls with lower thermal conductivity and electrical conductivity than the first-type solder balls 811. In particular, for solder balls using a resin core or a similar structure, the reduction in the amount of metal can reduce the thermal expansion coefficient of the solder balls, thereby reducing the shear stress generated under temperature changes, and avoiding the breakage of the solder joints of the solder balls due to excessive shear stress.

[0041] For the back conductive element 820, it can be similar to Figure 4 and Figure 5 Back side solder balls 420 are shown, or the same type of solder balls may be used.

[0042] It can be seen that by connecting different types of electronic components 815 through a plurality of different types of conductive elements 810, especially according to the heat dissipation requirements of different types of chips, this can satisfy the electronic components 815 to achieve better heat dissipation, thereby improving the reliability of the entire semiconductor package. Figure 8 In the figure, a plurality of electronic components 815 are shown, and different types of conductive elements are used to connect these electronic components 815 to the package substrate. However, in some other embodiments, especially for larger electronic components (such as Figure 6In the chiplet shown in the figure, different regions inside it may have different functions, and these functions make these regions have different heat dissipation requirements. Similarly, for regions with higher heat dissipation requirements (such as logic circuit functional regions), conductive elements with higher thermal conductivity and electrical conductivity can be used, while for regions with lower heat dissipation requirements (such as storage functional regions), conductive elements with lower thermal conductivity and electrical conductivity can be used.

[0043] Although the semiconductor package of the present application is described in conjunction with the corresponding drawings, it will be understood by those skilled in the art that modifications and adaptations may be made to the semiconductor package without departing from the scope of the present invention.

[0044] The discussion herein includes many illustrative figures showing various parts of semiconductor packages. For clarity of illustration, these figures do not show all aspects of each example semiconductor package. Any example semiconductor package provided herein may share any or all features with any or all other semiconductor packages provided herein.

[0045] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. In addition, other embodiments will be apparent to those skilled in the art by considering the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that the present application and the examples herein be considered merely exemplary, with the true scope and spirit of the invention being indicated by the list of the appended exemplary claims.

Claims

1. A semiconductor package, characterized in that: include: A packaging substrate having a front side and a back side, wherein the packaging substrate comprises: A plurality of front conductive patterns formed on the front surface; and a plurality of groups of interconnect structures, which are electrically coupled to the plurality of groups of front conductive patterns respectively; A plurality of electronic components are mounted on the front surface of the packaging substrate and are electrically coupled to the plurality of front conductive patterns through a plurality of front conductive elements; The plurality of groups of front conductive elements at least include a group of first-type conductive elements and a group of second-type conductive elements, the first-type conductive elements are connected to a first electronic element among the plurality of electronic elements, and the second-type conductive elements are connected to a second electronic element among the plurality of electronic elements; and The thermal conductivity of the first type conductive element is higher than that of the second type conductive element, and the power consumption of the first electronic element is higher than that of the second electronic element.

2. The semiconductor package according to claim 1, wherein: The first type conductive element includes a conductive copper pillar, or includes a conductive solder ball having a copper core and solder covering the outside of the copper core.

3. The semiconductor package according to claim 2, wherein: The second type conductive element includes a copper-free conductive solder ball.

4. The semiconductor package according to claim 3, wherein: The second type conductive element includes a pure tin solder ball, or a conductive solder ball having a resin core and solder coated outside the resin core.

5. The semiconductor package according to claim 1, wherein: The first electronic component includes a logic circuit electronic component or a power circuit electronic component, and the second electronic component includes a control circuit electronic component.

6. The semiconductor package according to claim 1, wherein: The packaging substrate also includes multiple groups of back-side conductive patterns, which are formed on the back side and are electrically coupled to the multiple groups of front-side conductive patterns through the multiple groups of interconnection structures; the semiconductor package also includes multiple groups of back-side conductive elements, which are respectively connected to the multiple groups of back-side conductive patterns.

7. The semiconductor package according to claim 6, wherein: The plurality of groups of back-side conductive elements include at least a plurality of groups of second-type conductive elements.

8. The semiconductor package according to claim 7, wherein: The plurality of groups of back-side conductive elements at least include a group of first-type conductive elements and a group of second-type conductive elements.

9. A semiconductor package, characterized in that: include: A packaging substrate having a front side and a back side, wherein the packaging substrate comprises: A plurality of front conductive patterns formed on the front surface; and a plurality of groups of interconnect structures, which are electrically coupled to the plurality of groups of front conductive patterns respectively; An electronic component mounted on the front surface of the packaging substrate and electrically coupled to the plurality of front conductive patterns through a plurality of front conductive elements; The electronic component includes a plurality of circuit function parts, the plurality of groups of front conductive elements include at least one group of first type conductive elements and one group of second type conductive elements, the first type conductive elements are connected to a first circuit function part among the plurality of circuit function parts, and the second type conductive elements are connected to a second circuit function part among the plurality of circuit function parts; and The thermal conductivity of the first type conductive element is higher than that of the second type conductive element, and the power consumption of the first circuit functional part is higher than that of the second circuit functional part.

10. The semiconductor package according to claim 9, wherein: The first type conductive element includes a conductive copper pillar, or includes a conductive solder ball having a copper core and solder covering the outside of the copper core.

11. The semiconductor package according to claim 10, wherein: The second type conductive element includes a copper-free conductive solder ball.

12. The semiconductor package according to claim 11, wherein: The second type conductive element includes a pure tin solder ball and a conductive solder ball having a resin core and solder coated outside the resin core.

13. The semiconductor package according to claim 9, wherein: The first circuit functional portion includes a logic circuit or a power supply circuit, and the second circuit functional portion includes a control circuit.

14. The semiconductor package according to claim 9, wherein: The packaging substrate also includes multiple groups of back-side conductive patterns, which are formed on the back side and are electrically coupled to the multiple groups of front-side conductive patterns through the multiple groups of interconnection structures; the semiconductor package also includes multiple groups of back-side conductive elements, which are respectively connected to the multiple groups of back-side conductive patterns.

15. The semiconductor package according to claim 14, wherein: The plurality of groups of back-side conductive elements include at least a plurality of groups of second-type conductive elements.

16. The semiconductor package according to claim 15, wherein: The plurality of groups of back-side conductive elements at least include a group of first-type conductive elements and a group of second-type conductive elements.

17. The semiconductor package according to claim 9, wherein: The electronic component is a semiconductor chip or a semiconductor package.

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