Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package includes a first semiconductor chip, the first semiconductor chip including: a first semiconductor substrate having a first surface and a second surface opposite to each other; the circuit layer is located on the first surface; the first interconnection layer is positioned on the circuit layer; a second interconnection layer, wherein the second interconnection layer is located on the second surface; a through via, wherein the through via extends from the second surface into the first semiconductor substrate; and a capacitor extending from the second surface toward the first surface. The capacitor is spaced apart from the through via in a first direction parallel to the first surface of the first semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package. Background Art

[0002] Semiconductor packages are configured to facilitate the use of integrated circuit chips in electronic products. For example, a semiconductor package may include a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, many studies are being conducted to improve the reliability of semiconductor packages and reduce the size of semiconductor packages. Summary of the invention

[0003] One or more example embodiments provide a highly reliable semiconductor package configured to reduce parasitic inductance and resistance between a circuit layer including a semiconductor chip having a transistor and a capacitor, and stably supply power to the semiconductor chip.

[0004] According to one aspect of an embodiment of the inventive concept, a semiconductor package includes a first semiconductor chip. The first semiconductor chip includes: a first semiconductor substrate having a first surface and a second surface opposite to each other; a circuit layer, the circuit layer is located on the first surface; a first interconnect layer, the first interconnect layer is located on the circuit layer; a second interconnect layer, the second interconnect layer is located on the second surface; a penetration via, the penetration via extending from the second surface into the first semiconductor substrate; and a capacitor, the capacitor extending from the second surface toward the first surface. The capacitor is spaced apart from the penetration via in a first direction parallel to the first surface of the first semiconductor substrate.

[0005] According to one aspect of the embodiment, a semiconductor package includes: a first semiconductor chip; and a second semiconductor chip, the second semiconductor chip is located on the first semiconductor chip. The first semiconductor chip includes: a first semiconductor substrate, the first semiconductor substrate having a first surface and a second surface opposite to each other, wherein the first surface is located between the second semiconductor chip and the second surface; a signal line layer and a buried power rail, the signal line layer and the buried power rail are located on the first surface; a power distribution interconnect layer, the power distribution interconnect layer is located on the second surface; a penetration via, the penetration via extends from the power distribution interconnect layer to the buried power rail; and a capacitor, the capacitor is arranged between the first surface and the power distribution interconnect layer.

[0006] According to one aspect of the embodiment, a semiconductor package includes: a package substrate; an interposer, the interposer being located on the package substrate; a chip stack and a chip structure, the chip stack and the chip structure being disposed on the interposer and spaced apart from each other in a horizontal direction; and a molding structure, the molding structure being disposed on a side surface of the chip stack, a side surface of the chip structure, and a top surface of the interposer. The chip structure includes: a first semiconductor chip; and a second semiconductor chip, the second semiconductor chip being disposed on the first semiconductor chip. The first semiconductor chip includes: a first semiconductor substrate, the first semiconductor substrate having a first surface and a second surface opposite to each other, wherein the first surface is disposed between the second semiconductor chip and the second surface; a first interconnect layer, the first interconnect layer being disposed on the first surface; a second interconnect layer, the second interconnect layer being disposed on the second surface; and a capacitor, the capacitor being disposed between the second interconnect layer and the first semiconductor substrate. The second semiconductor chip includes: a second semiconductor substrate; and an insulating layer, the insulating layer being disposed between the second semiconductor substrate and the first interconnect layer. The chip stack includes a plurality of semiconductor chips and a first through-via extending into the plurality of semiconductor chips. The capacitor is disposed in a trench extending from the second surface toward the first surface into the first semiconductor substrate. The insulating layer and the first interconnection layer are in contact with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects and features will become more apparent from the following description of example embodiments taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a cross-sectional view schematically illustrating a semiconductor package according to example embodiments;

[0009] Figure 2 is a diagram illustrating an exemplary embodiment of the Figure 1 An enlarged view of portion “aa”;

[0010] Figure 3 is a diagram illustrating an exemplary embodiment of the Figure 1 An enlarged view of portion “aa”;

[0011] Figure 4 is a cross-sectional view schematically illustrating a semiconductor package according to example embodiments;

[0012] Figure 5 is a diagram illustrating an exemplary embodiment of the Figure 4 An enlarged view of part "bb" of;

[0013] Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A and Fig. 12A is a cross-sectional view illustrating a process of manufacturing a semiconductor package according to example embodiments;

[0014] Figure 6B is a diagram illustrating an exemplary embodiment of the Fig. 6A An enlarged view of part "cc";

[0015] Figure 7B is a diagram illustrating an exemplary embodiment of the Fig. 7A A magnified view of part “dd”;

[0016] Figure 8B is a diagram illustrating an exemplary embodiment of the Fig. 8A An enlarged view of part “ee”;

[0017] Fig. 9B is a diagram illustrating an exemplary embodiment of the Fig.9A An enlarged view of the portion “ff”;

[0018] Fig. 10B and Fig. 10C is a diagram illustrating an exemplary embodiment of the Fig. 10A A portion "gg" of and in particular an enlarged cross-sectional view of a process for manufacturing a capacitor;

[0019] Fig. 11B is a diagram illustrating an exemplary embodiment of the Fig.11A An enlarged view of part “hh”;

[0020] Fig. 12B is a diagram illustrating an exemplary embodiment of the Fig. 12A an enlarged view of part “ii” of;

[0021] Fig.13A is a cross-sectional view illustrating a process of manufacturing a semiconductor package according to example embodiments;

[0022] Fig. 13B is a diagram illustrating an exemplary embodiment of the Fig.13A An enlarged view of part “jj”. DETAILED DESCRIPTION

[0023] Example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0024] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0025] Figure 1 is a cross-sectional view schematically illustrating a semiconductor package according to example embodiments. Figure 2 It's a picture. Figure 1 An enlarged view of portion “aa” of FIG.

[0026] refer to Figure 1 and Figure 2 , the semiconductor package 1000 may include a package substrate 600 , an interposer 500 , a chip structure 10 , a sub-semiconductor package 20 , and a first molding structure 590 .

[0027] The interposer 500 may be disposed on the package substrate 600 . The chip structure 10 , the sub-semiconductor package 20 , and the first molding structure 590 may be disposed on the interposer 500 .

[0028] The chip structure 10 may include a first semiconductor chip 100 and a second semiconductor chip 200. In example embodiments, the chip structure 10 may be a system on chip (SOC).

[0029] The second semiconductor chip 200 may be disposed on the first semiconductor chip 100. The first and second semiconductor chips 100 and 200 may be bonded to each other in a hybrid bonding manner without connection terminals (eg, solder balls, bumps, and pillars) interposed therebetween.

[0030] like Figure 1 and Figure 2 As shown, the first semiconductor chip 100 may include a first semiconductor substrate 110 , a first circuit layer 120 , a first interconnection layer 130 , a through via 111 , a capacitor 112 , and a second interconnection layer 140 .

[0031] The first semiconductor substrate 110 may be, for example, a silicon (Si) substrate. The first semiconductor substrate 110 may include a first surface 110a and a second surface 110b opposite to each other. The second semiconductor chip 200 may be closer to the first surface 110a than the second surface 110b. The first circuit layer 120 may be arranged on the first surface 110a of the first semiconductor substrate 110. The first surface 110a may contact the bottom surface of the device isolation layer 123 to be described below. The first surface 110a may be referred to as a front surface, and the second surface 110b may be referred to as a rear surface. The term "front surface" may indicate a surface provided with the first circuit layer 120, and the term "rear surface" may indicate a surface where the first circuit layer 120 is not provided.

[0032] The first circuit layer 120 may be disposed on the first surface 110a of the first semiconductor substrate 110. The first circuit layer 120 may indicate a layer or a region where an integrated circuit (eg, a transistor) is formed.

[0033] The first circuit layer 120 may include fins 121 and epitaxial patterns 122. The space between the fins 121 may be filled with a device isolation layer 123. Each fin 121 may protrude vertically with respect to the first surface 110a of the first semiconductor substrate 110 and the device isolation layer 123. The fin 121 may be used as a channel structure of a fin field effect transistor (FinFET), but example embodiments are not limited to this example. According to example embodiments, the transistor of the first semiconductor chip 100 may be one of a single or combined FinFET, a nanowire transistor, a nanosheet transistor, and the like. In example embodiments, the fin 121 may be formed of or include silicon (Si). Each epitaxial pattern 122 may be formed of or include a semiconductor material (e.g., silicon (Si), germanium (Ge), and silicon germanium (SiGe)). The device isolation layer 123 may be formed of or include an insulating material. The device isolation layer 123 may be formed of or include an insulating material. The device isolation layer 123 may be formed of at least one of an oxide material (e.g., silicon oxide (SiO 2 )) is formed or includes at least one of oxide materials (e.g., silicon oxide (SiO 2 )).

[0034] The epitaxial pattern 122 may constitute a transistor in combination with an epitaxial contact 132 described below.

[0035] The buried power rail 124 may be disposed on the first semiconductor substrate 110. The buried power rail 124 may extend to penetrate the device isolation layer 123 and may extend through the first surface 110a into an upper portion of the first semiconductor substrate 110. In example embodiments, the buried power rail 124 may include a protruding portion extending to a height higher than an upper surface of the device isolation layer 123. In example embodiments, a top surface of the buried power rail 124 may be located at a height lower than a bottom surface of the device isolation layer 123. The buried power rail 124 may be formed of or include at least one of a metal material (e.g., copper (Cu), cobalt (Co), tungsten (W), ruthenium (Ru), or an alloy thereof).

[0036] The first interconnection layer 130 may be disposed on the first circuit layer 120. The first interconnection layer 130 may include a first insulating layer 131, and an epitaxial contact 132, a vertical contact 133, and a first interconnection line 134 disposed in the first insulating layer 131.

[0037] The first insulating layer 131 may be made of an oxide material such as SiO 2 ) or includes an insulating material such as an oxide material (e.g., SiO 2 There may be no observable interface between the first insulating layer 131 and the device isolation layer 123.

[0038] The epitaxial contact 132 may be disposed on the epitaxial pattern 122. The epitaxial contact 132 may be a metal layer extending in a first direction D1 and contacting the epitaxial pattern 122, the first direction D1 being parallel to the first surface 100a of the first semiconductor substrate 110. The second direction D2 may be parallel to the first surface 100a and perpendicular to the first direction D1. The third direction D3 may be perpendicular to the first surface 100a.

[0039] The vertical contact 133 may be disposed between the epitaxial contact 132 and the buried power rail 124 to connect them to each other. The vertical contact 133 may be a via plug extending from the epitaxial contact 132 in a second direction D2 perpendicular to the first surface 100a of the first semiconductor substrate 110.

[0040] The first interconnection line 134 may be disposed on the epitaxial contact 132. The first interconnection line 134 may be formed of or include at least one of a metal material (e.g., copper and aluminum). The first interconnection line 134 may be used as part of a routing structure for signal transmission and may be referred to as a signal line 134.

[0041] The epitaxial pattern 122 may include a power tap epitaxial pattern, which is used as an interconnection element for power supply, and a non-power tap epitaxial pattern that is not used for power supply. The signal line 134 may be connected to the non-power tap epitaxial pattern and may be used as a routing structure for signal transmission between transistors. The distribution line 142 described below may be connected to the power tap epitaxial pattern, but may not be connected to the signal line 134.

[0042] The penetration path 111 may extend from the second surface 110b of the first semiconductor substrate 110 toward the first surface 110a along the third direction D3. The first semiconductor substrate 110 may include a plurality of penetration holes HL formed to have a specific depth in the third direction D3. The penetration path 111 may be disposed in the penetration hole HL. The penetration path 111 may include a barrier pattern and a conductive pattern located on the barrier pattern. The barrier pattern may be formed of at least one of tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TiSN), tungsten silicon nitride (WSiN), or ruthenium titanium nitride (RuTiN), or include at least one of tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TiSN), tungsten silicon nitride (WSiN), or ruthenium titanium nitride (RuTiN). The conductive pattern may be formed of at least one of tungsten (W), copper (Cu), polysilicon, or aluminum (Al), or include at least one of tungsten (W), copper (Cu), polysilicon, or aluminum (Al). The through via 111 may be in contact with the buried power rail 124 .

[0043] The capacitor 112 may be spaced apart from the penetration path 111 in the first direction D1 and / or the second direction D2. The first semiconductor substrate 110 may include at least one trench TR. The trench TR may be formed to have a certain depth in the third direction D3. The capacitor 112 may be disposed in the trench TR. The capacitor 112 may include a first electrode E1, a second electrode E2, and a dielectric pattern DP between the first electrode E1 and the second electrode E2. In example embodiments, the first electrode E1 and the second electrode E2 may be formed of or include polycrystalline silicon. The dielectric pattern DP may be made of silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ) or includes silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ). The insulating pattern IP may be interposed between the inner surface of the trench TR and the capacitor 112. The insulating pattern IP may be made of silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ) or includes silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 In example embodiments, the first electrode E1 and the second electrode E2 may be formed of or include at least one of the metal materials.

[0044] A first distance t1 between the first surface 110a and the second surface 110b of the first semiconductor substrate 110 may be greater than a second distance t2 between the capacitor 112 and the first surface 110a. For example, the second distance t2 may be the shortest distance between the capacitor 112 and the first surface 110a.

[0045] The second interconnect layer 140 may be disposed on the second surface 110b of the first semiconductor substrate 110. The second interconnect layer 140 may include a second insulating layer 141 and a second interconnect line 142 located in the second insulating layer 141. The second insulating layer 141 may be formed of an insulating material (e.g., silicon oxide) or include an insulating material (e.g., silicon oxide). The second interconnect line 142 may be formed of a metal material (e.g., copper, aluminum) or include a metal material (e.g., copper, aluminum). The second interconnect line 142 may be referred to as a power distribution line or a power distribution network (PDN). The power distribution line 142 may be connected to the capacitor 112 and the penetration path 111. In detail, the power distribution line 142 may be connected to two electrodes E1 and E2 of the capacitor 112.

[0046] The chip pad 150 and the protective layer 160 may be disposed on the second interconnect layer 140. The chip pad 150 may be formed of or include aluminum or copper. The protective layer 160 may be formed of an insulating material (eg, silicon nitride (Si 3 N 4 )) or includes an insulating material (eg, silicon nitride (Si 3 N 4 )). The first connection terminals 180 may be respectively disposed on the chip pads 150. The first connection terminals 180 may include solder balls, bumps, pillars, etc. A first underfill pattern 310 may be provided to cover side surfaces of the first connection terminals 180. The first underfill pattern 310 may be formed of or include an insulating material (e.g., epoxy resin).

[0047] The second semiconductor chip 200 may include a second semiconductor substrate 210 , a second circuit layer 220 , and a third interconnection layer 230 .

[0048] The second semiconductor substrate 210 may include a third surface 210a and a fourth surface 210b opposite to each other. The third surface 210a may be closer to the first semiconductor chip 100 than the fourth surface 210b. The fourth surface 210b may be exposed to the outside of the first molding structure 590. In example embodiments, the second semiconductor substrate 210 may be formed of or include silicon, and the thickness of the second semiconductor substrate 210 may be greater than the thickness of the first semiconductor substrate 110.

[0049] The second circuit layer 220 may be disposed on the third surface 210a of the second semiconductor substrate 210 and may include an integrated circuit 221 (eg, a transistor). For example, the second semiconductor chip 200 may be a memory chip (eg, a static random access memory (SRAM) chip).

[0050] The third interconnect layer 230 may be disposed on the second circuit layer 220. The third interconnect layer 230 may include a third insulating layer 231 and a third interconnect line 232. The third interconnect line 232 may be disposed in the third insulating layer 231. The third interconnect line 232 may be formed of or include at least one of a metal material (e.g., aluminum or copper). The third insulating layer 231 may be formed of, for example, silicon oxide or include, for example, silicon oxide.

[0051] The bottom third interconnect line (hereinafter referred to as the third interconnect line 232b) of the third interconnect lines 232 may contact the top first interconnect line (hereinafter referred to as the first interconnect line 134t) of the first interconnect lines 134. In example embodiments, there may be no observable interface between the third interconnect line 232b and the first interconnect line 134t that are in contact with each other. For example, a solder ball, a bump, a column, etc. may not be between the third interconnect line 232b and the first interconnect line 134t. The first insulating layer 131 and the third insulating layer 231 may contact each other. In example embodiments, there may be no observable interface between the first insulating layer 131 and the third insulating layer 231.

[0052] The sub-semiconductor package 20 may be disposed to be spaced apart from the chip structure 10 in the first direction D1 and / or the second direction D2. The sub-semiconductor package 20 may be referred to as a chip stack 20 or a high bandwidth memory (HBM) 20. The sub-semiconductor package 20 may include a third semiconductor chip 410 and fourth semiconductor chips 420 and 420t, and a second molding structure 490 disposed on the third semiconductor chip 410. The third semiconductor chip 410 may be referred to as a base chip 410, and the fourth semiconductor chips 420 and 420t may be referred to as memory chips 420 and 420t.

[0053] The base chip 410 may be a logic chip. As an example, the base chip 410 may be a memory controller.

[0054] The memory chips 420 and 420t may be stacked on the base chip 410 along the third direction D3. The memory chips 420 and 420t may be the same kind of semiconductor chips and may include the same circuits. The memory chips 420 and 420t may be dynamic random access memory (DRAM) chips or NAND flash memory chips.

[0055] The base chip 410 and the memory chips 420 and 420t may each include a circuit layer. The base chip 410 and the memory chip 420 may include a penetration path. The memory chip 420t, which is the topmost memory chip among the memory chips 420 and 420t, may not include a penetration path disposed therein. In an example embodiment, the topmost memory chip 420t may include a penetration path. The penetration path of the base chip 410 may be connected to the penetration path of the memory chip 420 adjacent thereto through a microbump. The penetration paths of adjacent memory chips in the memory chip 420 may be connected to each other through microbumps.

[0056] The adhesive layer AD may be interposed between the base chip 410 and the memory chips 420 adjacent to each other and between the memory chips 420 adjacent to each other. In example embodiments, the adhesive layer AD may be a non-conductive film (NCF) containing a polymer.

[0057] The second molding structure 490 may cover the top surface of the base chip 410, the side surfaces of the memory chips 420 and 420t, and the side surface of the adhesive layer AD. The top surface of the uppermost memory chip 420t may be exposed to the outside of the second molding structure 490. For example, the top surface of the uppermost memory chip 420t may correspond to the top surface of the semiconductor package 1000.

[0058] The second connection terminal 480 may be disposed under the base chip 410. The second connection terminal 480 may include a solder ball, a bump, a column, etc. The second underfill pattern 312 may cover the side surface of the second connection terminal 480. The second underfill pattern 312 may be formed of or include an insulating material (e.g., epoxy resin).

[0059] In an example embodiment, the package substrate 600 may be a printed circuit board (PCB). The package substrate 600 may include an upper pad 610 and a lower pad 620 respectively disposed on the top surface and the bottom surface thereof or in the upper or lower portion thereof. An external connection terminal 680 may be disposed on each lower pad 620 and may be connected to an external board (e.g., a main board). The external connection terminal 680 may be formed of at least one of a conductive material (such as a soldering material) or include at least one of a conductive material (such as a soldering material).

[0060] In an example embodiment, the interposer 500 may be a silicon interposer. The interposer 500 may include a support substrate 510, a fourth interconnect layer 530 located on the support substrate, and a plurality of penetration vias 511 penetrating the support substrate 510. The support substrate 510 may be, for example, a silicon substrate. The interposer 500 may connect the chip structure 10 to the sub-semiconductor package 20. The third connection terminal 580 may be disposed between the interposer 500 and the package substrate 600. The third connection terminal 580 may be formed of at least one of a conductive material (e.g., a soldering material) or include at least one of a conductive material (e.g., a soldering material). The third bottom fill pattern 330 may be disposed on the package substrate 600 to cover the side surface of the third connection terminal 580. The third bottom fill pattern 330 may be formed of an insulating material (e.g., an epoxy resin) or include an insulating material (e.g., an epoxy resin).

[0061] The first molding structure 590 and the second molding structure 490 may be formed of or include an insulating material, such as an epoxy molding compound (EMC).

[0062] According to example embodiments, the first semiconductor chip 100 may have a back side power distribution network (BSPDN) structure, and may have a structure in which the capacitor 112 is located in the first semiconductor substrate 110 .

[0063] In the comparative example, the capacitor may be disposed outside the first semiconductor chip 100, rather than inside the first semiconductor chip 100. In addition, all the signal lines 134 and the distribution lines 142 may be provided as a single interconnection layer disposed on the first circuit layer 120. For example, all the signal lines 134 and the distribution lines 142 may be disposed on the first surface 110a of the first semiconductor substrate 110. In order to suppress interference or disturbance problems between the signal lines 134 and the distribution lines 142, the interconnection layer having the signal lines 134 and the distribution lines 142 should be formed to have a large thickness (for example, greater than the sum of the thicknesses of the first interconnection layer 130 and the second interconnection layer 140, according to an example embodiment). For example, in the comparative example, the total length of the interconnection element connecting the first circuit layer 120 to the capacitor may be equal to or greater than 10 μm.

[0064] According to example embodiments, capacitor 112 may be disposed adjacent to first circuit layer 120. Distribution line 142, through via 111, and buried power rail 124 may be used to connect capacitor 112 to first circuit layer 120, and the total length of the interconnection path formed by distribution line 142, through via 111, and buried power rail 124 may be less than 10 μm.

[0065] The capacitor 112 can be used to reduce noise problems (e.g., parasitic inductance and resistance) that may be generated between the conductive paths connecting the transistor, the signal line 134, and the distribution line 142. In the first semiconductor chip 100 according to the example embodiment, since the capacitor 112 is disposed on the rear surface 110b of the first semiconductor substrate 110, the distance between the transistor of the first circuit layer 120 and the capacitor 112 can be reduced, and therefore, the noise problem can be effectively reduced. In addition, since the capacitor 112 is connected to the distribution line 142, power can be stably supplied to the chip structure 10. In the example embodiment, the capacitor 112 can be connected to the metal layer on the first surface 110a through the penetration path 111.

[0066] Figure 3 It's a picture. Figure 1 In addition to the features described below, the package may also have the same Figure 1 and Figure 2 Those features described are substantially the same features, and therefore, overlapping descriptions thereof may be omitted.

[0067] refer to Figure 1 and Figure 3 , the first semiconductor substrate 110 may include a doping region 110R. The doping region 110R may have a conductivity type different from that of the first semiconductor substrate 110. For example, in the case where the first semiconductor substrate 110 has a conductivity type of n-, the doping region 110R has a conductivity type of p++.

[0068] Figure 4 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Figure 5 It's a picture. Figure 4 In addition to the features described below, the package may also have the same Figure 1 and Figure 2 Those features described are substantially the same features, and therefore, overlapping descriptions thereof may be omitted.

[0069] refer to Figure 4 and Figure 5 , the second semiconductor chip 200 of the semiconductor package 1100 may be a dummy chip. In this regard, the second semiconductor chip 200 may not include the second circuit layer 220 , and any integrated circuit may not be disposed on the second semiconductor substrate 210 .

[0070] The third surface 210a of the second semiconductor substrate 210 may be in contact with the third insulating layer 231. The third interconnection line 232 may not be disposed in the third insulating layer 231. In example embodiments, the third interconnection line 232 may be disposed in the third insulating layer 231, such as Figure 1 and Figure 2 shown.

[0071] Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A and Fig. 12A is a cross-sectional view illustrating a process of manufacturing a semiconductor package according to example embodiments. Figure 6B It's a picture. Fig. 6A An enlarged view of part “cc”. Figure 7B It's a picture. Fig. 7A An enlarged view of part “dd”. Figure 8B It's a picture. Fig. 8A An enlarged view of part “ee”. Fig. 9B It's a picture. Fig.9A An enlarged view of portion “ff”. Fig. 10B and Fig. 10C It's a picture. Fig. 10A gg" and in particular an enlarged cross-sectional view of the process of manufacturing the capacitor. Fig. 11B It's a picture. Fig.11A An enlarged view of the portion “hh”.

[0072] refer to Fig. 6A and Figure 6B , a first wafer WF1 and a second wafer WF2 may be provided. The first wafer WF1 may include a first preliminary semiconductor substrate 110P, a first circuit layer 120 , and a first interconnection layer 130 .

[0073] In detail, the fins 121 may be formed by patterning the surface of the preliminary semiconductor substrate 110P. Each fin 121 may be used as a current path of a transistor. Although the fins 121 are illustrated as having a fin structure of a FinFET, each fin 121 may include various elements (such as nanowires or nanosheets) for a nanowire transistor or a nanosheet transistor, or any combination of these structures. In an example embodiment, the space between the fins 121 may be formed of silicon oxide (SiO 2 ) is formed of or includes silicon oxide (SiO 2 ) is filled with the device isolation layer 123. The buried power rail 124 may be formed to penetrate the device isolation layer 123, and in example embodiments, may extend into the preliminary semiconductor substrate 110P.

[0074] An epitaxial pattern 122 may be formed on the fin 121. In example embodiments, the epitaxial pattern 122 may be used as an active region of a transistor including a source / drain region, and may be formed of or include silicon (Si). The vertical contact 133 and the epitaxial contact 132 may be formed simultaneously or sequentially. Next, a first interconnect line 134 may be formed on the epitaxial contact 132.

[0075] The second wafer WF2 may include a second semiconductor substrate 210 , a second circuit layer 220 , and a third interconnection layer 230 .

[0076] refer to Fig. 7A and Figure 7B , a wafer-to-wafer bonding process may be performed. As a result, the second wafer WF2 may be in contact with the first wafer WF1.

[0077] The second wafer WF2 may be directly bonded to the first wafer WF1 by a direct bonding process without using any adhesive layer. During the bonding process, the first wafer WF1 and the second wafer WF2 may be exposed to a high heat environment. The first interconnect layer 130 and the third interconnect layer 230 may be in contact with each other. In detail, the first interconnect line 134t and the third interconnect line 232b may be disposed in contact with each other, and the first insulating layer 131 and the third insulating layer 231 may be disposed in contact with each other.

[0078] refer to Fig. 8A and Figure 8B As shown, the first wafer WF1 and the second wafer WF2 may be reversed. A thinning process including a chemical mechanical polishing (CMP) process, a grinding process, or a dry etching process may be performed to reduce the thickness of the preliminary semiconductor substrate 110P of the first wafer WF1. As a result of the thinning process, a first semiconductor substrate 110 may be formed.

[0079] refer to Fig.9A and Fig. 9B , a penetration hole HL may be formed in the first semiconductor substrate 110 to expose the buried power rail 124. Next, a penetration via 111 may be formed on the buried power rail 124 to contact the buried power rail 124. The formation of the penetration via 111 may include forming a barrier layer, forming a conductive layer on the barrier layer, and patterning the barrier layer and the conductive layer.

[0080] refer to Fig. 10A and Fig. 10B, at least one trench TR recessed from the second surface 110b toward the first surface 110a may be formed in the first semiconductor substrate 110. Thereafter, an insulating layer IL, a first conductive layer EL1, a dielectric layer DL, and a second conductive layer EL2 may be sequentially formed to fill the trench TR. The insulating layer IL, the first conductive layer EL1, the dielectric layer DL, and the second conductive layer EL2 may be formed by a deposition method such as a chemical vapor deposition (CVD), a physical vapor deposition (PVD), and an atomic layer deposition (ALD) method.

[0081] refer to Fig. 10A and Fig. 10C , the insulating pattern IP, the first electrode E1, the dielectric pattern DP, and the second electrode E2 may be formed by patterning the insulating layer IL, the first conductive layer EL1, the dielectric layer DL, and the second conductive layer EL2, respectively. The first electrode E1, the dielectric pattern DP, and the second electrode E2 may constitute a capacitor 112. In example embodiments, the capacitor 112 may be formed, and then the penetration via 111 may be formed.

[0082] refer to Fig.11A and Fig. 11B A second interconnection layer 140 may be formed on the second surface 110 b of the first semiconductor substrate 110 . A second interconnection line 142 may be connected to the penetration via 111 and the capacitor 112 . A protection layer 160 and a chip pad 150 may be formed on the second interconnection layer 140 .

[0083] refer to Fig. 12A and Fig. 12B , external connection terminals may be formed on the chip pad 150. Next, a sawing process may be performed along the sawing lines SL. As a result of the sawing process, a chip structure 10 including the first semiconductor chip 100 and the second semiconductor chip 200 may be formed.

[0084] Return to reference Figure 1 , a chip assembly process or the like may be performed on the interposer 500 , the chip structure 10 , and the sub-semiconductor package 20 located on the package substrate 700 to form a first molding structure 590 , and in this case, the semiconductor package 1000 may be formed.

[0085] Fig.13A is a cross-sectional view illustrating a process of manufacturing a semiconductor package according to example embodiments. Fig. 13B It's a picture. Fig.13A An enlarged view of part “jj”.

[0086] refer to Fig.13A, the second wafer WF2 may be provided to include a second semiconductor substrate 210 and a third insulating layer 231 that are in direct contact with each other. In this regard, the second wafer WF2 may not include the second circuit layer 220. Fig.13A and Fig. 13B As shown, the third insulating layer 231 may be in contact with the first insulating layer 131. In example embodiments, the third interconnection line 232 may be disposed in the third insulating layer 231. 6A to 12A The subsequent steps of the manufacturing process are performed in a manner substantially the same as described above. In this case, the semiconductor package can be formed to have Figure 4 The semiconductor package 1100 has substantially the same structure.

[0087] According to example embodiments, a semiconductor package may include a semiconductor chip, wherein a capacitor and a power distribution interconnect layer are disposed on a rear surface of a semiconductor substrate and a circuit layer is disposed on a front surface of the semiconductor substrate. In this case, a distance between a capacitor in the semiconductor chip and a transistor of the circuit layer can be reduced, and power can be stably supplied to the semiconductor chip. As a result, the reliability of the semiconductor package can be improved.

[0088] While aspects of the example embodiments have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising a first semiconductor chip, in, The first semiconductor chip comprises: a first semiconductor substrate including a first surface and a second surface opposite to each other; a circuit layer, the circuit layer being located on the first surface; a first interconnect layer, the first interconnect layer being located on the circuit layer; a second interconnect layer, the second interconnect layer being located on the second surface; a through via extending from the second surface into the first semiconductor substrate; and a capacitor extending from the second surface toward the first surface, and The capacitor is spaced apart from the penetration via in a first direction parallel to the first surface of the first semiconductor substrate.

2. The semiconductor package according to claim 1, wherein: The capacitor is spaced apart from the first surface.

3. The semiconductor package according to claim 1, wherein: A first distance between the first surface and the second surface is greater than a second distance between the capacitor and the first surface.

4. The semiconductor package according to claim 1, wherein: The first interconnect layer includes signal lines, and Wherein, the second interconnect layer includes power distribution lines.

5. The semiconductor package according to claim 1, further comprising a second semiconductor chip located on the first semiconductor chip, in, The first semiconductor chip is a logic chip, and The second semiconductor chip is a dummy chip or a memory chip.

6. The semiconductor package according to claim 5, wherein: The first surface is located between the second semiconductor chip and the second surface, Wherein, the first interconnection layer comprises a first interconnection line, Wherein, the second semiconductor chip comprises: a second semiconductor substrate; and a third interconnect layer, the third interconnect layer being located on the second semiconductor substrate, Wherein, the third interconnection layer includes a second interconnection line, and The uppermost first interconnection line among the first interconnections and the lowermost second interconnection line among the second interconnections are in contact with each other.

7. The semiconductor package according to claim 6, wherein: The first interconnect layer further includes a first insulating layer located on the first interconnect line, Wherein, the third interconnection layer further includes a second insulating layer located on the second interconnection line, and Wherein, the first insulating layer and the second insulating layer are in contact with each other.

8. The semiconductor package according to claim 7, wherein: The first insulating layer and the second insulating layer each include silicon oxide.

9. The semiconductor package according to claim 1, wherein: The capacitor comprises: a first electrode; a second electrode, the second electrode being located on the first electrode; and a dielectric pattern located between the first electrode and the second electrode, and Wherein, the first electrode and the second electrode both include polysilicon.

10. The semiconductor package according to claim 1, wherein The second interconnect layer includes power distribution lines, and Wherein, the power distribution line is connected to the capacitor.

11. The semiconductor package according to claim 1, wherein: The capacitor is disposed in a trench extending from the second surface toward the first surface into the first semiconductor substrate.

12. The semiconductor package according to claim 1, wherein The first semiconductor substrate is doped to have a first conductivity type, The first semiconductor substrate includes a doped region having a second conductivity type different from the first conductivity type, and Wherein, the capacitor is arranged in the doped region.

13. A semiconductor package, comprising: a first semiconductor chip; as well as a second semiconductor chip, the second semiconductor chip being located on the first semiconductor chip, Wherein, the first semiconductor chip comprises: a first semiconductor substrate, the first semiconductor substrate comprising a first surface and a second surface opposite to each other, wherein the first surface is located between the second semiconductor chip and the second surface; a signal line layer and a buried power rail, the signal line layer and the buried power rail being located on the first surface; a power distribution interconnect layer, the power distribution interconnect layer being located on the second surface; a through-via extending from the power distribution interconnect layer to the buried power rail; and A capacitor is disposed between the first surface and the power distribution interconnect layer.

14. The semiconductor package according to claim 13, wherein: The first semiconductor chip and the second semiconductor chip are bonded to each other in a hybrid bonding manner.

15. The semiconductor package according to claim 13, wherein: The first semiconductor chip is a logic chip, and The second semiconductor chip is a memory chip or a dummy chip.

16. The semiconductor package according to claim 13, wherein: The power distribution interconnect layer includes power distribution lines, and Wherein, the power distribution line is connected to the capacitor.

17. A semiconductor package, comprising: Package substrate; An interposer, the interposer being located on the packaging substrate; a chip stack and a chip structure, the chip stack and the chip structure being disposed on the interposer and spaced apart from each other in a horizontal direction; as well as a molding structure located on a side surface of the chip stack, a side surface of the chip structure, and a top surface of the interposer, Wherein, the chip structure includes: a first semiconductor chip; and a second semiconductor chip, the second semiconductor chip being located on the first semiconductor chip, Wherein, the first semiconductor chip comprises: a first semiconductor substrate, the first semiconductor substrate comprising a first surface and a second surface opposite to each other, wherein the first surface is located between the second semiconductor chip and the second surface; a first interconnect layer, the first interconnect layer being located on the first surface; a second interconnect layer, the second interconnect layer being located on the second surface; and a capacitor located between the second interconnect layer and the first semiconductor substrate, Wherein, the second semiconductor chip comprises: a second semiconductor substrate; and an insulating layer, the insulating layer being located between the second semiconductor substrate and the first interconnection layer, wherein the chip stack comprises a plurality of semiconductor chips and a first through-via extending into the plurality of semiconductor chips, wherein the capacitor is arranged in a trench extending from the second surface toward the first surface into the first semiconductor substrate, and Wherein, the insulating layer and the first interconnection layer are in contact with each other.

18. The semiconductor package according to claim 17, wherein: The first semiconductor chip further includes a second through via extending from the second interconnect layer into the first semiconductor substrate, wherein the second interconnect layer comprises power distribution lines, and Wherein, the power distribution line is connected to the capacitor and the penetration via.

19. The semiconductor package according to claim 17, further comprising an insulating pattern disposed between the capacitor and the trench, in, The capacitor comprises: a first electrode, the first electrode being located on the insulating pattern; a second electrode, the second electrode being located on the first electrode; and A dielectric pattern is located between the first electrode and the second electrode.

20. The semiconductor package according to claim 18, wherein The thickness of the second semiconductor substrate is greater than the thickness of the first semiconductor substrate.

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