LED chip, preparation method thereof and display device

Abstract

The invention provides an LED chip and a preparation method thereof, a display device, and an LED chip, the LED chip comprises an epitaxial layer, the epitaxial layer comprises a plurality of light-emitting tables arranged at intervals, and each light-emitting table comprises a table surface far away from one side of a driving backboard and a side surface connected with the table surface; the middle dielectric layer and the middle metal layer are sequentially arranged on the light-emitting table in a stacked mode, the middle dielectric layer is arranged on the surface of the side, away from the light-emitting table, of the middle metal layer, the middle dielectric layer and the middle metal layer at least cover the side face, the middle dielectric layer is used for adjusting and controlling the phase of plasmon resonance, and the middle metal layer is used for adjusting and controlling the phase of plasmon resonance. The middle metal layer is used for generating plasmons on the side face. According to the LED chip, high PPI of a small-size LED is achieved, and the light-emitting performance of the LED chip can be better improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an LED chip and a preparation method thereof, and a display device. Background Art

[0002] Micro-LED has the advantages of high contrast, high brightness, high reliability, low power consumption, long life and fast response, and has become one of the preferred technologies for near-eye displays such as augmented reality (AR) and virtual reality (VR). Due to the demand for near-eye display, the Micro-LED screen used in AR is required to have a high pixel density of more than 5000PPI. At the same time, due to the glasses form of AR, the screen size of Micro-LED needs to be controlled below 0.5 inches, which requires the pixel size of Micro-LED to be less than 10μm.

[0003] In addition, improving the luminous efficiency of Micro-LEDs is still a hot topic in scientific research. Among the many methods to enhance the luminous efficiency of LEDs, using surface plasmon coupling to improve the luminous efficiency of light-emitting devices is an effective way to enhance the luminescence of devices.

[0004] Surface Plasmon Polariton (SPP) is an electromagnetic wave that oscillates at the interface between metal and dielectric, and can form a strong local field on the metal surface. Generally, on LED chips, the method usually used to excite surface plasmons is to achieve wave vector matching under the illumination of light source through prism coupling, grating coupling or single scatterer scattering. However, such optical excitation method is difficult to meet the requirements of high integration and small volume of integrated technology; in addition, this method can only improve the luminous efficiency to a limited extent. Summary of the invention

[0005] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, one object of the present invention is to provide an LED chip and a preparation method thereof, and a display device, which can meet the needs of small-size LEDs and improve the luminous efficiency of the LED chip.

[0006] In one aspect of the present invention, the present invention provides an LED chip, comprising: an epitaxial layer, the epitaxial layer comprising a plurality of light-emitting tables arranged at intervals, the light-emitting tables having a table top and a side surface connected to the table top; an intermediate dielectric layer and an intermediate metal layer sequentially stacked on the light-emitting tables, the intermediate dielectric layer being arranged on a side surface of the intermediate metal layer away from the light-emitting tables, wherein the intermediate dielectric layer and the intermediate metal layer at least cover the side surface, the intermediate dielectric layer being used to regulate the phase of plasmon resonance, and the intermediate metal layer being used to generate plasmons on the side surface.

[0007] According to an embodiment of the present invention, the epitaxial layer includes a stacked P-type semiconductor layer, a multi-quantum well layer, and an N-type semiconductor layer, and the N-type semiconductor layer is arranged on a side close to the table; the N-type semiconductor layer is an n-GaN layer; the thickness of the N-type semiconductor layer is 1 to 2.5 μm; the multi-quantum well layer includes alternately grown InGaN layers and GaN layers, and the total thickness of the multi-quantum well layer is 30 to 100 nm; the P-type semiconductor layer is a p-GaN layer, and the P-type semiconductor layer includes an electron blocking layer and a hole injection layer, and the total thickness of the P-type semiconductor layer is 10 to 30 nm.

[0008] According to an embodiment of the present invention, the side surface and the driving back plate are arranged at an angle, and the angle ranges from 90° to 110°.

[0009] According to an embodiment of the present invention, the refractive index of the intermediate dielectric layer is the same as or nearly the same as the refractive index of the multi-quantum well layer; the material of the intermediate dielectric layer includes AlN, Al2O3, SiO2, SiN x One or more of; the thickness of the intermediate dielectric layer is 5 to 15 nm; the intermediate metal layer includes one or more of Au and Ag; the thickness of the intermediate metal layer is 5 to 15 nm.

[0010] According to an embodiment of the present invention, the wavelength of the emitted light of the light emitting platform is 450-480nm, the material of the intermediate metal layer is Ag, and the wavelength of the plasmon generated by the side is 450nm; or the wavelength of the emitted light of the light emitting platform is 520-570nm, the material of the intermediate metal layer is Au, and the wavelength of the plasmon generated by the side is 560nm.

[0011] According to an embodiment of the present invention, the LED chip also includes: a first electrode layer arranged on the table top; and a second electrode layer arranged on the surface of the epitaxial layer away from the table top; a driving backplane arranged on the side of the second electrode layer away from the table top, and the second electrode layer is electrically connected to the driving backplane.

[0012] According to an embodiment of the present invention, the second electrode layer includes a plurality of first metal contacts, and the orthographic projections of the first metal contacts on the driving backplane correspond one-to-one to the orthographic projections of the light-emitting platform on the driving backplane; the driving backplane includes a bonding metal layer on a surface of a side close to the light-emitting platform, and the bonding metal layer includes a plurality of second metal contacts, and the orthographic projections of the first metal contacts on the driving backplane coincide with the second metal contacts, and the second metal contacts are bonded to the first metal contacts.

[0013] According to an embodiment of the present invention, the first electrode layer is an ITO layer; the second electrode layer includes a stacked Pt layer, an Au layer, and a Sn layer, and the Sn layer is arranged on a side close to the second metal contact; and the bonding metal layer is an Al layer.

[0014] According to an embodiment of the present invention, the intermediate dielectric layer and the intermediate metal layer extend from the side and cover the table top, and the first electrode layer is arranged on a surface of the intermediate dielectric layer on a side away from the driving substrate; the intermediate dielectric layer and the intermediate metal layer are provided with vias at positions corresponding to the table top and expose the table top, and the first electrode layer fills the vias.

[0015] According to an embodiment of the present invention, the intermediate metal layer and the intermediate dielectric layer extend from the side and cover the table top, and the LED chip also includes: an insulating layer arranged on the surface of the epitaxial layer close to the driving backplane, and the surface of the insulating layer on the side away from the driving backplane is flush with the surface of the intermediate metal layer on the side away from the driving backplane.

[0016] According to an embodiment of the present invention, the LED chip also includes: a light shielding block arranged between the light-emitting tables, the light shielding block includes a first light shielding portion located on the surface of the first electrode layer on the side away from the driving backplane and a second light shielding portion extending from the surface of the first light shielding portion toward the driving backplane, the orthographic projection of the first light shielding portion on the driving backplane at least covers the orthographic projection of the second light shielding portion on the driving backplane.

[0017] According to an embodiment of the present invention,

[0018] The surface of the second light shielding portion close to the driving backplane is flush with the surface of the P-type semiconductor away from the driving backplane; the first electrode layer is provided with a first groove penetrating the first electrode layer, the insulating layer is provided with a second groove partially penetrating the insulating layer, and the second light shielding portion is filled in the first groove and the second groove.

[0019] In another aspect of the present invention, the present invention provides a method for preparing an LED chip, the method comprising: growing an epitaxial layer; forming a plurality of light-emitting tables arranged at intervals on the epitaxial layer, the light-emitting tables having a table top and a side surface connected to the table top; sequentially growing an intermediate metal layer and an intermediate dielectric layer on the light-emitting tables, the intermediate dielectric layer being arranged on a side surface of the intermediate metal layer away from the light-emitting table, wherein the intermediate dielectric layer and the intermediate metal layer at least cover the side surface, the intermediate dielectric layer is used to regulate the phase of plasmon resonance, and the intermediate metal layer is used to generate plasmons on the side surface.

[0020] According to an embodiment of the present invention, the growing epitaxial layer includes: providing a substrate, the material of the substrate including any one of sapphire, silicon, gallium nitride, gallium oxide or silicon carbide; growing an undoped GaN layer on the surface of the substrate; growing an epitaxial layer on the undoped GaN layer, the epitaxial layer including an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer grown in sequence on the substrate; the N-type semiconductor layer is an n-GaN layer; the thickness of the N-type semiconductor layer is 1 to 2.5 μm; the multi-quantum well layer includes alternately grown InGaN layers and GaN layers, and the total thickness of the multi-quantum well layer is 30 to 100 nm; the P-type semiconductor layer is a p-GaN layer, the P-type semiconductor layer includes an electron blocking layer and a hole injection layer, and the total thickness of the P-type semiconductor layer is 10 to 30 nm.

[0021] According to an embodiment of the present invention, the method for preparing the LED chip also includes: forming a second electrode layer on the surface of the epitaxial layer on the side away from the substrate; the second electrode layer includes a stacked Pt layer, an Au layer, and a Sn layer, and the Sn layer is arranged on the side away from the substrate; forming a plurality of first metal contacts on the second electrode layer, and the orthographic projections of the first metal contacts on the substrate correspond one-to-one to the orthographic projections of the light-emitting table on the substrate.

[0022] According to an embodiment of the present invention, the method also includes: providing a driving backplane; the driving backplane is a CMOS substrate; forming a bonding metal layer on the surface of the driving backplane, the bonding metal layer is an Al layer; forming a plurality of second metal contacts on the bonding metal layer, the orthographic projection of the second metal contact on the driving backplane coincides with the orthographic projection of the first metal contact on the driving backplane; bonding the second metal contact to the first metal contact by eutectic bonding, thereby bonding the epitaxial layer to the driving backplane.

[0023] According to an embodiment of the present invention, forming a plurality of light-emitting tables spaced apart on the epitaxial layer comprises: removing the substrate on the epitaxial layer by femtosecond pulse laser stripping; removing the undoped GaN layer by chemical mechanical polishing; and forming a plurality of light-emitting tables spaced apart on the epitaxial layer by etching, wherein an angle is formed between the side surface and the table top, and the angle ranges from 90° to 110°.

[0024] According to an embodiment of the present invention, an intermediate metal layer and an intermediate dielectric layer are sequentially grown on the light-emitting platform, and the method includes: depositing the intermediate dielectric layer on the side and the surface of the light-emitting platform by atomic layer evaporation; depositing the intermediate metal layer on the surface of the intermediate dielectric layer by electron beam evaporation; optionally, the wavelength of the emitted light of the light-emitting platform is 450-480nm, the intermediate metal layer is made of Ag, and the wavelength of plasmons generated on the side is 450nm; or the wavelength of the emitted light of the light-emitting platform is 520-570nm, the intermediate metal layer is made of Au, and the wavelength of plasmons generated on the side is 560nm.

[0025] According to an embodiment of the present invention, the intermediate metal layer and the intermediate dielectric layer extend from the side and cover the table top, and the method further includes: forming an insulating layer on the surface of the epitaxial layer close to the driving backplane, and the surface of the insulating layer on the side away from the driving backplane is flush with the surface of the intermediate metal layer on the side away from the driving backplane; removing at least part of the intermediate metal layer and the intermediate dielectric layer on the table top to form a via hole exposing the table top; forming a first electrode layer on the surface of the intermediate dielectric layer and the insulating layer, and the first electrode layer fills the via hole.

[0026] According to an embodiment of the present invention, the method further includes: forming a first groove penetrating the second electrode layer and a second groove penetrating a portion of the insulating layer on the second electrode layer and the insulating layer corresponding to the light-emitting table by etching, wherein the surface of the second groove close to the driving backplane is flush with the surface of the P-type semiconductor away from the driving backplane; forming a light shielding block on the surface of the first electrode layer, the light shielding block includes a first light shielding portion located on the surface of the first electrode layer away from the driving backplane and a second light shielding portion filled in the first groove and the second groove, the orthographic projection of the first light shielding portion on the driving backplane at least covers the orthographic projection of the second light shielding portion on the driving backplane; the first light shielding portion and the second light shielding portion are metal.

[0027] In another aspect of the present invention, the present invention provides a display device, comprising an LED chip as described in any one of the above or an LED chip prepared by any one of the above methods. Thus, the LED chip satisfies the requirement of small-size LED to achieve high PPI, and can better improve the luminous performance of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0029] Figure 1is a schematic diagram of the structure of an LED chip in one embodiment of the present invention;

[0030] Figure 2 is a schematic structural diagram of an LED chip in another embodiment of the present invention;

[0031] Figure 3 is a top view of an LED chip in one embodiment of the present invention;

[0032] Figure 4 is a schematic structural diagram of an LED chip in another embodiment of the present invention;

[0033] Figure 5 is a flow chart of a partial structure of preparing a Micro-LED chip in one embodiment of the present invention;

[0034] Figure 6 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0035] Figure 7 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0036] Figure 8 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0037] Fig. 9 is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention;

[0038] Fig.10 This is a flow chart of a partial structure of preparing a Micro-LED chip in another embodiment of the present invention. DETAILED DESCRIPTION

[0039] The scheme of the present invention will be explained below in conjunction with embodiments. It will be appreciated by those skilled in the art that the following embodiments are only used to illustrate the present invention and should not be considered as limiting the scope of the present invention. Where specific techniques or conditions are not indicated in the embodiments, the techniques or conditions described in the literature in this area or the product specifications are followed. The present invention will be described below with reference to specific embodiments, it should be noted that these embodiments are merely illustrative and do not limit the present invention in any way.

[0040] Please refer to Figure 1 In one aspect of the present invention, the present invention provides an LED chip, comprising:

[0041] The epitaxial layer 2000 includes a plurality of light-emitting platforms 200 arranged at intervals, wherein the light-emitting platforms 200 have a platform 202 and a side surface 201 connected to the platform 202;

[0042] An intermediate dielectric layer 300 and an intermediate metal layer 400 are sequentially stacked on the light-emitting platform 200, wherein the intermediate dielectric layer 300 is disposed on a surface of the intermediate metal layer 400 away from the light-emitting platform 200, wherein the intermediate dielectric layer 300 and the intermediate metal layer 400 at least cover the side surface 201, the intermediate dielectric layer 300 is used to regulate the phase of plasmon resonance, and the intermediate metal layer 400 is used to generate plasmons on the side surface 201.

[0043] The present invention utilizes the plasmon resonance effect caused by the interaction between light and metal to effectively increase the spontaneous radiation rate of carriers in the quantum well in the side 201 area of ​​the small-sized LED, improve the luminous efficiency and luminous intensity, meet the display panel's demand for high PPI, and improve imaging quality.

[0044] The present invention generates plasmons SPP through the intermediate metal layer 400, and performs phase adjustment through the intermediate dielectric layer 300, so that the wave vector of the surface plasmon matches the wave vector of the electron and hole plasma in the multi-quantum well layer 220, so that when they resonate, the plasma in the multi-quantum well layer 220 can transfer energy to the intermediate metal layer 400 at an extremely fast rate, and then radiate the energy through the intermediate metal layer 400, so as to enhance the spontaneous radiation rate and efficiency of the region, and improve the luminous efficiency of the LED.

[0045] In the present invention, the cross-sectional shape of the light-emitting platform 200 in the direction parallel to the epitaxial layer 2000 is circular or square; the cross-sectional shape in the direction perpendicular to the epitaxial layer 2000 is trapezoidal, wherein the side surface 201 and the platform 202 are arranged at an angle, and the angle ranges from 90° to 110°. The epitaxial wafer includes a stacked P-type semiconductor layer 210, a multi-quantum well layer 220, and an N-type semiconductor layer 230, and the N-type semiconductor layer 230 is arranged on the side close to the platform 202; in the embodiment of the present invention, the orthographic projection area of ​​the P-type semiconductor layer 210 on the surface of the epitaxial layer 2000 away from the platform 202 is greater than or equal to the orthographic projection area of ​​the N-type semiconductor layer 230 on the surface of the epitaxial layer 2000 away from the platform 202, and a good current blocking structure can be formed by increasing the area of ​​the P-type semiconductor layer 210, effectively expanding the injected current, so that the injected current will not be crowded in the N-type semiconductor layer 230, and the uniform distribution of the current is improved, thereby improving the luminous performance of the LED.

[0046] In an embodiment of the present invention, the N-type semiconductor layer 230 is an n-GaN layer; the thickness of the N-type semiconductor layer 230 is 1 to 2.5 μm; the multi-quantum well layer 220 includes alternately grown InGaN layers and GaN layers, and the total thickness of the multi-quantum well layer 220 is 30 to 100 nm; the P-type semiconductor layer 210 is a p-GaN layer, and the P-type semiconductor layer 210 includes an electron blocking layer and a hole injection layer, and the total thickness of the P-type semiconductor layer 210 is 10 to 30 nm.

[0047] Since the light-emitting stage 200 needs to be formed by etching, the existing etching process will introduce a large amount of etching damage on the side 201 of the light-emitting stage 200, and the etching damage will further increase as the size of the light-emitting stage 200 decreases and the specific surface area increases, resulting in a sudden drop in the external quantum efficiency and luminous intensity of the LED chip. In the present invention, the intermediate dielectric layer 300 is grown on the side 201 of the light-emitting stage 200, and the etching damage on the side 201 of the light-emitting stage 200 can also be repaired, further improving the luminous intensity and luminous uniformity.

[0048] In addition, since there is dispersion in media with different refractive indices for a given light frequency, and SPP and plasma have different dispersion relations, resulting in a mismatch in the wave vectors of SPP and plasma, the phase of the plasmon resonance is regulated by the intermediate dielectric layer 300 so that the SPP can satisfy the wave vector matching and phase matching with the quantum well of the light-emitting stage 200 when passing through the intermediate dielectric layer 300, thereby forming a strong coupling through resonance.

[0049] In order to effectively excite surface plasmons, the present invention achieves phase matching between SPP and electron-hole plasma and strong coupling by making the refractive index of the intermediate dielectric layer 300 the same or nearly the same as the refractive index of the multi-quantum well layer 220. It should be noted that in this application, nearly the same means that an error within the range of 0 to 10% is allowed. Among them, the material of the intermediate dielectric layer 300 includes AlN, Al2O3, SiO2, SiN x The intermediate dielectric layer 300 preferably uses AlN having a refractive index close to that of the InGaN material of the multi-quantum well layer 220. In other embodiments, the material of the intermediate dielectric layer 300 is adjusted as needed to match the phase of the SPP and the plasma.

[0050] On the other hand, the intermediate dielectric layer 300 can also prevent the light emitted from the light emitting stage 200 from being totally reflected at the interface between the intermediate dielectric layer 300 and the light emitting stage 200 due to the difference in refractive index. By controlling the refractive index of the intermediate dielectric layer 300, the coupling efficiency of light-surface plasmon can be maximized by withdrawing a high concentration.

[0051] The thickness of the intermediate dielectric layer 300 is 5 to 15 nm; the intermediate metal layer 400 includes one or more of Au and Ag; the thickness of the intermediate metal layer 400 is 5 to 15 nm. The main factor affecting the surface plasmon effect is that for different radiation wavelengths, there are mutually matching coupling materials. In the present invention, the emission wavelength of the light-emitting stage 200 is controlled and adjusted according to the composition of In in the multi-quantum well layer 220. In this application, blue light and green light are preferably prepared. Of course, the same inventive concept can also be applied to GaN-based and GaAs red light systems.

[0052] According to the metal full-frequency dispersion relation of surface plasmon, when the frequency ω of light satisfies 0<ω<ω sp (ω sp When the short-wave limiting frequency of the surface plasmon SPP is exceeded, bound surface electromagnetic waves, namely surface plasmon SPP, can be induced on the metal-medium surface. The penetration depth of the SPP from the metal layer to the inner side of the table 202 is generally less than 30nm. Therefore, it can form a strong coupling with the quantum well within 30nm of the side 201 of the light-emitting table 200 to enhance the spontaneous radiation rate and efficiency of the light-emitting table 200 in this area.

[0053] According to the formula:

[0054]

[0055] Among them, ω sp is the short-wave limiting frequency of the surface plasmon SPP, ω p is the frequency of the plasma, ε d is the dielectric constant of the intermediate dielectric layer 300 .

[0056] Therefore, different surface plasmons SPP need to be induced for different wavelengths of light to achieve resonant coupling. For example, for the blue light band, for example, the light emitted by the light emitting stage 200 is blue light, the wavelength of the blue light is 450-480nm, the material of the intermediate metal layer 400 is Ag, and the wavelength of the plasmon generated by the side 201 is 450nm; for another example, for the green light band, the light emitted by the light emitting stage 200 is green light, the wavelength of the green light is 520-570nm, the material of the intermediate metal layer 400 is Au, and the wavelength of the plasmon generated by the side 201 is 560nm.

[0057] In the present invention, the LED chip further comprises a driving backplane 100, on which a pixel circuit for driving the LED chip to emit light is disposed. Figure 2-3 As shown, the LED chip also includes:

[0058] A first electrode layer 700 is arranged on the table 202 of the light-emitting table 200; the first electrode layer 700 is an ITO layer; a second electrode layer 800 is arranged on the surface of the epitaxial layer 2000 away from the table 202; a driving backplane 100 is arranged on the side of the second electrode layer 800 away from the table 202, and the second electrode layer 800 is electrically connected to the driving backplane 100.

[0059] The second electrode layer 800 includes a plurality of first metal contacts 810, and the orthographic projections of the first metal contacts 810 on the driving backplane 100 correspond one to one with the orthographic projections of the light-emitting table 200 on the driving backplane 100; the second electrode layer 800 may include one or more metal layers, for example, the second electrode layer 800 includes a stacked Pt layer, an Au layer, and a Sn layer, and the Sn layer is arranged on a side close to the second metal contact 110.

[0060] A bonding metal layer is arranged on the surface of the driving backplane 100 on one side close to the light-emitting table 200, and the bonding metal layer includes a plurality of second metal contacts 110. The orthographic projection of the second metal contacts 110 on the driving backplane 100 coincides with the orthographic projection of the first metal contacts 810 on the driving backplane 100. The second metal contacts 110 are bonded to the first metal contacts 810. For example, the bonding metal layer is an Al layer.

[0061] In an embodiment of the present invention, the intermediate dielectric layer 300 can be formed by depositing on the light-emitting table 200 using atomic layer evaporation (ALD), and the intermediate metal layer 400 can be formed by depositing on the intermediate dielectric layer 300 using electron beam evaporation. Specifically, the intermediate dielectric layer 300 and the intermediate metal layer 400 extend from the side 201 and cover the table 202, and the first electrode layer 700 is arranged on a side surface of the intermediate dielectric layer 300 away from the driving backplane 100; the intermediate dielectric layer 300 and the intermediate metal layer 400 are provided with vias 401 at positions corresponding to the table 202 and expose the table 202, and the first electrode layer 700 fills the vias 401.

[0062] The via hole 401 penetrates the intermediate metal layer 400 and the intermediate dielectric layer 300 on the table 202 of the light-emitting table 200 to expose the p-GaN layer on the table 202, wherein the intermediate metal layer 400 contacts the first electrode layer 700 at the position of the via hole 401, and in particular, can further contact above the table 202, that is, the intermediate metal layer 400 located above the table 202 contacts the first electrode layer 700, and the first electrode layer 700 is a p-electrode for hole injection, so that the intermediate metal layer 400 can be used as both a waveguide structure and an electrode layer of the LED. The purpose of this is to reduce the diffusion of the injection current and realize the excitation of surface plasmons at a lower injection current.

[0063] In the present invention, the LED chip further includes: an insulating layer 900 disposed on the surface of the epitaxial layer 2000 close to the driving backplane 100, and the surface of the insulating layer 900 on the side away from the driving backplane 100 is flush with the surface of the intermediate metal layer 400 on the side away from the driving backplane 100. The intermediate metal layer 400 on the table 202 of the light-emitting table 200 is exposed through the insulating layer 900, so that the intermediate metal layer 400 can contact the first electrode layer 700 above the table 202. In this way, the contact area between the intermediate metal layer 400 and the first electrode layer 700 can be increased.

[0064] In one embodiment of the present invention, Figure 4 As shown, the LED chip also includes: a shading block 1000 arranged between the light-emitting tables 200, the shading block 1000 includes a first shading portion 1010 located on the surface of the first electrode layer 700 away from the driving backplane 100 and a second shading portion 1020 located on the side of the first shading portion 1010 close to the driving backplane 100, the second shading portion 1020 extends from the surface of the first shading portion 1010 toward the driving backplane 100, and optionally, the surface of the second shading portion 1020 on the side close to the driving backplane 100 is flush with the surface of the P-type semiconductor on the side away from the driving backplane 100.

[0065] Among them, the material of the first shading portion 1010 and the second shading portion 1020 is preferably set to a metal material, for example, Cu, Al, Ag, Au; the metal material can achieve a shading function to prevent light crosstalk between the light-emitting stages 200 and reduce the divergence angle of the light-emitting stages 200. In addition, the metal material can contact the first electrode layer 700 to enhance the current diffusion and injection efficiency of the first electrode layer 700.

[0066] In this embodiment, the orthographic projection of the first light shielding portion 1010 on the driving backplane 100 at least covers the orthographic projection of the second light shielding portion 1020 on the driving backplane 100; the first electrode layer 700 is provided with a first groove 701 penetrating the first electrode layer 700, and the insulating layer 900 is provided with a second groove 901 partially passing through the insulating layer 900, optionally, the surface of the second groove 901 on the side close to the driving backplane 100 is flush with the surface of the P-type semiconductor 210 on the side away from the driving backplane 100; the second light shielding portion 1020 is filled in the first groove 701 and the second groove 901.

[0067] In another aspect of the present invention, the present invention also provides a method for preparing an LED chip, the method comprising:

[0068] S100: forming a GaN-based epitaxial layer, specifically including:

[0069] S110: Provide a substrate 500, wherein the specific type of the substrate 500 can be a sapphire substrate, a silicon substrate, an n-type doped silicon carbide substrate or an n-type doped gallium nitride substrate. Those skilled in the art can flexibly select a suitable substrate type according to the specific structural type of the LED chip.

[0070] In some embodiments, after the substrate is cleaned and decontaminated, a buffer layer with a thickness of 10 to 100 nm may be grown thereon. The material of the buffer layer may be aluminum nitride or aluminum gallium nitride, which may be deposited by physical vapor deposition (PVD). The material of the buffer layer may also be gallium nitride, and a portion of the undoped GaN layer 600 may be used as the buffer layer.

[0071] S120: growing an undoped GaN layer 600 on the surface of the substrate 500; the undoped GaN layer 600 (un-intentionally doped GaN, u-GaN) refers to a gallium nitride layer that does not include any dopant but may include contaminants or impurities that are not intentionally incorporated into the film, serving as the bulk layer of the N-type GaN layer to be epitaxially grown in the next step. The thickness of the undoped GaN layer 600 is 3 to 4 μm; specifically, it can be epitaxially grown using MOCVD (Metal Organic Chemical Vapor Deposition, a high-purity chemical vapor deposition technology used to prepare semiconductor materials and devices) equipment.

[0072] S130: growing an epitaxial layer 2000 on the non-doped GaN layer 600, wherein the epitaxial layer 2000 comprises an N-type semiconductor layer 230, a multi-quantum well layer 220, and a P-type semiconductor layer 210 sequentially grown on the substrate 500; the N-type semiconductor layer 230 may be a Si-doped n-GaN layer, wherein the Si doping concentration is 1018 cm -3 ~10 19 cm -3 The thickness of the N-type semiconductor layer 230 is 1 to 2.5 μm; the multi-quantum well layer 220 includes 5 to 8 periods of alternately grown InGaN layers and GaN layers, and the total thickness of the multi-quantum well layer 220 is 30 to 100 nm; the P-type semiconductor layer 210 is a Mg-doped p-GaN layer, and the P-type semiconductor layer 210 includes an electron blocking layer and a hole injection layer, and the total thickness of the P-type semiconductor layer 210 is 10 to 30 nm.

[0073] After the epitaxial layer growth is completed, ultrasonic treatment is performed in acetone solution for 10 minutes, and then rinsed with deionized water for 15 minutes to make the surface of the epitaxial layer clean. Figure 5 shown.

[0074] S200: forming a metal contact on the epitaxial layer, specifically including:

[0075] S210: forming a second electrode layer 800 on the surface of the epitaxial layer 2000 away from the substrate 500; the second electrode layer 800 may include one or more layers of metal, for example, a Pt layer and an Au layer are sequentially formed on the substrate 500 by electron beam evaporation, and the thicknesses are 100nm and 300nm respectively; and a Sn layer is formed on the Au layer by thermal evaporation, and the Sn layer is arranged on the side away from the substrate 500, and the thickness of the Sn layer is 200nm.

[0076] S220: A plurality of first metal contacts 810 are formed on the second electrode layer 800. The cross-sectional shape of the first metal contact 810 parallel to the driving backplane 100 may be circular. The orthographic projection of the first metal contact 810 on the driving backplane 100 corresponds one-to-one to the orthographic projection of the light-emitting table 200 on the driving backplane 100. For example, the diameter of the first metal contact 810 is less than 9 μm, and the spacing between the center points of two adjacent first metal contacts 810 is less than 10 μm, and the spacing between the center points of two adjacent first metal contacts 810 is kept greater than the diameter thereof, for example, the diameter may be 3 μm, and the spacing may be 8 μm. The photoresist on other areas except the retained area may be dissolved by an acetone solution, thereby stripping off the multi-layer metal layers on other areas to form the first metal contact 810. By rapid thermal annealing in an oxygen atmosphere for 3 to 5 minutes to form a good ohmic contact, the prepared structure is as follows Figure 6 shown.

[0077] S310: providing a driving backplane, wherein the driving backplane 100 is a CMOS substrate, which may be made of glass, PI, etc.

[0078] S320: forming a bonding metal layer on the surface of the driving backplane 100 . The bonding metal layer may be an Al layer, and may be formed on the driving backplane 100 by electron beam evaporation.

[0079] S330: A plurality of second metal contacts 110 are formed on the bonding metal layer through an etching process, wherein the shapes of the second metal contacts 110 match the shapes and positions of the first metal contacts 810 , and the orthographic projections of the second metal contacts 110 on the driving backplane 100 coincide with the orthographic projections of the first metal contacts 810 on the driving backplane 100 .

[0080] S400: Bond the second metal contact 110 to the first metal contact 810 by eutectic bonding to bond the epitaxial layer to the driver backplane 100. Align the structure prepared in step S220 with the IC driver board with the driver circuit and bond the first metal contact 810 to the second metal contact 110 by eutectic bonding technology. The bonding temperature is 200-300°C. After bonding, anneal at 400°C for 5-10 minutes to strengthen the metal. The structure after preparation is as shown in FIG. Figure 7 (a) shown.

[0081] S500: forming a plurality of light-emitting platforms 200 arranged at intervals on the driving backplane 100, wherein the light-emitting platforms 200 include a platform 202 away from the driving backplane 100 and a side surface 201 connected to the platform 202. Specifically, the steps include:

[0082] S510: In some embodiments, the substrate 500 is a sapphire substrate, and the substrate 500 in the GaN-based epitaxial layer bonded to the driving backplane 100 is removed by femtosecond pulse laser stripping; the substrate 500 in the structure prepared in S400 is removed by femtosecond pulse laser with a wavelength of 260nm.

[0083] S520: Remove the non-doped GaN layer 600 by chemical mechanical polishing to expose the n-GaN on the epitaxial layer 2000, and obtain a substrate-free GaN-based LED epitaxial layer bonded to the driving backplane. The structure after preparation is as follows Figure 7 (b) as shown.

[0084] S530: Etching the epitaxial layer 2000 to form a plurality of the light-emitting tables 200 that are spaced apart. For example, the light-emitting table 200 (Mesa) is prepared by using a photolithography process and a plasma (ICP-RIE) etching process in sequence. The cross-sectional shape of the light-emitting table 200 in a direction parallel to the substrate can be circular or square, and the diameter of the circle or the side length of the square is preferably 500 to 3000 nm. The inclination angle of the side 201 of the light-emitting table 200 can be controlled by controlling the gas ratio of ICP-RIE, the ICP power, etc. The side 201 is arranged at an angle with the driving backplane 100, and the angle ranges from 70° to 90°. The structure after preparation is as follows Figure 8 (a) shown.

[0085] S600: sequentially growing an intermediate metal layer 400 and an intermediate dielectric layer 300 on the light-emitting platform 200, wherein the intermediate dielectric layer 300 is disposed on a side surface of the intermediate metal layer 400 away from the light-emitting platform 200, wherein the intermediate dielectric layer 300 and the intermediate metal layer 400 at least cover the side surface 201, the intermediate dielectric layer 300 is used to adjust the phase of plasmon resonance, and the intermediate metal layer 400 is used to generate plasmons on the side surface 201. Specifically comprising:

[0086] S610: Depositing the intermediate dielectric layer 300 on the side surface 201 and the table surface 202 of the light-emitting platform 200 by atomic layer evaporation; the material of the intermediate dielectric layer 300 includes AlN, Al2O3, SiO2, SiN x The intermediate dielectric layer 300 preferably uses AlN with a refractive index close to that of the InGaN material of the multi-quantum well layer 220, and the deposition thickness of AlN is 5 to 15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, and 15 nm. The structure after preparation is as follows Figure 8 (b) as shown.

[0087] S620: Deposit the intermediate metal layer 400 on the surface of the intermediate dielectric layer 300 by electron beam evaporation, the thickness of the intermediate metal layer 400 is 5-15nm; if the light emitted by the light emitting platform 200 is blue light, the wavelength of the blue light is 450-480nm, the intermediate metal layer 400 is made of Ag, the wavelength of the plasmon generated by the side 201 is 450nm, and a 5nm Ag layer is deposited on the intermediate dielectric layer 300 by electron beam evaporation technology; or if the light emitted by the light emitting platform 200 is green light, the wavelength of the green light is 520-570nm, the intermediate metal layer 400 is made of Au, the wavelength of the plasmon generated by the side 201 is 560nm, and a 5nm Au layer is deposited on the intermediate dielectric layer 300 by electron beam evaporation technology. The structure after preparation is as follows Figure 8 (c) as shown.

[0088] S700: An insulating layer 900 is formed on the surface of the driving backplane 100; the material of the insulating layer 900 may be silicon nitride or silicon oxide. The insulating layer 900 may be grown between adjacent light-emitting stages 200 on the driving backplane 100 by plasma enhanced chemical vapor deposition (PECVD) with a thickness of 1 to 2.6 μm. The insulating layer 900 on the top of the stage 202 is removed by an etching process, so that the surface of the insulating layer 900 on the side away from the driving backplane 100 is flush with the surface of the intermediate metal layer 400 on the side away from the driving backplane 100.

[0089] S800: Remove at least part of the intermediate metal layer 400 and the intermediate dielectric layer 300 on the table 202 to form a via 401 exposing the table 202; the intermediate metal layer 400 and the intermediate dielectric layer 300 above the table 202 can be removed by photolithography and ICP etching processes to form a via 401 above the light-emitting table 200 to expose the p-GaN on the table 202 for subsequent preparation of the first electrode layer 700. The shape and size of the via 401 are determined according to the shape and size of the light-emitting table 200. For example, the cross-sectional shape of the first via 401 in the direction parallel to the substrate is circular or square, and the size of the first via 401 can be 60% to 80% of the size of the light-emitting table 200. The structure after preparation is as shown below. Fig. 9 (a) shown.

[0090] S900: Form a first electrode layer 700 on the surface of the intermediate dielectric layer 300 and the insulating layer 900, and the first electrode layer 700 fills the via hole 401. The material of the first electrode layer 700 is ITO, and the second electrode layer 800 is deposited on the surface of the intermediate dielectric layer 300 and the insulating layer 900 and in the via hole 401 by using a photolithography process and a magnetron sputtering process. The thickness of the second electrode layer 800 on the surface of the intermediate dielectric layer 300 and the insulating layer 900 is 100 to 500 nm. After the ITO deposition is completed, it is immediately subjected to rapid thermal annealing in an oxygen atmosphere for 3 to 5 minutes to improve the conductivity. The structure after preparation is as follows Fig. 9 (b) as shown.

[0091] In an optional embodiment, the method for preparing the LED chip further includes:

[0092] S1000: forming a light shielding block 1000 on the insulating layer 900. Specifically comprising:

[0093] S1010: A first groove 701 penetrating the second electrode layer 800 and a second groove 901 penetrating a portion of the insulating layer 900 are formed on the second electrode layer 800 and the insulating layer 900 corresponding to the light-emitting platform 200 by etching, wherein the surface of the second groove 901 on the side close to the driving backplane 100 is flush with the surface of the P-type semiconductor on the side away from the driving backplane 100; the first groove 701 and the second groove 901 are formed by the same etching process, and the diameter of the first groove 701 is the same as the diameter of the second groove 901, for example, the diameter is 1 to 3 μm. The structure after preparation is as shown in FIG. Fig.10 (a) shown.

[0094] S1020: forming a light shielding block 1000 on the surface of the first electrode layer 700; the material of the first light shielding portion 1010 and the second light shielding portion 1020 is a metal material, such as Al; depositing an Al layer by photolithography and electron beam evaporation to form a first light shielding portion 1010 located on the surface of the first electrode layer 700 away from the driving backplane 100 and a second light shielding portion 1020 filled in the first groove 701 and the second groove 901, the orthographic projection of the first light shielding portion 1010 on the driving backplane 100 at least covers the orthographic projection of the second light shielding portion 1020 on the driving backplane 100, the diameter of the first light shielding portion 1010 is 5μm, and the thickness is 0.5 to 3μm. The structure after preparation is as follows Fig.10 (b) as shown.

[0095] The LED chip in the present invention may be a micro light emitting diode (Micro Light Emitting Diode Display, Micro LED) chip, or a nano light emitting diode (Nano-Pixel Light-Emitting Display, NanoLED) chip.

[0096] It should be noted that the above materials and values ​​are set only to facilitate those skilled in the art to fully implement this embodiment, and they can be adjusted accordingly according to actual needs. Those skilled in the art should know that any obvious conventional material replacement and value change are within the protection scope of this embodiment.

[0097] In another aspect of the present invention, the present invention further provides a display device, comprising an LED chip as described in any one of the above or an LED chip prepared by any one of the above methods. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a wearable device, a car display, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0098] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0099] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0100] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. An LED chip, characterized in that: include: An epitaxial layer, the epitaxial layer comprising a plurality of light-emitting platforms arranged at intervals, the light-emitting platforms having a platform and a side surface connected to the platform; An intermediate dielectric layer and an intermediate metal layer are sequentially stacked on the light-emitting platform, wherein the intermediate dielectric layer is arranged on a surface of the intermediate metal layer away from the light-emitting platform, wherein the intermediate dielectric layer and the intermediate metal layer at least cover the side surface, the intermediate dielectric layer is used to regulate the phase of plasmon resonance, and the intermediate metal layer is used to generate plasmons on the side surface.

2. The LED chip according to claim 1, characterized in that: The epitaxial layer includes a stacked P-type semiconductor layer, a multi-quantum well layer, and an N-type semiconductor layer, wherein the N-type semiconductor layer is arranged on a side close to the mesa; The N-type semiconductor layer is an n-GaN layer; the thickness of the N-type semiconductor layer is 1 to 2.5 μm; The multi-quantum well layer comprises an InGaN layer and a GaN layer grown alternately, and the total thickness of the multi-quantum well layer is 30 to 100 nm; The P-type semiconductor layer is a p-GaN layer, the P-type semiconductor layer comprises an electron blocking layer and a hole injection layer, and the total thickness of the P-type semiconductor layer is 10-30 nm.

3. The LED chip according to claim 1, characterized in that: The side surface and the table top are arranged at an angle, and the angle ranges from 90° to 110°.

4. The LED chip according to claim 2, characterized in that: The refractive index of the intermediate dielectric layer is the same as or nearly the same as the refractive index of the multi-quantum well layer; The material of the intermediate dielectric layer includes AlN, Al2O3, SiO2, SiN x One or more of; The thickness of the intermediate dielectric layer is 5 to 15 nm; The intermediate metal layer includes one or more of Au and Ag; The thickness of the intermediate metal layer is 5-15 nm.

5. The LED chip according to claim 4, characterized in that: The wavelength of the light emitted by the light emitting platform is 450-480nm, the material of the intermediate metal layer is Ag, and the wavelength of the plasmon generated by the side surface is 450nm; or The wavelength of the light emitted by the light emitting platform is 520-570 nm, the material of the intermediate metal layer is Au, and the wavelength of the plasmon generated by the side surface is 560 nm.

6. The LED chip according to claim 2, characterized in that: Also includes: A first electrode layer disposed on the table; as well as A second electrode layer is disposed on a surface of the epitaxial layer away from the mesa; A driving backplane is arranged on a side of the second electrode layer away from the mesa, and the second electrode layer is electrically connected to the driving backplane.

7. The LED chip according to claim 6, characterized in that: The second electrode layer includes a plurality of first metal contacts, and the orthographic projections of the first metal contacts on the driving backplane correspond one to one with the orthographic projections of the light-emitting platform on the driving backplane; The driving backplane has a bonding metal layer on a surface of one side close to the light-emitting table, the bonding metal layer includes a plurality of second metal contacts, the orthographic projection of the first metal contact on the driving backplane coincides with the second metal contact, and the second metal contact is bonded to the first metal contact.

8. The LED chip according to claim 7, characterized in that: The first electrode layer is an ITO layer; The second electrode layer includes a stacked Pt layer, an Au layer, and a Sn layer, wherein the Sn layer is disposed on a side close to the second metal contact; The bonding metal layer is an Al layer.

9. The LED chip according to claim 6, characterized in that: The intermediate dielectric layer and the intermediate metal layer extend from the side surface and cover the table surface, and the first electrode layer is arranged on a surface of the intermediate dielectric layer away from the driving substrate; The intermediate dielectric layer and the intermediate metal layer are provided with vias at positions corresponding to the mesas to expose the mesas, and the first electrode layer fills the vias.

10. The LED chip according to claim 6, characterized in that: The intermediate metal layer and the intermediate dielectric layer extend from the side surface and cover the table surface, and the LED chip further includes: An insulating layer is disposed on a surface of the epitaxial layer close to the driving backplane, and a surface of the insulating layer on a side away from the driving backplane is flush with a surface of the intermediate metal layer on a side away from the driving backplane.

11. The LED chip according to claim 10, characterized in that: Also includes: A shading block is arranged between the light-emitting tables, and the shading block includes a first shading portion located on the surface of the first electrode layer on a side away from the driving backplane, and a second shading portion extending from the surface of the first shading portion toward the driving backplane, and the orthographic projection of the first shading portion on the driving backplane at least covers the orthographic projection of the second shading portion on the driving backplane.

12. The LED chip according to claim 11, characterized in that: The surface of the second light shielding portion on the side close to the driving backplane is flush with the surface of the P-type semiconductor on the side away from the driving backplane; The first electrode layer is provided with a first groove penetrating the first electrode layer, the insulating layer is provided with a second groove partially penetrating the insulating layer, and the second light shielding portion is filled in the first groove and the second groove.

13. A method for preparing an LED chip, characterized in that: The method comprises: growing an epitaxial layer; forming a plurality of light-emitting platforms spaced apart from each other on the epitaxial layer, wherein the light-emitting platforms have a platform and a side surface connected to the platform; An intermediate metal layer and an intermediate dielectric layer are sequentially grown on the light-emitting platform, wherein the intermediate dielectric layer is arranged on a surface of the intermediate metal layer on a side away from the light-emitting platform, wherein the intermediate dielectric layer and the intermediate metal layer at least cover the side surface, the intermediate dielectric layer is used to regulate the phase of plasmon resonance, and the intermediate metal layer is used to generate plasmons on the side surface.

14. The method according to claim 13, characterized in that The growing epitaxial layer comprises: Providing a substrate, wherein the material of the substrate includes any one of sapphire, silicon, gallium nitride, gallium oxide or silicon carbide; growing an undoped GaN layer on the surface of the substrate; An epitaxial layer is grown on the undoped GaN layer, and the epitaxial layer includes an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer grown in sequence on a substrate; the N-type semiconductor layer is an n-GaN layer; the thickness of the N-type semiconductor layer is 1 to 2.5 μm; the multi-quantum well layer includes an InGaN layer and a GaN layer grown alternately, and the total thickness of the multi-quantum well layer is 30 to 100 nm; the P-type semiconductor layer is a p-GaN layer, and the P-type semiconductor layer includes an electron blocking layer and a hole injection layer, and the total thickness of the P-type semiconductor layer is 10 to 30 nm.

15. The method according to claim 14, characterized in that The method further comprises: A second electrode layer is formed on a surface of the epitaxial layer away from the substrate; the second electrode layer comprises a stacked Pt layer, an Au layer, and a Sn layer, and the Sn layer is arranged on a side away from the substrate; A plurality of first metal contacts are formed on the second electrode layer, and the orthographic projections of the first metal contacts on the substrate correspond one-to-one to the orthographic projections of the light-emitting platform on the substrate.

16. The method according to claim 15, characterized in that The method further comprises: Providing a driving backplane; the driving backplane is a CMOS substrate; Forming a bonding metal layer on the surface of the driving backplane, wherein the bonding metal layer is an Al layer; forming a plurality of second metal contacts on the bonding metal layer, wherein the orthographic projections of the second metal contacts on the driving backplane coincide with the orthographic projections of the first metal contacts on the driving backplane; The second metal contact is bonded to the first metal contact by eutectic bonding, so that the epitaxial layer is bonded to the driving backplane.

17. The method according to claim 14, characterized in that The step of forming a plurality of light-emitting platforms spaced apart from each other on the epitaxial layer comprises: removing the substrate on the epitaxial layer by femtosecond pulse laser lift-off; Removing the non-doped GaN layer by chemical mechanical polishing; The epitaxial layer is etched to form a plurality of light-emitting platforms that are spaced apart from each other, and the side surfaces are arranged at an angle with the platform surface, and the angle ranges from 90° to 110°.

18. The method according to claim 13, characterized in that The intermediate metal layer and the intermediate dielectric layer are sequentially grown on the light-emitting platform, and the method comprises: Depositing the intermediate dielectric layer on the side and top of the light-emitting platform by atomic layer evaporation; Depositing the intermediate metal layer on the surface of the intermediate dielectric layer by electron beam evaporation; optionally, The wavelength of the light emitted by the light emitting platform is 450-480nm, the material of the intermediate metal layer is Ag, and the wavelength of the plasmon generated by the side surface is 450nm; or The wavelength of the light emitted by the light emitting platform is 520-570 nm, the material of the intermediate metal layer is Au, and the wavelength of the plasmon generated by the side surface is 560 nm.

19. The method according to claim 16, characterized in that The intermediate metal layer and the intermediate dielectric layer extend from the side surface and cover the table surface, and the method further includes: An insulating layer is formed on a surface of the epitaxial layer close to the driving backplane, wherein a surface of the insulating layer on a side away from the driving backplane is flush with a surface of the intermediate metal layer on a side away from the driving backplane; removing at least a portion of the intermediate metal layer and the intermediate dielectric layer on the mesa to form a via hole exposing the mesa; A first electrode layer is formed on the surfaces of the intermediate dielectric layer and the insulating layer, and the first electrode layer fills the via hole.

20. The method according to claim 19, characterized in that The method further comprises: A first groove penetrating the second electrode layer and a second groove penetrating a portion of the insulating layer are formed on the second electrode layer and the insulating layer corresponding to the light-emitting stages by etching, wherein the surface of the second groove on the side close to the driving backplane is flush with the surface of the P-type semiconductor on the side away from the driving backplane; A light shielding block is formed on the surface of the first electrode layer, and the light shielding block includes a first light shielding portion located on the surface of the first electrode layer on a side away from the driving backplane, and a second light shielding portion filled in the first groove and the second groove, and the orthographic projection of the first light shielding portion on the driving backplane at least covers the orthographic projection of the second light shielding portion on the driving backplane; the first light shielding portion and the second light shielding portion are metal.

21. A display device, characterized in that: The invention comprises an LED chip according to any one of claims 1 to 12 or an LED chip prepared by the method according to any one of claims 13 to 20.

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