Wiring substrate, preparation method thereof and display device

Abstract

The invention discloses a wiring substrate, a preparation method thereof and a display device, which are used for preventing a fan-out region electrode from being corroded. The wiring substrate provided by the embodiment of the invention comprises the components of a substrate which comprises a fan-out region; the plurality of first electrodes are positioned on one side of the substrate; the first protection layer is positioned on one side, deviating from the substrate, of the plurality of first electrodes and comprises a plurality of first openings penetrating through the thickness of the first protection layer; each first opening in the plurality of first openings corresponds to one first electrode, and the orthographic projection of the first opening on the substrate is overlapped with the orthographic projection of the first electrode on the substrate; the first protective layer at least covers the side surface of the first electrode.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a wiring substrate and a preparation method thereof, and a display device. Background Art

[0002] Micro light-emitting diodes are increasingly being used in the display field due to their smaller size, ultra-high brightness, and long life. Summary of the invention

[0003] The embodiments of the present disclosure provide a wiring substrate and a method for manufacturing the same, and a display device, so as to prevent electrodes in a fan-out area from being corroded.

[0004] The present disclosure provides a wiring substrate, the wiring substrate comprising:

[0005] A substrate base plate, including a fan-out region;

[0006] A plurality of first electrodes are located on one side of the substrate;

[0007] The first protective layer is located on the side of the multiple first electrodes away from the substrate, and includes multiple first openings that penetrate its thickness; each of the multiple first openings corresponds to a first electrode, and the orthographic projection of the first opening on the substrate overlaps with the orthographic projection of the first electrode on the substrate; the first protective layer at least covers the side surfaces of the first electrode.

[0008] In some embodiments, an orthographic projection of the first opening on the substrate falls within an orthographic projection of the first electrode on the substrate.

[0009] In some embodiments, the wiring substrate further comprises:

[0010] A plurality of anti-oxidation layers are located on a side of the plurality of first electrodes away from the base substrate; each of the plurality of anti-oxidation layers is electrically connected to a first electrode of the plurality of first electrodes; and the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

[0011] In some embodiments, an orthographic projection of the first opening on the base substrate falls within an orthographic projection of the anti-oxidation layer on the base substrate;

[0012] Furthermore, the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the edge of the first protection layer at the first opening on the base substrate.

[0013] In some embodiments, the wiring substrate further comprises:

[0014] The second protection layer is located on the side of the first protection layer away from the base substrate, and comprises a second opening; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second opening on the base substrate.

[0015] In some embodiments, an orthographic projection of the anti-oxidation layer on the base substrate falls within an orthographic projection of the second opening on the base substrate.

[0016] In some embodiments, the wiring substrate further comprises:

[0017] The second protection layer is located on the side of the first protection layer away from the first conductive layer, and includes a plurality of second openings penetrating through the thickness thereof; the orthographic projection of the second openings on the substrate falls within the orthographic projection of the first electrode on the substrate.

[0018] In some embodiments, the second opening and the first opening are formed in the same patterning process.

[0019] In some embodiments, at the first opening and the second opening, the anti-oxidation layer covers the side surfaces of the first protection layer and the side surfaces of the second protection layer.

[0020] In some embodiments, at the contact point between the anti-oxidation layer and the second protective layer, a surface of the anti-oxidation layer away from the substrate and a surface of the second protective layer away from the substrate are located in the same plane.

[0021] In some embodiments, the first electrode has a first surface facing away from the substrate; and a distance between an edge of the first opening and an edge of the first surface is greater than or equal to 8 micrometers and less than or equal to 9 micrometers.

[0022] In some embodiments, the wiring substrate further comprises:

[0023] A plurality of second electrodes are located between the base substrate and the plurality of first electrodes in the fan-out region; each of the plurality of second electrodes is electrically connected to the first electrode, and an orthographic projection of the second electrode on the base substrate overlaps an orthographic projection of the first electrode on the base substrate;

[0024] A first insulating layer is located between the base substrate and the plurality of second electrodes; the first insulating layer includes a plurality of third openings penetrating the thickness thereof; the orthographic projections of the third openings on the base substrate fall within the orthographic projections of the first electrodes on the base substrate, and the orthographic projections of the third openings on the base substrate fall within the orthographic projections of the second electrodes on the base substrate;

[0025] The second insulating layer is located on the side of the first insulating layer away from the base substrate; the first insulating layer includes a plurality of fourth openings extending through its thickness; the orthographic projection of the third opening on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, and the orthographic projection of the second electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate; the first electrode is electrically connected to the second electrode at the fourth opening and the third opening.

[0026] The present disclosure provides a method for preparing a wiring substrate, the method comprising:

[0027] Providing a substrate substrate; the substrate substrate includes a fan-out region;

[0028] forming a plurality of first electrodes in a fan-out region of the base substrate;

[0029] A first protective layer is formed on a side of the plurality of first electrodes facing away from the base substrate, and the first protective layer is patterned to form a plurality of first openings penetrating the thickness thereof; each of the plurality of first openings corresponds to a first electrode, and the orthographic projection of the first opening on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate, and the first protective layer at least covers the side surfaces of the first electrode.

[0030] In some embodiments, after patterning the first protective layer to form a plurality of first openings penetrating the first protective layer, the method further includes:

[0031] An anti-oxidation layer is formed on the side of each first electrode away from the base substrate by chemical plating process; the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

[0032] In some embodiments, after patterning the first protection layer to form a plurality of first openings penetrating the first protection layer and before forming the anti-oxidation layer, the method further includes:

[0033] forming a second protective layer on a side of the first protective layer away from the substrate;

[0034] The second protection layer is patterned to form a plurality of second openings penetrating the thickness thereof; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second opening on the base substrate.

[0035] In some embodiments, before patterning the first protection layer to form a plurality of first openings penetrating the first protection layer, the method further includes:

[0036] forming a second protective layer on a side of the first protective layer away from the substrate;

[0037] The first protective layer is subjected to a patterning process to form a plurality of first openings penetrating the thickness thereof, specifically comprising:

[0038] The second protection layer and the first protection layer are subjected to a patterning process to form a plurality of second openings penetrating the second protection layer and a plurality of first openings penetrating the first protection layer.

[0039] In some embodiments, before forming a plurality of first electrodes in the fan-out region of the substrate, the method further comprises:

[0040] forming a plurality of second electrodes in the fan-out region of the base substrate;

[0041] A pattern of a first insulating layer is formed on a side of the plurality of second electrodes away from the base substrate; the first insulating layer includes a plurality of third openings penetrating the thickness thereof; the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the second electrode on the base substrate;

[0042] A pattern of a second insulating layer is formed on the side of the first insulating layer facing away from the base substrate; the orthographic projection of the third opening on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, and the orthographic projection of the second electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate.

[0043] An embodiment of the present disclosure provides a light-emitting substrate, which includes the wiring substrate provided by the embodiment of the present disclosure and a light-emitting device bound to the wiring substrate.

[0044] In some embodiments, the light emitting device is a micro-sized inorganic electroluminescent device.

[0045] An embodiment of the present disclosure provides a display device, and the display device includes the light-emitting substrate provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A schematic diagram of the structure of a wiring substrate provided for related technology;

[0048] Figure 2 A schematic diagram of the structure of a wiring substrate provided in an embodiment of the present disclosure;

[0049] Figure 3 A schematic diagram of the structure of another wiring substrate provided in an embodiment of the present disclosure;

[0050] Figure 4 A schematic diagram of the structure of another wiring substrate provided in an embodiment of the present disclosure;

[0051] Figure 5 The embodiments of the present disclosure provide Figure 4 Schematic diagram of the enlarged structure of the D region in the middle;

[0052] Figure 6 The embodiments of the present disclosure provide Figure 4 Schematic diagram of the enlarged structure of the middle E region;

[0053] Figure 7 A schematic diagram of the structure of another wiring substrate provided in an embodiment of the present disclosure;

[0054] Figure 8 A schematic diagram of the structure of another wiring substrate provided in an embodiment of the present disclosure;

[0055] Fig. 9 A schematic diagram of the structure of another wiring substrate provided in an embodiment of the present disclosure;

[0056] Fig.10 A schematic diagram of the structure of another wiring substrate provided in an embodiment of the present disclosure;

[0057] Fig.11 A schematic diagram of the structure of another wiring substrate provided in an embodiment of the present disclosure;

[0058] Fig.12 A schematic diagram of the structure of another wiring substrate provided in an embodiment of the present disclosure;

[0059] Fig.13 A method provided in the embodiment of the present disclosure Figure 5 Cross-sectional view of GG';

[0060] Fig.14 Another embodiment of the present disclosure provides Figure 5 Cross-sectional view of GG';

[0061] Fig.15 A method provided in the embodiment of the present disclosure Figure 5 Cross-sectional view of JJ';

[0062] Fig.16 Another embodiment of the present disclosure provides Figure 5 Cross-sectional view of JJ';

[0063] Fig.17 A schematic diagram of a process for preparing a wiring substrate provided in an embodiment of the present disclosure;

[0064] Fig.18 A schematic structural diagram of a light-emitting substrate provided in an embodiment of the present disclosure;

[0065] Fig.19 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0068] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0069] In related technologies, such as Figure 1As shown, the wiring substrate includes: an electrode structure 01 bound to a circuit board and arranged on one side of a substrate 06, and a protective layer 02 covering the electrode structure 01; the electrode structure 01 includes a lower electrode 011 and an upper electrode 012 connected to the lower electrode 011, and the protective layer 02 has a relatively large opening to expose the surface of the upper electrode 011, and the wiring substrate also includes a first insulating film layer 03, a second insulating film layer 04 and a third insulating film layer 05 located between the upper electrode 012 and the upper electrode 011. In order to ensure the electrical connection effect between the circuit board and the electrode structure 01, the opening of the protective layer 02 usually completely exposes the surface of the upper electrode 012, that is, the protective layer 02 does not cover the upper electrode 012. The upper electrode 012 is usually a stacked structure, for example, including a copper layer directly in contact with the lower electrode 011, and a molybdenum-niobium alloy layer located on the side of the copper layer away from the lower electrode 011. In addition, the wiring substrate also includes a plurality of pads arranged in the same layer as the upper electrode 012, that is, the pads also include a copper layer and a molybdenum-niobium alloy layer, and the surfaces of the plurality of pads also need to be exposed by the opening of the protective layer 02, so that the pads can be connected to the pins of other components through solder. Therefore, the surface of the pad exposed by the opening of the protective layer 02 needs to be solderable, and the molybdenum-niobium alloy layer only has an anti-oxidation function and has poor solderability. Before welding, the molybdenum-niobium alloy layer needs to be removed to ensure that the pads can be reliably connected to the components through solder. Therefore, in the process of manufacturing the wiring substrate, in the process of manufacturing the opening of the protective layer 02, in some cases, in order to take into account the reliability of other areas of the wiring substrate, it is necessary to perform an over-etching process on the protective layer 02; in this process, not only the molybdenum-niobium alloy layer is removed in the area where the upper electrode 012 is exposed by the opening, but also a portion of the first insulating film layer 03 and the second insulating film layer 04 under the protective layer 02 will be etched away, that is, Figure 1 In area A, the protective layer 02 is completely removed and a portion of the first insulating film layer 03 and the second insulating film layer 04 are etched away. Since this area lacks the protection of the protective layer 02, water vapor can easily invade along the interface between the upper electrode 012 and the first insulating film layer 03, and can also easily invade along the second insulating film layer 04 to corrode the lower electrode 011.

[0070] The present disclosure provides a wiring substrate. Figure 2 , Figure 3 As shown, the wiring substrate includes:

[0071] The substrate 1 includes a fan-out region 101;

[0072] A plurality of first electrodes 2 are located on one side of the base substrate 1;

[0073] The first protective layer 3 is located on the side of the multiple first electrodes 2 away from the base substrate 1, and includes multiple first openings 301 running through its thickness; each first opening 301 of the multiple first openings 301 corresponds to a first electrode 2, and the orthographic projection of the first opening 301 on the base substrate 1 overlaps with the orthographic projection of the first electrode 2 on the base substrate 1; the first protective layer 3 at least covers the side surface 201 of the first electrode 2.

[0074] In the wiring substrate provided by the embodiment of the present disclosure, the first protective layer at least covers the side surfaces of the first electrode, that is, the first opening does not expose the entire area of ​​the first electrode. By setting a smaller first opening so that the first protective layer can protect the side surfaces of the first electrode, corrosion caused by the invasion of water vapor from the side surfaces of the first electrode can be avoided, thereby avoiding affecting the yield of the wiring substrate.

[0075] It should be noted that if Figure 2 , Figure 3 As shown, the first electrode 201 further has a second surface 202 facing the substrate 1 and a first surface 203 facing away from the substrate 1 , and the side surface 201 of the first electrode 2 connects the second surface 202 and the first surface 203 .

[0076] In some embodiments, Figure 4 As shown, in the fan-out region 10 , a plurality of first electrodes 2 are arranged along the first direction X; the number of first openings 301 is equal to the number of first electrodes 2 , and one first opening 301 corresponds to one first electrode 2 ; that is, the plurality of first openings 301 are also arranged along the first direction X.

[0077] It should be noted that Figure 2 For example, along Figure 4 The cross-sectional view of BB', Figure 3 For example, along Figure 4 Cross-sectional view of CC'.

[0078] In a specific implementation, the plurality of first electrodes are used to bind to a circuit board, that is, the plurality of first electrodes serve as signal input terminals of the wiring substrate. The circuit board is, for example, a flexible circuit board or a printed circuit board.

[0079] In some embodiments, Figure 4 As shown, the substrate 1 further includes: a pad area 102, and a first peripheral area 103 and a second peripheral area 104 respectively located on both sides of the pad area 102 in a first direction X; in a second direction Y, the fan-out area 10 is located on one side of the pad area 102; the second direction Y intersects with the first direction X; Figure 4 In the figure, the second direction Y is perpendicular to the first direction X as an example for illustration; the pad area 102 includes a plurality of pad group units 1021 .

[0080] In some embodiments, Figure 4As shown, the wiring substrate further includes a plurality of signal lines 9 , and the signal lines 9 are electrically connected to the pad group unit 1021 and the first electrode 2 .

[0081] In specific implementation, the wiring substrate provided by the embodiment of the present disclosure can be applied to a light-emitting substrate, the first pad group is used to bind with the light-emitting device, and the second pad group is used to bind with the driver chip. Thus, the signal provided by the circuit board can be transmitted to the corresponding signal line through the first electrode, and then transmitted to the pad group unit to drive the light-emitting device to emit light.

[0082] In some embodiments, Figure 2 to Figure 4 As shown, the orthographic projection of the first opening 301 on the base substrate 1 falls within the orthographic projection of the first electrode 2 on the base substrate 1. Figure 2 , Figure 3 As shown, the first protective layer 3 not only covers the side of the first electrode 2, but also covers a part of the surface of the first electrode 2 facing away from the substrate 1. This can avoid the opening still exposing the side of the first electrode due to process errors, improve the protection effect of the first protective layer on the side of the first electrode, avoid corrosion caused by water vapor invading from the side of the first electrode, and avoid affecting the yield of the wiring substrate.

[0083] In some embodiments, Figure 2 , Figure 3 As shown, in any direction parallel to the plane where the substrate 1 is located, the first width L1 of the first opening 301 is smaller than the width L2 of the first surface 203 of the first electrode 2 .

[0084] It should be noted that Figure 2 , Figure 3 In the embodiment, at the first opening 301, the side surface of the first protective layer 3 is an inclined surface which is not perpendicular to the plane where the base substrate 1 is located, and the first width L1 of the first opening 301 is the minimum width of the first opening 301 in a direction parallel to the plane where the base substrate is located.

[0085] In some embodiments, L2 - L1 is the distance between the edge of the first opening and the edge of the first surface, and L2 - L1 is greater than or equal to 8 micrometers and less than or equal to 9 micrometers.

[0086] In some embodiments, in the first direction X, L1 is greater than or equal to 190 micrometers and less than or equal to 194 micrometers, L2 is greater than or equal to 198 micrometers and less than or equal to 202 micrometers, and in the second direction Y, L1 is greater than or equal to 790 micrometers and less than or equal to 794 micrometers, L2 is greater than or equal to 798 micrometers and less than or equal to 802 micrometers.

[0087] In some embodiments, Figure 7 , Figure 8 As shown, the wiring substrate also includes:

[0088] Multiple anti-oxidation layers 4 are located on the side of the multiple first electrodes 2 away from the base substrate 1; each of the multiple anti-oxidation layers 4 is electrically connected to one of the multiple first electrodes 2; the orthographic projection of the anti-oxidation layer 4 on the base substrate 1 covers the orthographic projection of the first opening 301 on the base substrate 1.

[0089] It should be noted that Figure 7 For example, along Figure 4 The cross-sectional view of BB', Figure 8 For example, along Figure 4 Cross-sectional view of CC'.

[0090] In the wiring substrate provided by the embodiment of the present disclosure, an anti-oxidation layer is provided on the side of the first electrode facing away from the base substrate, which can protect the surface of the first electrode facing away from the base substrate and improve the electrical connection performance of the wiring substrate and the circuit board.

[0091] In a specific implementation, the anti-oxidation layer on the side of the first electrode facing away from the substrate is bound to the circuit board, for example, the anti-oxidation layer and the circuit board are electrically connected via conductive glue to achieve the binding of the anti-oxidation layer and the circuit board. The conductive glue can be anisotropic conductive glue.

[0092] In some embodiments, Figure 7 , Figure 8 As shown, the orthographic projection of the first opening 301 on the base substrate 1 falls within the orthographic projection of the anti-oxidation layer 4 on the base substrate 1;

[0093] Furthermore, the orthographic projection of the anti-oxidation layer 4 on the base substrate 1 covers the orthographic projection of the edge of the first protection layer 3 at the first opening 301 on the base substrate 1 .

[0094] In some embodiments, Figure 7 , Figure 8 As shown, the anti-oxidation layer 4 includes a first sublayer 14 and a second sublayer 15 stacked and arranged on a side of the first electrode 2 facing away from the substrate 1 .

[0095] In a specific implementation, the anti-oxidation layer is formed by, for example, a chemical plating process, that is, a first sub-layer is first grown on the side of the first electrode away from the substrate and then a second sub-layer is grown.

[0096] In some embodiments, the material of the first electrode includes copper, the material of the first sublayer included in the oxidation protection layer includes nickel, and the material of the second sublayer included in the oxidation protection layer includes gold.

[0097] In a specific implementation, the anti-oxidation layer is formed in a chemical gold (chemical nickel gold) process, where a first sub-layer, namely a nickel layer, is grown first, and then a second sub-layer, namely a gold layer, is grown.

[0098] In some embodiments, the thickness of the first sub-layer is greater than the thickness of the second sub-layer. The thickness of the first sub-layer is greater than the thickness of the first opening.

[0099] In some embodiments, the thickness of the first sublayer is greater than or equal to 4 microns and less than or equal to 5 microns, and the thickness of the second sublayer is greater than or equal to 0.01 microns and less than or equal to 1 micron. That is, the thickness of nickel is greater than or equal to 4 microns and less than or equal to 5 microns, and the thickness of gold is greater than or equal to 0.01 microns and less than or equal to 1 micron.

[0100] In a specific implementation, the total thickness of the anti-oxidation layer is greater than or equal to 4.01 micrometers and less than or equal to 6 micrometers. For example, the total thickness of the anti-oxidation layer is 5 micrometers.

[0101] In a specific implementation, when the anti-oxidation layer is formed by a gold deposition process, since the gold deposition process sequentially grows a nickel layer and a gold layer on a metal layer using the replacement principle, the size of the anti-oxidation layer formed by the gold deposition process is limited by the size of the first electrode corresponding thereto. In a specific implementation, the orthographic projection of the anti-oxidation layer on the substrate coincides with the orthographic projection of the first electrode on the substrate, or the orthographic projection of the anti-oxidation layer on the substrate falls within the orthographic projection of the first electrode on the substrate. In any direction parallel to the plane where the substrate is located, the width of the anti-oxidation layer is less than or equal to the width of the first electrode corresponding thereto.

[0102] On this basis, when the first protective layer covers the edge of the first electrode, the orthographic projection of the anti-oxidation layer on the substrate covers the orthographic projection of the edge of the first protective layer at the first opening on the substrate, and makes the width of the anti-oxidation layer equal to the width of the first electrode corresponding thereto in any direction parallel to the plane of the substrate, thereby maximizing the anti-oxidation layer under process limitations, thereby maximizing the area of ​​the binding area between the anti-oxidation layer and the circuit board, which is beneficial to improving the binding yield.

[0103] It should be noted that Figure 7 , Figure 8 The first electrode 2 includes only one first protective layer 3 on the side facing away from the substrate 1. Figures 9 to 11 As shown, the wiring substrate also includes:

[0104] The second protection layer 5 is located on a side of the first protection layer 3 away from the substrate 1 , and includes a second opening 501 .

[0105] It should be noted that the thickness of the first protective layer is relatively thin, usually about 2400 angstroms, and the structure covered by the first protective layer is not flat, so the thin first protective layer covering the non-flat area of ​​the structure is prone to cracks, affecting the protective effect of the first protective layer on the underlying film layer. The wiring substrate provided by the embodiment of the present disclosure also includes a second protective layer on the side of the first protective layer away from the base substrate. Even if cracks appear in the first protective layer, the second protective layer can cover the cracks to prevent water vapor and the like from invading through the cracks, thereby improving the protection effect and thus improving the yield of the wiring substrate.

[0106] It should be noted that the thickness of the second protective layer is greater than that of the first protective layer, the thickness of the first protective layer is about 2400 angstroms, and the thickness of the second protective layer is about 3 microns. In the related art, when the wiring substrate includes a second protective layer, the opening of the second protective layer also needs to expose the first electrode, that is, the openings of the second protective layer and the first protective layer are both large openings. In addition, in the wiring substrate in the related art, the first electrode does not include an anti-oxidation layer on the side away from the base substrate. If the opening of the first protective layer is set to a small opening, it will cause a large step difference between the film layers at the opening. When the first electrode is bound to the circuit board through a conductive glue, the film layer step difference is too large to affect the filling of the conductive glue, that is, the conductive glue has poor fluidity, which may cause the conductive glue and the first electrode to have an uncontacted area, thereby affecting the binding reliability. The wiring substrate provided in the embodiment of the present disclosure is provided with an anti-oxidation layer on the side of the first electrode away from the base substrate, and the thickness of the anti-oxidation layer is relatively thick. Even if the opening of the first protective layer is set to a small opening, the presence of the anti-oxidation layer can eliminate the problem of poor fluidity of the conductive glue caused by the large step difference, avoid affecting the binding effect, and improve the binding yield.

[0107] In some embodiments, Fig. 9 As shown, the orthographic projection of the first electrode 2 on the substrate 1 falls within the orthographic projection of the second opening 501 on the substrate 1 .

[0108] In some embodiments, Fig. 9 As shown, the orthographic projection of the anti-oxidation layer 4 on the base substrate 1 falls within the orthographic projection of the second opening 501 on the base substrate 1 .

[0109] Right now Fig. 9 In the embodiment, the second opening included in the second protective layer is a large opening that exposes the first electrode and the area where the anti-oxidation layer is located.

[0110] In the wiring substrate provided by the embodiment of the present disclosure, the second opening included in the second protective layer is a large opening that exposes the area where the first electrode and the anti-oxidation layer are located, which can reduce the step difference in the area, improve the fluidity of the conductive adhesive, and help improve the binding yield.

[0111] In some embodiments, Fig.12As shown, the second protective layer 5 includes a second opening 501, and the second opening 501 corresponds to multiple first electrodes 2 and multiple anti-oxidation layers 4, that is, the orthographic projections of the multiple first electrodes 2 on the base substrate 1 fall within the orthographic projection of the second opening 501 on the base substrate 1, and the orthographic projections of the multiple anti-oxidation layers 4 on the base substrate 1 fall within the orthographic projection of the second opening 501 on the base substrate 1.

[0112] It should be noted that Fig. 9 For example, along Fig.12 The cross-sectional view of FF', Fig.12 The cross-sectional view of GG' Figure 8 The same is true, that is, the second protective layer is not provided in the region between two adjacent electrodes in the first direction X.

[0113] In some embodiments, Fig. 9 As shown, in the area corresponding to the second opening 501 , the distance L3 between the second protection layer 5 and the first electrode 2 is greater than or equal to 498 micrometers and less than or equal to 502 micrometers.

[0114] In a specific implementation, in the first direction, the distance between two adjacent first electrodes is greater than or equal to 58 microns and less than or equal to 62 microns, that is, the distance between two adjacent first electrodes is small. When the opening of the second protective layer needs to expose the first electrode, the second protective layer corresponding to the area between the two adjacent first electrodes is removed, which is conducive to reducing the difficulty of patterning the second protective layer.

[0115] Or, in some embodiments, Fig.10 , Fig.11 As shown, the orthographic projection of the second opening 501 on the base substrate 1 falls within the orthographic projection of the first electrode 2 on the base substrate 1 ; and the second protective layer 5 covers the surface of the first protective layer 3 facing away from the base substrate 1 .

[0116] That is, in the wiring substrate provided in the embodiment of the present disclosure, the second opening included in the second protective layer is also a small opening that only exposes a part of the first electrode. Since the first protective layer covers the side of the first electrode, that is, the first protective layer needs to climb where it covers the first electrode, and since the first protective layer is relatively thin, cracks are still likely to appear in the first protective layer where it covers the first electrode. In the wiring substrate provided in the embodiment of the present disclosure, the second opening is also a small opening that only exposes a part of the first electrode, and the second protective layer covers the first protective layer, which can enhance the protection effect on the first electrode. Even if cracks appear in the first protective layer where it covers the first electrode, water vapor can be prevented from invading and corroding the first electrode along the cracks.

[0117] In some embodiments, the number of the second openings is equal to the number of the first electrodes, that is, one second opening corresponds to one first electrode.

[0118] In some embodiments, Fig.10 , Fig.11 As shown, the second opening 501 and the first opening 301 are made in the same patterning process. In a specific implementation, after forming the first protective layer, the patterning process is not performed first to form the first opening, but after forming the second protective layer, the second protective layer and the first protective layer are patterned to form the second opening. Fig.10 , Fig.11 The opening 14 shown penetrates through the thickness of the second protective layer 5 and the first protective layer 3 , that is, the opening 14 includes the second opening 501 and the first opening 301 .

[0119] In the wiring substrate provided by the embodiment of the present disclosure, the second opening and the first opening are manufactured in the same patterning process, which can simplify the wiring substrate manufacturing process, and the patterning process of the second opening and the first opening only uses one mask plate, which can save costs.

[0120] In some embodiments, Fig.10 , Fig.11 As shown, at the first opening 301 and the second opening 501 , the anti-oxidation layer 4 covers the side surfaces of the first protective layer 3 and the side surfaces of the second protective layer 5 .

[0121] In some embodiments, Fig.10 , Fig.11 As shown, at the contact point between the anti-oxidation layer 4 and the second protective layer 5 , the surface of the anti-oxidation layer 4 away from the substrate 1 and the surface of the second protective layer 5 away from the substrate 1 are located in the same plane.

[0122] In the wiring substrate provided by the embodiment of the present disclosure, the anti-oxidation layer covers the side of the first protective layer and the side of the second protective layer, which is conducive to improving the protection effect of the first electrode. In addition, at the contact point between the anti-oxidation layer and the second protective layer, the surface of the anti-oxidation layer facing away from the substrate and the surface of the second protective layer facing away from the substrate are located in the same plane, which can reduce the step difference in this area, improve the fluidity of the conductive adhesive, and help improve the binding yield.

[0123] In some embodiments, Figure 2 , Figure 7 , Fig. 9 , Fig.10 As shown, the wiring substrate also includes:

[0124] A plurality of second electrodes 6 are located between the base substrate 1 and the plurality of first electrodes 2 in the fan-out region; each of the plurality of second electrodes 6 is electrically connected to the first electrode 2, and an orthographic projection of the second electrode 6 on the base substrate 1 overlaps with an orthographic projection of the first electrode 2 on the base substrate 1;

[0125] The first insulating layer 7 is located between the base substrate 1 and the plurality of second electrodes 6; the first insulating layer 7 includes a plurality of third openings 701 penetrating the thickness thereof; the orthographic projection of the third opening 701 on the base substrate 1 falls within the orthographic projection of the first electrode 2 on the base substrate 1, and the orthographic projection of the third opening 701 on the base substrate 1 falls within the orthographic projection of the second electrode 6 on the base substrate 1;

[0126] The second insulating layer 8 is located on the side of the first insulating layer 7 away from the base substrate 1; the first insulating layer 7 includes a plurality of fourth openings 801 running through its thickness; the orthographic projection of the third opening 701 on the base substrate 1 falls within the orthographic projection of the fourth opening 801 on the base substrate 1, the orthographic projection of the first electrode 2 on the base substrate 1 falls within the orthographic projection of the fourth opening 801 on the base substrate 1, and the orthographic projection of the second electrode 6 on the base substrate 1 falls within the orthographic projection of the fourth opening 801 on the base substrate 1; the first electrode 2 is electrically connected to the second electrode 6 at the fourth opening 801 and the third opening 701.

[0127] The wiring substrate provided by the embodiment of the present disclosure also includes a second electrode electrically connected to the first electrode in the fan-out area, that is, the electrically connected first electrode and the second electrode serve together as the signal input end of the wiring substrate, and the double-layer wiring of the signal input end is conducive to increasing the resistance of the signal input end, thereby reducing the impedance. In addition, the orthographic projections of the first electrode and the second electrode on the substrate substrate both fall within the orthographic projection of the fourth opening on the substrate substrate, that is, the orthographic projection of the first electrode on the substrate substrate and the orthographic projection of the second insulating layer on the substrate substrate do not overlap each other, that is, there is no second insulating layer directly below the first electrode, thereby reducing the number of film layers at the connection between the first electrode and the second electrode, thereby reducing the thickness of the film layer, avoiding a large step difference in the electrical connection area between the first electrode and the second electrode that affects the overlap of the first electrode and the second electrode, and is conducive to improving the yield of the wiring substrate.

[0128] In specific implementation, Figure 2 , Figure 7 , Fig. 9 , Fig.10 As shown, the wiring substrate further includes: a buffer layer 11 located between the second electrode 6 and the base substrate 1, a third insulating layer 12 located between the second electrode 6 and the first insulating layer 7, and a fourth insulating layer 13 located between the first insulating layer 7 and the second insulating layer 8. The third insulating layer 12 and the fourth insulating layer 13 also have openings, and the orthographic projections of the openings of the third insulating layer 12 and the fourth insulating layer 13 on the base substrate 1 both fall within the orthographic projection of the first electrode 2 on the base substrate 1, that is, the first electrode 2 is electrically connected to the second electrode 6 through the openings penetrating the fourth insulating layer 13, the first insulating layer 7, and the third insulating layer 12.

[0129] In a specific implementation, the buffer layer can prevent the second electrode from being directly disposed on the substrate from falling off. The first insulating layer and the second insulating layer not only play an insulating role, but also play a flattening role.

[0130] In a specific implementation, the thickness of the first insulating layer is about 3.5 microns, the thickness of the second insulating layer is about 4 microns, the thickness of the third insulating layer is about 2400 angstroms, and the thickness of the fourth insulating layer is about 1200 angstroms.

[0131] In a specific implementation, the first protective layer, the third insulating layer, and the fourth insulating layer are, for example, inorganic layers, that is, the first protective layer, the third insulating layer, and the fourth insulating layer include inorganic insulating materials, and the inorganic insulating materials are, for example, at least one of silicon nitride, silicon oxide, silicon oxynitride, and amorphous silicon; the second protective layer, the first insulating layer, and the second insulating layer are organic layers, that is, the second protective layer, the first insulating layer, and the second insulating layer include organic insulating materials, and the organic insulating materials include, for example: dipentaerythritol pentaacrylate, a mixture of dipentaerythritol hexaacrylate, a copolymer of acrylic acid and acrylate, a photoinitiator, etc.

[0132] In some embodiments, Figure 2 , Figure 7 , Fig. 9 , Fig.10 As shown, at least in the fan-out area, the signal line 9 includes a first sub-signal line 9-1 and a second sub-signal line 9-2 located in different layers. That is, at least in the fan-out area, the signal line 9 is wired in two layers, which is beneficial to increase the resistance of the signal line, thereby reducing the impedance of the signal line, and avoiding excessive voltage drop in signal transmission caused by too large impedance.

[0133] In a specific implementation, in an area outside the fan-out area, the signal line includes at least one of a first sub-signal line and a second sub-signal line.

[0134] In some embodiments, Figure 2 , Figure 7 , Fig. 9 , Fig.10 As shown, the first sub-signal line 9-1 is disposed in the same layer as the second electrode 6, and the second sub-signal line 9-2 is disposed in the same layer as the first electrode 2. The second sub-signal line 9-2 is electrically connected to the first sub-signal line 9-1 through a via hole penetrating the fourth insulating layer 13, the second insulating layer 8, the first insulating layer 7, and the third insulating layer 12.

[0135] The film layer where the second sub-signal line and the first electrode are located is called a first conductive layer, and the film layer where the first sub-signal line and the second electrode are located is called a second conductive layer.

[0136] In some embodiments, Figure 2 , Figure 7 , Fig. 9 , Fig.10As shown, the first signal sub-line 9-1 is connected to the second electrode 6. Thus, the signal line is electrically connected to the second electrode, the first electrode, and then to the circuit board.

[0137] In a specific implementation, for example, the first signal sub-line 9 - 1 is formed integrally with the second electrode 6 .

[0138] In specific implementation, Figure 2 , Figure 7 , Fig. 9 , Fig.10 As shown, the second signal sub-line 9 - 2 and the first electrode 2 are disconnected from each other.

[0139] In a specific implementation, the second sub-signal line may be connected to the first electrode, while the first sub-signal line and the second electrode may be disconnected from each other.

[0140] In a specific implementation, the first conductive layer and the second conductive layer include a third sublayer, and the material of the third sublayer includes copper. The first conductive layer and the second conductive layer may also include a fourth sublayer on the side of the third sublayer away from the substrate. Specifically, the material of the third sublayer includes copper, and the fourth sublayer is a molybdenum-niobium layer formed by a magnetron sputtering process on the surface of the copper away from the substrate. The formation of a molybdenum-niobium layer on the surface of the copper away from the substrate can protect the copper from corrosion of the conductive layer, and can also increase the surface adhesion of the first conductive layer and the second conductive layer to avoid the problem of film detachment and peeling. It should be noted that the first electrode exposed in the first opening does not include the fourth sublayer, i.e., the molybdenum-niobium layer, and the first opening is formed by an over-engraving process, so that the molybdenum-niobium layer on the surface of the first electrode in this area is removed in the graphical process of forming the first opening.

[0141] In some embodiments, Figure 5 , Figure 6 As shown, each pad group unit 1021 includes: at least one first pad group H1 and a second pad group H2 electrically connected to the at least one first pad group H1, the first pad group H1 includes a first pad H11 and a second pad H12, the second pad group H2 includes: a ground pad H21, an output pad H23, an address pad H24 and a power supply pad H22.

[0142] It should be noted that Figure 5 for Figure 4 The structural diagram of the D area in the middle, Figure 6 for Figure 4 Schematic diagram of the structure of area E in the middle.

[0143] In some embodiments, Figure 5 The cross-sectional view of GG' is shown in Fig.13 , Fig.14As shown, the first pad H11 and the second pad H12 are disposed in the same layer as the first electrode. The first pad H11 and the second pad H12 are both located in the first conductive layer 18 .

[0144] In a specific implementation, if the side of the first electrode facing away from the substrate includes the first protective layer but does not include the second protective layer, such as Fig.13 As shown, the wiring substrate also includes a plurality of fourth openings 302 and a plurality of fifth openings 303 that penetrate the first protective layer 3 and expose the first conductive layer 18; the orthographic projections of the fourth openings 302 and the fifth openings 303 on the base substrate 1 fall within the orthographic projection of the first conductive layer 18 on the base substrate 1, and the portion of the first conductive layer 18 exposed by the fourth opening 302 is the first solder pad H11, and the portion of the first conductive layer 18 exposed by the fifth opening 303 is the second solder pad H12.

[0145] In a specific implementation, if the side of the first electrode facing away from the substrate includes a first protective layer and a second protective layer, such as Fig.14 As shown, the wiring substrate also includes a plurality of sixth openings 16 and a plurality of seventh openings 17 that penetrate the first protective layer 3 and the second protective layer 4 and expose the first conductive layer 18; the orthographic projections of the sixth openings 16 and the seventh openings 17 on the base substrate 1 fall within the orthographic projection of the first conductive layer 18 on the base substrate 1, and the portion of the first conductive layer 18 exposed by the sixth opening 16 is the first solder pad H11, and the portion of the first conductive layer 18 exposed by the seventh opening 17 is the second solder pad H12.

[0146] In some embodiments, Figure 5 The cross-sectional view of JJ' is shown in Fig.15 , Fig.16 As shown, the ground pad H21, output pad H23, address pad (not shown) and power pad (not shown) included in the second pad group H2 are arranged in the same layer as the first electrode. The ground pad H21, output pad H23, address pad (not shown) and power pad (not shown) included in the second pad group H2 are all located in the first conductive layer 18.

[0147] It should be noted that Figure 5 In the description, an example is taken in which the second pad group includes four pads and the second pad group includes one output pad. Of course, the second pad group may also include multiple output pads.

[0148] In a specific implementation, if the side of the first electrode facing away from the substrate includes the first protective layer but does not include the second protective layer, such as Fig.15As shown, the wiring substrate also includes a plurality of eighth openings 304, a plurality of ninth openings 305, a plurality of tenth openings (not shown) and a plurality of eleventh openings (not shown) that penetrate the first protective layer 3 and expose the first conductive layer 18; the orthographic projections of the eighth opening 304, the ninth opening 305, the tenth opening (not shown) and the eleventh opening (not shown) on the base substrate 1 fall within the orthographic projection of the first conductive layer 18 on the base substrate 1, the portion of the first conductive layer 18 exposed by the eighth opening 304 is the ground pad H21, the portion of the first conductive layer 18 exposed by the ninth opening 305 is the output pad H23, the portion of the first conductive layer exposed by the tenth opening is the address pad, and the portion of the first conductive layer exposed by the eleventh opening is the power supply pad.

[0149] In a specific implementation, if the side of the first electrode facing away from the substrate includes a first protective layer and a second protective layer, such as Fig.16 As shown, the wiring substrate also includes a plurality of twelfth openings 19, a plurality of thirteenth openings 20, a plurality of fourteenth openings (not shown) and a plurality of fifteenth openings (not shown) that penetrate the first protective layer 3 and the second protective layer 4 and expose the first conductive layer 18; the orthographic projections of the twelfth opening 19, the thirteenth opening 20, the fourteenth opening and the fifteenth opening on the base substrate 1 fall within the orthographic projection of the first conductive layer 18 on the base substrate 1, the portion of the first conductive layer 18 exposed by the twelfth opening 19 is the ground pad H21, the portion of the first conductive layer 18 exposed by the thirteenth opening 20 is the output pad H23, the portion of the first conductive layer exposed by the tenth opening is the address pad, and the portion of the first conductive layer exposed by the eleventh opening is the power supply pad.

[0150] In specific implementation, Figure 5 As shown, the plurality of signal lines 9 include, for example: a plurality of constant voltage signal lines VLED, a plurality of common voltage signal lines GND, a plurality of power signal lines 901, a plurality of address signal lines (not shown), and a plurality of cascade lines 903. In a specific implementation, the address signal lines 902, the cascade lines 903, and the power signal lines 901 all include a portion located in the pad area 102.

[0151] In a specific implementation, the address signal line includes a first address signal line and a second address signal line.

[0152] It should be noted that Figure 5 , Figure 6In the example, the pad group unit 1021 includes four first pad groups H1 connected in sequence. Here, each pad group H1 is regarded as a whole, and the four first pad groups H1 are connected in series. The four first pad groups H1 are H1-1, H1-2, H1-3, and H1-4. The constant voltage signal line VLED is electrically connected to the first pad H11 of the first pad group H1-1. Of course, each pad group unit can also include other numbers of first pad groups. When each pad group unit includes multiple first pad groups, the multiple first pad groups can be connected in series or in parallel.

[0153] In a specific implementation, a plurality of second pad groups in a column of pad group units can be cascaded, and the address pads of the first level second pad group in the same column are connected to the first address signal line. Figure 5 , Figure 6 As shown, the output pad H23 of the kth (k is a positive integer) second pad group H2 and the address pad H24 of the (k+1)th second pad group H2 are connected via a cascade line 903, and the output pad H23 of the last second pad group H2 is connected to a feedback signal line 905; the second address signal line (not shown) is located between the common voltage signal line GND and the constant voltage signal line VLED between two adjacent pad group columns, and the second address signal line 9022 is electrically connected to the first address signal line 9021 on the side of the pad area away from the fan-out area; the cascade line 903 is also connected to a second pad H22 ( Figure 2 , Figure 3 The second pad H22 of H1-4 in a column is electrically connected; each power supply pad H22 in a column of pad group 5-1 is electrically connected to the same power signal line 901; each ground pad H21 in a column of pad group 5-1 is electrically connected to the same common voltage signal line GND.

[0154] In specific implementation, Figure 5 , Figure 6 As shown, among the various signal lines 9 electrically connected to a column pad group unit 1021, the cascade line 903 and the power signal line 901 are located between the first pad group H1 and the common voltage signal line GND, the cascade line 903 is located in the area between the power signal line 901 and the first pad group H1, and the address signal line 902 is located on the side of the power signal line 901 away from the common voltage signal line GND adjacent to it.

[0155] In some embodiments, Figure 5 , Figure 6 As shown, the electrostatic shielding line 904 passes through the first peripheral area 103 and the second peripheral area 104. The first frame area 103 includes the electrostatic shielding line 904, the power signal line 901, the feedback signal line 905 and the fixed voltage signal line GND, and the second frame area 104 includes the electrostatic shielding line 904 and the constant voltage signal line VLED.

[0156] In some embodiments, Figure 5 , Figure 6 As shown, the power signal line 901 is integrally connected to the power supply pad H22; the power signal line 901 passes through the area between the ground pad H21 and the output pad H23 and is electrically connected to the power supply pad H22, and the ground pad H21 is electrically connected to the common voltage signal line GND.

[0157] In specific implementation, Figure 5 , Figure 6 As shown, the pad group unit 1021 also includes three first connecting leads 15, two longitudinal first connecting leads 15 extending along the first direction Y, and one transverse first connecting lead 15 extending along the second direction X. The first pad group H1-1 is electrically connected to the first pad group H1-2 through the longitudinal first connecting leads 15, the first pad group H1-3 is electrically connected to the first pad group H1-4 through the longitudinal first connecting leads 15, and the first pad group H1-2 is electrically connected to the first pad group H1-3 through the transverse first connecting leads 15.

[0158] In a specific implementation, if the signal line is wired in a single layer in an area outside the fan-out area, in order to reduce the process steps and save the production cost, the constant voltage signal line, the cascade line, the address signal line, the feedback signal line, the power signal line, the first connecting lead, and the common voltage signal line can be arranged in the same layer, that is, the above structure is located in the same conductive layer. For example, in the area of ​​single-layer wiring, the above structure is arranged in the same layer as the first electrode. It should be noted that in the present disclosure, "arrangement in the same layer" refers to the use of the same film forming process to form a film layer for making a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to one mask. Depending on the specific pattern, a patterning process may include exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or may be at different heights or have different thicknesses.

[0159] Based on the same inventive concept, the present disclosure also provides a method for preparing a wiring substrate. Fig.17 As shown, including:

[0160] S101, providing a substrate; the substrate includes a fan-out area;

[0161] S102, forming a plurality of first electrodes in a fan-out region of the substrate;

[0162] S103, forming a first protective layer on the side of the multiple first electrodes away from the base substrate, and performing a patterning process on the first protective layer to form a plurality of first openings penetrating the thickness thereof; each of the multiple first openings corresponds to a first electrode, and the orthographic projection of the first opening on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate, and the first protective layer at least covers the side surfaces of the first electrode.

[0163] In the method for preparing a wiring substrate provided by an embodiment of the present disclosure, after the first protective layer is subjected to a patterning process to form a first opening exposing the first electrode, the first protective layer at least covers the side surface of the first electrode, that is, the first opening does not expose the entire area of ​​the first electrode. By setting a smaller first opening so that the first protective layer can protect the side surface of the first electrode, corrosion caused by the invasion of water vapor from the side surface of the first electrode can be avoided, thereby avoiding affecting the yield of the wiring substrate.

[0164] In some embodiments, after the first protective layer is patterned to form a plurality of first openings penetrating the first protective layer, the method further includes:

[0165] An anti-oxidation layer is formed on the side of each first electrode away from the base substrate by chemical plating process; the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

[0166] In some embodiments, an anti-oxidation layer is formed on a side of each first electrode facing away from the substrate by a chemical plating process, specifically comprising:

[0167] The anti-oxidation layer is formed by using chemical gold (chemical nickel gold) process technology.

[0168] Specifically, a first sub-layer, namely a nickel layer, is first grown on a side of the first electrode facing away from the substrate, and then a second sub-layer, namely a gold layer, is grown.

[0169] In some embodiments, after patterning the first protection layer to form a plurality of first openings penetrating the first protection layer and before forming the anti-oxidation layer, the method further includes:

[0170] forming a second protective layer on a side of the first protective layer away from the substrate;

[0171] The second protection layer is patterned to form a plurality of second openings penetrating the thickness thereof; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second opening on the base substrate.

[0172] In a specific implementation, the mask plate used for patterning the second protective layer to form the second opening is different from the mask plate used for patterning the first protective layer to form the first opening.

[0173] In some embodiments, before patterning the first protection layer to form a plurality of first openings penetrating the first protection layer, the method further includes:

[0174] forming a second protective layer on a side of the first protective layer away from the substrate;

[0175] The first protective layer is subjected to a patterning process to form a plurality of first openings penetrating the thickness thereof, specifically comprising:

[0176] The second protection layer and the first protection layer are subjected to a patterning process to form a plurality of second openings penetrating the second protection layer and a plurality of first openings penetrating the first protection layer.

[0177] That is, after the first protective layer is formed, the first opening is not formed first, and after the second protective layer is formed, an opening penetrating the second protective layer and the first protective layer is formed in one patterning process, and the opening includes the first opening and the second opening. Thus, the first opening and the second opening can be formed using one mask plate, which can save costs.

[0178] In some embodiments, a plurality of first electrodes are formed in a fan-out region of a substrate, specifically comprising:

[0179] forming a third sub-layer of a plurality of first electrodes in the fan-out region of the substrate;

[0180] forming a fourth sub-layer on a side of the third sub-layer facing away from the substrate by using a magnetron sputtering process;

[0181] The first protection layer is patterned to form a plurality of first openings penetrating the thickness thereof, and the fourth sub-layer at the first openings is removed.

[0182] In some embodiments, before forming a plurality of first electrodes in the fan-out region of the substrate, the method further includes:

[0183] forming a plurality of second electrodes in the fan-out region of the base substrate;

[0184] A pattern of a first insulating layer is formed on a side of the plurality of second electrodes away from the base substrate; the first insulating layer includes a plurality of third openings penetrating the thickness thereof; the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the second electrode on the base substrate;

[0185] A pattern of a second insulating layer is formed on the side of the first insulating layer facing away from the base substrate; the orthographic projection of the third opening on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, and the orthographic projection of the second electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate.

[0186] In some embodiments, before forming a plurality of second electrodes in the fan-out region of the substrate, the method further includes:

[0187] A buffer layer is formed.

[0188] In some embodiments, before forming a pattern of the first insulating layer on a side of the plurality of second electrodes facing away from the substrate, the method further includes:

[0189] forming a third insulating layer on a side of the plurality of second electrodes facing away from the substrate;

[0190] In a specific implementation, a patterning process may be performed on the first insulating layer and the third insulating layer to form the third opening of the first insulating layer and the opening of the third insulating layer.

[0191] In some embodiments, after forming a pattern of a second insulating layer on a side of the first insulating layer facing away from the substrate and before forming a plurality of first electrodes, the method further includes:

[0192] A pattern of a fourth insulating layer is formed on a side of the second insulating layer facing away from the substrate.

[0193] In some embodiments, forming a plurality of second electrodes further comprises:

[0194] forming a pattern of a first sub-signal line;

[0195] While forming a plurality of first electrodes, the method further includes:

[0196] The patterns of the second sub-signal line, the first pad group, and the second pad group are formed.

[0197] The present disclosure provides a light-emitting substrate, such as Fig.18 As shown, the light-emitting substrate includes a wiring substrate 24 provided in an embodiment of the present disclosure, and a light-emitting device bound to the wiring substrate 24 .

[0198] In some embodiments, Fig.18 As shown, the light-emitting substrate also includes: a plurality of driving chips IC.

[0199] In some embodiments, when the wiring substrate includes a plurality of first pad groups and a plurality of second pad groups, the light emitting device is electrically connected to the first pad groups, and the driving chip is electrically connected to the second pad groups.

[0200] In a specific implementation, the light emitting device has two pins, and the two pins are electrically connected to the first pad and the second pad of the first pad group, respectively. The driver chip has the same number of pins as the pads in the second pad group, for example, the driver chip has 4 pins, and the 4 pins are electrically connected to the ground pad, the output pad, the address pad, and the power supply pad, respectively.

[0201] In some embodiments, the light emitting device is a micro-sized inorganic electroluminescent device.

[0202] In a specific implementation, the micro-sized inorganic electroluminescent device is, for example, a mini light emitting diode (Mini Light Emitting Diode, Mini-LED) or a micro light emitting diode (Micro Light Emitting Diode, Micro-LED). Mini-LED and Micro-LED are small in size and high in brightness, and can be widely used in display devices or their backlight modules. For example, the typical size (such as length) of Micro-LED is less than 100 microns, such as 10 microns to 80 microns; the typical size (such as length) of Mini-LED is 80 microns to 350 microns, such as 80 microns to 120 microns. The light-emitting element can be at least one of Micro-LED or Mini-LED.

[0203] The light-emitting substrate provided in the embodiment of the present disclosure includes the wiring substrate provided in the embodiment of the present disclosure, so the implementation of the light-emitting substrate can refer to the embodiment of the above-mentioned wiring substrate, and the repeated parts will not be repeated.

[0204] The present disclosure provides a display device, such as Fig.19 As shown, the display device includes a light-emitting substrate 22 provided in an embodiment of the present disclosure.

[0205] In a specific implementation, the light-emitting substrate can be applied to the display field. For example, the light-emitting substrate can be used as a backlight source of a display panel. Fig.19 As shown, the display device also includes a display panel 23 located on the light emitting side of the light emitting substrate 22; the display panel 23 is, for example, a liquid crystal display panel, including: an array substrate 2301 and an opposing substrate 2302 arranged opposite to each other, and a liquid crystal layer 2303 located between the array substrate 2301 and the opposing substrate 2302.

[0206] The display device provided in the embodiment of the present disclosure includes the wiring substrate provided in the embodiment of the present disclosure, so the implementation of the display device can refer to the embodiment of the above-mentioned wiring substrate, and the repeated parts will not be repeated.

[0207] The display device provided in the embodiment of the present disclosure is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by a person skilled in the art, and will not be described in detail here, nor should they be used as a limitation of the present disclosure. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be described in detail.

[0208] To summarize, in the wiring substrate, light-emitting substrate and display device provided by the embodiments of the present disclosure, the first protective layer at least covers the side surfaces of the first electrode, that is, the first opening does not expose the entire area of ​​the first electrode. By setting a smaller first opening so that the first protective layer can protect the side surfaces of the first electrode, corrosion caused by the invasion of water vapor from the side surfaces of the first electrode can be avoided, thereby avoiding affecting the yield of the wiring substrate.

[0209] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0210] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A wiring substrate, wherein: The wiring substrate comprises: A substrate base plate, including a fan-out region; A plurality of first electrodes are located on one side of the substrate; A first protective layer is located on a side of the multiple first electrodes away from the base substrate, and includes multiple first openings that penetrate its thickness; each of the multiple first openings corresponds to a first electrode, and the orthographic projection of the first opening on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate; the first protective layer at least covers the side surfaces of the first electrode.

2. The wiring substrate according to claim 1, wherein: The orthographic projection of the first opening on the base substrate falls within the orthographic projection of the first electrode on the base substrate.

3. The wiring substrate according to claim 2, wherein: The wiring substrate further includes: A plurality of anti-oxidation layers are located on a side of a plurality of first electrodes away from the base substrate; each of the plurality of anti-oxidation layers is electrically connected to one of the plurality of first electrodes; and the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

4. The wiring substrate according to claim 3, wherein: The orthographic projection of the first opening on the base substrate falls within the orthographic projection of the anti-oxidation layer on the base substrate; The orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the edge of the first protection layer at the first opening on the base substrate.

5. The wiring substrate according to claim 4, wherein: The wiring substrate further includes: The second protection layer is located on a side of the first protection layer away from the base substrate, and comprises a second opening; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second opening on the base substrate.

6. The wiring substrate according to claim 5, wherein: The orthographic projection of the anti-oxidation layer on the base substrate falls within the orthographic projection of the second opening on the base substrate.

7. The wiring substrate according to claim 3, wherein: The wiring substrate further includes: The second protective layer is located on a side of the first protective layer away from the first conductive layer, and includes a plurality of second openings penetrating through the thickness thereof; the orthographic projection of the second openings on the base substrate falls within the orthographic projection of the first electrode on the base substrate.

8. The wiring substrate according to claim 7, wherein: The second opening and the first opening are made in the same patterning process.

9. The wiring substrate according to claim 8, wherein: At the first opening and the second opening, the anti-oxidation layer covers the side surfaces of the first protection layer and the side surfaces of the second protection layer.

10. The wiring substrate according to claim 9, wherein: At the contact point between the anti-oxidation layer and the second protective layer, a surface of the anti-oxidation layer away from the base substrate and a surface of the second protective layer away from the base substrate are located in the same plane.

11. The wiring substrate according to any one of claims 1 to 10, wherein: The first electrode has a first surface facing away from the substrate; a distance between an edge of the first opening and an edge of the first surface is greater than or equal to 8 micrometers and less than or equal to 9 micrometers.

12. The wiring substrate according to any one of claims 1 to 10, wherein: The wiring substrate further includes: A plurality of second electrodes are located between the base substrate and the plurality of first electrodes in the fan-out region; each of the plurality of second electrodes is electrically connected to the first electrode, and an orthographic projection of the second electrode on the base substrate overlaps an orthographic projection of the first electrode on the base substrate; A first insulating layer is located between the base substrate and the plurality of second electrodes; the first insulating layer comprises a plurality of third openings penetrating the thickness thereof; the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the second electrode on the base substrate; A second insulating layer is located on a side of the first insulating layer away from the base substrate; the first insulating layer includes a plurality of fourth openings extending through its thickness; the orthographic projection of the third opening on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, and the orthographic projection of the second electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate; the first electrode is electrically connected to the second electrode at the fourth opening and the third opening.

13. A method for preparing a wiring substrate, wherein: The method comprises: Providing a substrate substrate; the substrate substrate includes a fan-out region; forming a plurality of first electrodes in the fan-out region of the base substrate; A first protective layer is formed on a side of the multiple first electrodes away from the base substrate, and the first protective layer is patterned to form a plurality of first openings extending through the thickness thereof; each of the multiple first openings corresponds to one first electrode, an orthographic projection of the first opening on the base substrate overlaps with an orthographic projection of the first electrode on the base substrate, and the first protective layer at least covers a side surface of the first electrode.

14. The method according to claim 13, wherein: After the first protective layer is patterned to form a plurality of first openings penetrating the first protective layer, the method further comprises: An anti-oxidation layer is formed on a side of each first electrode away from the base substrate by chemical plating; the orthographic projection of the anti-oxidation layer on the base substrate covers the orthographic projection of the first opening on the base substrate.

15. The method according to claim 14, wherein: After the first protective layer is patterned to form a plurality of first openings penetrating the thickness thereof and before the anti-oxidation layer is formed, the method further comprises: forming a second protective layer on a side of the first protective layer away from the base substrate; The second protective layer is subjected to a patterning process to form a plurality of second openings penetrating the thickness thereof; the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the second opening on the base substrate.

16. The method according to claim 14, wherein: Before patterning the first protective layer to form a plurality of first openings penetrating the first protective layer, the method further includes: forming a second protective layer on a side of the first protective layer away from the base substrate; The step of patterning the first protective layer to form a plurality of first openings penetrating the thickness of the first protective layer specifically includes: The second protection layer and the first protection layer are subjected to a patterning process to form a plurality of second openings penetrating the second protection layer and a plurality of first openings penetrating the first protection layer.

17. The method according to any one of claims 13 to 16, wherein: Before forming a plurality of first electrodes in the fan-out region of the substrate, the method further comprises: forming a plurality of second electrodes in the fan-out region of the base substrate; A pattern of a first insulating layer is formed on a side of the plurality of second electrodes away from the base substrate; the first insulating layer includes a plurality of third openings penetrating the thickness thereof; the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the third openings on the base substrate falls within the orthographic projection of the second electrode on the base substrate; A pattern of a second insulating layer is formed on the side of the first insulating layer facing away from the base substrate; the orthographic projection of the third opening on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, the orthographic projection of the first electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate, and the orthographic projection of the second electrode on the base substrate falls within the orthographic projection of the fourth opening on the base substrate.

18. A light-emitting substrate, wherein: The light emitting substrate comprises the wiring substrate according to any one of claims 1 to 12, and a light emitting device bound to the wiring substrate.

19. The light emitting substrate according to claim 18, wherein: The light emitting device is a micro-sized inorganic electroluminescent device.

20. A display device, wherein: The display device comprises the light emitting substrate according to claim 18 or 19.

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