Array substrate and display device

Abstract

The invention provides an array substrate and a display device. The array substrate comprises a substrate body, a first conductive layer and a second conductive layer, and the first conductive layer is arranged on one side of the substrate body and comprises a first conductive part; the second conductive layer is arranged on the side, away from the substrate, of the first conductive layer and comprises a second conductive part, and the projection of at least part of the second conductive part and the projection of at least part of the first conductive part on the substrate are not overlapped. The first conductive part below the overlapping area of the second conductive part and the first conductive part is hollowed out, so that short circuit of the overlapping area due to static electricity, processing technology, testing and the like can be avoided, and the performance stability of the product is improved.

Description

[0001] This application is a divisional application of the invention application with an application date of January 28, 2021, Chinese application number 202180000084.7, and invention name “Array substrate and display device”. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0003] Mini-LED is a new type of LED display technology derived from small-pitch LEDs, also known as sub-millimeter light-emitting diodes. Its grain size is approximately between 100 and 200um, which is between traditional LEDs and Micro LEDs. Due to its good display effect and thin experience, as well as its high contrast and long life, it has a clear trend of use in the high-end display field. Summary of the invention

[0004] The purpose of the present disclosure is to provide an array substrate and a display device.

[0005] According to a first aspect of the present disclosure, there is provided an array substrate, comprising:

[0006] substrate substrate;

[0007] A first conductive layer, disposed on one side of the base substrate, comprises a first conductive portion;

[0008] The second conductive layer is arranged on a side of the first conductive layer away from the base substrate and includes a second conductive portion.

[0009] wherein a projection of at least part of the second conductive portion on the substrate does not overlap with a projection of the first conductive portion on the substrate;

[0010] The first conductive portion has an opening area, and at least a portion of the projection of the second conductive portion on the substrate is located within the area surrounded by the projection of the opening area;

[0011] The second conductive part at least includes a pad for arranging the light-emitting chip, and the pad and the first conductive layer are insulated from each other in the opening area;

[0012] The second conductive part includes a first lead, and a projection of at least one section of the first lead on the base substrate does not overlap with a projection of the first conductive layer on the base substrate;

[0013] The opening area is used to reduce the overlapping area between the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first lead on the substrate. The opening area includes a second opening area, and the second opening area includes at least one second sub-opening area. The number of second sub-opening areas is multiple, and at least two second sub-opening areas are interconnected.

[0014] According to a second aspect of the present disclosure, there is provided an array substrate, comprising:

[0015] substrate substrate;

[0016] A first conductive layer, disposed on one side of the base substrate, includes a first conductive portion;

[0017] The second conductive layer is arranged on a side of the first conductive layer away from the base substrate and includes a second conductive portion.

[0018] wherein a projection of at least part of the second conductive portion on the substrate does not overlap with a projection of the first conductive portion on the substrate;

[0019] The first conductive portion has an opening area, and at least a portion of the projection of the second conductive portion on the substrate is located within the area surrounded by the projection of the opening area;

[0020] The second conductive part at least includes a pad for arranging the light-emitting chip, and the pad and the first conductive layer are insulated from each other in the opening area;

[0021] At least part of the first conductive portion includes an opening area extending along the first direction, including a third opening area, and the third opening area includes at least one third sub-opening area; the second conductive portion includes a second lead extending along the second direction, and the second direction intersects with the first direction; the projection of at least part of the second lead on the substrate overlaps with the area enclosed by the projection of the third sub-opening area.

[0022] According to a third aspect of the present disclosure, an array substrate is provided, comprising:

[0023] substrate substrate;

[0024] A first conductive layer, disposed on one side of the base substrate, comprises a first conductive portion;

[0025] A second conductive layer, disposed on a side of the first conductive layer away from the base substrate, comprising a second conductive portion;

[0026] Wherein, a projection of at least a portion of the second conductive portion on the base substrate does not overlap with a projection of the first conductive portion on the base substrate.

[0027] The first conductive portion has an opening area, and at least a portion of the projection of the second conductive portion on the substrate is located within the area surrounded by the projection of the opening area;

[0028] The second conductive part at least includes a pad for arranging the light-emitting chip, and the pad and the first conductive layer are insulated from each other in the opening area;

[0029] The first conductive layer has a thickness greater than 1.5-7 micrometers, and the first conductive layer includes copper.

[0030] In an exemplary embodiment of the present disclosure, a projection edge of a portion of the second conductive portion corresponding to the opening area has a gap with a projection edge of the opening area.

[0031] In an exemplary embodiment of the present disclosure, the second conductive portion includes at least any one of a pad, a first lead, a second lead, and a functional unit;

[0032] The opening region includes at least any one of a first opening region, a second opening region, a third opening region, and a fourth opening region.

[0033] In an exemplary embodiment of the present disclosure, the opening area includes a first opening area, and the first opening area includes a plurality of first sub-opening areas;

[0034] The second conductive portion includes a plurality of groups of pads, each group of pads includes a plurality of sub-pads;

[0035] The projections of at least some of the sub-pads on the base substrate are respectively located in the area surrounded by the projections of the first sub-opening areas, and the projection periphery of each sub-pad has a gap with the projection edge of the corresponding first sub-opening area.

[0036] In an exemplary embodiment of the present disclosure, the first sub-opening areas corresponding to the sub-pads of the same group of pads are connected to each other.

[0037] In an exemplary embodiment of the present disclosure, at least a portion of the first conductive portion extends along the first direction, the opening region includes a second opening region, and the second opening region includes at least one second sub-opening region;

[0038] The second conductive portion includes a first lead extending along a first direction;

[0039] The projection of at least part of the first lead on the base substrate overlaps with the area enclosed by the projection of the second sub-opening area, and a gap exists between the projection edge of at least one side of the first lead and the projection edge of the second sub-opening area.

[0040] In an exemplary embodiment of the present disclosure, at least a portion of the first conductive portion extending along the first direction includes an opening area including a third opening area, the third opening area includes at least one third sub-opening area, and edges on opposite sides of the second lead have a gap with a projected edge of the third sub-opening area.

[0041] In an exemplary embodiment of the present disclosure, there are multiple third sub-opening areas, and at least two third sub-opening areas are connected to each other.

[0042] In an exemplary embodiment of the present disclosure, the opening region includes a fourth opening region, and the fourth opening region includes at least one fourth sub-opening region;

[0043] The second conductive part includes a plurality of functional units;

[0044] The projections of each functional unit on the substrate are located in a one-to-one correspondence within the area surrounded by the projections of each fourth sub-opening area, and the projection periphery of each functional unit has a gap with the projection edge of the corresponding fourth sub-opening area.

[0045] In an exemplary embodiment of the present disclosure, there are multiple fourth sub-opening areas, and at least two fourth sub-opening areas are connected to each other.

[0046] In an exemplary embodiment of the present disclosure, the functional unit includes a first test conductive portion electrically connected to the pad, the first lead or the second lead, and the first test conductive portion is used to detect electrical properties of the pad, the first lead or the second lead.

[0047] In an exemplary embodiment of the present disclosure, at least two of the first opening area, the second opening area, the third opening area, and the fourth opening area are interconnected.

[0048] In an exemplary embodiment of the present disclosure, a gap between a projected edge of the second conductive portion and a projected edge of a corresponding sub-opening region is greater than or equal to a preset value, and the preset value includes a sum of a process tolerance, a maximum size of impurities, and a reserved spacing;

[0049] Among them, the process tolerance refers to the dimensional deviation allowed in the preparation process of the first conductive part and / or the second conductive part, the maximum impurity size refers to the maximum diameter of the impurity particles in the process, and the reserved spacing is the spacing value artificially set to form a gap.

[0050] In an exemplary embodiment of the present disclosure, the first conductive layer further includes a plurality of conductive islands, at least one sub-opening area includes a conductive island, and a gap exists between the outer periphery of the conductive island and the edge of the corresponding sub-opening area;

[0051] A projection of at least one of the sub-pad, the first lead, the second lead or the first test conductive portion on the substrate is located within a projection of a corresponding conductive island or completely overlaps with a projection of each conductive island.

[0052] In an exemplary embodiment of the present disclosure, at least two sub-opening areas in the same opening area are interconnected, and the conductive islands in the interconnected sub-opening areas are independent of each other or connected as a whole.

[0053] In an exemplary embodiment of the present disclosure, at least two of the first opening area, the second opening area, the third opening area, and the fourth opening area are interconnected, and the conductive islands in the interconnected opening areas are independent of each other or connected as a whole.

[0054] In an exemplary embodiment of the present disclosure, the second conductive layer further includes a second test conductive portion, which overlaps with a projection of the first conductive portion on the base substrate and is electrically connected through a via, and the second test conductive portion is used to detect electrical properties of the first conductive portion.

[0055] In an exemplary embodiment of the present disclosure, a first insulating layer and a first inorganic layer are disposed between the first conductive layer and the second conductive layer, and a second insulating layer and a second inorganic layer are disposed on a side of the second conductive layer away from the base substrate.

[0056] In an exemplary embodiment of the present disclosure, the pad includes four sub-pads, namely a first input pad, a second input pad, an output pad, and a common voltage pad;

[0057] The first input pad is configured to receive a first input signal, the first input signal is an address signal, and is used to select a driver chip of a corresponding address, and an address to be transmitted can be obtained by parsing the address signal;

[0058] The second input pad is configured to receive a second input signal, the second input signal is a power line carrier communication signal from a source power line, the second input signal is used to provide power to the driver chip and transmit communication data to the driver chip, the communication data is used to control the light emission duration of the corresponding light emitting unit;

[0059] The output pad is configured to output a driving signal, where the driving signal may be a driving voltage from a driving voltage line, and is used to drive the light emitting element to emit light;

[0060] The common voltage pad is configured to receive a common voltage signal, which is a ground signal from a common voltage line.

[0061] In an exemplary embodiment of the present disclosure, a size of the second opening area along the first direction is larger than a size along the second direction, and a size of the third opening area along the second direction is larger than a size along the first direction.

[0062] In an exemplary embodiment of the present disclosure, there is a gap between the outer periphery of the conductive island and the first conductive portion, the second conductive portion is located on a side of the conductive island away from the substrate, and the conductive island is insulated from the first conductive portion; the conductive island is insulated from the second conductive portion.

[0063] According to yet another aspect of the present disclosure, a display device is provided, comprising the array substrate described above.

[0064] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0066] Figure 1 It is a structural schematic diagram of a mini LED array substrate;

[0067] Figure 2 for Figure 1 A partial enlarged view of the middle M area;

[0068] Figure 3 A schematic diagram of a pad structure of an LED light-emitting device in one embodiment;

[0069] Figure 4 for Figure 3 Schematic diagram of the cross section along the AA direction;

[0070] Figure 5 It is a schematic diagram of another pad structure of an LED light-emitting device;

[0071] Figure 6 for Figure 5 Schematic diagram of the cross section along the AA direction;

[0072] Figure 7 A schematic diagram of a pad structure of an IC driver chip pad;

[0073] Figure 8 It is a schematic diagram of another pad structure of an IC driver chip pad;

[0074] Fig. 9 is a structural schematic diagram of a first lead;

[0075] Fig.10 is a structural schematic diagram of a second lead;

[0076] Fig.11 is a structural schematic diagram of a first test conductive part;

[0077] Fig.12 A schematic diagram of a structure in which each opening area is connected;

[0078] Fig.13 A schematic diagram of a pad structure including a conductive island of an LED light emitting device;

[0079] Fig.14 for Fig.13 Schematic diagram of the cross section along the AA direction;

[0080] Fig.15 A schematic diagram of another pad structure of an LED light-emitting device including a conductive island;

[0081] Fig.16 for Fig.15 Schematic diagram of the cross section along the AA direction;

[0082] Fig.17 A schematic diagram of a pad structure of an IC driver chip pad including a conductive island;

[0083] Fig.18 A schematic diagram of another pad structure of an IC driver chip pad including a conductive island;

[0084] Fig.19 A schematic diagram of a structure in which a first lead and a second lead include a conductive island;

[0085] Fig. 20 It is a structural schematic diagram of a first test conductive part including a conductive island and a second test conductive part;

[0086] Fig.21 for Fig. 20 Schematic diagram of the cross section along the AA direction;

[0087] Fig. 22 for Figure 1 Another partial magnification of the middle M area.

[0088] In the figure: 100, first conductive layer; 10, first conductive part; 110, opening area; 111, first opening area; 1110, first sub-opening area; 112, second opening area; 1120, second sub-opening area; 113, third opening area; 1130, third sub-opening area; 114, fourth opening area; 1140, fourth sub-opening area; 120, conductive island; 200, second conductive layer; 20, second conductive part; 210, pad; 2110, sub-pad; 220, first lead; 230, second lead; 241, first test conductive part; 242, second test conductive part; 300, first insulating layer; 400, first inorganic layer; 500, second insulating layer; 600, second inorganic layer; 900, substrate. DETAILED DESCRIPTION

[0089] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0090] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0091] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0092] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring the main technical ideas of the present disclosure.

[0093] When a structure is “on” another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure via another structure.

[0094] The terms "a", "an", "the" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0095] like Figure 1 The figure shows a schematic diagram of the structure of a mini LED array substrate. Figure 2 for Figure 1 The partial enlarged view of the middle M area shows the structure of a light-emitting unit. The light-emitting unit includes four light-emitting devices connected in series, with the light-emitting device electrically connected to the driving voltage line VLED as the starting point of the series connection of the four light-emitting devices, and the light-emitting device electrically connected to the driver IC as the end point of the series connection of the four light-emitting devices. The four light-emitting devices are driven by a driver IC.

[0096] It should be noted that in the embodiments of the present disclosure, the number of light-emitting devices in each light-emitting unit is not limited, and can be any number such as 5, 6, 7, 8, etc., and is not limited to 4. At the same time, the light-emitting device can be Mini LED, OLED or any other form of light-emitting device.

[0097] In the embodiment of the present disclosure, the Mini-LED array substrate includes a base substrate 900, a first conductive layer 100, and a second conductive layer 200. The first conductive layer 100 is provided on one side of the base substrate 900, and includes a first conductive portion 10. The second conductive layer 200 is provided on the side of the first conductive layer 100 away from the base substrate 900, and includes a second conductive portion 20. A first insulating layer 300 and a first inorganic layer 400 are provided between the first conductive layer 100 and the second conductive layer 200, and a second insulating layer 500 and a second inorganic layer 600 are provided above the second conductive layer 200.

[0098] The first conductive layer 100 is usually used to arrange various signal lines, that is, the first conductive part 10 can be various signal lines, such as a common voltage line GND, a driving voltage line VLED, a source power line PWR, a source address line DI, etc. Optionally, the film layer has a thickness of about 1.5 to 7 μm, and its material includes copper, for example, a stacked material such as MoNb / Cu / MoNb can be formed by sputtering, and the bottom MoNb Used to improve adhesion, the middle layer Cu is used to transmit electrical signals, and the top layer MoNb For anti-oxidation. The film layer can also be formed by electroplating, first forming a seed layer MoNiTi to increase the grain nucleation density, and then forming an anti-oxidation layer MoNiTi after electroplating.

[0099] Since the first conductive layer 100 is thick, the oxide layer formed thereby is thicker, so that the first insulating layer 300 and the first inorganic layer 400 between the first conductive layer 100 and the second conductive layer 200 are more easily damaged, thereby causing a short circuit between the first conductive layer 100 and the second conductive layer 200.

[0100] The second conductive layer 200 is usually used to set various pads, that is, the second conductive part 20 can be various pads, such as pads for mounting functional elements or pads for mounting functional element driver chips; the second conductive layer 200 can also be provided with leads for connection, that is, the second conductive part 20 can also be a lead. Optionally, the film layer thickness is about The material may be, for example, a stacked material of MoNb / Cu / CuNi, wherein the bottom layer MoNb is used to improve adhesion, the middle layer Cu is used to transmit electrical signals, and the top layer CuNi can take into account both anti-oxidation and solid crystal firmness.

[0101] An insulating layer is disposed between the first conductive layer 100 and the second conductive layer 200 .

[0102] Due to limitations of substrate size, process, etc., when manufacturing the second conductive part 20 located on the upper layer, it is often inevitable to overlap with the first conductive part 10 below. The overlapping area of ​​the two is a weak performance area, which is prone to short circuit or open circuit, resulting in defects or affecting reliability.

[0103] For example, if the upper pad overlaps the lower signal line, when the functional components are subsequently soldered, such as when the LED chip is soldered using SMT reflow soldering technology, the soldering temperature reaches 260-265°C, which easily exceeds the temperature resistance of the middle insulation layer, causing the OC at the pad to break, and then causing a short circuit between the pad and the signal line. In addition, when the LED chip is solidified, the sharp-angled particles of the LED may also pierce the pad and the insulation layer, causing a short circuit between the pad and the signal line.

[0104] For another example, if the upper lead overlaps with the lower signal line, the air static electricity generated at the edge of the overlap can easily break through the insulation layer, causing a short circuit between the lead and the signal line. In addition, the particles generated during the process cannot be completely eliminated. When the particles fall on the overlapping area of ​​the lead and the signal line, it is easy to cause unstable conduction between the lead and the signal line, affecting the reliability of the product. Furthermore, when using the needle test method to test the current or voltage of the upper lead, it is easy to pierce the insulation layer and pierce the signal line below, resulting in inaccurate testing or reduced accuracy.

[0105] One reason for the short circuit between the first conductive part 10 and the second conductive part 20 is that the first conductive part 10 is usually thicker and wider to provide a larger voltage / current and lower resistance, and the second conductive part 20 is usually narrower and shorter, and exists as a lead, pad or other structure. Therefore, there is a certain potential difference between the two. Because in the glass-based film manufacturing process, the insulating layer between the two conductive parts is in a semi-solid and semi-liquid state before solidification, the water vapor introduced in this process may remain in the insulating layer. The essence of Cu growth in the conductive part is electrochemical corrosion. Water can easily induce an electrochemical reaction in the presence of a potential difference, forming OH in the insulating layer. - , OH - This will cause a short circuit between the first conductive portion 10 and the second conductive portion 20 .

[0106] It can be seen that in order to ensure product quality and performance, a short circuit between the first conductive part 10 and the second conductive part 20 should be avoided as much as possible.

[0107] In the array substrate disclosed herein, at least part of the second conductive part 20 and the first conductive part 10 do not overlap in projection on the base substrate, that is, in the thickness direction of the array substrate, at least part of the second conductive part 20 and the first conductive part 10 do not overlap, so that the non-overlapping parts can avoid short circuits between the two due to static electricity, process technology, testing, etc., thereby improving product performance stability. Of course, in a completely ideal situation, if the projections of all the second conductive parts 20 and the first conductive parts 10 on the base substrate do not overlap, short circuits can be completely avoided.

[0108] In the present disclosure, when describing the "overlap" between two structures, it means that the orthographic projection of one structure on the substrate at least partially overlaps with the orthographic projection of the other structure on the substrate. The array substrate of the embodiment of the present disclosure is described in detail below:

[0109] Since the first conductive part 10 needs to provide a larger voltage / current and a lower IR drop, it is usually set wider, and the second conductive part 20 is usually used as a smaller structure such as a lead or a pad, and is usually set narrower. For example, for small-sized products, the line width ratio of the first conductive part 10 to the second conductive part 20 is about 20 to 30, and for large-sized products, the line width ratio of the first conductive part 10 to the second conductive part 20 can be as high as 100 times or more, so the second conductive part and the first conductive part 10 must overlap.

[0110] refer to Figure 2In one embodiment, the present disclosure sets an opening area 110 in the first conductive part 10, wherein the opening area 110 includes both a hollow area located in the middle of the first conductive part 10, the hollow area having a complete annular edge, and a hollow area located at the edge of the first conductive part 10, the hollow area having a partial edge, which is specifically described in detail below in conjunction with the accompanying drawings. Since the opening area 110 is a hollow area, the present disclosure considers that its projection on the substrate is the projection of the edge of the surrounding film layer, that is, an annular edge. The present disclosure uses the area surrounded by the annular projection edge as a reference, so that the projection of at least part of the second conductive part 20 (that is, the second conductive part 20 at the overlap) on the substrate 900 is located within the area surrounded by the projection of the opening area 110. It should be noted that the projection of the second conductive part 20 at the overlap referred to in the present disclosure is located within the area surrounded by the projection of the opening area 110, including two situations, one of which is that at least part of the projection edge of the second conductive part 20 is located inside the projection edge of the opening area, and the projection area of ​​the second conductive part 20 is smaller than the area surrounded by the projection of the opening area. The other is that the projection of the second conductive part 20 and the projection of the opening area 110 completely overlap, which means that the two projections have the same shape and completely overlap. In either case, the first conductive part 10 below the overlapping area is hollowed out, thereby preventing the first conductive part 10 and the second conductive part 20 from short-circuiting in the overlapping area due to static electricity, process technology, testing, etc., thereby avoiding affecting the stability of product performance.

[0111] Furthermore, a certain gap may be set between the projected edge of the portion of the second conductive portion 20 corresponding to the opening area 110 and the projected edge of the opening area 110, so that a certain distance is maintained between the second conductive portion 20 and the edge of the first conductive portion 10, further reducing the possibility of a short circuit between the two.

[0112] In one embodiment, the second conductive part 20 includes a plurality of pads 210. In this embodiment, the pads 210 may be pads for mounting functional devices, such as light emitting devices, sensors, etc., or pads for mounting functional device driver chips.

[0113] refer to Figure 3 ,for Figure 2 A partial enlarged schematic diagram of the N region in the middle. Taking the pad for mounting a light-emitting device as an example, the pad 210 includes two sub-pads 2110, one is an anode pad (shown as P in the figure), and the other is a cathode pad (shown as N in the figure). Figure 4 ,for Figure 3 Schematic diagram of the cross section along the AA direction.

[0114] In this embodiment, the first conductive portion 10 is a common voltage line GND, and the pad of the light-emitting device overlaps with the common voltage line GND in the thickness direction of the array substrate. In this embodiment, the opening area 110 of the first conductive portion 10 includes a first opening area 111, and the first opening area 111 includes two first sub-opening areas 1110; in the thickness direction of the substrate, the projection of the anode pad on the base substrate 900 is located in the area surrounded by the projection of one first sub-opening area 1110, and the projection of the anode pad has a gap with the projection of the first sub-opening area 1110. Similarly, the projection of the cathode pad on the base substrate 900 is located in the area surrounded by the projection of another first sub-opening area 1110, and the projection of the cathode pad has a gap with the projection of the first sub-opening area 1110. In this embodiment, the two first sub-opening areas 1110 are separated by the first conductive portion 10 that is not hollowed out, so that each first sub-opening area 1110 corresponds to its own sub-pad 2110.

[0115] The area of ​​the first conductive part 10 facing the anode pad and the cathode pad is hollowed out so that the anode pad, the cathode pad and the first conductive part 10 below no longer overlap, thereby avoiding the problem of short circuit between the pad and the first conductive part 10 due to welding, die bonding, etc.

[0116] Furthermore, the first sub-opening areas 1110 corresponding to the sub-pads of the same pad group are connected to each other. Figure 5 and Figure 6 , Figure 6 for Figure 5 Schematic diagram of the cross section along the AA direction. In this embodiment, the two first sub-opening areas 1110 are interconnected to form an opening, that is, the projections of the anode pad and the cathode pad are located in the area surrounded by the projections of the same large opening area. This structure can not only prevent the anode pad, the cathode pad and the first conductive part 10 from being short-circuited, but also reduce the process difficulty of hollowing out the first conductive part 10.

[0117] In this embodiment, the sub-pad 2110 and the first sub-opening area 1110 have the same shape, which is approximately rectangular.

[0118] refer to Figure 7, taking the pad for installing the IC driver chip as an example, the pad includes four sub-pads 2110, namely the first input pad Di, the second input pad Pwr, the output pad Out and the common voltage pad Gnd. The above-mentioned first input pad Di is configured to receive a first input signal, which is, for example, an address signal, for gating the IC driver chip of the corresponding address. For example, the first input signal can be an 8-bit address signal from the source address line DI, and the address to be transmitted can be obtained by parsing the address signal. The second input pad Pwr is configured to receive a second input signal, which is, for example, a power line carrier communication signal from the source power line PWR. The second input signal not only provides power to the IC driver chip, but also transmits communication data to the IC driver chip, which can be used to control the light-emitting duration of the corresponding light-emitting unit, and then control its visual light-emitting brightness. The output pad Out is configured to output a drive signal. For example, the drive signal can be a drive voltage from the drive voltage line VLED, which is used to drive the light-emitting element to emit light. The common voltage pad Gnd is configured to receive a common voltage signal, such as a ground signal from a common voltage line GND.

[0119] In this embodiment, the first conductive part 10 is a common voltage line GND, and the pad of the IC driver chip overlaps with the common voltage line GND in the thickness direction of the array substrate. The first opening area 111 of the first conductive part 10 includes four first sub-opening areas 1110; in the thickness direction of the substrate, the projection of the first input pad Di on the base substrate 900 is located in the area surrounded by the projection of the first first sub-opening area 1110, and the projection peripheral edge of the first input pad Di has a gap with the projection edge of the first sub-opening area 1110. The projection of the second input pad Pwr on the base substrate 900 is located in the area surrounded by the projection of the second first sub-opening area 1110, and the projection peripheral edge of the second input pad Pwr has a gap with the projection edge of the first sub-opening area 1110. The projection of the output pad Out on the base substrate 900 is located in the area surrounded by the projection of the third first sub-opening area 1110, and the projection peripheral edge of the output pad Out has a gap with the projection edge of the first sub-opening area 1110. The projection of the common voltage pad Gnd on the base substrate 900 is located within the area surrounded by the projection of the fourth first sub-opening area 1110, and there is a gap between the outer peripheral edge of the projection of the common voltage pad Gnd and the projection edge of the first sub-opening area 1110. In this embodiment, the four first sub-opening areas 1110 are separated by the first conductive portion 10 that is not hollowed out, so that each first sub-opening area 1110 corresponds to its own sub-pad 2110.

[0120] The area of ​​the first conductive part 10 facing the four sub-pads 2110 is hollowed out so that the four sub-pads 2110 no longer overlap with the first conductive part 10 below, thereby avoiding the problem of short circuit between the pads and the first conductive part 10 .

[0121] Furthermore, the first sub-opening areas 1110 corresponding to the sub-pads of the same pad group are connected to each other, thereby reducing the difficulty of hollowing out. Figure 8 In this embodiment, the four first sub-opening areas 1110 are interconnected to form an opening, that is, the projections of the first input pad Di, the second input pad Pwr, the output pad Out, and the common voltage pad Gnd are located in the area surrounded by the projection of the same large opening area 110. This structure can prevent each sub-pad 2110 from being short-circuited with the first conductive part 10 below, and reduce the precision requirement for hollowing out the first conductive part 10.

[0122] In this embodiment, the sub-pad 2110 is substantially pentagonal in shape, and the first sub-opening area 1110 is substantially rectangular in shape.

[0123] It should be noted that the present disclosure does not limit the specific shape of the first sub-opening area 1110, which may be consistent with or inconsistent with the shape of the sub-pad 2110. Among them, "approximately pentagonal" and "approximately rectangular" mean that the outer contour of the sub-pad 2110 and the shape of the boundary of the first sub-opening area 1110 are pentagonal or rectangular as a whole, but are not limited to standard pentagons or rectangles.

[0124] In other embodiments, the pad may also have other numbers of sub-pads, for example, 1, 3, etc. Correspondingly, the first opening area 111 includes a corresponding number of first sub-opening areas 1110, so that each sub-pad corresponds to a first sub-opening area 1110, so as to avoid overlapping at the sub-pads. They will not be described one by one here.

[0125] The present disclosure does not limit the number of pads. Figure 1 Taking the structure shown in as an example, the array substrate includes a plurality of light-emitting device pads and a plurality of IC driver chip pads. In one embodiment, the first sub-opening areas 1110 corresponding to all pads for binding the same functional device are interconnected, for example, the first sub-opening areas 1110 corresponding to all pads for binding the light-emitting device are interconnected, and the first sub-opening areas 1110 corresponding to all pads for binding the IC driver chip are interconnected.

[0126] In one embodiment, reference Fig. 9The second conductive part 20 includes a first lead 220, and the first lead 220 extends in the longitudinal direction (first direction) in the figure. Taking the figure as an example, the first lead 220 is a longitudinal lead extending from the LED light-emitting device. In other embodiments, the first lead 220 can also be a longitudinal lead extending from the IC driver chip pad.

[0127] Continue to refer Fig. 9 In this embodiment, the first conductive portion 10 is also a common voltage line GND, and the longitudinally extending first lead overlaps with the longitudinally extending portion of the common voltage line GND in the thickness direction of the array substrate.

[0128] The opening of the first conductive part 10 includes a second opening area 112, and the second opening area 112 is located in the longitudinally extending portion of the first conductive part 10. The second opening area 112 includes at least one second sub-opening area, and the projection of at least one section of the first lead 220 on the base substrate 900 is located in the area surrounded by the projection of the second sub-opening area 1120, that is, the first conductive part 10 corresponding to the lower portion of at least one section of the first lead 220 is hollowed out, so that the first lead 220 and the lower first conductive part 10 no longer overlap in this area, thereby avoiding a short circuit between the first lead 220 and the first conductive part 10 due to static electricity, testing, and process.

[0129] The first lead 220 may be completely hollowed out. Fig. 9 That is to say, the second opening area 112 can be arranged below all the first leads 220 , or only below a part of the first leads 220 . Fig. 9 The second opening area 112 corresponding to the lower portion of the first lead 220 includes only one second sub-opening area 1120. In other embodiments, it may include multiple second sub-opening areas. When there are multiple second sub-opening areas 1120, at least two second sub-opening areas 1120 may be interconnected, thereby reducing the difficulty of hollowing out.

[0130] In the present disclosure, a projection edge of at least one side of the first lead 220 and a projection edge of the second opening area 112 have a gap. Specifically, in one embodiment, referring to Figure 2 The second opening area 112 on the right side is a closed area disposed inside the first conductive part 10, having four boundaries, and there are gaps between the left and right projected edges of the first lead 220 on the right side and the left and right projected edges of the second opening area 112. The second opening area 112 on the left side is a semi-closed area disposed at the inner edge of the first conductive part 10, that is, the second opening area 112 has three boundaries, the left side is connected to the blank area outside the first conductive part 10, and there is a gap between the right projected edge of the first lead 220 on the left side and the right projected edge of the second opening area 112.

[0131] In one embodiment, reference Fig.10 The second conductive part 20 further includes a second lead 230, which extends in a lateral direction. The second lead 230 may be a lateral lead extending from a pad of an IC driver chip, or may be a lateral lead extending from an LED light emitting device.

[0132] In this embodiment, the first conductive portion 10 is also a common voltage line GND, and the transversely extending second lead 230 overlaps with the longitudinally extending portion of the common voltage line GND in the thickness direction of the array substrate.

[0133] The opening of the first conductive part 10 includes a third opening area 113, and the third opening area 113 is located in the longitudinally extending portion of the first conductive part 10; the third opening area 113 includes at least one third sub-opening area, and the projection of at least one section of the second lead 230 on the base substrate 900 is located in the area surrounded by the projection of the third sub-opening area 1130. In other words, the first conductive part 10 corresponding to at least one section of the second lead 230 is hollowed out, so that the second lead 230 and the first conductive part 10 below no longer overlap in this area, thereby avoiding short circuits between the second lead 230 and the first conductive part 10 due to static electricity, testing, and process reasons.

[0134] The second lead 230 may be completely hollowed out or only have a section hollowed out. In other words, the third opening area 113 may be disposed under the entire second lead 230 or only under a portion of the second lead 230 . Fig. 9 The third opening area 113 corresponding to the lower portion of the second lead 230 includes only one third sub-opening area 1130. In other embodiments, it may include multiple third sub-opening areas 1130. When there are multiple third sub-opening areas 1130, at least two third sub-opening areas may be interconnected, thereby reducing the difficulty of hollowing out.

[0135] In this embodiment, the first conductive portion 10 below the second lead 230 is hollowed out, thereby preventing a short circuit between the second lead 230 and the first conductive portion 10 due to static electricity or process reasons.

[0136] In the present disclosure, in the longitudinal direction, the third opening area 113 corresponding to the second lead 230 can be located at the upper edge or the lower edge of the first conductive part 10, or can be located in the middle of the first conductive part 10. Therefore, there is a gap between the projected edge of at least one of the upper and lower sides of the second lead 230 and the projected edge of the third opening area 113. Fig.10The third opening area 113 shown in the figure is a closed opening area, the projection of a section of the second lead 230 overlaps with the projection of the third opening area 113, and the projection edge of at least one of the upper and lower sides has a gap with the projection edge of the third opening area 113.

[0137] It should be noted that since the second lead 230 extends in the lateral direction, the third opening area 113 also extends in the lateral direction. For the third opening area 113 in a first conductive part 10, the lateral length of the third opening area 113 should be less than the width of the first conductive part 10, otherwise the first conductive part 10 will be cut off. Therefore, when the second lead 230 passes through the entire first conductive part 10 in the lateral direction, only a portion of the second lead 230 should be hollowed out. It can be understood that the longer the length of the third opening area 113 in the lateral direction, the greater the impact on the IR Drop of the first conductive part 10 extending longitudinally, resulting in a decrease in signal strength. However, the longer the length of the third opening area 113 in the lateral direction, the less the overlap area between the second lead 230 and the first conductive part 10, and the less likely it is to generate static electricity. In actual products, the lateral length of the third opening area 113 needs to be set by comprehensively considering two reasons. In addition, the second lead 230 may also cross over a plurality of longitudinally extending first conductive portions 10 at the same time, and then one or more third sub-opening areas 1130 may be provided in each first conductive portion 10. When a second lead 230 does not cross over a first conductive portion 10, that is, when the projection of the second lead 230 is only located within the projection of one first conductive portion 10, the corresponding third opening area 113 may include a plurality of third sub-opening areas 1130, which respectively correspond to a plurality of portions on the second lead 230.

[0138] In other embodiments, the second direction in which the second lead 230 extends may not be perpendicular to the first direction. Regardless of the direction, it should be ensured that the third opening area 113 corresponding to the second lead 230 does not cut off the first conductive portion 10 and minimizes the impact on IR Drop.

[0139] In this embodiment, since the first lead 220 or the second lead 230 is generally in the shape of a strip, the second opening area 112 and the third opening area 113 are also in the shape of a strip. The present disclosure does not limit the specific shapes of the second opening area 112 and the third opening area 113, which may be consistent with the shape of the lead or inconsistent.

[0140] In one embodiment, the second conductive part 20 further includes several functional units for realizing specific functions. For example, in this embodiment, the functional unit may be a first test conductive part 241, which is electrically connected to the pad, the first lead or the second lead, and is used to detect the electrical properties of the pad or the first lead or the second lead. For example, a needle test method may be used to test the current or voltage characteristics of the pad. Specifically, Fig.11The first test conductive part 241 and the fourth opening area 114 corresponding to the three sub-pads in the IC driver chip pad are shown in the figure. The three first test conductive parts 241 are respectively arranged near the first input pad Di, the second input pad Pwr, and the output pad Out. One end is connected to the sub-pad for testing the voltage and / or current of the sub-pad, and the other end can also be connected to the first lead or the second lead. The film layer (such as the second insulating layer 500 and the second inorganic layer 600) above the first test conductive part 241 is opened to expose the first test conductive part 241 to facilitate the needle test here.

[0141] The opening area 110 includes a fourth opening area 114, and the fourth opening area 114 includes three fourth sub-opening areas 1140. The projections of the three first test conductive parts 241 on the substrate are located one by one within the projections of each fourth sub-opening area 1140, and there is a gap between the projection of the first test conductive part 241 and the projection edge of the corresponding fourth sub-opening area 1140. In other words, the first conductive part 10 corresponding to the lower part of the first test conductive part 241 is hollowed out so that the first test conductive part 241 and the lower first conductive part 10 no longer overlap in this area, thereby avoiding the needle piercing the first test conductive part 241 and contacting the first conductive part 10 during the needle test, causing a short circuit or inaccurate test. Since the common voltage pad Gnd is connected to the common voltage line GND through a via, the current or voltage of the common voltage pad Gnd can be directly tested on the common voltage line GND. The number of the first test conductive parts 241 in this embodiment is only an example, and the specific number can be set as needed. For example, only one first test conductive part 241 can be set for a certain sub-pad, and this application does not specifically limit the number of the first test conductive parts 241. In this embodiment, the three fourth sub-opening areas 1140 are interconnected, thereby reducing the difficulty of hollowing out. In other embodiments, each fourth sub-opening area 1140 can also be independent of each other.

[0142] The above describes in detail the types of various second conductive parts 20 and the opening areas 110 corresponding to the first conductive parts. The array substrate disclosed in the present invention may include only any one of the second conductive parts 20 and the corresponding opening area 110, or may include at least any two second conductive parts 20 and the corresponding two opening areas 110. For example, the array substrate may include a pad 210 and a first lead 220 arranged longitudinally, and also include a first opening area 111 and a second opening area 112; it may also include a pad 210 and a first test conductive part 241, and also include a first opening area 111 and a fourth opening area 114; it may also include a pad 210, a first lead 220, a second lead 230 and a first test conductive part 241, and also include a first opening area 111, a second opening area 112, a third opening area 113 and a fourth opening area 114, etc., which are not listed here one by one.

[0143] In the present disclosure, when multiple opening areas are included, the multiple opening areas can be interconnected to further form a larger opening, thereby reducing the difficulty of hollowing out, that is, at least two of the first opening area 111, the second opening area 112, the third opening area 113 and the fourth opening area 114 are interconnected. The corresponding pads 210, the first leads 220, the second leads 230 or the first test conductive parts 241 in the larger opening can be connected to each other or not.

[0144] For example, refer to Fig.11 The fourth opening areas 114 of the first test conductive portion 241 can be interconnected with the first opening areas 111 corresponding to the adjacent sub-pads to form a large opening area.

[0145] For example, refer to Fig.12 In the array substrate, the first opening area 111 corresponding to the soldering pad of the first LED light-emitting device at the lower left, the second opening area 112 corresponding to the soldering pad 210 of the second LED light-emitting device at the upper left, and the third opening area 113 corresponding to the soldering pad 230 are connected in sequence; the first opening area 111 corresponding to the soldering pad 210 of the third LED light-emitting device at the upper right, the second opening area 112 corresponding to the soldering pad 220 at the right, and the first opening area 111 corresponding to the soldering pad 210 of the fourth LED light-emitting device at the lower right are connected in sequence.

[0146] At the same time, as shown in the figure, the first opening area 111 corresponding to the pad of the IC driver chip and the first opening area 111 corresponding below the pad 210 of the LED light-emitting device are also connected to each other.

[0147] In the above implementation mode, reference Figure 7, a certain gap d should be ensured between the projection edge of the second conductive part 20 on the base substrate 900 and the projection edge corresponding to the sub-opening area to ensure that the second conductive part 20 does not contact the first conductive part 10 below. In this embodiment, the gap is greater than or equal to a preset value, which includes the sum of process tolerance, maximum impurity size and reserved spacing. Among them, process tolerance refers to the dimensional deviation allowed in the process related process. Since the gap d is formed between the first conductive part 10 and the second conductive part 20, the tolerances of these two film layers will affect the size of the gap, so it includes the process tolerance of the first conductive part and the process tolerance of the second conductive part. The maximum size of impurities refers to the maximum diameter of impurity particles (partical) encountered in the process. If impurity particles fall into the gap, it may cause the first conductive part and the second conductive part to connect. Therefore, the influence of the impurity size needs to be considered when designing the gap size. The reserved spacing refers to a spacing value artificially set to form a gap. When the gap between the second conductive part 20 and the projected edge of the sub-opening area is greater than or equal to the sum of the above values, the contact between the two due to process tolerance and the presence of foreign particles can be avoided, ensuring that there is a sufficient distance between the second conductive part 20 and the first conductive part 10 below to prevent short circuit. Of course, on this basis, the preset value can further include dimensional deviations caused by other factors. Figure 7 In the structure shown, since the edge of the first opening area 111 and the edge of the sub-pad 2110 have different shapes, the minimum gap d between the projected edge of the sub-pad 2110 and the corresponding projected edge of the first opening area 111 should be greater than or equal to a preset value.

[0148] According to the current process technology, the process tolerance is about ±5um, the maximum size of impurities is about ±10um, and the reserved spacing is preferably 5um, so the gap d between the second conductive part 20 and the projected edge of the opening area 110 is greater than or equal to 20um. Furthermore, since an excessively large opening area may cause an excessively large IR Drop of the first conductive part 10, the gap between the second conductive part 20 and the projected edge of the opening area 110 is preferably less than or equal to 100μm, so as to minimize the IRDrop of the first conductive part 10.

[0149] In one embodiment, referring to Figure 13-Figure 20, the first conductive layer 100 further includes a plurality of conductive islands 120, at least one sub-opening area has a conductive island 120, and there is a gap between the outer periphery of the conductive island 120 and the first conductive part 10. The conductive island 120 and the first conductive part 10 are made of the same material, which can also be understood as digging an annular groove in the first conductive part 10 to form a separate conductive area, namely the conductive island 120. The second conductive part 20 above the opening area with the conductive island 120 is just located above the conductive island 120, and the projection of the second conductive part 20 on the base substrate 900 is correspondingly located within the projection of the conductive island 120 or completely overlaps with the projection of the conductive island 120. Since the second conductive part 20 is located above the conductive island 120, and the conductive island 120 is spaced apart from the first conductive part 10, even if the second conductive part 20 is short-circuited with the conductive island 120, the first conductive part 10 will not be affected.

[0150] In the present disclosure, when describing that two structures are “completely overlapped”, it means that the orthographic projection of one of the structures on the substrate is completely located within the orthographic projection of the other structure on the substrate.

[0151] For example, taking the solder pad used to install the LED light emitting device as an example, refer to Fig.13 and Fig.14 A conductive island 120 is correspondingly disposed in the first sub-opening area 1110 below the anode pad, and a conductive island 120 is correspondingly disposed in the first sub-opening area 1110 below the cathode pad. There is a gap between the outer periphery of the two conductive islands 120 and the first conductive portion 10. In one embodiment, referring to Fig.15 and 16 The two first sub-opening areas 1110 are interconnected to form an opening, and the two conductive islands 120 are interconnected to form an integrated structure, thereby reducing the difficulty of slotting and facilitating processing.

[0152] Take the pad for mounting IC driver chip as an example, refer to Fig.17 , a conductive island 120 is respectively disposed in the first sub-opening area 1110 below the first input pad Di2113, the second input pad Pwr2114, the output pad Out2115 and the common voltage pad Gnd2116, and there is a gap between the outer periphery of the four conductive islands 120 and the first conductive portion 10, and the four first sub-opening areas 1110 are interconnected to form an opening. In one embodiment, referring to Fig.18 , the four conductive islands 120 are interconnected into an integrated structure.

[0153] Taking the first lead 220 and the second lead 230 as an example, refer to Fig.19 A conductive island 120 is disposed in the second opening area 112 below the first lead 220 , and there is a gap between the outer periphery of the conductive island 120 and the first conductive portion 10 .

[0154] Taking the first test conductive portion 241 as an example, refer to Fig. 20 A conductive island 120 is disposed in each of the three fourth sub-opening areas 1140 below the three first test conductive parts 241 , and a gap exists between the outer periphery of the conductive island 120 and the first conductive part 10 .

[0155] exist Fig.14 , 17 In the structure shown, each sub-opening area of ​​the opening area under the same pad is connected to each other, and the conductive islands 120 in each sub-opening area are independent of each other. Fig.15 , 18 In the structure shown, the sub-opening areas of the opening area under the same pad are interconnected, and the conductive islands 120 in each sub-opening area are interconnected to reduce the difficulty of preparation. Of course, in other embodiments, at least two of the first opening area 111, the second opening area 112, the third opening area 113, and the fourth opening area 114 can be interconnected, and the conductive islands 120 in the interconnected opening areas can also be independent of each other or connected as a whole. For example, the two conductive islands 120 under the first lead 220 and the pad 210 can also be connected to each other into an integrated structure, the two conductive islands 120 under the first lead 220 and the second lead 230 can also be connected to each other into an integrated structure, or the conductive islands 120 under the pad 210 and the first test conductive portion 241 can also be connected to each other, that is, the conductive islands in any interconnected opening areas can be connected as a whole.

[0156] A certain gap d should also be ensured between the outer periphery of the conductive island 120 and the edge of the sub-opening area of ​​the first conductive part 10 to ensure that the second conductive part 20 above the conductive island 120 does not form an electrical contact with the first conductive part 10 below. Similar to the gap d, the gap h is also preferably greater than or equal to the preset value including the sum of the process tolerance, the maximum size of impurities and the reserved spacing. The difference is that since the gap h is formed between the first conductive part 10 and the conductive island 120 in the first conductive layer, when calculating the preset value, the process tolerance refers to the process tolerance caused by the relevant process when making the first conductive part. Similarly, the gap h between the outer periphery of the conductive island 120 and the edge of the sub-opening area of ​​the first conductive part 10 is preferably greater than or equal to 20μm, thereby avoiding the conductive island 120 from contacting the first conductive part 10 due to factors such as process deviation. Further, the gap h between the outer periphery of the conductive island 120 and the edge of the sub-opening area of ​​the first conductive part 10 is also preferably less than or equal to 100μm, which can minimize the IR Drop of the first conductive part 10.

[0157] In the embodiments of the present disclosure, the first conductive portion can be formed by magnetron sputtering or electroplating. Since electroplating is usually used to form a thicker film layer, if a hollowed-out structure is formed in the opening area, a large film thickness discontinuity will often appear at the edge of the opening area. Considering the uniformity or flatness of the film layer, a large thickness discontinuity is actually undesirable. Therefore, when the electroplating process is used, it is preferably used to prepare an array substrate containing a conductive island structure, so that the film layer formed is thicker and has better flatness. The film layer thickness usually formed by the magnetron sputtering process is thinner than that of the electroplating process, and is more suitable for forming a hollowed-out structure in the opening area.

[0158] Reference Fig. 20 and Fig.21 , Fig.21 for Fig. 20 In the cross-sectional schematic diagram at AA in the figure, the second conductive layer also includes a second test conductive part 242, which overlaps with the projection of the first conductive part 10 on the substrate and is electrically connected through a via. The second test conductive part 242 is used to detect the electrical properties of the first conductive part 10. For example, when the common voltage line GND needs to be tested, the second test conductive part 242 can be set in the second conductive layer, and the second test conductive part 242 can be electrically connected to the common voltage line GND through a via, so that the performance data of the common voltage line GND can be obtained. In the prior art, the film layer above the area to be tested of the first conductive part 10 is opened, so as to directly test the first conductive part 10. Then, during the preparation process, the area to be tested of the first conductive part 10 needs to be exposed to the air to wait for other film layers to be prepared above. Due to the limitation of material properties, the first conductive part 10 is easily corroded if it is exposed for too long, which affects signal transmission. The second test conductive part 242 covers the first conductive part 10 to protect the first conductive part 10 and prevent it from being corroded. The second test conductive part 242 belongs to the second conductive layer. The copper-nickel alloy in the material thereof has strong corrosion resistance and is not easily corroded even when exposed to the outside, thereby ensuring a good test effect.

[0159] In the above embodiments, each pad, lead and common voltage line GND overlap as an example for description. Fig. 22 ,for Figure 1 Another partial enlarged view of the middle M area, that is, another schematic layout diagram of an array substrate. Each pad and lead can also overlap with other signal lines, for example, overlap with the driving voltage line VLED, that is, the first conductive portion 10 can also be the driving voltage line VLED, then the corresponding opening area 110 is set in the driving voltage line VLED. The specific structure is similar to the previous embodiment and will not be repeated here.

[0160] The array substrate disclosed in the present invention can be bound with a light-emitting device and used as a substrate with a light-emitting function, and can also be further applied to a display device as a backlight unit.

[0161] The embodiment of the present invention further provides a display device, which includes the array substrate in the above embodiment. Since the display device includes the above array substrate, it has the same beneficial effects, and the present invention will not be repeated here.

[0162] The present invention does not impose any specific restrictions on the applicability of the display device, which can be any product or component with a flexible display function, such as a television, a laptop computer, a tablet computer, a wearable display device, a mobile phone, a car display, a navigation, an e-book, a digital photo frame, an advertising light box, etc.

[0163] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate, characterized in that: include: substrate substrate; A first conductive layer, disposed on one side of the base substrate, comprises a first conductive portion; A second conductive layer, disposed on a side of the first conductive layer away from the base substrate, comprising a second conductive portion; wherein a projection of at least part of the second conductive portion on the substrate does not overlap with a projection of the first conductive portion on the substrate; The first conductive portion has an opening area, and at least a portion of the projection of the second conductive portion on the substrate is located within the area surrounded by the projection of the opening area; The second conductive portion at least includes a pad for arranging a light-emitting chip, and the pad and the first conductive layer are insulated from each other in the opening area; The second conductive portion includes a first lead, and a projection of at least a section of the first lead on the base substrate does not overlap with a projection of the first conductive layer on the base substrate; The opening area is used to reduce the overlapping area between the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first lead on the substrate, and the opening area includes a second opening area, and the second opening area includes at least one second sub-opening area. The number of the second sub-opening areas is multiple, and at least two of the second sub-opening areas are connected to each other.

2. An array substrate, characterized in that: include: substrate substrate; A first conductive layer, disposed on one side of the base substrate, includes a first conductive portion; A second conductive layer, disposed on a side of the first conductive layer away from the base substrate, comprising a second conductive portion; wherein a projection of at least part of the second conductive portion on the substrate does not overlap with a projection of the first conductive portion on the substrate; The first conductive portion has an opening area, and at least a portion of the projection of the second conductive portion on the substrate is located within the area surrounded by the projection of the opening area; The second conductive portion at least includes a pad for arranging a light-emitting chip, and the pad and the first conductive layer are insulated from each other in the opening area; At least a portion of the first conductive portion extends along the first direction, and the opening area includes a third opening area, and the third opening area includes at least one third sub-opening area; the second conductive portion includes a second lead extending along a second direction, and the second direction intersects with the first direction; at least a portion of the projection of the second lead on the substrate overlaps with the area enclosed by the projection of the third sub-opening area.

3. An array substrate, characterized in that: include: substrate substrate; A first conductive layer, disposed on one side of the base substrate, comprises a first conductive portion; A second conductive layer, disposed on a side of the first conductive layer away from the base substrate, comprising a second conductive portion; wherein a projection of at least part of the second conductive portion on the substrate does not overlap with a projection of the first conductive portion on the substrate; The first conductive portion has an opening area, and at least a portion of the projection of the second conductive portion on the substrate is located within the area surrounded by the projection of the opening area; The second conductive portion at least includes a pad for arranging a light-emitting chip, and the pad and the first conductive layer are insulated from each other in the opening area; The thickness of the first conductive layer is greater than 1.5-7 micrometers, and the first conductive layer includes copper.

4. The array substrate according to any one of claims 1 to 3, characterized in that: A gap exists between a projected edge of a portion of the second conductive portion corresponding to the opening area and a projected edge of the opening area.

5. The array substrate according to claim 4, characterized in that: The second conductive portion includes at least any one of a pad, a first lead, a second lead, and a functional unit; The opening region includes at least any one of a first opening region, a second opening region, a third opening region, and a fourth opening region.

6. The array substrate according to claim 5, characterized in that: The opening area includes a first opening area, and the first opening area includes a plurality of first sub-opening areas; The second conductive portion includes a plurality of groups of pads, and each group of pads includes a plurality of sub-pads; Projections of at least some of the sub-pads on the base substrate are located one-to-one in the area surrounded by the projections of the first sub-opening areas, and the projection periphery of each sub-pad has a gap with the projection edge of the corresponding first sub-opening area.

7. The array substrate according to claim 6, characterized in that: The first sub-opening areas corresponding to the sub-pads of the same group of pads are connected to each other.

8. The array substrate according to claim 5, characterized in that: At least a portion of the first conductive portion extends along a first direction, the opening area includes a second opening area, and the second opening area includes at least one second sub-opening area; The second conductive portion includes a first lead extending along the first direction; The projection of at least part of the first lead on the base substrate overlaps with the area enclosed by the projection of the second sub-opening area, and a gap exists between the projection edge of at least one side of the first lead and the projection edge of the second sub-opening area.

9. The array substrate according to claim 5, characterized in that: At least a portion of the first conductive portion extends along the first direction, the opening area includes a third opening area, the third opening area includes at least one third sub-opening area, and there is a gap between edges of opposite sides of the second lead and a projected edge of the third sub-opening area.

10. The array substrate according to claim 9, characterized in that: There are multiple third sub-opening areas, and at least two of the third sub-opening areas are connected to each other.

11. The array substrate according to claim 3, characterized in that: The opening area includes a fourth opening area, and the fourth opening area includes at least one fourth sub-opening area; The second conductive part includes a plurality of functional units; The projections of the functional units on the base substrate are located one by one within the area surrounded by the projections of the fourth sub-opening areas, and the projection peripheries of the functional units have gaps with the projection edges of the corresponding fourth sub-opening areas.

12. The array substrate according to claim 11, characterized in that: There are multiple fourth sub-opening areas, and at least two of the fourth sub-opening areas are connected to each other.

13. The array substrate according to claim 12, characterized in that: The functional unit includes a first test conductive portion electrically connected to the pad, the first lead or the second lead, and the first test conductive portion is used to detect electrical properties of the pad, the first lead or the second lead.

14. The array substrate according to claim 5, characterized in that: At least two of the first opening area, the second opening area, the third opening area, and the fourth opening area are interconnected.

15. The array substrate according to claim 5, characterized in that: The gap between the projected edge of the second conductive portion and the projected edge of the corresponding sub-opening area is greater than or equal to a preset value, and the preset value includes the sum of the process tolerance, the maximum size of the impurities and the reserved spacing; Among them, the process tolerance refers to the dimensional deviation allowed in the preparation process of the first conductive part and / or the second conductive part, the maximum impurity size refers to the maximum diameter of the impurity particles in the process, and the reserved spacing is the spacing value artificially set to form the gap.

16. The array substrate according to claim 6, characterized in that: The first conductive layer further comprises a plurality of conductive islands, at least one of the sub-opening regions comprises the conductive island, and a gap exists between the periphery of the conductive island and the edge of the corresponding sub-opening region; A projection of at least one of the sub-pad, the first lead, the second lead or the first test conductive portion on the substrate is located within a projection of a corresponding conductive island or completely overlaps with a projection of each conductive island.

17. The array substrate according to claim 16, characterized in that: At least two sub-opening areas of the same opening area are interconnected, and the conductive islands in the interconnected sub-opening areas are independent of each other or connected as a whole.

18. The array substrate according to claim 16, characterized in that: At least two of the first opening area, the second opening area, the third opening area, and the fourth opening area are interconnected, and the conductive islands in the interconnected opening areas are independent of each other or connected as a whole.

19. The array substrate according to claim 1, characterized in that: The second conductive layer further includes a second test conductive portion, which overlaps with a projection of the first conductive portion on the base substrate and is electrically connected through a via, and the second test conductive portion is used to detect electrical properties of the first conductive portion.

20. The array substrate according to any one of claims 1 to 3, characterized in that: A first insulating layer and a first inorganic layer are disposed between the first conductive layer and the second conductive layer, and a second insulating layer and a second inorganic layer are disposed on a side of the second conductive layer away from the base substrate.

21. The array substrate according to any one of claims 1 to 3, characterized in that: The pad includes four sub-pads, namely a first input pad, a second input pad, an output pad and a common voltage pad; The first input pad is configured to receive a first input signal, wherein the first input signal is an address signal for selecting a driver chip of a corresponding address, and an address to be transmitted can be obtained by parsing the address signal; The second input pad is configured to receive a second input signal, the second input signal is a power line carrier communication signal from a source power line, the second input signal is used to provide power to the driver chip and transmit communication data to the driver chip, the communication data is used to control the light emission duration of the corresponding light emitting unit; The output pad is configured to output a driving signal, and the driving signal may be a driving voltage from a driving voltage line, and is used to drive the light emitting element to emit light; The common voltage pad is configured to receive a common voltage signal, where the common voltage signal is a ground signal from a common voltage line.

22. The array substrate according to claim 8, characterized in that: The size of the second opening area along the first direction is larger than that along the second direction, and the size of the third opening area along the second direction is larger than that along the first direction.

23. The array substrate according to claim 16, characterized in that: There is a gap between the outer periphery of the conductive island and the first conductive part. The second conductive part is located on a side of the conductive island away from the substrate. The conductive island is insulated from the first conductive part; the conductive island is insulated from the second conductive part.

24. A display device, characterized in that: Comprising the array substrate according to any one of claims 1-23.

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