Turn-off converter valve and overvoltage suppression method for turn-off converter valve

Abstract

The invention provides a turn-off converter valve and an overvoltage suppression method for the turn-off converter valve, and relates to the technical field of high-voltage direct-current power transmission. The turn-off converter valve comprises N2 turn-off valve sections, wherein each turn-off valve section comprises N1 turn-off power semiconductor devices; the gate pole driving unit is connected with the turn-off power semiconductor device and is used for triggering and conducting the turn-off power semiconductor device under the condition that the voltage at the two ends of the cathode and the anode of the turn-off power semiconductor device is greater than a preset protective triggering action threshold so as to realize turn-off power semiconductor device level overvoltage suppression; the first lightning arrester is connected in parallel with the N1 turn-off power semiconductor devices which are connected in series so as to realize turn-off valve section-level overvoltage suppression; and the second lightning arrester is connected in parallel with N2 turn-off valve sections which are connected in series, so that turn-off single-valve-level overvoltage suppression is realized, a constraint relationship among triple protection is given, and the problem of overvoltage suppression during turn-off of the turn-off converter valve is solved.

Description

Technical Field

[0001] The present application relates to the technical field of high-voltage direct current transmission, and in particular to a switchable converter valve and an overvoltage suppression method for the switchable converter valve. Background Art

[0002] Line-commuted converters (LCCs) based on semi-controlled devices are widely used in DC transmission systems due to their low loss and low cost. The switching devices for commutation in semi-controlled converters can be either uncontrolled devices (such as diodes) or semi-controlled devices (such as thyristors). However, when semi-controlled converters are operated under weak AC system connection or when the AC system fails, commutation failures are prone to occur due to AC system voltage disturbances.

[0003] In order to solve the problem of commutation failure on the receiving side of the DC transmission system, some scholars have proposed in recent years to use a converter valve with controllable shutoff capability in the receiving system, that is, to add a controllable shutoff device to the original converter valve bridge arm to achieve forced commutation, thereby effectively avoiding the occurrence of commutation failure. However, the new topology is a complex system with a large number of uncontrolled devices, semi-controlled devices, and fully controlled devices in series / parallel, and the turnable device will generate a high overvoltage when the device is forced to shut down. If the overvoltage is not suppressed, it will cause the device to break down and be damaged. Therefore, how to suppress the overvoltage when the turnable converter valve is turned off is a technical difficulty that needs to be considered. Summary of the invention

[0004] In order to solve at least one of the above problems, the present application proposes a switchable converter valve and an overvoltage suppression method for the switchable converter valve.

[0005] According to the first aspect of the present application, at least one embodiment of the present application provides a switchable converter valve, comprising: N2 switchable valve sections, N2 is an integer greater than or equal to 1, the N2 switchable valve sections are connected in series, each of the N2 switchable valve sections comprises N1 switchable power semiconductor devices, N1 is an integer greater than 1, the N1 switchable power semiconductor devices are connected in series; a gate drive unit, connected to the switchable power semiconductor device, for triggering the switchable power semiconductor device to conduct when the voltage across the anode and cathode of the switchable power semiconductor device is greater than a preset protective trigger action threshold. A power semiconductor device to achieve overvoltage suppression at the turnable power semiconductor device level; a first lightning arrester connected in parallel with the N1 turnable power semiconductor devices connected in series, for turning on the first lightning arrester when the terminal voltage of the N1 turnable power semiconductor devices is greater than the protective residual voltage of the first lightning arrester, so as to achieve overvoltage suppression at the turnable valve section level; a second lightning arrester connected in parallel with the N2 turnable valve sections connected in series, for turning on the second lightning arrester when the terminal voltage of the N2 turnable valve sections is greater than the protective residual voltage of the second lightning arrester, so as to achieve overvoltage suppression at the turnable single valve level.

[0006] For example, in some embodiments of the present application, it also includes: a DC equalizing resistor, connected in parallel with the turnable power semiconductor device; a damping circuit, connected in parallel with the turnable power semiconductor device, and the damping circuit includes a damping capacitor and a damping resistor connected in series.

[0007] For example, in some embodiments of the present application, the turn-off power semiconductor device includes at least one of an IGCT, an IGBT, an IGET and a MOSFET.

[0008] According to the second aspect of the present application, at least one embodiment of the present application provides an overvoltage suppression method for a switchable converter valve, which is executed by the switchable converter valve as described in any one of the first aspects, and the overvoltage suppression method includes: when the gate drive unit detects that the voltage across the anode and cathode of the switchable power semiconductor device is greater than the protective trigger action threshold, the gate drive unit triggers the switchable power semiconductor device to turn on the switchable power semiconductor device to achieve overvoltage suppression at the switchable power semiconductor device level; when the terminal voltage of the N1 switchable power semiconductor devices is greater than the protective residual voltage of the first lightning arrester, the first lightning arrester is turned on to achieve overvoltage suppression at the switchable valve section level; when the terminal voltage of the N2 switchable valve sections is greater than the protective residual voltage of the second lightning arrester, the second lightning arrester is turned on to achieve overvoltage suppression at the switchable single valve level.

[0009] For example, in some embodiments of the present application, the protective trigger action threshold, the protective residual voltage of the first lightning arrester, and the protective residual voltage of the second lightning arrester satisfy the following constraints:

[0010]

[0011] Among them, U BOD is the protective trigger action threshold, U MOV1 is the protection residual voltage of the first arrester, k1 is the deviation value of the protection trigger action threshold, U DRM is the off-state repetitive peak voltage of the turn-off power semiconductor device, k d is the voltage distribution unevenness coefficient of the device in the switchable converter valve, U MOV2 is the protection residual voltage of the second arrester, N res is the device redundancy level of the switchable converter valve, and k2 is the uneven pressure coefficient of the valve section voltage distribution in the switchable converter valve.

[0012] For example, in some embodiments of the present application, the protection residual voltage of the first lightning arrester also satisfies the following constraints:

[0013]

[0014] Wherein, k3 is the uneven pressure coefficient when the shutoff power semiconductor device in the shutoff valve section is shut off.

[0015] For example, in some embodiments of the present application, the DC reference voltage of the first lightning arrester is higher than the voltage peak value of the turn-off power semiconductor device during normal operation:

[0016]

[0017] Among them, U res is the DC reference voltage of the first lightning arrester, k4 is the charge rate of the first lightning arrester, U PCOV The maximum peak value of the continuous operating voltage of the switchable converter valve including the commutation overshoot.

[0018] For example, in some embodiments of the present application, the coordination current of the first lightning arrester under the protection residual voltage satisfies:

[0019] I MOV1 >k5·I off

[0020] Among them, I MOV1 is the matching current, k5 is the maximum turn-off current peak value of the turn-off power semiconductor device, I off is the withstand current of the turn-off power semiconductor device during the turn-off period.

[0021] For example, in some embodiments of the present application, the withstand energy of the first lightning arrester during the shutdown of the turn-off power semiconductor device satisfies:

[0022]

[0023] Among them, E MOV1 is the withstand energy of the first lightning arrester during the shutdown of the turnable power semiconductor device, L hx is the commutation inductance of the switchable converter valve, and N3 is the number of times the switchable power semiconductor device is continuously turned off.

[0024] For example, in some embodiments of the present application, the total withstand voltage value of the turnable power semiconductor device in the turnable converter valve at the minimum series connection number is higher than the withstand voltage level of the second lightning arrester:

[0025]

[0026] Among them, k m is the safety factor of the second lightning arrester under impulse voltage.

[0027] Through the above-mentioned example embodiments, the present application provides a switchable converter valve and an overvoltage suppression method for the switchable converter valve, which realizes overvoltage suppression at the switchable power semiconductor device level through protective triggering of the gate drive unit; realizes overvoltage suppression at the switchable valve section level through a first lightning arrester connected in parallel; realizes overvoltage suppression at the switchable single valve level through a second lightning arrester connected in parallel; and provides the constraint relationship between the above-mentioned triple protections to solve the problem of overvoltage suppression during the shutdown period of the new switchable converter valve.

[0028] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] By describing in detail exemplary embodiments thereof with reference to the accompanying drawings, the above and other objects, features and advantages of the present application will become more apparent. The accompanying drawings described below are only some embodiments of the present application, and are not intended to limit the present application.

[0030] Figure 1 A schematic diagram showing a topology of a switchable converter valve according to an exemplary embodiment;

[0031] Figure 2 A flow chart of an overvoltage suppression method for a switchable converter valve according to an exemplary embodiment is shown. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0033] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of these specific details, or other modes, components, materials, devices, etc. may be adopted. In these cases, known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0034] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0035] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0036] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present application, and therefore cannot be used to limit the scope of protection of the present application.

[0037] Figure 1 A schematic diagram of a switchable converter valve topology is shown in accordance with an exemplary embodiment.

[0038] like Figure 1As shown, the switchable converter valve includes: N2 switchable valve sections 11-1N2, N2 is an integer greater than or equal to 1. The N2 switchable valve sections are connected in series. Each switchable valve section includes N1 switchable power semiconductor devices 111-11N1, N1 is an integer greater than 1. The N1 switchable power semiconductor devices are connected in series. The first lightning arrester MOV1-11~MOV1-1 N2, the second lightning arrester MOV2-1 and the gate drive unit.

[0039] Among them, the first lightning arrester is connected in parallel with the N1 turnable power semiconductor devices connected in series, and is used for the first lightning arrester to be turned on when the terminal voltage of the N1 turnable power semiconductor devices is greater than the protective residual voltage of the first lightning arrester, so as to achieve the overvoltage suppression of the turnable valve section level. The second lightning arrester is connected in parallel with the N2 turnable valve sections connected in series, and is used for the second lightning arrester to be turned on when the terminal voltage of the N2 turnable valve sections is greater than the protective residual voltage of the second lightning arrester, so as to achieve the overvoltage suppression of the turnable single valve level. Taking the turnable power semiconductor device 111 as an example, a gate drive unit 1111 is configured, and the gate drive unit 1111 is used to detect whether the voltage across the anode and cathode of the turnable power semiconductor device 111 is greater than the preset protective trigger action threshold, and trigger the turn-on trigger power semiconductor device 111 when the voltage across the anode and cathode of the turnable power semiconductor device 111 is greater than the protective trigger action threshold.

[0040] According to some embodiments, taking the turnable power semiconductor device 111 as an example, the turnable converter valve further includes: a DC voltage balancing resistor 1112 and a damping circuit.

[0041] The DC voltage balancing resistor 1112 is connected in parallel with the turn-off power semiconductor device 111. The damping circuit is connected in parallel with the turn-off power semiconductor device 111. The damping circuit includes a damping capacitor 1113 and a damping resistor 1114 connected in series.

[0042] According to some embodiments, the turn-off power semiconductor device includes at least one of an IGCT, an IGBT, an IGET, and a MOSFET.

[0043] Figure 2 A flow chart of an overvoltage suppression method for a switchable converter valve according to an exemplary embodiment is shown.

[0044] like Figure 2 As shown, the overvoltage suppression method for a switchable converter valve includes steps S1-S3.

[0045] In step S1 , power semiconductor device level overvoltage suppression may be turned off.

[0046] When the gate drive unit detects that the voltage across the anode and cathode of the turn-off power semiconductor device is greater than the protective trigger action threshold, the gate drive unit triggers the turn-off power semiconductor device to turn on, so as to achieve overvoltage suppression at the turn-off power semiconductor device level.

[0047] In step S2 , the valve section level overvoltage suppression may be switched off.

[0048] When the terminal voltage of N1 turn-off power semiconductor devices is greater than the protective residual voltage of the first lightning arrester, the first lightning arrester is turned on to achieve overvoltage suppression at the turn-off valve stage.

[0049] In step S3, the single valve level overvoltage suppression may be turned off.

[0050] When the terminal voltage of the N2 turn-off valve sections is greater than the protective residual voltage of the second lightning arrester, the second lightning arrester is turned on to achieve turn-off single-valve level overvoltage suppression.

[0051] The protective trigger action threshold, the protective residual voltage of the first lightning arrester, and the protective residual voltage of the second lightning arrester meet the following constraints:

[0052]

[0053] Among them, U BOD is the protective trigger action threshold, U MOV1 is the protective residual voltage of the first arrester, k1 is the deviation value of the protective trigger action threshold, U DRM is the off-state repetitive peak voltage of the turn-off power semiconductor device, k d is the voltage distribution unevenness coefficient of the device in the switchable converter valve, U MOV2 is the protection residual voltage of the second arrester, N res is the device redundancy level of the switchable converter valve, which is a non-negative integer, and k2 is the voltage distribution uneven pressure coefficient of the valve section in the switchable converter valve.

[0054] According to some embodiments, U DRM , U MOV2 Usually a known parameter, given by U DRM , U MOV2 Calculate U BOD , U MOV1 .

[0055] According to some embodiments, the protection residual voltage of the first lightning arrester also satisfies the following constraints:

[0056]

[0057] Wherein, k3 is the uneven pressure coefficient when the power semiconductor device that can be turned off in the shutoff valve section is turned off. The more devices are connected in series in the shutoff valve section, the greater the uneven pressure coefficient when the power semiconductor device that can be turned off is turned off.

[0058] According to some embodiments, when N1 is 2, k3 is 1.15, and when N1 is 3, k3 is 1.2.

[0059] According to some embodiments, the DC reference voltage of the first lightning arrester should be higher than the voltage peak value of the turn-off power semiconductor device during normal operation:

[0060]

[0061] Among them, U res is the DC reference voltage of the first arrester, k4 is the charge rate of the first arrester, U PCOV The maximum peak value of the continuous operating voltage of the switchable converter valve including the commutation overshoot.

[0062] According to some embodiments, the coordination current of the first lightning arrester under the protection residual voltage satisfies:

[0063] I MOV1 >k5·I off

[0064] Among them, I MOV1 To match the current, k5 is the maximum turn-off current peak value of the power semiconductor device that can be turned off, I off It is the withstand current of the turn-off power semiconductor device during the turn-off period.

[0065] According to some embodiments, the withstand energy of the first lightning arrester during the shutdown of the turn-off power semiconductor device satisfies:

[0066]

[0067] Among them, E MOV1 is the withstand energy of the first lightning arrester during the shutdown period of the turn-off power semiconductor device, L hx is the commutation inductance of the turn-off converter valve, and N3 is the number of times the turn-off power semiconductor device is continuously turned off.

[0068] The total withstand voltage value of the switchable power semiconductor device in the switchable converter valve at the minimum series connection number should be higher than the withstand voltage level of the second lightning arrester:

[0069]

[0070] Among them, k m is the safety factor of the second arrester under impulse voltage.

[0071] According to some embodiments, kd , k m , k1, k2, k3 are greater than or equal to 1, k4, k5 are positive numbers less than or equal to 1.

[0072] The present application provides a method for overvoltage suppression for a switchable converter valve, which realizes overvoltage suppression at the switchable power semiconductor device level by protective triggering of a gate drive unit; realizes overvoltage suppression at the switchable valve section level by connecting a first lightning arrester in parallel; realizes overvoltage suppression at the switchable single valve level by connecting a second lightning arrester in parallel; and provides a constraint relationship between the above-mentioned triple protections to solve the problem of overvoltage suppression during the shutdown period of the new switchable converter valve.

[0073] It should be clearly understood that the present application describes how to form and use specific examples, but the present application is not limited to any details of these examples. On the contrary, based on the teaching of the content disclosed in the present application, these principles can be applied to many other embodiments.

[0074] In addition, it should be noted that the above figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It is easy to understand that the processes shown in the above figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0075] The exemplary embodiments of the present application are specifically shown and described above. It should be understood that the present application is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present application is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A switchable flow control valve, characterized in that: include: N2 turnable valve sections, N2 is an integer greater than or equal to 1, the N2 turnable valve sections are connected in series, each of the N2 turnable valve sections includes N1 turnable power semiconductor devices, N1 is an integer greater than 1, and the N1 turnable power semiconductor devices are connected in series; A gate drive unit connected to the turnable power semiconductor device, and configured to trigger the turnable power semiconductor device to turn on when the voltage across the anode and cathode of the turnable power semiconductor device is greater than a preset protective trigger action threshold, so as to achieve overvoltage suppression at the turnable power semiconductor device level; A first lightning arrester is connected in parallel with the N1 turnable power semiconductor devices connected in series, and is used for turning on the first lightning arrester when the terminal voltage of the N1 turnable power semiconductor devices is greater than the protection residual voltage of the first lightning arrester, so as to achieve overvoltage suppression at the turnable valve stage level; The second lightning arrester is connected in parallel with the N2 shutoff valve sections connected in series, and is used for turning on the second lightning arrester when the terminal voltage of the N2 shutoff valve sections is greater than the protective residual voltage of the second lightning arrester, so as to achieve shutoff single-valve level overvoltage suppression.

2. The switchable converter valve according to claim 1, characterized in that: Also includes: A DC voltage balancing resistor connected in parallel with the turn-off power semiconductor device; A damping circuit is connected in parallel with the turn-off power semiconductor device, wherein the damping circuit comprises a damping capacitor and a damping resistor connected in series.

3. The switchable converter valve according to claim 1 or 2, characterized in that: The turn-off power semiconductor device includes at least one of an IGCT, an IGBT, an IGET and a MOSFET.

4. A method for suppressing overvoltage of a switchable converter valve, characterized in that: The overvoltage suppression method is performed by the switchable converter valve according to any one of claims 1 to 3, comprising: When the gate driving unit detects that the voltage across the anode and cathode of the turn-off power semiconductor device is greater than the protective trigger action threshold, the gate driving unit triggers and turns on the turn-off power semiconductor device to achieve overvoltage suppression at the turn-off power semiconductor device level; When the terminal voltage of the N1 turn-off power semiconductor devices is greater than the protection residual voltage of the first lightning arrester, the first lightning arrester is turned on to achieve overvoltage suppression at the turn-off valve stage level; When the terminal voltages of the N2 turn-off valve sections are greater than the protective residual voltage of the second lightning arrester, the second lightning arrester is turned on to achieve turn-off single-valve level overvoltage suppression.

5. The overvoltage suppression method according to claim 4, characterized in that: The protective trigger action threshold, the protective residual voltage of the first lightning arrester and the protective residual voltage of the second lightning arrester meet the following constraints: Among them, U BOD is the protective trigger action threshold, U MOV1 is the protection residual voltage of the first arrester, k1 is the deviation value of the protection trigger action threshold, U DRM is the off-state repetitive peak voltage of the turn-off power semiconductor device, k d is the voltage distribution unevenness coefficient of the device in the switchable converter valve, U MOV2 is the protection residual voltage of the second arrester, N res is the device redundancy level of the switchable converter valve, and k2 is the uneven pressure coefficient of the valve section voltage distribution in the switchable converter valve.

6. The overvoltage suppression method according to claim 5, characterized in that: The protection residual voltage of the first arrester also meets the following constraints: Wherein, k3 is the uneven pressure coefficient when the shutoff power semiconductor device in the shutoff valve section is shut off.

7. The overvoltage suppression method according to claim 5, characterized in that: The DC reference voltage of the first lightning arrester is higher than the voltage peak value of the turn-off power semiconductor device during normal operation: Among them, U res is the DC reference voltage of the first lightning arrester, k4 is the charge rate of the first lightning arrester, U PCOV The maximum peak value of the continuous operating voltage of the switchable converter valve including the commutation overshoot.

8. The overvoltage suppression method according to claim 5, characterized in that: The coordination current of the first lightning arrester under the protection residual voltage satisfies: I MOV1 >k5·I off Among them, I MOV1 is the matching current, k5 is the maximum turn-off current peak value of the turn-off power semiconductor device, I off is the withstand current of the turn-off power semiconductor device during the turn-off period.

9. The overvoltage suppression method according to claim 8, characterized in that: The withstand energy of the first lightning arrester during the shutdown of the turnable power semiconductor device satisfies: Among them, E MOV1 is the withstand energy of the first lightning arrester during the shutdown of the turnable power semiconductor device, L hx is the commutation inductance of the switchable converter valve, and N3 is the number of times the switchable power semiconductor device is continuously turned off.

10. The overvoltage suppression method according to claim 6, characterized in that: The total withstand voltage value of the switchable power semiconductor devices in the switchable converter valve at the minimum series connection number is higher than the withstand voltage level of the second lightning arrester: Among them, k m is the safety factor of the second lightning arrester under impulse voltage.

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