Performing operations on memory server

Abstract

The invention relates to performing operations on a memory server. In some examples, a system includes a plurality of memory servers that manage access to data in memory. The computer node includes a plurality of buffers associated with the memory server. A processor performs a plurality of functions accessible by the computer node to access data of the memory server, the plurality of functions including: associating information specifying a type of operation to be performed on the data using the plurality of buffers with the plurality of buffers; queuing the operations in the plurality of buffers; initiating execution of the operation at the memory server associated with the plurality of buffers based on the type specified by the information; and providing a result of the operation from the memory server to the computer node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Some embodiments of the disclosure are described with respect to the following figures.

[0002] Figure 1 is a block diagram of an arrangement including a cluster of computer nodes coupled to a networked storage, according to some examples.

[0003] Figure 2 is a block diagram of a request, a buffer storing operation elements specified by the request, and a queue in a memory server according to some examples.

[0004] Figure 3 is a flow diagram of a process for queuing operations in a buffer of a computer node, according to some examples.

[0005] Figure 4 is a flow diagram of a process for sending operations queued in a buffer of a computer node to a memory server for execution, according to some examples.

[0006] Figure 5 is a block diagram of a system according to some examples.

[0007] Figure 6 is a flowchart of a process for offloading operations to a storage server according to some examples.

[0008] Figure 7 is a block diagram of a storage medium storing machine-readable instructions according to some examples.

[0009] Throughout the drawings, the same reference numerals refer to similar, but not necessarily identical, elements. The drawings are not necessarily drawn to scale, and the dimensions of some parts may be exaggerated to more clearly illustrate the examples shown. In addition, the drawings provide examples and / or implementations consistent with the description; however, the description is not limited to the examples and / or implementations provided in the drawings. DETAILED DESCRIPTION

[0010] Calculation can be unloaded from the computer node to the processor of the memory server as a part of the network attached memory through the network. This calculation unloading may be associated with various problems. In some methods, specific hardware can be added to the memory server and / or the computer node to enable calculation to be unloaded to the memory server. However, adding such specific hardware will increase the cost and complexity of the memory server or the computer node. In other methods, the application is reconfigured to add a code for managing the calculation to be unloaded to the memory server. Reconfiguring the application will increase the complexity of the application, which will increase the development time and cost associated with the application. In addition, if there are a variety of different types of applications (possibly from different suppliers) that can be executed in the computer node, each of the different types of applications must be reconfigured to support the calculation to be unloaded to the memory server of the network attached memory, which means that program developers will have to spend time and resources to reconfigure a variety of different types of applications. In addition, in a large system with a cluster of computer nodes interconnected to the network attached memory, unloading calculation to the memory server may be associated with a relatively large number of messages between the computer node and the memory server, which will consume processing and network resources.

[0011] According to some embodiments of the present disclosure, in order to solve one or more of the above problems, a computer node can access an offload-related function to offload the calculation from the computer node to the storage server of the network attached storage. Using the offload-related function accessible by the computer node, a solution based on machine-readable instructions (e.g., software) is provided for offloading the calculation from the computer node to the storage server of the network attached storage, which is more cost-effective and less complex than using specific hardware to implement the calculation offload. In addition, the offload-related function can be accessed by an application in the computer node. It is not necessary to modify the application to add specific code to manage the offloading of the calculation; the application can simply issue a request that can cause the execution of the offload-related function. Further, by supporting the queuing of the calculation in a queue associated with the storage server of the network attached storage, the information of the calculation can be collected, and then the information is sent from the queue to the storage server as part of a write operation, which reduces the number of messages transmitted to the storage server over the network in order to offload the calculation to the storage server. When offloading the calculation to the storage server of the network attached storage, reducing the number of messages allows more efficient use of network resources.

[0012] Network attached storage refers to storage that is accessible to one or more computer nodes over a network. The computer nodes issue requests to access data in the network attached storage over the network. The network attached storage can be implemented using memory devices such as persistent memory devices and / or volatile memory devices.

[0013] An example of a network attached memory is a networked memory (FAM). A FAM may include a collection of memory servers. Each memory server may include a persistent memory or may be coupled to a persistent memory. In a further example, each memory server may include a volatile memory or a combination of a persistent memory and a volatile memory. The memory server manages access to data in the persistent memory in response to a request from a computer node.

[0014] In some examples, a computer node can use remote direct memory access (RDMA) to remotely access the persistent memory of a memory server in a FAM through a network. In other examples, a FAM may include a volatile memory or a combination of a persistent memory and a volatile memory. The RDMA data transmission between a computer node and a memory server includes data transmission between a computer node and a persistent memory of a memory server through a network. In some examples, one-sided RDMA is used to access the data of a FAM. For one-sided RDMA, a FAM exposes its persistent memory for access by a computer node based on a request made by a computer node. In contrast, two-sided RDMA relates to tasks performed by processors in a computer node and a memory server.

[0015] The one-sided RDMA data transfer is handled by the network interface of the memory server. In a one-sided RDMA data transfer, data read from or written to the persistent memory of the memory server can bypass the processor of the memory server. Therefore, the one-sided RDMA data transfer does not involve any work performed by the processor of the memory server. Because the processor of the memory server does not participate in the one-sided RDMA data transfer, the processor can be used for other operations when the memory server processes the RDMA data transfer.

[0016] The computer node can perform calculations on the data of the FAM. Usually, the calculation is performed by the processor of the computer node. However, if the processor of the memory server of the FAM has available processing capacity, it may be desirable to offload the calculation from the computer node to the memory server of the FAM. Offloading the calculation from the computer node to the memory server of the FAM can have the following benefits: offloading reduces the possibility of processor overload of the computer node, offloading utilizes the available capacity that was originally not utilized in the FAM, and performing memory-side calculations at the FAM can reduce network traffic in some cases.

[0017] Unloading calculation from remote computer nodes to the available processors of the memory server may be associated with various problems as described above. According to some embodiments of the present disclosure, in order to solve such one or more problems, the computer node can access the function for unloading calculation from the computer node to the memory server of the FAM. Such function is referred to as "unloading related function". "Function" can refer to a routine or method or any other machine-readable instruction set for performing a specific task.

[0018] The offload-related functions may be accessed by a computer node using an explicit request issued by the computer node (e.g., such as a call to an application programming interface (API) or a library). Alternatively, the offload-related functions may be accessed by a computer node based on an activity in the computer node that may trigger the execution of the offload-related functions. In some examples, the offload-related functions may include: a buffer descriptor setting function that associates information specifying the type of operation to be performed on data using multiple buffers in the computer node with the multiple buffers; a queuing function that is used to queue the operation in the multiple buffers; an operation initiation function that is used to initiate the execution of the operation at a memory server associated with the buffer; and a result providing function that provides the result of the operation from the memory server to the computer node. In further examples, there may be additional or alternative offload-related functions that may be accessed by a computer node.

[0019] The techniques or mechanisms according to some embodiments of the present disclosure can improve computer functionality in a computing system including computer nodes and a memory server of a FAM by using offload-related functions to offload computations from computer nodes to reduce the possibility of computer node overload, utilizing available processing capacity of the memory server of the FAM, and performing memory-side computations at the FAM to reduce network traffic in some cases.

[0020] In some examples, one-sided communication is used between the computer node and the memory server. The one-sided communication between the computer node and the memory server includes the memory server exposing an interface to the computer node, and the computer node issuing a request to access the memory server. The memory server does not initiate a request to the computer node. By using one-sided communication, compared to two-sided communication in which both the computer node and the memory server can initiate requests about each other, the consumption of processing resources of the memory server is reduced.

[0021] The results produced by the computations offloaded to the memory server are stored in the persistent memory of the FAM. Therefore, even if the memory server crashes, the results are stored persistently to allow recovery from the memory server crash.

[0022] Figure 1 1 is a block diagram of an example system 100 including a plurality of computer nodes 102-1 to 102-N (N≥2). Computer nodes 102-1 to 102-N are part of a computer node cluster. Computer nodes 102-1 to 102-N are interconnected to FAM 106 via network 104. FAM 106 includes a plurality of memory servers 108-1 to 108-M (M≥2). It should be noted that M may be the same as or different from N. More generally, N≥1 and M≥1, which means that system 100 may include one or more computer nodes and / or one or more memory servers.

[0023] Examples of network 104 may include an interconnect (e.g., a high throughput, low latency interconnect) between processors and memory, which may be based on open source standards, protocols defined by standards bodies, or proprietary implementations. A "computer node" may refer to a computer, a portion of a computer, or a collection of multiple computers.

[0024] Each memory server includes a corresponding processor and persistent memory. For example, memory server 108-1 includes processor 110-1 and persistent memory 112-1, and memory server 108-M includes processor 110-M and persistent memory 112-M. Although referred to in the singular sense, it should be noted that each memory server may include one or more processors. Furthermore, in a different example, the persistent memory may be external to the memory server; in this example, the memory server is connected to the persistent memory and is able to access the persistent memory.

[0025] The persistent memory may be implemented with one or more persistent memory devices, such as flash memory devices, disk-based storage devices, or other types of memory devices capable of retaining data when power is removed. The processor of the memory server may refer to a central processing unit (CPU) that executes the operating system (OS) and other machine-readable instructions of the memory server, including firmware such as a basic input / output system (BIOS) and application programs. Alternatively or additionally, the processor of the memory server may refer to another type of processor, such as a graphics processing unit (GPU) that handles specific calculations in the memory server.

[0026] In other examples, the memory server includes volatile memory, i.e., memory that loses data if power is removed from the memory. Volatile memory can be implemented with one or more volatile memory devices, such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, or other types of memory devices that retain data when power is on but lose data when power is removed. Alternatively, the memory server includes both volatile memory and persistent memory.

[0027] Each storage server further includes a network interface controller (NIC) to allow the storage server to communicate over the network 104. The NIC may include a transceiver that transmits and receives signals. Further, the NIC may include one or more protocol layers that perform communications over the network 104 according to corresponding one or more network protocols. The storage server 108-1 includes the NIC 114-1, and the storage server 108-M includes the NIC 114-M.

[0028] Each computer node also includes a processor and a local memory. For example, computer node 102-1 includes processor 115-1 and local memory 116-1, and computer node 102-N includes processor 115-N and local memory 116-N. Although referred to in the singular sense, it should be noted that each computer node may include one or more processors. Local memory may be implemented using one or more memory devices, which may be any one or some combination of the following: a DRAM device, an SRAM device, a flash memory device, or another type of memory device.

[0029] Each computer node also includes a NIC to communicate over network 104. Computer node 102-1 includes NIC 117-1, and computer node 102-N includes NIC 117-N.

[0030] The processor of a computer node is capable of executing one or more processing elements (PEs). A PE can be a thread or process associated with a program being executed in the computer node. The program can be an application or another type of program, such as an OS, firmware, or another type of machine-readable instruction. Figure 1 As shown, processor 115 - 1 executes PE 118 - 1 , and processor 115 -N executes PE 118 -N.

[0031] Each PE is able to access data of FAM 106. The access may include a read access for reading data from FAM 106 or a write access for writing data to FAM 106. Additionally, the PE may perform computations on data read from FAM 106 or data to be written to FAM 106. According to some embodiments of the present disclosure, a PE executing in a computer node may employ a FAM programming interface to offload operations including computations to one or more memory servers of FAM 106. If not offloaded, the computation of the operation will be performed by the processor of the computer node.

[0032] exist Figure 1 In the example of , computer node 102-1 includes FAM programming interface 120-1, and computer node 102-N includes FAM programming interface 120-N. The FAM programming interface may include an API, library, or any other program accessible subsystem accessible by a PE in a computer node to request that operations be offloaded to one or more memory servers of FAM 106.

[0033] In an example, the FAM programming interface may include an API that includes functions that can be used by a computer node (or more specifically, by a PE in a computer node) to manage the FAM and access data of the FAM. An example of such an API is the OpenFAM API.

[0034] Each computer node further includes a FAM client, which is a program that executes in the computer node to manage access to FAM 106 (eg, in response to PE calls to the FAM programming interface). Computer node 102-1 includes FAM client 130-1, and computer node 102-N includes FAM client 130-N.

[0035] According to some embodiments of the present disclosure, the FAM programming interface includes offload-related functions that can be called by the PE to offload operations to the memory server of the FAM 106 and obtain the results of the operations performed by the memory server of the FAM 106. Figure 1 In the example of , the offload-related functions of the FAM programming interface 120-1 include a queuing function 122-1, a sending function 124-1, and a result retrieval function 126-1. The FAM programming interface 120-N similarly includes a queuing function 122-N, a sending function 124-N, and a result retrieval function 126-N. Figure 1 Specific examples of offload-related functionality in a FAM programming interface are depicted in FIG. 1 , but in other examples, additional or alternative offload-related functionality may be included in the FAM programming interface.

[0036] Further, according to some embodiments of the present disclosure, the FAM client can also perform various offload-related functions discussed further below. The FAM client 130-1 can perform an offload-related function 132-1, and the FAM client 130-N can perform an offload-related function 132-N.

[0037] The programming interface and the offload-related functions of the FAM client together constitute a set of offload-related functions of the memory server of the FAM 106 that can be accessed by the PEs in the computer nodes for performing offload operations to the FAM 106.

[0038] The following describes the uninstall-related functions of the FAM programming interface 120-1 in more detail. The discussion also applies to the uninstall-related functions of the FAM programming interface 120-N.

[0039] PE 118-1 can issue multiple requests to apply calculations to the data of FAM 106. The calculation is part of an operation, such as an indexed vector addition operation that adds the data values ​​of the vector based on the index of the data value, a matrix multiplication operation that multiplies matrices, a scatter operation that scatters the data values ​​to the target at the corresponding index, a collection operation that collects data values ​​from the source at the corresponding index, a scatter-gather operation that performs both scattering and gathering, or another operation that calculates data. Instead of sending such calculations to FAM 106 individually through network 104 when it is enabled (which may involve a large number of messages through network 104), these calculations can be aggregated by first queuing the calculations in a buffer in computer node 102-1. The queued calculations can be sent to one or more memory servers of FAM 106 later.

[0040] Furthermore, operations may involve data associated with multiple memory servers. Thus, using multiple buffers in a computer node for corresponding memory servers allows computations for each memory server to be collected in the corresponding buffer (e.g., computations to be offloaded to a first memory server are queued in a first buffer, computations to be offloaded to a second memory server are queued in a second buffer, and computations to be offloaded to other memory servers are queued in other buffers).

[0041] The queuing function 122-1, when called by the PE 118-1, queues the computation into the buffers 128-1 to 128-M in the local memory 116-1. More specifically, queuing the computation into the buffers refers to queuing an operation element that includes information that allows the computation to be applied. For example, an operation element may include a memory address (also called an "offset") and a data value. The requested computation of the operation is applied to the data value at the memory address.

[0042] Each buffer corresponds to a respective memory server of FAM 106. For example, buffer 128-1 corresponds to memory server 108-1, and buffer 128-M corresponds to memory server 108-M. A buffer "corresponds" to a memory server if the buffer is used to queue information for computation to be offloaded to the memory server. Similarly, queuing function 122-N in computer node 102-N, when called by PE 118-N, queues computations to buffers 129-1 through 129-M in local memory 116-N.

[0043] although Figure 1 A one-to-one correspondence between buffers and memory servers of FAM 106 is shown, but in other examples, one buffer may correspond to multiple memory servers, or alternatively, multiple buffers may correspond to one memory server.

[0044] A call to the queuing function 122-1 of the FAM programming interface 120-1 allows an entity (eg, PE 118-1) to explicitly enable queuing of computations into a buffer. Alternatively, queuing of computations may be implicitly requested based on activity patterns in the computer node 102-1 or performance hints in the computer node 102-1.

[0045] The activity pattern may include a collection of requests submitted by an entity (e.g., PE 118-1) that are related to the same operation (e.g., indexed vector addition or another operation involving computation on data). When the FAM client 130-1 detects that the number of requests in the request set exceeds a specified number threshold, or the amount of data to be processed for the request set exceeds a specified size threshold, the FAM client 130-1 may automatically trigger queuing of computations for the request set for offloading to a memory server of the FAM 106 without making any explicit calls to the queuing function 122-1 in the FAM programming interface 120-1. More generally, in response to determining that the activity pattern indicates that a relatively large amount of computation would benefit from being offloaded to a memory server of the FAM 106, the FAM client 130-1 may trigger queuing of computations for offloading to a memory server without making explicit calls to the FAM programming interface 120-1.

[0046] The performance hint may include information in the computer node 102-1 that sets the performance target to be achieved when performing an operation in the computer node 102-1. The performance hint may be in the form of a target time to complete the operation, a target rate at which the processor executes instructions when performing the operation, or another parameter indicating the performance target. If the FAM client 130-1 determines that the performance target cannot be achieved at the computer node 102-1, the FAM client 130-1 may automatically trigger the calculation of the request set for unloading to the memory server of the FAM 106 to be queued, without any explicit call to the queuing function 122-1 in the FAM programming interface 120-1. More generally, in response to determining that the performance standard indicated by the performance hint may not be met if the operation is performed at the computer node 102-1, the FAM client 130-1 may trigger the calculation for unloading to the memory server to be queued, without explicit call to the FAM programming interface 120-1.

[0047] The send function 124-1, when invoked by the PE 118-1, causes computations queued in one or more buffers in the local memory 116-1 to be sent over the network 104 to the corresponding memory server(s) of the FAM 106. For example, the PE 118-1 may enable the send function 124-1 to send computations queued in all or a subset of the buffers 128-1 through 128-M to the corresponding memory servers 108-1 through 108-M.

[0048] Computations sent by a computer node to a memory server may be queued into a FAM queue at the memory server. Memory server 108-1 includes a FAM queue 134-1 into which offloaded computations from either of buffers 128-1 and 129-1 are queued, and memory server 108-M includes a FAM queue 134-M into which offloaded computations from either of buffers 128-M and 129-M are queued. It should be noted that in some examples, a FAM queue may include multiple buffers, one buffer for storing data and another buffer for storing control information related to operations to be applied to the data.

[0049] The call to the send function 122-2 of the FAM programming interface 120-1 allows an entity (e.g., PE 118-1) to explicitly enable the sending of queued computations to one or more memory servers. Alternatively, a request to send queued computations to a memory server may be implicitly made based on the state of the buffer or based on the state of the memory server. For example, the state of the buffer may be a buffer full state of the buffer, where the buffer full state refers to how full the buffer is. If the FAM client 130-1 detects that the buffer exceeds a specified fullness threshold (e.g., more than 75% fullness, more than 90% fullness, 100% fullness, or another threshold), the FAM client 130-1 automatically triggers the sending of queued computations from the buffer to the memory server.

[0050] The state of the memory server may refer to the available processing capacity of the processor of the memory server. The memory server may provide an indication of the use of the processor of the memory server to the FAM client 130-1. The indication of use may be expressed as a percentage used (e.g., 10% used, 40% used, 90% used, or another percentage used value). If the processor of the memory server is lightly used, this indicates that the processor has a large available capacity.

[0051] The result retrieval function 126-1 retrieves the result of the operation from one or more memory servers of the FAM 106 to which the computation has been offloaded when called by the PE 118-1. For example, the memory server may provide a completion indication that the operation is completed. The PE 118-1 may call the result retrieval function 126-1 to determine the status of the operation at the memory server, and if the operation is completed as indicated by the completion indication, the result retrieval function 126-1 retrieves the result of the operation from the memory server. In some examples, the result retrieval function 126-1 is a function for accessing a wait object (waitObj). The wait object causes a first thread (e.g., PE 118-1) to suspend execution, waiting for the operation to be completed by a second thread (e.g., a thread in the memory server to which the operation has been offloaded). The wait object may include a status indicator for indicating whether the operation has been completed. In other examples, other types of status indicators may be used to allow the memory server to indicate that the offloaded operation has been completed.

[0052] Figure 2 An example of queuing computations into buffers 228-1, 228-2, 228-3, and 228-4 in computer node 202 is shown. Buffers 228-1, 228-2, 228-3, and 228-4 are Figure 1 An example of any one of the buffers 128-1 to 128-M or 129-1 to 129-M, and the computer node 202 is Figure 1 1 to 102-N. The computations queued in buffers 228-1 to 228-4 are then sent to the corresponding memory servers 208-1, 208-2, 208-3, and 208-4. More specifically, the computations queued in buffer 228-1 are sent to memory server 208-1, the computations queued in buffer 228-2 are sent to memory server 208-2, the computations queued in buffer 228-3 are sent to memory server 208-3, and the computations queued in buffer 228-4 are sent to memory server 208-4. Memory servers 208-1 to 208-4 are Figure 1 Buffers 228-1 to 228-4 are included in the local memory of computer node 202 (e.g., Figure 1 In any one of the local memories 116-1 to 116-N in.

[0053] exist Figure 2 In the example of FIG. 1 , PE 218 in computer node 202 issues requests (including request 1, request 2, request 3, request 4, request 5, and request 6) to perform computations as part of an operation. Figure 2 In the example of , the operations requested by requests 1-6 may be indexed vector additions or any other type of operation, such as matrix multiplication, a scatter operation, a gather operation, a scatter-gather operation, a sort operation, a merge operation, or another operation that performs computation on data. PE 218 is Figure 1 An example of either of PE 118-1, 118-N.

[0054] Each request issued by PE 218 includes a plurality of offset-value pairs. The offset represents a memory address used at computer node 202, and the value associated with the offset represents a data value subject to the requested operation.

[0055] Each offset value pair of the request is referred to as an operation element to which the requested operation is applied. Different offsets can be mapped to different memory servers. For example, the computer node 202 can store mapping information that maps offsets to memory servers. Based on the offsets of the operation elements, the operation elements in requests 1-6 are added to different buffers 228-1 to 228-4. For example, the operation element (10, 4) of request 1 is added to buffer 128-1, the operation element (5000, 12) of request 2 is added to buffer 120-2, the operation element (9088, 10) of request 4 is added to buffer 128-3, and the operation element (14967, 2) of request 6 is added to buffer 128-4.

[0056] Once the operation elements of requests 1-6 have been accumulated in buffers 228-1 to 228-4, computer node 202 may send the operation elements in buffers 228-1 to 228-4 to the corresponding memory servers 208-1 to 208-4. More specifically, the operation elements in buffer 228-1 are sent to memory server 208-1, where they are queued in FAM queue 234-1 at memory server 208-1. Similarly, the operation elements in buffer 228-2 are sent to memory server 208-2 and queued in FAM queue 234-2, the operation elements in buffer 228-3 are sent to memory server 208-3 and queued in FAM queue 234-3, and the operation elements in buffer 228-4 are sent to memory server 208-4 and queued in FAM queue 234-4. FAM queues 234-1 to 234-4 are Figure 1 Example of FAM queues 134-1 to 134-M in FIG.

[0057] The numbers included in each of the FAM queues 234-1 through 234-4 represent memory addresses of the memory address space used by the memory servers 208-1 through 208-4. In some examples, the memory address space in the computer node 202 (e.g., including Figure 2 The offset shown in () may be different from the memory address space used at the memory server. The conversion between the offset of the memory address space of the computer node 202 and the memory address of the memory address space of the memory server may be performed at the computer node 202, such as by the FAM client or a different entity.

[0058] Figure 3 is used according to some examples to calculate (for example, Figure 2 Flow chart of the process of queuing the requested operation elements) in the buffers 328-1 to 328-M in the computer node 302. Figure 3 The process is executed in the computer node 302. Buffers 328-1 to 328-M are Figure 1 An example of any one of the buffers 128-1 to 128-M or 129-1 to 129-M, and the computer node 302 is Figure 1 An example of any one of the computer nodes 102-1 to 102-N.

[0059] PE 318 in computer node 302 issues (at 303) a queue request, such as by calling a queue function (e.g., Figure 1 PE 318 is any one of the queuing functions 122-1 to 122-N. Figure 1An example of any one of PEs 118-1 to 118-N. Figure 3 In the example of FIG. 3 , it is assumed that queuing the computation in buffers 328 - 1 to 328 -M is explicitly requested. In other examples, as described above, queuing the computation in buffers 328 - 1 to 328 -M can be implicitly triggered by FAM client 330 in computer node 302. FAM client 330 is Figure 1 An example of any one of the FAM clients 130-1 to 130-N.

[0060] FAM client 330 receives an indication of the queue request issued by PE 318. In response, FAM client 330 executes a task in block 304. The task of block 304 is executed once in response to the queue request.

[0061] The tasks in block 304 include a buffer acquisition task 306, in which the FAM client 330 acquires a set of buffers for a memory server as part of a given memory address space. In some examples, the computer node 302 may use multiple memory address spaces, for example, the multiple memory address spaces may be used for different use cases. Each memory address space may include a different set of memory servers. Depending on which memory address space is used, a different set of buffers may be acquired by the FAM client 330. The set of buffers is acquired from a pre-allocated pool of buffers that includes the buffers for the FAM (e.g., Figure 1 Buffers for all memory servers in the FAM 106).

[0062] In some examples, the queuing function called by PE 318 may have the following syntax:

[0063] FAM_Queue_Function(FAM_Queue_OP,FAM_Descriptor,Elements_Set).

[0064] Although three arguments (FAM_Queue_OP, FAM_Descriptor, Elements) are depicted above, it is noted that in other examples, the queuing function 122-1 may include additional or alternative arguments. FAM_Queue_OP represents the type of operation to be performed, such as indexed vector addition, matrix multiplication, or another type of operation. FAM_Descriptor represents a given memory address space in which an operation of a specified type (FAM_Queue_OP) is to be applied. Elements_Set represents the elements of the operation to be queued (from one or more requests, such as Figure 2 Requests 1-6 in .

[0065] The tasks in block 304 further include an operation code (operation code / opcode) saving task 308, wherein the FAM client 330 saves the information of the operation code (indicating the type of operation indicated by FAM_Queue_OP) together with the memory addresses of the buffers 328-1 to 328-M into the buffer descriptor. The memory addresses of the buffers 328-1 to 328-M are the addresses in the local memory where the buffers 328-1 to 328-M are located. The buffer descriptor is a local memory stored in a memory (e.g., Figure 1 The buffer descriptor is a data structure in the local memory 116-1 or 116-N of the memory server that can be accessed later (e.g., by the FAM client 330 in response to a request to send the queued computation to the memory server) to determine where the buffer 328-1 to 328-M is located in the local memory and what type of operation is to be applied. The buffer descriptor is part of the metadata associated with the buffer 328-1 to 328-M.

[0066] Box 310 includes tasks to be performed for each operation element (in Elements_Set) to be queued. The tasks in box 310 include a memory server identification task 312, in which the FAM client 330 identifies a memory server for the offset of the current operation element (in Elements_Set) to be queued. As described above, different offsets can be mapped to different memory servers. The "current" operation element is the operation element currently being processed by the FAM client 330 for queuing. The FAM client 330 traverses the tasks of box 310 for all operation elements of the Elements_Set.

[0067] The tasks in box 310 further include a buffer lookup task 314, in which the FAM client 330 identifies a buffer for the identified memory server. The FAM client 330 may maintain mapping information associating the buffers with the corresponding memory servers. The tasks in box 310 further include a buffer append task 316, in which the FAM client 330 appends the current operation element including the (offset, value) pair to, for example, the identified buffer.

[0068] Once all operating elements of the Elements_Set have been queued to buffers 328-1 to 328-M, FAM client 330 returns (at 317) the status of the queue request to PE 318. The status can be accessed through the FAM programming interface (e.g., Figure 1 120-1) in the communication.

[0069] Other computer nodes may perform similar processes for queuing computations in the other computer nodes.

[0070] Figure 4 is a flow chart of a process for sending queued computations from a buffer 428 in a computer node 402 to a memory server 408 to perform offloaded memory-side operations. The buffer 428 is Figure 1 An example of any one of the buffers 128-1 to 128-M or 129-1 to 129-M, and the memory server 408 is Figure 1 An example of any one of the storage servers 108-1 to 108-M. The computer node 402 is Figure 1 An example of any one of the computer nodes 102-1 to 102-N.

[0071] PE 418 in computer node 402 issues (at 403) a send request, such as by calling a send function (e.g., Figure 1 Any one of the sending functions 124-1 to 124-N in the example. Figure 4 In the example of FIG. 4 , it is assumed that sending the computation queued in buffer 428 is explicitly requested. In other examples, as described above, sending the computation queued in buffer 428 can be implicitly triggered by FAM client 430 in computer node 402. FAM client 430 is Figure 1 An example of any one of the FAM clients 130-1 to 130-N.

[0072] FAM client 430 receives an indication of the send request issued by PE 318. In response, FAM client 430 retrieves (at 404) a buffer descriptor associated with buffer 428. It should be noted that the buffer descriptor includes an opcode indicating the type of operation to be performed and the memory address of the buffer.

[0073] If buffer 428 is not empty, FAM client 430 writes (at 406) the operation elements in buffer 428 to memory server 408. Memory server 408 is an example of any one of memory servers 108-1 to 108-M. If the send request is a request to send the operation elements of multiple buffers to the corresponding memory server, FAM client 430 writes the operation elements in each of the other non-empty buffers to the corresponding memory server.

[0074] Once the FAM client 430 detects (at 407) that writing of the operation elements in the buffer 428 to the memory server 408 is complete, the FAM client 430 returns (at 410) the wait object waitObj to the PE 418.

[0075] The wait object waitObj may include a status indicator for indicating whether the operation has been completed. The wait object waitObj may further include other information, such as information of the request that triggered the operation (e.g., an identifier of the request) or further information. The wait object waitObj is used by PE 418 to obtain the status of the unloaded memory side operation. If the unloaded memory side operation is completed, PE 418 may obtain the result of the memory side operation. The result may include a sum generated by an indexed vector addition, a product generated by a matrix multiplication, or another result of the calculation.

[0076] The operation element from the buffer 428 is added to the FAM queue 434 in the memory server 408 along with information indicating the operation to be applied (as indicated by the operation code in the buffer descriptor). The FAM queue 434 is Figure 1 The combination of information indicating an operation and an operation element constitutes a calculation request queued in the FAM queue 434.

[0077] When a compute request is queued to the FAM queue 434, a processor in the memory server 408 (or more specifically, a memory server thread executing on a processor of the memory server 408) retrieves (at 414) the next compute request from the FAM queue 434 and performs (at 416) the computation indicated by the retrieved compute request. The memory server thread iterates through each compute request in the FAM queue 434 to perform the offloaded memory-side operations.

[0078] PE 418 may periodically or intermittently check (at 412) waitObj, such as by calling a result retrieval function (e.g., Figure 1 408) to determine the status of waitObj in order to obtain the result of the offloaded memory side operation. The call to the result retrieval function by PE 418 causes FAM client 430 to check (at 417) the status of the memory side operation executed at memory server 408.

[0079] When the memory server thread has completed the computation of all computation requests in the FAM queue 434, the memory server 408 adds (at 420) the result of the offloaded memory-side operation (e.g., a sum, a product, or another computation result) to the completion queue. For example, the completion queue may be part of the persistent memory 112-1 of the memory server 108-1. If the memory server 408 has not yet completed the memory-side operation, the PE 418 obtains (at 420) a status indication indicating an uncompleted state or an ongoing state of the memory-side operation from the memory server 408. However, if the memory-side operation is complete and the completion queue contains the result of the memory-side operation, the PE 418 obtains (at 420) a status indication indicating the completion of the memory-side operation from the memory server 408. If the status indication indicates that the memory-side operation is complete, the PE 418 calls a result retrieval function to obtain the result from the completion queue of the memory server 408.

[0080] As described above, PE 418 periodically or intermittently checks the wait object waitObj by calling the result retrieval function. If PE 418 determines that the memory side operation has not completed based on the first call of the result retrieval function, PE 418 can make one or more other calls to the result retrieval function later to determine whether the memory side operation is completed.

[0081] In an alternative example, instead of PE 418 repeatedly polling the memory server for the status of the offloaded memory-side operation, the memory server may push a completion indication to PE 418 when the memory-side operation is complete, at which time PE 418 may retrieve the results of the memory-side operation.

[0082] Figure 5 is a block diagram of a system 500 according to some examples. The system 500 includes a computer node 502. In other examples, the system 500 may include more than one computer node.

[0083] The system 500 further includes a plurality of memory servers 504 that manage access to data in memory 506 (eg, persistent memory and / or volatile memory). The memory 506 may include memory devices accessible by corresponding memory servers 504.

[0084] The system 500 further includes a plurality of buffers 508 in the computer node 502. The plurality of buffers 508 are associated with the memory server 504.

[0085] System 500 includes a processor 510 configured to execute a plurality of functions 512 accessible by a computer node 502 to access data of a storage server 504. Processor 510 may be part of computer node 502. For example, the plurality of functions 512 may include functions of a programming interface and functions of a FAM client.

[0086] The plurality of functions 512 include an operation type association function 514 that associates information 516 specifying the type of operation to be performed on data using the plurality of buffers 508 with the plurality of buffers 508. Associating the information specifying the type of operation with the buffer may refer to including or adding the information in a descriptor or other data structure. In some examples, the information 516 may include a buffer descriptor. The operation type association function 514 may be part of a FAM client and may perform, for example, Figure 3 The operation code of task 308 is saved.

[0087] The plurality of functions 512 include a queuing function 518 for queuing an operation in the plurality of buffers 508. Queuing an operation in a buffer may refer to adding information that allows the operation to be performed in the buffer. The queuing function 518 may be, for example, Figure 1 The queuing function 122-1 or 122-N in the FAM programming interface 120-1 or 120-N.

[0088] The plurality of functions 512 include an operation initiation function 520 that initiates execution of an operation at a memory server 504 associated with the plurality of buffers 508 based on a type specified by the information 516. Initiating execution of an operation at a memory server may refer to sending information that causes the operation to be initiated to the memory server. In some examples, initiating execution of an operation at the memory server 504 includes writing an operation element of the operation queued in the plurality of buffers to the memory server, and includes providing the information 516 of the type of operation to the memory server 504.

[0089] The plurality of functions 512 include a result providing function 522 that provides the result of the operation from the storage server 504 to the computer node 502. Providing the result of the operation to the computer node may refer to sending the result to the computer node or retrieving the result by the computer node. The result providing function 522 may be, for example, Figure 1 The result retrieval function 126-1 or 126-N of the FAM programming interface 120-1 or 120-N.

[0090] Figure 6 Depicted is a process for offloading operations to a FAM's storage server. Figure 6The process of FIG. 6 includes storing data (at 602) in a memory by a computer node, the memory being coupled to a memory server that manages access to the data in the memory. The memory server may be, for example, Figure 1 Part of FAM 106 ET FAM.

[0091] The process includes providing (at 604) by a computer node a plurality of buffers associated with a memory server in the computer node. Providing the buffers in the computer node may refer to allocating a portion of memory to include the buffers. The plurality of buffers may be included in a local memory of the computer node.

[0092] The process includes calling (at 606) an initialization function by a computer node, the initialization function requesting that operations be offloaded to a storage server. Calling an initialization function may refer to enabling the initialization function. In some examples, the initialization function may be, for example, Figure 1 For example, the initialization function may be called by accessing a programming interface.

[0093] The process includes queuing (at 608) operations in the plurality of buffers by the processor in response to a call to the initialization function by the computer node. Queuing operations in the buffers may refer to adding information that allows the operations to be performed in the buffers. For example, queuing operations in the plurality of buffers includes accumulating operation elements of the operations in the buffers.

[0094] The process includes sending (at 610) operations queued in the plurality of buffers by the processor to the memory server for execution at the memory server. Sending the operations to the memory server may refer to transmitting information of the operations so that the memory server may perform the operations. For example, sending may be performed by, for example, Figure 1 The sending function 124-1 or 124-N of the programming interface 120-1 or 120-N is executed.

[0095] The process includes providing, by the processor, the result of the operation from the storage server to the computer node (at 612). For example, when the wait object waitObj indicates a completion status of the operation, the result can be obtained by the computer node from the storage server.

[0096] Figure 7 is a block diagram of a non-transitory machine-readable or computer-readable storage medium 700 having stored thereon machine-readable instructions that, when executed, cause a computer node to perform various tasks.

[0097] The machine readable instructions include buffer providing instructions 702 for providing a plurality of buffers in a computer node. The plurality of buffers are connected to a network attached storage (e.g., Figure 1 The FAM 106) is associated with a storage server.

[0098] The machine readable instructions include function execution instructions 704 for executing a plurality of functions accessible by a processing element in a computer node to access data of a memory server.

[0099] The plurality of functions includes an operation type association function 706 that associates information specifying a type of operation to be performed on data using the plurality of buffers with the plurality of buffers. For example, the information may include a buffer descriptor.

[0100] The plurality of functions include a queuing function 708 that queues operations in the plurality of buffers and an operation initiating function 710 that initiates execution of operations at memory servers associated with the plurality of buffers based on a type specified by the information.

[0101] The plurality of functions includes a result providing function 712 that provides the result of the operation from the storage server to the computer node. The result providing function 712 may, for example, access a wait object.

[0102] Storage media (e.g. Figure 7 700 in ) may include any one or some combination of the following: a semiconductor memory device, such as DRAM or SRAM, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory; a magnetic disk, such as a fixed disk, a floppy disk, and a removable disk; another magnetic medium, including a tape; an optical medium, such as a compact disk (CD) or a digital video disk (DVD); or another type of storage device. Note that the instructions discussed above may be provided on one computer-readable or machine-readable storage medium, or alternatively, may be provided on multiple computer-readable or machine-readable storage media distributed in a large system with possibly multiple nodes. Such one or more computer-readable or machine-readable storage media are considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. One or more storage media may be located in a machine running machine-readable instructions, or at a remote site, from which machine-readable instructions may be downloaded over a network for execution.

[0103] In the present disclosure, unless the context clearly indicates otherwise, the use of the terms "a", "an" or "the" is intended to include the plural forms as well. Similarly, when used in the present disclosure, the terms "includes / including / comprises / comprising", "have / having" specify the presence of stated elements, but do not exclude the presence or addition of other elements.

[0104] In the foregoing description, many details are set forth to enable an understanding of the subject matter disclosed herein. However, embodiments may be practiced without some of these details. Other embodiments may include modifications and variations of the details discussed above. The appended claims are intended to cover such modifications and variations.

Claims

1. A system comprising: a plurality of storage servers that manage access to data in the storage; Computer nodes; a plurality of buffers in the computer node, wherein the plurality of buffers are associated with the memory server; and a processor configured to execute a plurality of functions accessible by the computer node to access data of the memory server, the plurality of functions comprising: associating with the plurality of buffers information specifying a type of operation to be performed on the data using the plurality of buffers, enqueueing the operations in the plurality of buffers, initiating execution of the operation at the memory server associated with the plurality of buffers based on the type specified by the information, and A result of the operation is provided from the memory server to the computer node.

2. The system of claim 1, wherein: The plurality of functions are accessible by the computer node using a programming interface.

3. The system of claim 2, wherein: The plurality of functions includes a queuing function that queues the operations in the plurality of buffers in response to calls to the programming interface by the computer node.

4. The system of claim 2, wherein: The plurality of functions includes a send function that sends queued operations from the plurality of buffers to the memory server in response to a call to the programming interface by the computer node.

5. The system of claim 1, wherein: The processor queues the operations in the plurality of buffers based on activity patterns in the computer node.

6. The system of claim 1, wherein: The processor queues the operations in the plurality of buffers based on performance hints in the computer node.

7. The system of claim 1, wherein: The processor sends an operation element of the operation from a buffer of the plurality of buffers to a memory server in response to a buffer full status of the buffer.

8. The system of claim 1, wherein: The processor sends an operation element of the operation from a buffer of the plurality of buffers to the memory server in response to detecting available processing capacity of the memory server.

9. The system of claim 1, wherein: The computer node is a first computer node, and the system further comprises: a second computer node, the second computer node comprising a plurality of buffers associated with the memory server, wherein a processor of the second computer node is configured to perform a plurality of second computer node functions, the plurality of second computer node functions comprising: queueing a second operation in the plurality of buffers in the second computer node, and Execution of the second operation is initiated at the memory server by sending the queued second operation to the memory server.

10. The system of claim 1, wherein: Initiating execution of the operation at the memory server includes writing operation elements of the operation queued in the plurality of buffers to the memory server.

11. The system of claim 10, wherein: Initiating performance of the operation at the memory server further includes providing information of a type of the operation to the memory server.

12. The system of claim 1, wherein: Associating information specifying the type of operation with the plurality of buffers includes adding the information and addresses of the plurality of buffers to a buffer descriptor.

13. The system of claim 12, wherein: Initiating execution of the operation at the memory server includes accessing the buffer descriptor and providing information of a type of the operation to the memory server.

14. A method comprising: storing, by a computer node, data in a memory coupled to a memory server that manages access to the data in the memory; providing, by the computer node, a plurality of buffers associated with the memory server in the computer node; calling, by the computer node, an initialization function, the initialization function requesting that operations be offloaded to the storage server; In response to the computer node calling the initialization function, queuing, by a processor, the operations in the plurality of buffers; sending, by the processor, the operations queued in the plurality of buffers to the memory server for execution at the memory server; as well as A result of the operation is provided by the processor from the memory server to the computer node.

15. The method of claim 14, wherein: The calling of the initialization function includes calling a programming interface including the initialization function.

16. The method of claim 15, wherein: Sending the operation to the storage server is performed in response to calling a send function of the programming interface.

17. The method of claim 16, wherein: Providing the result of the operation from the storage server to the computer node is performed in response to the computer node invoking a result retrieval function of the programming interface.

18. The method of claim 14, wherein: Sending the operation to the memory server includes sending operation elements of the operation from the plurality of buffers to the memory server, each of the operation elements including a memory address and a data value.

19. A non-transitory machine-readable storage medium comprising instructions that, when executed, cause a computer node to: A plurality of buffers are provided in the computer node, wherein: The plurality of buffers are associated with a storage server of a network attached storage; Executing a plurality of functions accessible by a processing element in the computer node to access data of the memory server, the plurality of functions comprising: associating with the plurality of buffers information specifying a type of operation to be performed on the data using the plurality of buffers, enqueueing the operations in the plurality of buffers, initiating execution of the operation at the memory server associated with the plurality of buffers based on the type specified by the information, and A result of the operation is provided from the memory server to the computer node.

20. The non-transitory machine-readable storage medium of claim 19, wherein: The plurality of functions include functions of a programming interface.

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