Instruction tagging for in-object memory tagging

Abstract

Instruction tagging techniques for in-object memory tagging are described. In an embodiment, an apparatus includes an instruction decoder to decode a first instruction having an instruction tag value; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the first instruction, including generating a first data tag value based on a relative enumeration in the instruction tag value and the pointer to the data.

Description

Background Art

[0001] Computers and other information processing systems can be vulnerable to various software vulnerabilities. Therefore, memory security and safety are important concerns in computer system architecture and design to defend against possible vulnerabilities in software. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Various examples according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0003] Figure 1A A computing system for instruction tagging is illustrated according to an embodiment.

[0004] Figure 1B The diagram illustrates granular memory locations with corresponding tags stored in a tag table according to an embodiment.

[0005] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E The diagram illustrates aspects of instruction tagging according to an embodiment.

[0006] Figure 3 The diagram illustrates a method for instruction tagging according to an embodiment.

[0007] Figure 4 An example computing system is illustrated.

[0008] Figure 5 The figure shows a block diagram of an example processor and / or System on a Chip (SoC) that may have one or more cores and an integrated memory controller.

[0009] Fig. 6A is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example.

[0010] Figure 6B is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example.

[0011] Figure 7 The figure shows an example of execution unit(s) circuitry.

[0012] Figure 8 is a block diagram illustrating converting binary instructions in a source instruction set architecture to binary instructions in a target instruction set architecture using a software instruction converter according to an example. DETAILED DESCRIPTION

[0013] The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for instruction tagging for in-object memory tagging. According to some examples, an apparatus includes: an instruction decoder for decoding a first instruction having an associated instruction tag value; and execution circuitry coupled to the instruction decoder, the execution circuitry for performing one or more operations corresponding to the first instruction, including: generating a first data tag comparison value based on the instruction tag value and a relative enumeration in a pointer to data, and comparing with a second tag value stored in a memory associated with an accessed portion of the data.

[0014] As mentioned in the Background section, memory security and safety are important concerns in computer system architecture and design.

[0015] Examples of computer memory security violations include overflowing a buffer to cause adjacent memory locations to be overwritten, reading past the end of a buffer, and creating a dangling pointer that does not resolve to a valid destination (e.g., a use-after-free vulnerability). Some methods of protecting memory from attacks include methods that include tagging data with metadata to encode information about ownership, memory size, location, type, version, etc. However, these methods (particularly for implementations with fine-grained tagging) may require additional storage and / or additional instructions, and may have a negative impact on performance. Embodiments according to the present specification may provide methods that use less storage (e.g., less metadata) and / or have less impact on performance, even for protecting data at a fine granularity.

[0016] For example, embodiments may use tagging of individual instructions in conjunction with memory tagging to isolate object instances and their individual member variables from each other. In embodiments, tagging of member variables (e.g., individual and each member variable of a data object) may be associated with an object instance and an instruction tagging enumeration. By using instruction tags to uniquely tag member variables to match memory tags, protection may be maintained despite software vulnerabilities such as allowing one member variable to flow into another member variable.

[0017] As described and / or illustrated by examples below and / or in the figures, embodiments may use instruction tagging and tagged addressing (pointer tagging) to protect individually tagged members of objects, structures, frames, etc. For example, object instances (e.g., each object instance) and object member variables (e.g., each object member variable) may be tagged with unique values ​​at the hardware level to provide distinction between objects and members within objects.

[0018] Descriptions of embodiments based on instruction tags, relative enumeration of pointers, cryptographic capability computing (C3), etc. are provided as examples. Embodiments may include and / or relate to other memory security techniques.

[0019] Figure 1A FIG. 1 shows an apparatus (eg, a computing system) 100 for instruction tagging according to an embodiment. The apparatus 100 may correspond to a computer system such as Figure 4 A computer system such as the multi-processor system 400 in FIG.

[0020] Figure 1A The device 100 is shown as including a processor 110 and a memory 150, each of which may represent any number of corresponding components (eg, multiple processors and / or processor cores, multiple dynamic random-access memories (DRAMs), etc.).

[0021] For example, processor 100 may represent all or part of one or more hardware components including one or more processors, processor cores, or execution cores integrated on a single substrate or packaged in a single package, each of which may include multiple execution threads and / or multiple execution cores in any combination. Each processor represented as processor 110 or in processor 100 may be any type of processor, including a general-purpose microprocessor (such as a processor such as a processor 110 or processor 110). Processor family or from The processor 110 may be a processor from another processor family of Intel Corporation or another company), a dedicated processor or a microcontroller, or any other device or component in an information processing system in which an embodiment may be implemented. The processor 110 may be architected and designed to operate according to any instruction set architecture (ISA) with or without microcode control. For convenience and / or example, some features (e.g., instructions, etc.) may be implemented by being compatible with a particular processor architecture (e.g., 64 and / or IA32), but the embodiments are not limited to these features, names, architectures, etc.

[0022] Processor 110 may be implemented using circuit systems, gates, logic, structures, hardware, etc., all or part of which may be included in discrete components and / or integrated into the circuit systems of a processing device or any other device in a computer or other information processing system. For example, Figure 1AThe processor 110 in the embodiment may correspond to and / or be implemented / included in any of the following: Figure 4 The processor 470, 480 or 415, Figure 5 One of the processors 500 or cores 502A to 502N in the Figure 6B Core 690 in, each of which is described below.

[0023] Memory 150 may represent one or more DRAMs and / or other memory components that provide system memory or other memory or storage in or for device 100. Memory 150 may include one or more memory objects 152. Any such memory object may represent an object, region, structure, segment, stack frame, etc. in memory in addition to associated program code or instructions, and in addition to data tagging in accordance with an embodiment, the use of instruction tagging may also be applied, which may be related and may be referred to as objects for convenience.

[0024] As shown, processor 110 includes instruction unit 120, execution unit 140, and secure memory access unit 130 (which may be included in execution unit 140). Processor 110 may include any number of each of these elements (e.g., multiple execution units) and / or Figure 1A Any other elements not shown.

[0025] As described below, instruction unit 120 may be used with Figure 6B The front end unit 630 corresponds to and / or is implemented / included in Figure 6B The front end unit 630 in the embodiment of the present invention may include any circuit system, gate, logic, structure, hardware, etc. (such as an instruction decoder) to obtain, receive, decode, interpret, schedule and / or process instructions to be executed by the processor 110, such as data movement, load, or store instructions (e.g., mov) 122, address calculation instructions (e.g., load effective address or lea) 124, etc. Figure 1A In , instructions that may be decoded or otherwise handled by instruction unit 120 are represented as blocks with dashed boundaries because the instructions themselves are not hardware, but instruction unit 120 may include hardware or logic capable of decoding or otherwise handling these instructions.

[0026] Any instruction format may be used in embodiments; for example, an instruction may include an opcode and one or more operands, where the opcode may be decoded into one or more microinstructions or micro-operations for execution by execution unit 140. Operands or other parameters may be associated with the instruction implicitly, directly, indirectly, or in any other manner.

[0027] The execution unit 140 can be connected with Figure 6B The execution engine 650 and / or Figure 6B and Figure 7 Any of the execution unit circuit systems 662 in the Figure 6B The execution engine 650 and / or Figure 6B and Figure 7 Any of the execution unit circuit systems 662 in the 662 (each as described below), and / or including any circuit systems, gates, logic, structures, hardware, etc. (such as arithmetic units, logic units, floating point units, shifters, load / store units, etc.) to process data and execute instructions (including Figure 1A Execution unit 140 may represent any one or more physically or logically distinct execution units.

[0028] The secure memory access unit 130 may represent and / or include any circuit system, gate, logic, structure, hardware, etc. (such as a cryptographic unit, an arithmetic unit, a logic unit, a load / store unit, etc.) to control, execute, participate in, etc. the encryption, decryption, decoding, encoding, etc. of the objects and their members described in this specification.

[0029] The secure memory access unit 130 may include a memory tagging unit 132 , which may represent and / or include any circuitry, gates, logic, structure, hardware, etc. to control, perform, participate in, etc., memory tagging.

[0030] For example, the memory tagging unit 132 can access tagging information from memory. Tags can be stored in an isolated memory or in a separate table, where there is a tag location corresponding to each particle (e.g., 8 bytes) of a memory location. The tag location can be associated with a physical or virtual / linear address location of an instruction or data particle stored in memory. When a data particle is accessed by code, the memory tagging unit looks up the instruction tag of the associated code particle and data particle location from memory, a cache hierarchy, or a tag cache (which can also cache previous tag lookups for the same address). The tag can alternatively be stored in an error correcting code (ECC) memory or calculated from an ECC code and included in a cache line as associated metadata for a cache line stored in a cache hierarchy. The memory tagging unit can combine the instruction tag value with the address / pointer tag value and compare the value with the accessed data tag value.

[0031] Despite Figure 1A10 as separate units, but in various embodiments, secure memory access unit 130 and / or memory tagging unit 132 may be partially or fully integrated or included in another unit of processor 110, such as instruction unit 120 and / or execution unit 140.

[0032] For example, embodiments may provide memory tagging of individual member variables, data elements, and the like (any of which may be referred to as members) of objects, stack frames, data structures, and the like (any of which may be referred to as objects) using a combination of instruction tagging and relative enumeration fields in pointers to provide tags for individual members. Embodiments may provide finer granularity of protection than typical memory tagging approaches, for example, reducing 16-byte particles to 8-byte particles to better match the size of individual members in a 64-bit processor architecture. Various embodiments may use larger particles (with additional padding or separation between variables, combining members under the same tag, etc.) or may use smaller particles.

[0033] In an embodiment, a granular memory location (eg, a location for each particle or granular size) may have a corresponding tag stored in a tag table, such as Figure 1B As shown. When the processor performs a load or store operation on a memory location, the processor will look up the tag value in the tag table corresponding to the memory location to verify the tag value. In addition to data, instructions are also stored in memory and therefore may have associated tags. The instruction tag value is used in conjunction with the linear / virtual memory address (pointer) tag to calculate the tag of the data particle, which is then compared to the associated tag value of the data particle stored in the tag table. Embodiments may alternatively store the tag value in a parallel memory such as an ECC memory, or calculate the tag value based on an ECC value associated with a cache line (e.g., the tag value is carried in the cache line as additional metadata) (e.g., as an additional Reed-Solomon codeword indicating the tag value of a cache line or portion thereof). The advantage of parallel memory access is that the tag value is provided while accessing the memory for code / data, rather than using an additional memory access to access a tag table from a separate location in the memory.

[0034] The embodiments may be described by way of example using the following C source code example and its corresponding x86 assembly code:

[0035] Embodiments may include and / or be implemented according to two concepts. The first concept is to flatten the data structure / object and enumerate the member variables, such as Figure 2AThe second concept is to provide a relative enumeration field in a pointer (e.g., linear / virtual address), such as Figure 2B as shown in the example.

[0036] refer to Figure 2A , where each tag corresponds to an 8-byte particle, for an instance of the SStrings structure, there will be: two tags with a value of 1 each to cover the first 16-byte character array; a single tag with a value of 2 to cover the first 64-bit integer; two tags with a value of 3 each to cover the second 16-byte character array; a single tag with a value of 4 to cover the second 64-bit integer.

[0037] refer to Figure 2B , the value in the relative enumeration field (e.g., a pointer tag value) represents the starting value of the enumeration in the instance of the object. It can be (as shown) a 4-bit tag to be consistent with existing memory tagging techniques, but other sizes are possible in various embodiments. Given the finite size of the tag field, the value may roll over (e.g., when enumerating a 4-bit value from 15, additional increments may return to a value of 0).

[0038] In an embodiment, in conjunction with a load or store operation, the processor adds a tag value associated with the executed instruction to the relative enumeration in the pointer (address), and then compares the resulting value to the memory tag associated with the data granule that the load or store operation attempts to access. For instructions that do not attempt to access, copy, move, etc. data (e.g., instructions other than load or store), the tag value may be ignored. In an embodiment, load / store instructions may be aligned with their corresponding tags (granules).

[0039] refer to Figure 2C , tags are applied to instructions that name SStrings structures so that there is a direct association between the instructions and the data members of the composite structure that they access. Since tags are associated with code segments, the compiler can create templates of associated memory tags corresponding to instructions, and the loader or other component can set the memory tags accordingly or provide templates to other software to initialize the memory tags of the code sections. Software tools can also be developed to tag existing code sections after refactoring (decompiling) the code. Tags can be applied to load / store instructions associated with individual memory data accesses. Since the tag values ​​between any two string members are different, an overflow from one member to another will cause a tag mismatch (when compared to the memory tag of the data), thereby preventing data leakage and memory corruption of the members.

[0040] Reference now Figure 2DThe pointer relative enumeration manipulation example shown, in order to allow manipulation across functions and specialized libraries that operate on more primitive data types, the pointer relative enumeration field allows the compiler or other tool to specify the relative offset of the label corresponding to the location of the associated LEA instruction. This results in the LEA operation providing the address (pointer) to the associated substructure with the correct relative enumeration. For example, LEA can add the label value to the input memory address related enumeration field of the input address (e.g., in the input register) to produce a correctly formatted / encoded / encrypted address with the updated enumeration of the output address (e.g., in the output register).

[0041] Then, refer to Figure 2E As shown in the example, an access function can use a relative enumeration pointer field with an instruction tag by adding the relative enumeration in the address to the enumeration specified in the instruction tag, which is designed for functions that only understand substructures of primitive data types of nested structures or objects. The string comparison function can understand the primitive data structure of the string buffer and the size variable of the string length, but not the specific data structure that may contain one or more of these string structures. The relative enumeration provides the relative position of the nested primitive structures within the larger structure, as well as the instance of the specific allocation structure that is incorporated. For example, the SStringCompare function understands the more primitive SString data type, not the composite SStrings data type. However, the source address and destination address passed into the function have the correct relative enumeration for each SString substructure nested in the SStrings data structure. The tag value added to the mov instruction is then used to correctly access the byte array members of the SString structure.

[0042] Figure 3 The diagram shows a method 300 for instruction tagging according to an embodiment. The method 300 may be performed by and / or in conjunction with the operation of an apparatus (such as the apparatus 100 in FIG. 1 ), and / or in conjunction with the compilation of code to be executed by an apparatus (such as the apparatus 100 in FIG. 1 ); therefore, all or any part of the foregoing description of the apparatus 100 may be applicable to the method 300.

[0043] At 310, a relative enumeration of pointers is added to a tag value of a tagged instruction used to execute a load / store instruction (e.g., to attempt a memory access) to generate a first (generated) tag value. At 320, a storage location of a second (stored) tag value associated with data for the load / store operation (corresponding to the load / store instruction) is identified.

[0044] The first (generated) tag value is compared to the second (stored) tag value at 330. If there is a match, then the memory access is allowed at 332. If there is a mismatch, then the memory access is blocked at 334 (e.g., by triggering an exception, fault, error, etc.).

[0045] In an embodiment, the initialization of memory by a memory allocator may differ from existing initialization in conventional memory tagging, as knowledge of the allocated object / structure type (internal structure) may be required to generate the correct corresponding memory tag value for the object / structure. When an allocation function (e.g., malloc or new) is called, a template for the memory tag may be used to set the memory tag of the corresponding object type (e.g., using a set tag instruction or similar instruction). Before setting the tags, the relative enumeration of the instance of the object is first added to these tags, so they correspond to the correct instance of the object and the relative enumeration of the various members of the object. When the size and type cast of the new memory allocation (e.g., ptr=(cast-type*)malloc(byte-size), i.e., ptr=(cast-type*)malloc(byte-size)) are known, the compiler may initialize the memory tags of the new instance of the object. Other embodiments may rely on a constructor to first access the memory and configure the tags. Alternatively, an "undefined" tag value may be used to trigger an exception on the first access, allowing the exception handler to select the correct tag template for the newly allocated object type.

[0046] In an embodiment, a data copy and / or move function (e.g., memcpy) can preserve the tag enumeration of an object (or group of objects) by also copying the tag value of the source to the tag value of the destination. The destination may have a different starting relative enumeration in the pointer field, so the memory tags can be adjusted by adding the relative enumeration difference between the source and the destination. In this way, memcpy does not need to know anything about the internal structure of the object when copying it, but can still create the correct tag value for the copy.

[0047] Similar to heap allocation, stack frames can also be tagged for individual variables on the call stack. The compiler can use templates to do this tagging so that when a function is called, the memory tags associated with the new stack frame are filled with the correct values ​​corresponding to the instructions of the called function. These stack frame "tag templates" can be copied from the template location to update the tag value corresponding to the current stack frame. Similarly, the stack pointer can be updated with the correct relative enumeration of the current stack frame instance to prevent the stack frame from being replayed using the same enumeration.

[0048] Global variables may also be individually tagged along with their access instructions to prevent overflow or underflow of global buffers or global variables accessed with the wrong data type (eg, overwriting a byte global variable location with a large floating point number by the processor).

[0049] In some embodiments, load / store and LEA instructions may instead use prefix values ​​to indicate tag values, rather than tagging individual instructions using the memory tags of the code segment. This approach may allow instructions to be misaligned and provide more compressed code than requiring instructions to be aligned to the memory granule size for tagging. However, this approach may sacrifice compatibility with existing code that may be provided by tagging instruction approaches and using compiler support to add prefix values ​​to compiled instructions.

[0050] Example Apparatus, Methods, etc.

[0051] According to some examples, an apparatus (e.g., a processing device) includes: an instruction decoder for decoding a first instruction having an instruction tag value; an execution circuit system coupled to the instruction decoder, the execution circuit system for performing one or more operations corresponding to the first instruction, including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to the data.

[0052] According to some examples, a method includes: decoding, by an instruction decoder of a processing device, a first instruction having an instruction tag value; and executing, by an execution circuit system coupled to the instruction decoder, one or more operations corresponding to the first instruction, including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to data.

[0053] Any such examples may include any of the following aspects or any combination thereof. The instruction decoder may also be used to decode a second instruction having a pointer tag value based on a relative enumeration in a pointer. The method may also include: decoding, by the instruction decoder, a second instruction having a pointer tag value based on a relative enumeration in a pointer. The data may correspond to a member of an object. The instruction tag value may be associated with a member. The pointer tag value may be associated with an object. The one or more operations may also include identifying a memory location of a second data tag value associated with the data. The one or more operations also include comparing the second data tag value with the first data tag value. The one or more operations also include blocking access to the data in response to detecting a mismatch between the second data tag value and the first data tag value. The first data tag value may be obtained from the sum of the instruction tag value and the relative enumeration.

[0054] According to some examples, the device may include means for performing any function disclosed herein; the device may include a data storage device that stores code that, when executed by a hardware processor or controller, causes the hardware processor or controller to perform any method or part of a method disclosed herein; the device, method, system, etc. may be as described in the detailed description; a non-transitory machine-readable medium may store instructions that, when executed by a machine, causes the machine to perform any method or part of a method disclosed herein. Embodiments may include any details, features, etc., or combinations of details, features, etc., described in this specification.

[0055] Example Computer Architecture

[0056] The description of the example computer architecture is described in detail below. Other system designs and configurations for laptops, desktop computers, handheld personal computers (PCs), personal digital assistants, engineering workstations, servers, separate servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices known in the art are also suitable. In general, various systems or electronic devices that can contain processors and / or other execution logic as disclosed herein are generally suitable.

[0057] Figure 4 The figure shows an example computing system. Multiprocessor system 400 is a system provided with an interface and includes multiple processors or cores, which include a first processor 470 and a second processor 480 coupled via an interface 450 such as a point-to-point (PP) interconnect, a fabric and / or a bus. In some examples, the first processor 470 and the second processor 480 are isomorphic. In some examples, the first processor 470 and the second processor 480 are heterogeneous. Although example system 400 is shown as having two processors, the system can have three or more processors, or can be a single processor system. In some examples, the computing system is a system on chip (SoC).

[0058] Processors 470 and 480 are shown as including integrated memory controller (IMC) circuitry 472 and 482, respectively. Processor 470 also includes interface circuitry 476 and 478; similarly, second processor 480 includes interface circuitry 486 and 488. Processors 470, 480 may exchange information via interface 450 using interface circuitry 478, 488. IMCs 472 and 482 couple processors 470, 480 to respective memories, namely memory 432 and memory 434, which may be portions of main memory locally attached to the respective processors.

[0059] Processors 470, 480 may each use interface circuits 476, 494, 486, 498 to exchange information with a network interface (NW I / F) 490 via separate interfaces 452, 454. Network interface 490 (e.g., one or more of an interconnect, bus, and / or fabric, and in some examples, a chipset) may optionally exchange information with a coprocessor 438 via interface circuit 492. In some examples, coprocessor 438 is a special-purpose processor such as, for example, a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general-purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, and the like.

[0060] A shared cache (not shown) may be included in any processor 470, 480, or external to both processors but connected to these processors via an interface (such as, the PP interconnect) so that if the processor is placed in a low power mode, the local cache information of either or both processors can be stored in the shared cache.

[0061] The network interface 490 can be coupled to the first interface 416 via the interface circuit 496. In some examples, the first interface 416 can be an interface such as a peripheral component interconnect (PCI) interconnect, a PCI express interconnect, or another I / O interconnect. In some examples, the first interface 416 is coupled to a power control unit (PCU) 417, which may include circuitry, software, and / or firmware for performing power management operations related to the processors 470, 480, and / or the coprocessor 438. The PCU 417 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. The PCU 417 also provides control information to control the generated operating voltage. In various examples, the PCU 417 may include various power management logic units (circuitry) for performing hardware-based power management. Such power management may be entirely controlled by the processor (e.g., by various processor hardware, and which may be triggered by workload and / or power, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (such as a platform or power management source or system software).

[0062] PCU 417 is illustrated as existing as logic separate from processor 470 and / or processor 480. In other cases, PCU 417 may execute on a given one or more cores (not shown) of the cores of processor 470 or 480. In some cases, PCU 417 may be implemented as a (dedicated or general purpose) microcontroller or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other examples, the power management operations to be performed by PCU 417 may be implemented outside the processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In still other examples, the power management operations to be performed by PCU 417 may be implemented within BIOS or other system software.

[0063] Various I / O devices 414 may be coupled to the first interface 416 along with a bus bridge 418, which couples the first interface 416 to the second interface 420. In some examples, one or more additional processors 415 (such as a coprocessor, a high-throughput many integrated core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor) are coupled to the first interface 416. In some examples, the second interface 420 may be a low pin count (LPC) interface. Various devices may be coupled to the second interface 420, including, for example, a keyboard and / or mouse 422, a communication device 427, and a storage circuit system 428. The storage circuit system 428 may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device that may include instructions / code and data 430. Further, an audio I / O 424 may be coupled to the second interface 420. Note that other architectures are possible besides the point-to-point architecture described above. For example, a system such as multiprocessor system 400 may implement a multi-drop interface or other such architecture instead of a point-to-point architecture.

[0064] Example core architectures, processors, and computer architectures

[0065] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a special-purpose core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more special-purpose cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic or as a dedicated core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip (SoC), which may include the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor described above, and additional functionality on the same die. An example core architecture is described next, followed by a description of an example processor and computer architecture.

[0066] Figure 5 A block diagram of an example processor and / or SoC 500 that may have one or more cores and an integrated memory controller is shown. The solid line block diagram shows a processor 500 having a single core 502(A), a system agent unit circuitry 10, and a collection of one or more interface controller unit circuitry 516, while the optional addition of dashed line blocks shows an alternative processor 500 having multiple cores 502(A)-(N), a collection of one or more integrated memory controller units 514 in the system agent unit circuitry 510, and dedicated logic 508 and a collection of one or more interface controller unit circuitry 516. Note that the processor 500 may be Figure 4 one of the processors 470 or 480, or the coprocessors 438 or 415.

[0067] Thus, different implementations of processor 500 may include: 1) a CPU, where the dedicated logic 508 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 502(A)-(N) are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 502(A)-(N) are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 502(A)-(N) are a large number of general purpose in-order cores. Thus, processor 500 may be a general purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput many integrative core (MIC) coprocessor (including 30 or more cores), an embedded processor, and the like. The processor may be implemented on one or more chips. Processor 500 may be part of and / or implemented on one or more substrates using any of a variety of process technologies, such as, for example, complementary metal-oxide-semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0068] The memory hierarchy includes one or more levels of cache unit circuitry 502(A)-(N) within the cores 504(A)-(N), a set of one or more shared cache unit circuitry 506, and external memory (not shown) coupled to a set of (one or more) integrated memory controller unit circuitry 514. The set of one or more shared cache unit circuitry 506 may include one or more intermediate levels of cache (such as level 2 (L2), level 3 (L3), level 4 (L4)) or other levels of cache (such as last level cache (LLC)) and / or combinations thereof. Although in some examples, an interface network circuitry 512 (e.g., a ring interconnect) provides an interface to dedicated logic 508 (e.g., integrated graphics logic), the set of (one or more) shared cache unit circuitry 506, and the system agent unit circuitry 510, alternative examples use any number of well-known techniques for providing interfaces to such units. In some examples, coherency is maintained between the shared cache unit circuitry 506 and one or more of the cores 502(A)-(N). In some examples, the interface controller unit circuitry 516 couples the core 502 to one or more other devices 518, such as one or more I / O devices, storage, one or more communication devices (e.g., a wireless network, a wired network, etc.), etc.

[0069] In some examples, one or more of the cores 502(A)-(N) may be capable of multithreading. System agent unit circuitry 510 includes those components that coordinate and operate the cores 502(A)-(N). System agent unit circuitry 510 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, the logic and components required to regulate the power state of the cores 502(A)-(N) and / or the dedicated logic 508 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0070] The cores 502(A)-(N) may be homogeneous in terms of instruction set architecture (ISA). Alternatively, the cores 502(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores 502(A)-(N) may be capable of executing an ISA, while other cores may only be capable of executing a subset of that ISA or another ISA.

[0071] Example Core Architecture - In-order and Out-of-order Core Block Diagram

[0072] Fig. 6A is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example. Figure 6B is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example. Figure 6A-6B The solid line boxes in illustrate the in-order pipeline and in-order core, while the optional addition of dashed line boxes illustrate the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0073] exist Fig. 6A , the processor pipeline 600 includes a fetch stage 602, an optional length decode stage 604, a decode stage 606, an optional allocation (Alloc) stage 608, an optional rename stage 610, a dispatch (also called dispatch or issue) stage 612, an optional register read / memory read stage 614, an execute stage 616, a write back / memory write stage 618, an optional exception handling stage 622, and an optional commit stage 624. One or more operations can be performed in each of these processor pipeline stages. For example, during the fetch stage 602, one or more instructions are fetched from the instruction memory, during the decode stage 606, the fetched one or more instructions can be decoded, an address using a forwarded register port (e.g., a load store unit (LSU) address) can be generated, and branch forwarding (e.g., an immediate offset or link register (LR)) can be performed. In one example, the decode stage 606 and the register read / memory read stage 614 can be combined into one pipeline stage. In one example, during the execute stage 616, decoded instructions may be executed, LSU address / data pipelining to an Advanced Microcontroller Bus (AMB) interface may be performed, multiplication and addition operations may be performed, arithmetic operations with branch results may be performed, and so on.

[0074] As an example, Figure 6BAn example register renaming, out-of-order issue / execution architecture core may implement pipeline 600 as follows: 1) instruction fetch circuitry 638 performs fetch stage 602 and length decode stage 604; 2) decode circuitry 640 performs decode stage 606; 3) rename / allocator unit circuitry 652 performs allocate stage 608 and rename stage 610; 4) (one or more) scheduler circuitry 656 performs schedule stage 612; 5) (one or more) physical register file circuitry 658 and memory unit circuitry 670 perform register read / memory read stage 614; (one or more) execution clusters 660 perform execute stage 616; 6) memory unit circuitry 670 and (one or more) physical register file circuitry 658 perform write back / memory write stage 618; 7) each circuitry may involve an exception handling stage 622; and 8) retirement unit circuitry 654 and (one or more) physical register file circuitry 658 perform commit stage 624.

[0075] Figure 6B A processor core 690 is shown, which includes a front end unit circuit system 630 coupled to an execution engine unit circuit system 650, and both are coupled to a memory unit circuit system 670. The core 690 can be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As a further option, the core 690 can be a special purpose core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0076] The front end unit circuit system 630 may include a branch prediction circuit system 632 coupled to an instruction cache circuit system 634, which is coupled to an instruction translation lookaside buffer (TLB) 636, which is coupled to an instruction fetch circuit system 638, which is coupled to a decoding circuit system 640. In one example, the instruction cache circuit system 634 is included in the memory unit circuit system 670 instead of in the front end circuit system 630. The decoding circuit system 640 (or decoder) can decode the instruction and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals decoded from the original instruction, or otherwise reflecting the original instruction, or derived from the original instruction as output. The decoding circuit system 640 may further include an address generation unit (AGU, not shown) circuit system. In one example, the AGU generates an LSU address using the forwarded register port, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decoding circuit system 640 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read only memories (ROM), etc. In one example, the core 690 includes a microcode ROM (not shown) or other medium (e.g., in the decoding circuit system 640, or otherwise within the front-end circuit system 630) that stores microcode for certain macroinstructions. In one example, the decoding circuit system 640 includes a micro-op or operation cache (not shown) to hold / cache decoded operations, micro-tags, or micro-operations generated during the decoding stage or other stages of the processor pipeline 600. The decoding circuit system 640 may be coupled to the rename / allocator unit circuit system 652 in the execution engine circuit system 650.

[0077] Execution engine circuitry 650 includes rename / allocator unit circuitry 652 coupled to retirement unit circuitry 654 and a set of one or more scheduler circuitry 656. Scheduler circuitry(s) 656 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. In some examples, scheduler circuitry(s) 656 may include arithmetic logic unit (ALU) scheduler / scheduling circuitry, ALU queues, address generation unit (AGU) scheduler / scheduling circuitry, AGU queues, and the like. Scheduler circuitry(s) 656 are coupled to physical register file(s) circuitry 658. Each of the physical register file(s) circuitry in physical register file(s) circuitry 658 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one example, the physical register file(s) circuit system 658 includes a vector register unit circuit system, a write mask register unit circuit system, and a scalar register unit circuit system. These register units may provide architectural vector registers, vector mask registers, general registers, etc. The physical register file(s) circuit system 658 is coupled to a retirement unit circuit system 654 (also referred to as a retirement queue (“retire queue” or “retirement queue”) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using (one or more) reorder buffers (ROBs) and (one or more) retirement register files; using (one or more) future files, (one or more) history buffers and (one or more) retirement register files; using register maps and register pools, etc.). The retirement unit circuit system 654 and the physical register file(s) circuit system 658 are coupled to (one or more) execution clusters 660. The execution cluster(s) 660 includes a set 662 of one or more execution unit circuit systems and a set 664 of one or more memory access circuit systems. The execution unit(s) circuit system 662 may perform various arithmetic, logical, floating point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) and may be performed on various data types (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point).While some examples may include multiple execution units or execution unit circuitry dedicated to a particular function or set of functions, other examples may include only one execution unit circuitry or multiple execution units / execution unit circuitry that all perform all functions. Scheduler circuitry(s) 656, physical register file circuitry(s) 658, and execution cluster(s) 660 are shown as potentially multiple because some examples create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines each with its own scheduler circuitry, physical register file circuitry(s), and / or execution clusters—and in the case of separate memory access pipelines, certain examples are implemented where only the execution cluster of that pipeline has memory access unit circuitry(s) 664). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remaining pipelines may be in-order.

[0078] In some examples, the execution engine unit circuit system 650 can perform a load store unit (LSU) address / data pipeline to an Advanced Microcontroller Bus (AMB) interface (not shown), as well as address staging and writeback, data staging load, store, and branch.

[0079] The set of memory access circuitry 664 is coupled to the memory cell circuitry 670, which includes a data TLB circuitry 672, which is coupled to a data cache circuitry 674, which is coupled to a second level (L2) cache circuitry 676. In one example, the memory access circuitry 664 may include a load unit circuitry, a store address unit circuitry, and a store data unit circuitry, each of which is coupled to the data TLB circuitry 672 in the memory cell circuitry 670. The instruction cache circuitry 634 is further coupled to the second level (L2) cache circuitry 676 in the memory cell circuitry 670. In one example, the instruction cache 634 and the data cache 674 are combined into the L2 cache circuitry 676, the third level (L3) cache circuitry (not shown), and / or a single instruction and data cache in the main memory (not shown). The L2 cache circuitry 676 is coupled to one or more other levels of cache and ultimately to the main memory.

[0080] Core 690 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions that have been added with newer versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, core 690 includes logic to support packed data instruction set architecture extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0081] Example Execution Unit(s) Circuitry

[0082] Figure 7 The figure shows an example of execution unit circuitry (one or more) such as Figure 6B (one or more) execution unit circuit system 662. As shown, (one or more) execution unit circuit system 662 may include one or more ALU circuits 701, optional vector / single instruction multiple data (single instruction multiple data, SIMD) circuits 703, load / store circuits 705, branch / jump circuits 707 and / or floating-point unit (FPU) circuits 709. ALU circuit 701 performs integer arithmetic and / or Boolean operations. Vector / SIMD circuit 703 performs vector / SIMD operations on packed data (such as SIMD / vector registers). Load / store circuit 705 executes load and store instructions to load data from memory into registers or store data from registers to memory. Load / store circuit 705 may also generate addresses. Branch / jump circuit 707 causes branches or jumps to memory addresses depending on the instructions. FPU circuit 709 performs floating-point arithmetic. The width of the execution unit circuitry 662 varies depending on the example, and may range, for example, from 16 bits to 1024 bits. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0083] Program code can be applied to input information to perform the functions described herein and generate output information. Output information can be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system with a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.

[0084] Program code can be implemented with high-level process-oriented programming language or object-oriented programming language to communicate with the processing system. If necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described herein is not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.

[0085] Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Examples may be implemented as a computer program or program code executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0086] One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium, which represent various logic within a processor, which, when read by a machine, causes the machine to manufacture logic for performing the techniques described herein. Such representations, referred to as "intellectual property (IP) cores," may be stored on tangible machine-readable media and may be supplied to various customers or production facilities to be loaded into a manufacturing machine that actually manufactures the logic or processor.

[0087] Such machine-readable storage media may include, but are not limited to, non-transitory tangible arrangements of articles made or formed by a machine or apparatus, including storage media such as: a hard disk; any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), rewritable compact disks (CD-RW), and magneto-optical disks); semiconductor devices (such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); phase change memory (PCM); magnetic or optical cards; or any other type of medium suitable for storing electronic instructions.

[0088] Therefore, the examples also include non-transitory tangible machine-readable media containing instructions or containing design data, such as hardware description language (HDL), which defines the structures, circuits, devices, processors and / or system features described herein. Such examples may also be referred to as program products.

[0089] Simulation (including binary translation, code deformation, etc.).

[0090] In some cases, the instruction converter can be used to convert instructions from a source instruction set architecture to a target instruction set architecture. For example, the instruction converter can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), deform, simulate or otherwise convert instructions into one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0091] Figure 81 is a block diagram illustrating the use of a software instruction converter according to an example to convert binary instructions in a source ISA into binary instructions in a target ISA. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Figure 8 It is shown that a program in a high-level language 802 can be compiled using a first ISA compiler 804 to generate first ISA binary code 806 that can be natively executed by a processor 816 having at least one first ISA core. The processor 816 having at least one first ISA core represents any processor that can perform the same operations as a processor having at least one first ISA core by compatibly executing or otherwise processing the following: The first ISA compiler 804 represents a compiler that can be used to generate first ISA binary code 806 (e.g., object code) that can be executed on a processor 816 having at least one first ISA core with or without additional linking processing. Similarly, Figure 8 It is shown that a program in a high-level language 802 can be compiled using an alternative ISA compiler 808 to generate an alternative ISA binary code 810 that can be natively executed by a processor 814 without a first ISA core. An instruction converter 812 is used to convert the first ISA binary code 806 into a code that can be natively executed by a processor 814 without a first ISA core. The converted code does not have to be the same as the alternative ISA binary code 810; however, the converted code will complete general operations and consist of instructions from the alternative ISA. Thus, the instruction converter 812 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first ISA processor or core to execute the first ISA binary code 806 by emulation, simulation, or any other process.

[0092] References to "one example," "an example," "one embodiment," "an embodiment," etc. indicate that the described example or embodiment may include a particular feature, structure, or characteristic, but each example or embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same example or embodiment. Further, when a particular feature, structure, or characteristic is described in conjunction with an example or embodiment, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other examples or embodiments, whether or not explicitly described.

[0093] In addition, in the examples described above, unless otherwise specifically noted, delimited language such as phrases "at least one of A, B, or C" or "A, B, and / or C" is intended to be understood to mean A, B, or C, or any combination thereof (i.e., A and B, A and C, B and C, and A, B, and C). As used in this specification and claims, and unless otherwise specified, the use of ordinal adjectives "first," "second," "third," etc., used to describe elements merely indicates that a specific instance of an element or different instances of similar elements are being referenced, and is not intended to imply that the elements so described must be in a particular order in time, space, hierarchically, or in any other manner. In addition, as used in the description of the embodiments, the " / " character between items may mean that what is described may include the first item and / or the second item (and / or any other additional items), or may be implemented using, utilizing, and / or according to the first item and / or the second item (and / or any other additional items).

[0094] In addition, the terms "bit", "flag", "field", "entry", "indicator", etc. may be used to describe a storage location in a register, table, database, or other data structure of any type or content, whether implemented in hardware or software, and these terms are not intended to limit the embodiments to any particular type of storage location or the number of bits or other elements within any particular storage location. For example, the term "bit" may be used to refer to a bit position within a register and / or data stored or to be stored in the bit position. The term "clear" may be used to indicate storing a logic value of 0 in a storage location, or otherwise causing a logic value of 0 to be stored in a storage location; and the term "set" may be used to indicate storing a logic value of 1, all 1s, or some other specified value in a storage location, or otherwise causing a logic value of 1, all 1s, or some other specified value to be stored in a storage location; however, these terms are not intended to limit the embodiments to any particular logical convention, as any logical convention may be used within the embodiments.

[0095] Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the claims.

Claims

1. A processor device for instruction tagging, comprising: an instruction decoder for decoding a first instruction having an instruction tag value; as well as Execution circuitry, coupled to the instruction decoder, performs one or more operations corresponding to the first instruction, including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to data.

2. The processor device according to claim 1, characterized in that The instruction decoder is further configured to decode a second instruction having a pointer tag value based on the relative enumeration in the pointer.

3. The processor device according to claim 2, characterized in that The data corresponds to members of the object.

4. The processor device according to claim 3, characterized in that The instruction tag value is associated with the member.

5. The processor device according to claim 3, characterized in that The pointer tag value is associated with the object.

6. The processor device according to claim 1, characterized in that The one or more operations also include identifying a memory location of a second data tag value associated with the data.

7. The processor device according to claim 6, characterized in that The one or more operations also include comparing the second data tag value to the first data tag value.

8. The processor device according to claim 7, characterized in that The one or more operations also include preventing access to the data in response to detecting a mismatch between the second data tag value and the first data tag value.

9. The processor device according to claim 1, characterized in that The first data tag value is obtained from the sum of the instruction tag value and the relative enumeration.

10. A method for tagging instructions, comprising: decoding, by an instruction decoder of a processing device, a first instruction having an instruction tag value; as well as One or more operations corresponding to the first instruction are performed, via execution circuitry coupled to the instruction decoder, including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to data.

11. The method of claim 10, further comprising: A second instruction is decoded, by the instruction decoder, the second instruction having a pointer tag value based on the relative enumeration in the pointer.

12. The method according to claim 11, characterized in that The data corresponds to members of the object.

13. The method according to claim 12, characterized in that The instruction tag value is associated with the member.

14. The method according to claim 12, characterized in that The pointer tag value is associated with the object.

15. The method according to claim 10, characterized in that The one or more operations also include identifying a memory location of a second data tag value associated with the data.

16. The method according to claim 15, characterized in that The one or more operations also include comparing the second data tag value to the first data tag value.

17. The method according to claim 16, characterized in that The one or more operations also include preventing access to the data in response to detecting a mismatch between the second data tag value and the first data tag value.

18. The method according to claim 10, characterized in that The first data tag value is obtained from the sum of the instruction tag value and the relative enumeration.

19. A non-transitory machine-readable medium storing at least a single instruction, which, when executed by a machine, causes the machine to perform a method for instruction tagging, the method comprising: decoding, by an instruction decoder of a processing device, a first instruction having an instruction tag value; as well as One or more operations corresponding to the first instruction are performed, via execution circuitry coupled to the instruction decoder, including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to data.

20. The non-transitory machine-readable medium of claim 19, wherein: The one or more operations also include: identifying a memory location of a second data tag value associated with the data; comparing the second data tag value to the first data tag value; and Access to the data is blocked in response to detecting a mismatch between the second data tag value and the first data tag value.

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