Optimization method of quantum circuit based on time sequence alignment

Abstract

The invention discloses a quantum circuit optimization method based on time sequence alignment. The optimization method of the quantum circuit comprises the following steps: determining a first quantum circuit according to a dependency relationship of quantum gates in the quantum circuit; and processing the target quantum gate in the first quantum circuit to obtain a second quantum circuit. And performing delay processing on the single-bit quantum gate in the second quantum circuit according to the barrier gate to obtain a first optimized quantum circuit so as to realize optimization of the quantum circuit. Thus, the computer equipment delays the positions of part of quantum gates in the quantum circuit by inserting a time sequence alignment operation and ensures that the quantum gates do not run in advance by using a barrier gate, so that quantum bits entering the quantum circuit only participate in calculation when necessary, and the quantum bits are prevented from entering a superposition state too early; the interference of noise to the quantum bits in the calculation process is reduced, and the stability and reliability of quantum circuit operation are improved.

Description

Technical Field

[0001] The present application relates to the field of quantum circuit optimization, and more specifically, to a quantum circuit optimization method based on timing alignment. Background Art

[0002] Quantum circuits, which are used to implement quantum algorithms and quantum information processing, are composed of a series of quantum logic gates and are the basic components of quantum computers. Quantum circuits can implement quantum algorithms and simulate the behavior of quantum systems by operating the state of quantum bits. However, quantum bits in superposition are susceptible to noise such as quantum gate noise, decoherence of the quantum bits themselves, and bit flips, which lead to quantum state attenuation and errors, thus affecting the stability of quantum circuit operation. Summary of the invention

[0003] The present application provides a quantum circuit optimization method based on timing alignment.

[0004] The embodiment of the present application provides a method for optimizing a quantum circuit based on timing alignment, the method comprising:

[0005] Determine a first quantum circuit according to the dependency relationship of quantum gates in the quantum circuit;

[0006] Processing a target quantum gate in the first quantum circuit to obtain a second quantum circuit;

[0007] A first optimized quantum circuit is obtained by postponing the single-bit quantum gate in the second quantum circuit according to the barrier gate, so as to optimize the quantum circuit, wherein the barrier gate is configured to prevent the quantum gate after the barrier gate in the quantum circuit from running in advance.

[0008] In this way, the computer device determines the first quantum circuit through the dependency of quantum gates and the timing alignment means. The determined first quantum circuit can make all quantum gates that can be operated in parallel be in the same time layer, providing a basis for the subsequent use of barrier gates to postpone the processing of single-bit quantum gates in the quantum circuit, and optimizing the circuit structure. Then, the computer device processes the target quantum gates in the first quantum circuit that are not natively supported by the computer device architecture to obtain a second quantum circuit. The second quantum circuit obtained in this way includes a single-bit quantum gate and is easier to accurately implement than the first quantum circuit. Finally, the computer device processes the second quantum circuit according to the barrier gate to obtain the first optimized quantum circuit. The barrier gate can prevent the quantum gates after the barrier gate in the quantum circuit from running ahead of time, so that some quantum circuits maintain a specific order or structure. In this way, the first optimized quantum circuit obtained postpones the position of some quantum gates and uses barrier gates to ensure that these quantum gates will not run ahead of time, so that the quantum bits entering the quantum circuit only participate in the calculation when necessary, preventing the quantum bits from entering the superposition state too early, reducing the interference of noise on the quantum bits during the calculation process, and improving the stability and reliability of the operation of the quantum circuit.

[0009] In some embodiments, determining the first quantum circuit according to the dependency relationship of quantum gates in the quantum circuit includes:

[0010] Determine the parallel quantum gates that can be operated in parallel in the quantum circuit according to the dependency relationship;

[0011] The execution sequence of quantum gates in the quantum circuit is rearranged according to the parallel quantum gates to obtain the first quantum circuit.

[0012] In this way, the computer device determines the parallel quantum gates that can be operated in parallel in the quantum circuit through the dependency relationship. Then, the computer device re-arranges the execution sequence of the quantum gates in the quantum circuit according to the parallel quantum gates to obtain the first quantum circuit. In this way, the computer device re-arranges the execution sequence of the quantum gates in the quantum circuit through the dependency relationship, so that some quantum gates can be operated in parallel, which can reduce the execution time of the entire quantum circuit and improve the efficiency of quantum computing.

[0013] In certain embodiments, the method further comprises:

[0014] The functional equivalence of the first quantum circuit is verified according to the simulation test to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

[0015] In this way, the computer device verifies the functional equivalence of the first quantum circuit based on the simulation test to ensure that the first quantum circuit and the quantum circuit are functionally equivalent. In this way, it is ensured that the first quantum circuit optimized by the computer device can correctly perform the calculation task of the original quantum circuit, ensuring that the correctness of the algorithm will not be sacrificed.

[0016] In some embodiments, the step of processing the target quantum gate in the first quantum circuit to obtain the second quantum circuit includes:

[0017] The target quantum gate is processed according to the pre-supported quantum instruction set to obtain the second quantum circuit.

[0018] In this way, the computer device processes the target quantum gate according to the pre-supported quantum instruction set to obtain the second quantum circuit. In this way, the target quantum gate is decomposed into the basic quantum gates in the pre-supported quantum instruction set through the quantum instruction set, and the complex quantum gate operation is converted into a combination of basic quantum gates so as to be implemented on the existing quantum hardware, while improving the efficiency of quantum computing and having good universality.

[0019] In some embodiments, the step of postponing the single-bit quantum gate in the second quantum circuit according to the barrier gate to obtain the first optimized quantum circuit includes:

[0020] Postponing the single-bit quantum gate to before the nearest two-bit quantum gate, the nearest two-bit quantum gate being used to indicate the first two-bit quantum gate after the single-bit quantum gate in the second quantum circuit that acts on the same quantum bit as the single-bit quantum gate;

[0021] The barrier gate is added before the single-bit quantum gate located before the nearest two-bit quantum gate to obtain the first optimized quantum circuit.

[0022] In this way, the computer device postpones the single-bit quantum gate to the nearest two-bit quantum gate, and the nearest two-bit quantum gate is used to indicate the first two-bit quantum gate after the single-bit quantum gate in the second quantum circuit that acts on the same quantum bit as the single-bit quantum gate. Next, the computer device adds a barrier gate before the single-bit quantum gate located before the nearest two-bit quantum gate to obtain the first optimized quantum circuit. In this way, by postponing the single-bit quantum gate to the nearest two-bit quantum gate, the time for the quantum bit to enter the superposition state is postponed as much as possible, so that the quantum bit only participates in the calculation when necessary, and prevents the quantum bit from entering the superposition state too early. In addition, by adding a barrier gate before the single-bit quantum gate located before the nearest two-bit quantum gate, the single-bit quantum gate operation after the barrier gate is prevented from running prematurely, ensuring that some sub-circuits of the quantum circuit maintain a specific order or structure.

[0023] In certain embodiments, the optimization method further comprises:

[0024] Merging a plurality of first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit, wherein the first barrier interval is used to indicate a quantum circuit between every two barrier gates in the first optimized quantum circuit, and a first starting barrier interval of the first optimized quantum circuit and a first ending barrier interval of the first optimized quantum circuit are respectively determined by one of the barrier gates;

[0025] The single-bit quantum gates in the first optimized quantum circuit are sequentially embedded in the second optimized quantum circuit to obtain a third optimized quantum circuit.

[0026] In this way, the computer device merges multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit, wherein the first barrier interval is used to indicate the quantum circuit between every two barrier gates in the first optimized quantum circuit, and the first starting barrier interval of the first optimized quantum circuit and the first ending barrier interval of the first optimized quantum circuit are respectively determined by a barrier gate. Next, the computer device sequentially embeds the single-bit quantum gates in the first optimized quantum circuit into the second optimized quantum circuit to obtain a third optimized quantum circuit. In this way, by merging multiple first barrier intervals in the first optimized quantum circuit, the depth of the quantum circuit is reduced and the overall performance of the quantum circuit is improved. In addition, the single-bit quantum gates in the first optimized quantum circuit are sequentially embedded into the second optimized quantum circuit to ensure that the obtained third optimized quantum circuit is functionally equivalent to the first optimized quantum circuit.

[0027] In some embodiments, the step of merging the plurality of first barrier intervals in the first optimized quantum circuit to obtain the second optimized quantum circuit includes:

[0028] Using the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit;

[0029] The second end barrier interval is compared with a plurality of the first barrier intervals to obtain a second optimized quantum circuit.

[0030] In this way, the computer device uses the first starting barrier interval as the second final barrier interval of the second optimized quantum circuit. Then, the computer device compares the second final barrier interval with the plurality of first barrier intervals to obtain the second optimized quantum circuit. In this way, by comparing the second final barrier interval with the plurality of first barrier intervals, it is determined whether these first barrier intervals can be merged into the second final barrier interval, so as to reduce the depth of the quantum circuit and improve the execution efficiency of the quantum circuit.

[0031] In some embodiments, the comparing the second terminal barrier interval with a plurality of the first barrier intervals to obtain a second optimized quantum circuit comprises:

[0032] Comparing the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval, wherein the next first barrier interval is used to indicate the next first barrier interval in the first optimized quantum circuit that is located in the first barrier interval corresponding to the second end barrier interval;

[0033] When it is confirmed that the current two-bit quantum gate in the next first barrier interval can be moved to the second end barrier interval, the current two-bit quantum gate in the next first barrier interval is moved to the second end barrier interval to obtain the second optimized quantum circuit.

[0034] In this way, the computer device compares the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval, wherein the next first barrier interval is used to indicate the next first barrier interval in the first optimized quantum circuit that is located in the first barrier interval corresponding to the second end barrier interval. Then, in the case of confirming that the current two-bit quantum gate in the next first barrier interval can be moved to the second end barrier interval, the computer device moves the current two-bit quantum gate in the next first barrier interval to the second end barrier interval to obtain the second optimized quantum circuit. In this way, by comparing the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval, it is checked whether the two-bit quantum gate in the next first barrier interval can be moved to the second end barrier interval without affecting the execution order and result of the circuit. In addition, the computer device moves the two-bit quantum gate in the next first barrier interval to the second end barrier interval, which reduces the depth of the quantum circuit and improves the execution efficiency of the quantum circuit.

[0035] In some embodiments, the comparing the two-bit quantum gate in the second terminal barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval includes:

[0036] When the qubit acted by the current two-bit quantum gate in the next first barrier interval is inconsistent with the qubit acted by each two-bit quantum gate in the second last barrier interval, confirming that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval;

[0037] When at least one of the quantum bits acted by the current two-bit quantum gate in the next first barrier interval and the quantum bits acted by the two-bit quantum gate in the second final barrier interval is consistent, it is confirmed that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second final barrier interval.

[0038] In this way, when the qubits acted by the current two-bit quantum gate in the next first barrier interval and the qubits acted by each two-bit quantum gate in the second last barrier interval are not consistent, the computer device confirms that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval. Then, when at least one of the qubits acted by the current two-bit quantum gate in the next first barrier interval and the qubits acted by the two-bit quantum gate in the second last barrier interval are consistent, the computer device confirms that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval. In this way, by judging the consistency of the qubits acted by the current two-bit quantum gate in the next first barrier interval and the qubits acted by each two-bit quantum gate in the second last barrier interval, it is confirmed that moving the two-bit quantum gate will not affect the correct execution of the quantum circuit. If the qubits acted by the current two-bit quantum gate in the next first barrier interval and the qubits acted by the two-bit quantum gate in the second last barrier interval are completely inconsistent, that is, no qubit is the same in the two intervals, then the computer device confirms that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval, performs the move operation, and obtains the optimized quantum circuit. If at least one of the quantum bits acted upon by the current two-bit quantum gate in the next first barrier interval and the quantum bit acted upon by the two-bit quantum gate in the second final barrier interval is consistent, then the computer device confirms that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second final barrier interval, keeping the current quantum circuit structure unchanged.

[0039] In some embodiments, using the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit includes:

[0040] In a case where the next first barrier interval includes a two-bit quantum gate, the next first barrier interval is used as the second last barrier interval of the second optimized quantum circuit.

[0041] In this way, when the next first barrier interval includes a two-bit quantum gate, the next first barrier interval is used as the second end barrier interval of the second optimized quantum circuit. In this way, in the first optimized quantum circuit, the next barrier interval including the two-bit quantum gate is found, and this interval is called the next first barrier interval. In addition, the next first barrier interval is used as the second end barrier interval of the second optimized quantum circuit, which means that the end position of the second optimized quantum circuit is set to the interval including the two-bit quantum gate, and the interval including the two-bit quantum gate is subsequently used to merge the remaining first barrier intervals in the first optimized quantum circuit.

[0042] In certain embodiments, the method further comprises:

[0043] In a case where the next first barrier interval does not include a two-bit quantum gate, the second end barrier interval is compared with a plurality of the first barrier intervals to obtain a second optimized quantum circuit.

[0044] In this way, when the next first barrier interval does not include a two-bit quantum gate, the computer device compares the second end barrier interval with the multiple first barrier intervals to obtain a second optimized quantum circuit. In this way, if the next first barrier interval does not include a two-bit quantum gate, that is, the two-bit quantum gates in the next first barrier interval are all merged into the second end barrier interval, then the second end barrier interval is still used as the new second end barrier interval, and the remaining first barrier intervals in the first optimized quantum circuit are merged.

[0045] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0047] Figure 1 It is one of the flow charts of the implementation method of the present application;

[0048] Figure 2 is a schematic diagram of a first quantum circuit in an embodiment of the present application;

[0049] Figure 3 is a schematic diagram of a Hadamard gate according to an embodiment of the present application;

[0050] Figure 4 is a schematic diagram of a controlled NOT gate according to an embodiment of the present application;

[0051] Figure 5 is a schematic diagram of a second quantum circuit in an embodiment of the present application;

[0052] Figure 6 is a schematic diagram of a control phase gate according to an embodiment of the present application;

[0053] Figure 7 This is a schematic diagram of the first optimized quantum circuit flow in an implementation mode of the present application;

[0054] Figure 8 This is the second flow chart of the implementation method of the present application;

[0055] Fig. 9 This is the third flow chart of the implementation method of this application;

[0056] Fig.10 This is the fourth flow chart of the implementation method of the present application;

[0057] Fig.11 This is the fifth flow chart of the implementation method of the present application;

[0058] Fig.12 This is the sixth flow chart of the implementation method of the present application;

[0059] Fig.13 is a schematic diagram of a second optimized quantum circuit in an embodiment of the present application;

[0060] Fig.14 is a schematic diagram of a third optimized quantum circuit according to an embodiment of the present application;

[0061] Fig.15 This is the seventh flow chart of the implementation method of the present application;

[0062] Fig.16 This is the eighth flow chart of the implementation method of the present application;

[0063] Fig.17 This is the ninth flow chart of the implementation method of the present application;

[0064] Fig.18 This is the tenth flowchart of the implementation method of the present application;

[0065] Fig.19 This is the eleventh flow chart of the implementation method of the present application. DETAILED DESCRIPTION

[0066] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application, and cannot be understood as limiting the embodiments of the present application.

[0067] Quantum circuits, which are used to implement quantum algorithms and quantum information processing, are composed of a series of quantum logic gates and are the basic components of quantum computers. By operating the state of quantum bits, quantum algorithms can be implemented and the behavior of quantum systems can be simulated.

[0068] However, since qubits are in a superposition state, they are susceptible to various noises, which lead to quantum state decay and errors, and thus affect the stability of quantum circuit operation. These noises mainly include quantum gate noise, decoherence of the qubit itself, and bit flipping.

[0069] Quantum gate noise refers to errors introduced when performing quantum logic gate operations. This noise can be caused by imperfect gate implementation, environmental interference, errors in control electronics, etc. Quantum gate noise can cause the state of the qubit to deviate from the expected ideal state, thus affecting the accuracy of the quantum algorithm.

[0070] The decoherence of the qubit itself refers to the loss of superposition and coherence of the quantum state of the qubit due to the interaction between the qubit and the environment. This decoherence may be caused by the interaction between the qubit and the thermodynamic noise, electromagnetic field, vibration and other factors in the environment. Decoherence will cause the quantum state of the qubit to decay rapidly to a classical mixed state, thus affecting the stability of the quantum circuit operation and the reliability of the calculation results.

[0071] A bit flip is when the state of a quantum bit unexpectedly changes from |0> to |1>, or from |1> to |0>. This flip may be caused by random perturbations or noise on the quantum bit. A bit flip is a special type of error that directly changes the quantum state of the quantum bit, thereby affecting the accuracy of the quantum algorithm.

[0072] Based on the above questions, please refer to Figure 1 The embodiment of the present application provides a method for optimizing a quantum circuit based on timing alignment, the method comprising:

[0073] 011: Determine the first quantum circuit based on the dependency of quantum gates in the quantum circuit;

[0074] 012: Process the target quantum gate in the first quantum circuit to obtain a second quantum circuit;

[0075] 013: The single-bit quantum gate in the second quantum circuit is delayed according to the barrier gate to obtain a first optimized quantum circuit, so as to optimize the quantum circuit.

[0076] The embodiment of the present application also provides a computer device, including a memory and a processor. The optimization method of the quantum circuit of the embodiment of the present application can be implemented by the computer device of the embodiment of the present application. Specifically, a computer program is stored in the memory, and the processor is used to determine the first quantum circuit according to the dependency relationship of the quantum gates in the quantum circuit. And the target quantum gate in the first quantum circuit is processed to obtain the second quantum circuit. And the single-bit quantum gate in the second quantum circuit is postponed according to the barrier gate to obtain the first optimized quantum circuit, so as to optimize the quantum circuit.

[0077] The embodiment of the present application also provides a quantum circuit optimization device. The optimization method of the quantum circuit of the embodiment of the present application can be implemented by the quantum circuit optimization device of the embodiment of the present application. Specifically, the quantum circuit optimization device includes a determination module, a processing module and a postponement module. The determination module is used to determine the first quantum circuit according to the dependency relationship of the quantum gates in the quantum circuit. The processing module is used to process the target quantum gate in the first quantum circuit to obtain the second quantum circuit. The postponement module is used to postpone the single-bit quantum gate in the second quantum circuit according to the barrier gate to obtain the first optimized quantum circuit, so as to optimize the quantum circuit.

[0078] Specifically, time series alignment is used to adjust data at different time points or time series to a unified reference time point or time series.

[0079] A quantum circuit consists of a series of quantum gates, which are used to describe how quantum gates operate on the state of quantum bits. It is the basis for implementing quantum algorithms and quantum information processing.

[0080] Quantum gates, also called quantum logic gates, are the basic operating units in quantum computing. They perform specific mathematical operations on quantum bits to achieve complex computing tasks and build quantum algorithms and quantum protocols.

[0081] A qubit is the basic unit of a quantum circuit, similar to a bit in classical computing, but can be in a superposition state.

[0082] The dependency of quantum gates refers to the interaction and order relationship between different quantum gate operations in quantum computing. The judgment method is:

[0083] In a quantum circuit C, quantum operations are said to be dependent if they simultaneously satisfy the following conditions:

[0084] Share at least one quantum bit being acted upon;

[0085] And the execution order between quantum operations cannot be arbitrarily swapped to avoid changing the behavior or output of the quantum circuit.

[0086] A barrier gate is a non-interactive gate that prevents operations after the barrier gate from running prematurely when compiling a quantum circuit, allowing certain parts of the circuit to maintain a specific order or structure.

[0087] Quantum circuit optimization refers to the adjustment and improvement of the structure, connection method, operation sequence and other aspects of the quantum circuit. Its significance lies in reducing the depth of the quantum circuit and optimizing the order of quantum gates, thereby improving the computing speed and accuracy of the quantum computer.

[0088] Specifically, the computer device determines the first quantum circuit through the dependency relationship of quantum gates and the timing alignment means. The determined first quantum circuit can make all quantum gates that can be operated in parallel be in the same time layer, providing a basis for the subsequent use of barrier gates to postpone the processing of single-bit quantum gates in the quantum circuit, and optimizing the circuit structure. Then, the computer device processes the target quantum gates in the first quantum circuit that are not natively supported by the computer device architecture to obtain a second quantum circuit. The second quantum circuit obtained in this way includes a single-bit quantum gate and is easier to accurately implement than the first quantum circuit. Finally, the computer device processes the second quantum circuit according to the barrier gate to obtain the first optimized quantum circuit. The barrier gate can prevent the quantum gates after the barrier gate in the quantum circuit from running ahead of time, so that some quantum circuits maintain a specific order or structure. In this way, the first optimized quantum circuit obtained postpones the position of some quantum gates and uses barrier gates to ensure that these quantum gates will not run ahead of time, so that the quantum bits entering the quantum circuit only participate in the calculation when necessary, preventing the quantum bits from entering the superposition state too early, reducing the interference of noise on the quantum bits during the calculation process, and improving the stability and reliability of the operation of the quantum circuit. It should be noted that the quantum circuit optimization method provided in the embodiment of the present application optimizes the quantum circuit on a classical computer, and then uses a quantum computer to execute the optimized quantum circuit.

[0089] The following is an example to illustrate the optimization method of the quantum circuit of the implementation mode of the present application. In the embodiment of the present application, the target quantum gate is a complex quantum gate, such as a Toffoli gate, a SWAP gate, and other quantum gates that are difficult to run directly on a physical machine.

[0090] See also Figure 2 , Figure 2 This is a schematic diagram of the first quantum circuit. This schematic diagram is for reference only. Different quantum circuits may obtain different first quantum circuits after different processing. It is determined according to actual needs and is not limited here. Figure 2 It includes qubits such as q6 and q12, Hadamard gates, and controlled NOT gates, i.e. CNOT gates. Figure 3 , Figure 4 , Hadamard Figure 3 As shown, the CNOT gate is Figure 4 shown.

[0091] See also Figure 5 , Figure 5 This is a schematic diagram of the second quantum circuit. This schematic diagram is for reference only. Different first quantum circuits may obtain different second quantum circuits after different processing. It is determined according to actual needs and is not limited here. Figure 2 It includes the H gate and the control phase gate, namely the CZ gate, which is obtained by decomposing the CNOT. Figure 6 , CZ door Figure 6 shown.

[0092] See also Figure 7 , Figure 7 This is a schematic diagram of the first optimized quantum circuit. This schematic diagram is for reference only. Different second quantum circuits may obtain different first optimized quantum circuits after different processing. It is determined according to actual needs and is not limited here.

[0093] The computer device determines the first quantum circuit C1 through the dependency of quantum gates and timing alignment. The first quantum circuit C1 determined in this way can make all quantum gates that can be operated in parallel be in the same time layer, providing a basis for the subsequent use of barrier gates to postpone the processing of single-bit quantum gates in the quantum circuit, and optimizing the circuit structure. Then, the computer device processes the target quantum gates in the first quantum circuit C1 that are not natively supported by the computer device architecture to obtain the second quantum circuit C2. The second quantum circuit C2 obtained in this way includes a single-bit quantum gate and is easier to accurately implement than the first quantum circuit C1. Finally, the computer device processes the second quantum circuit C2 according to the barrier gate to obtain the first optimized quantum circuit C3. The barrier gate can prevent the quantum gates after the barrier gate in the quantum circuit from running prematurely, so that some quantum circuits maintain a specific order or structure.

[0094] To summarize, in the quantum circuit optimization method and computer device of the implementation mode of the present application, the computer device postpones the positions of some quantum gates in the quantum circuit by inserting timing alignment operations and uses barrier gates to ensure that these quantum gates do not run in advance, so that the quantum bits entering the quantum circuit participate in the calculation only when necessary, preventing the quantum bits from entering the superposition state too early, reducing the interference of noise on the quantum bits during the calculation process, and improving the stability and reliability of the operation of the quantum circuit.

[0095] See also Figure 8 In some embodiments, step 011 (determining a first quantum circuit according to the dependency relationship of quantum gates in the quantum circuit) comprises the steps of:

[0096] 0111: Determine the parallel quantum gates that can be operated in parallel in quantum circuits through dependencies;

[0097] 0112: Rearrange the execution sequence of quantum gates in the quantum circuit according to the parallel quantum gates to obtain the first quantum circuit.

[0098] In some embodiments, the determination module is used to determine the parallel quantum gates that can be operated in parallel in the quantum circuit through the dependency relationship. The sorting module is used to rearrange the execution sequence of the quantum gates in the quantum circuit according to the parallel quantum gates to obtain the first quantum circuit.

[0099] In some embodiments, the processor is further configured to determine parallel quantum gates that can be operated in parallel in the quantum circuit through dependency relationships, and to rearrange the execution sequence of the quantum gates in the quantum circuit according to the parallel quantum gates to obtain a first quantum circuit.

[0100] Specifically, the computer device determines the parallel quantum gates that can be operated in parallel in the quantum circuit through the dependency relationship. Then, the computer device re-arranges the execution sequence of the quantum gates in the quantum circuit according to the parallel quantum gates to obtain the first quantum circuit. In this way, the computer device re-arranges the execution sequence of the quantum gates in the quantum circuit through the dependency relationship, thereby operating the quantum gates in parallel, which can reduce the execution time of the entire quantum circuit and improve the efficiency of quantum computing.

[0101] Continuing with the above example, please refer again to Figure 2 In order to clearly and intuitively display the dependency of quantum gates in quantum circuit C, a dependency graph is usually constructed to map the dependencies between quantum gates into nodes and edges in a directed acyclic graph. The dependency graph can be used to identify parallel quantum gates that can be executed in parallel in quantum circuit C. Next, the sequence of quantum gates is rearranged on quantum circuit C so that the identified parallel quantum gates can be placed in the same time layer, thus obtaining the first quantum circuit C1. In this embodiment, the execution sequence of quantum gates is rearranged according to the left-aligned strategy to obtain the following: Figure 2 The first quantum circuit C1 is shown.

[0102] In this way, the computer device rearranges the execution sequence of quantum gates in the quantum circuit through dependencies, so that some quantum gates can be operated in parallel, which can reduce the execution time of the entire quantum circuit and improve the efficiency of quantum computing.

[0103] See also Fig. 9 In some embodiments, the method further comprises:

[0104] 014: Verify the functional equivalence of the first quantum circuit based on simulation tests to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

[0105] In some embodiments, the testing module is used to perform functional equivalence verification on the first quantum circuit according to the simulation test to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

[0106] In some embodiments, the processor is further configured to perform functional equivalence verification on the first quantum circuit according to a simulation test to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

[0107] Specifically, simulation testing usually refers to using a classical computer to simulate the behavior of a quantum computer to verify the correctness and performance of a quantum circuit or algorithm. By comparing the outputs of two quantum circuits, it can be determined whether they produce the same output for all possible inputs, thereby verifying their functional equivalence.

[0108] Functional equivalence verification refers to the process of confirming whether two quantum circuits are functionally identical or equivalent.

[0109] The computer equipment verifies the functional equivalence of the first quantum circuit based on the simulation test to ensure that the first quantum circuit and the quantum circuit are functionally equivalent. In this way, it is ensured that the first quantum circuit optimized by the computer equipment can correctly perform the calculation task of the original quantum circuit, ensuring that the correctness of the algorithm will not be sacrificed.

[0110] Continuing with the above example, the computer device performs functional equivalence verification on the first quantum circuit C1 according to the simulation test to ensure that the first quantum circuit C1 and quantum circuit C are functionally equivalent. In some embodiments, the simulation test may be to input test data of a known output result into the first quantum circuit C1, and compare the test result output by the first quantum circuit C1 with the known output result. If the test result is consistent with the known output result, it is determined that the functions of the first quantum circuit C1 and the original quantum circuit C are consistent. If the test result is inconsistent with the known output result, it is determined that the functions of the first quantum circuit C1 and the original quantum circuit C are different, and the first quantum circuit C1 cannot be equivalent to quantum circuit C.

[0111] In this way, it is ensured that the first quantum circuit C1 optimized by the computer equipment can correctly execute the calculation task of the original quantum circuit, and the correctness of the algorithm will not be sacrificed.

[0112] See also Fig.10 In some embodiments, step 012 (processing the target quantum gate in the first quantum circuit to obtain the second quantum circuit) includes:

[0113] 0121: Process the target quantum gate according to the pre-supported quantum instruction set to obtain a second quantum circuit.

[0114] In some embodiments, the processing module is used to process the target quantum gate according to the pre-supported quantum instruction set to obtain a second quantum circuit.

[0115] In some embodiments, the processor further processes the target quantum gate according to a pre-supported quantum instruction set to obtain a second quantum circuit.

[0116] Specifically, target quantum gates refer to compound gates that are not natively supported by computer device architectures.

[0117] A quantum instruction set refers to a series of quantum operations that can be performed by quantum computer hardware. The design of the quantum instruction set depends on the physical implementation and architecture of the quantum computer, and different quantum computers may have different instruction sets to optimize their specific hardware characteristics.

[0118] The computer device processes the target quantum gate according to the pre-supported quantum instruction set to obtain the second quantum circuit. In this way, the target quantum gate is decomposed into basic quantum gates in the pre-supported quantum instruction set through the quantum instruction set, and the complex quantum gate operation is converted into a combination of basic quantum gates so as to be implemented on the existing quantum hardware, while improving the efficiency of quantum computing.

[0119] Continuing with the above example, the Hadamard Gate, or H-Gate, is a fundamental gate in quantum computing that is used to rotate the state of a quantum bit from a computational ground state to a superposition state.

[0120] The controlled-NOT gate (CNOT) is a basic gate in quantum computing and plays a key role in quantum computing. The CNOT gate is a two-qubit gate consisting of a control bit and a target bit.

[0121] The computer device processes the target quantum gate in the first quantum circuit C1 according to the pre-supported quantum instruction set to obtain the second quantum circuit C2. Figure 5 In the embodiment of the present application, the target quantum gate is a CNOT gate. By decomposing the more complex CNOT gate into an H gate and a CZ gate, the obtained second quantum circuit is easier to accurately implement than the first quantum circuit. Figure 5 In the figure, we can see that there is a situation where the H gate acts on a stable state quantum bit.

[0122] In addition, since simple single-bit quantum gates are obtained by decomposing complex quantum gates, and related operations are performed on these simple single-bit quantum gates in subsequent processes, the quantum circuit optimization method provided in the present application can adapt to most quantum circuits and has good universality.

[0123] In this way, the target quantum gate is decomposed into basic quantum gates in the pre-supported quantum instruction set through the quantum instruction set, and the complex quantum gate operations are converted into a combination of basic quantum gates so that they can be implemented on existing quantum hardware, while improving the efficiency of quantum computing and having good universality.

[0124] See also Fig.11 In some embodiments, step 013 (delaying the single-bit quantum gate in the second quantum circuit according to the barrier gate to obtain the first optimized quantum circuit) includes:

[0125] 0131: Postpone the single-bit quantum gate to the nearest two-bit quantum gate;

[0126] 0132: Add a barrier gate before the single-bit quantum gate located in front of the nearest two-bit quantum gate to obtain the first optimized quantum circuit.

[0127] In some embodiments, the defer module is used to defer the single-bit quantum gate to the nearest two-bit quantum gate. The adding module is also used to add a barrier gate before the single-bit quantum gate located before the nearest two-bit quantum gate to obtain a first optimized quantum circuit.

[0128] In some embodiments, the processor is further configured to postpone the single-bit quantum gate to before the nearest two-bit quantum gate, and add a barrier gate before the single-bit quantum gate located before the nearest two-bit quantum gate, to obtain a first optimized quantum circuit.

[0129] Specifically, a single-qubit quantum gate is a basic building block in quantum computing, which is a quantum logic gate that operates on a single quantum bit.

[0130] A two-qubit quantum gate is a quantum logic gate that operates on two quantum bits simultaneously in quantum computing.

[0131] The computer device postpones the single-bit quantum gate to the nearest two-bit quantum gate, and the nearest two-bit quantum gate is used to indicate the first two-bit quantum gate after the single-bit quantum gate in the second quantum circuit that acts on the same quantum bit as the single-bit quantum gate. Next, the computer device adds a barrier gate before the single-bit quantum gate located before the nearest two-bit quantum gate to obtain the first optimized quantum circuit. In this way, by postponing the single-bit quantum gate to the nearest two-bit quantum gate, the time for the quantum bit to enter the superposition state is postponed as much as possible, so that the quantum bit only participates in the calculation when necessary, and prevents the influence of premature entry into the superposition state. In addition, by adding a barrier gate before the single-bit quantum gate located before the nearest two-bit quantum gate, the operation after the barrier gate is prevented from running prematurely, ensuring that some sub-circuits of the quantum circuit maintain a specific order or structure.

[0132] Continuing with the above example, the single-bit quantum gate is an H gate. In some embodiments, the single-bit quantum gate is not only an H gate, which is not limited here. The two-bit quantum gate is a CZ gate. In some embodiments, the two-bit quantum gate is not only a CZ gate, which is not limited here.

[0133] When running on a computer device, a qubit in the ground state, i.e., in the |0> state, is more stable than a qubit in the superposition state. Qubits in the superposition state are susceptible to noise such as quantum gate noise, decoherence of the qubit itself, and bit flipping, and the H gate in this embodiment is the key operation to convert the qubit from the stationary state to the superposition state.

[0134] Please refer to Figure 7 Therefore, the computer device postpones the H gate in the second quantum circuit C2 to the nearest CZ gate. The nearest CZ gate refers to the CZ gate that acts on the same quantum bit as the H gate after the H gate in the second quantum circuit C2. Then, the computer device adds a barrier gate P before the H gate located before the CZ gate to obtain the first optimized quantum circuit C3.

[0135] In this way, by postponing the H gate to the nearest CZ gate, the time for the quantum bit to enter the superposition state can be postponed as much as possible, so that the quantum bit only participates in the calculation when necessary, and prevents the influence of entering the superposition state too early. In addition, by adding a barrier gate P before the H gate located before the nearest CZ gate, the H gate operation after the barrier gate P is prevented from running in advance, ensuring that some sub-circuits of the quantum circuit maintain a specific order or structure.

[0136] See also Fig.12 In some embodiments, the optimization method further comprises:

[0137] 015: merging multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit;

[0138] 016: The single-bit quantum gates in the first optimized quantum circuit are sequentially embedded into the second optimized quantum circuit to obtain a third optimized quantum circuit.

[0139] In some embodiments, the merging module is used to merge multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit. The embedding module is used to sequentially embed the single-bit quantum gates in the first optimized quantum circuit into the second optimized quantum circuit to obtain a third optimized quantum circuit.

[0140] In some embodiments, the processor is further configured to merge multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit, and sequentially embed the single-bit quantum gates in the first optimized quantum circuit into the second optimized quantum circuit to obtain a third optimized quantum circuit.

[0141] Specifically, the computer device merges multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit, wherein the first barrier interval is used to indicate the quantum circuit between every two barrier gates in the first optimized quantum circuit, and the first starting barrier interval of the first optimized quantum circuit and the first ending barrier interval of the first optimized quantum circuit are respectively determined by a barrier gate. Then, the computer device sequentially embeds the single-bit quantum gates in the first optimized quantum circuit into the second optimized quantum circuit to obtain a third optimized quantum circuit.

[0142] Continuing with the above example, see Figure 7 , Fig.13 and Fig.14 , Fig.13 Optimize the quantum circuit for the second, Fig.14 For the third optimized quantum circuit, a plurality of first barrier intervals A are A1-A10.

[0143] The computer device merges multiple first barrier intervals A in the first optimized quantum circuit C3 to obtain a second optimized quantum circuit C4, wherein the first barrier interval A is used to indicate the quantum circuit between every two barrier gates P in the first optimized quantum circuit C3, and the first starting barrier interval A1 of the first optimized quantum circuit C3 and the first ending barrier interval A10 of the first optimized quantum circuit C3 are respectively determined by a barrier gate P. Next, the computer device sequentially embeds the single-bit quantum gates in the first optimized quantum circuit C3 into the second optimized quantum circuit C4 to obtain a third optimized quantum circuit C5.

[0144] In this way, by merging multiple first barrier intervals A in the first optimized quantum circuit C3, the depth of the quantum circuit is reduced and the overall performance of the quantum circuit is improved. In addition, the single-bit quantum gates in the first optimized quantum circuit C3 are sequentially embedded in the second optimized quantum circuit C4 to ensure that the obtained third optimized quantum circuit C5 is functionally equivalent to the first optimized quantum circuit C3.

[0145] See also Fig.15 In some embodiments, step 015 (merging multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit) includes:

[0146] 0151: using the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit;

[0147] 0152: Compare the second end barrier interval and the plurality of first barrier intervals to obtain a second optimized quantum circuit.

[0148] In some embodiments, the processing module is further configured to use the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit. The comparison module is configured to compare the second ending barrier interval with the plurality of first barrier intervals to obtain the second optimized quantum circuit.

[0149] In some embodiments, the processor is further configured to use the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit, and compare the second ending barrier interval with the plurality of first barrier intervals to obtain the second optimized quantum circuit.

[0150] Specifically, the second last barrier interval refers to the last barrier interval in the second optimized quantum circuit.

[0151] The computer device uses the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit. Then, the computer device compares the second ending barrier interval with the plurality of first barrier intervals to obtain the second optimized quantum circuit.

[0152] Continuing with the above example, see Figure 7 and Fig.13 , the computer device uses the first starting barrier interval A1 as the second final barrier interval of the second optimized quantum circuit C4. Then, the computer device compares the second final barrier interval with the plurality of first barrier intervals A to obtain the second optimized quantum circuit C4.

[0153] In this way, by comparing the second end barrier interval with the plurality of first barrier intervals A, it is determined whether the first barrier intervals A can be merged into the second end barrier interval, thereby achieving the effect of reducing the depth of the quantum circuit and improving the execution efficiency of the quantum circuit.

[0154] See also Fig.16 In some embodiments, step 0152 (comparing the second end barrier interval with the plurality of first barrier intervals to obtain a second optimized quantum circuit) includes:

[0155] 01521: Compare the two-bit quantum gate in the second last barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval;

[0156] 01522: When confirming that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval, the current two-bit quantum gate in the next first barrier interval is moved to the second last barrier interval to obtain a second optimized quantum circuit.

[0157] In some embodiments, the comparison module is further used to compare the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval. The movement module is used to move the current two-bit quantum gate in the next first barrier interval to the second end barrier interval when confirming that the current two-bit quantum gate in the next first barrier interval can be moved to the second end barrier interval to obtain a second optimized quantum circuit.

[0158] In some embodiments, the processor is further configured to compare the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval. When confirming that the current two-bit quantum gate in the next first barrier interval can be moved to the second end barrier interval, the current two-bit quantum gate in the next first barrier interval is moved to the second end barrier interval to obtain a second optimized quantum circuit.

[0159] Specifically, the computer device compares the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval, wherein the next first barrier interval is used to indicate the next first barrier interval in the first optimized quantum circuit that is located in the first barrier interval corresponding to the second end barrier interval. Then, when it is confirmed that the current two-bit quantum gate in the next first barrier interval can be moved to the second end barrier interval, the computer device moves the current two-bit quantum gate in the next first barrier interval to the second end barrier interval to obtain a second optimized quantum circuit.

[0160] Continuing with the above example, see Figure 7 and Fig.13 , the computer device compares the CZ gate in the second end barrier interval with the current CZ gate in the next first barrier interval A to confirm the movement of the current CZ gate in the next first barrier interval, wherein the next first barrier interval is used to indicate the next first barrier interval in the first barrier interval A corresponding to the second end barrier interval in the first optimized quantum circuit C3. Then, when it is confirmed that the current CZ gate in the next first barrier interval can be moved to the second end barrier interval, the computer device moves the current CZ gate in the next first barrier interval to the second end barrier interval to obtain the second optimized quantum circuit C4.

[0161] In this way, by comparing the CZ gate in the second end barrier interval with the current CZ gate in the next first barrier interval, it is checked whether the CZ gate in the next first barrier interval can be moved to the second end barrier interval without affecting the execution order and result of the circuit. In addition, the computer device moves the CZ gate in the next first barrier interval to the second end barrier interval, reducing the depth of the quantum circuit and improving the execution efficiency of the quantum circuit.

[0162] See also Fig.17 In some embodiments, step 01521 (comparing the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval) includes:

[0163] 015211: when the qubit acted by the current two-bit quantum gate in the next first barrier interval is inconsistent with the qubit acted by each two-bit quantum gate in the second last barrier interval, confirming that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval;

[0164] 015212: When at least one of the quantum bits acted upon by the current two-bit quantum gate in the next first barrier interval and the quantum bits acted upon by the two-bit quantum gate in the second last barrier interval is consistent, confirm that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval.

[0165] In some embodiments, the confirmation module is further used to confirm that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval when the quantum bit acted by the current two-bit quantum gate in the next first barrier interval is inconsistent with the quantum bit acted by each two-bit quantum gate in the second last barrier interval. The confirmation module is also used to confirm that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval when at least one of the quantum bits acted by the current two-bit quantum gate in the next first barrier interval and the quantum bits acted by the two-bit quantum gate in the second last barrier interval is consistent.

[0166] In some embodiments, the processor is further configured to confirm that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval when the quantum bit acted by the current two-bit quantum gate in the next first barrier interval is inconsistent with the quantum bit acted by each two-bit quantum gate in the second last barrier interval. And confirm that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval when at least one of the quantum bits acted by the current two-bit quantum gate in the next first barrier interval and the quantum bits acted by the two-bit quantum gate in the second last barrier interval is consistent.

[0167] Specifically, when the qubits acted by the current two-bit quantum gate in the next first barrier interval and the qubits acted by each two-bit quantum gate in the second last barrier interval are not consistent, the computer device confirms that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval. Then, when the qubits acted by the current two-bit quantum gate in the next first barrier interval and at least one of the qubits acted by the two-bit quantum gate in the second last barrier interval are consistent, the computer device confirms that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval. In this way, by judging the consistency of the qubits acted by the current two-bit quantum gate in the next first barrier interval and the qubits acted by each two-bit quantum gate in the second last barrier interval, it is confirmed that moving the two-bit quantum gate will not affect the correct execution of the quantum circuit. If the qubits acted by the current two-bit quantum gate in the next first barrier interval and the qubits acted by the two-bit quantum gate in the second last barrier interval are completely inconsistent, that is, no qubit is the same in the two intervals, then the computer device confirms that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval, performs the move operation, and obtains the optimized quantum circuit. If at least one of the quantum bits acted upon by the current two-bit quantum gate in the next first barrier interval and the quantum bit acted upon by the two-bit quantum gate in the second final barrier interval is consistent, then the computer device confirms that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second final barrier interval, keeping the current quantum circuit structure unchanged.

[0168] Continuing from the above example, see Figure 7 and Fig.13, when the qubit acted by the current CZ gate in the next first barrier interval is inconsistent with the qubit acted by each CZ gate in the second last barrier interval, the computer device confirms that the current CZ gate in the next first barrier interval can be moved to the second last barrier interval. Then, when at least one of the qubits acted by the current CZ gate in the next first barrier interval and the qubits acted by the two-bit quantum gate in the second last barrier interval is consistent, the computer device confirms that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval.

[0169] In this way, by judging the consistency of the quantum bit acted by the current CZ gate in the next first barrier interval and the quantum bit acted by each CZ gate in the second last barrier interval, it is confirmed that moving the CZ gate will not affect the correct execution of the quantum circuit. If the quantum bit acted by the current CZ gate in the next first barrier interval and the quantum bit acted by the CZ gate in the second last barrier interval are completely inconsistent, that is, no quantum bit is the same in the two intervals, then the computer device confirms that the current CZ gate in the next first barrier interval can be moved to the second last barrier interval, and performs the moving operation to obtain the optimized quantum circuit. If at least one of the quantum bits acted by the current CZ gate in the next first barrier interval and the quantum bits acted by the CZ gate in the second last barrier interval are consistent, then the computer device confirms that the current CZ gate in the next first barrier interval cannot be moved to the second last barrier interval, and keeps the current quantum circuit structure unchanged.

[0170] See also Fig.18 In some embodiments, step 0151 (using the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit) includes:

[0171] 01511: When the next first barrier interval includes a two-bit quantum gate, the next first barrier interval is used as the second last barrier interval of the second optimized quantum circuit.

[0172] In some embodiments, the processing module is configured to use the next first barrier interval as the second last barrier interval of the second optimized quantum circuit when the next first barrier interval includes a two-bit quantum gate.

[0173] In some embodiments, the processor is further configured to use the next first barrier interval as a second last barrier interval of the second optimized quantum circuit when the next first barrier interval includes a two-bit quantum gate.

[0174] Specifically, when the next first barrier interval includes a two-bit quantum gate, the next first barrier interval is used as the second last barrier interval of the second optimized quantum circuit.

[0175] Continuing with the above example, see Figure 7 and Fig.13 , when the next first barrier interval includes the CZ gate, the next first barrier interval is used as the second end barrier interval of the second optimized quantum circuit C4.

[0176] In this way, in the first optimized quantum circuit C3, the next barrier interval including the CZ gate is found, and this interval is called the next first barrier interval. In addition, this next first barrier interval is used as the second end barrier interval of the second optimized quantum circuit, which means that the end position of the second optimized quantum circuit C4 is set to this interval including the CZ gate, and the remaining first barrier interval A in the first optimized quantum circuit C3 is subsequently merged using this interval including the CZ gate.

[0177] See also Fig.19 In some embodiments, the method further comprises:

[0178] 01523: When the next first barrier interval does not include a two-bit quantum gate, compare the second last barrier interval with the plurality of first barrier intervals to obtain a second optimized quantum circuit.

[0179] In some embodiments, the comparison module is further configured to compare the second last barrier interval with the plurality of first barrier intervals to obtain a second optimized quantum circuit when the next first barrier interval does not include a two-bit quantum gate.

[0180] In some embodiments, the processor is further configured to compare the second final barrier interval with the plurality of first barrier intervals to obtain a second optimized quantum circuit when the next first barrier interval does not include a two-bit quantum gate.

[0181] Specifically, when the next first barrier interval does not include a two-bit quantum gate, the computer device compares the second final barrier interval with the plurality of first barrier intervals to obtain a second optimized quantum circuit.

[0182] Continuing with the above example, see Figure 7 and Fig.13 When the next first barrier interval does not include the CZ gate, the computer device compares the second end barrier interval with the plurality of first barrier intervals to obtain a second optimized quantum circuit C4.

[0183] In this way, if the next first barrier interval does not include the CZ gate, that is, the CZ gates of the next first barrier interval are all merged into the second final barrier interval, then the second final barrier interval is still used as the new second final barrier interval, and the remaining first barrier intervals A in the first optimized quantum circuit C3 are merged.

[0184] Continuing with the above example, the merging process of the first optimized quantum circuit is fully described below:

[0185] See also Figure 7 and Fig.13 , Figure 7 The first optimized quantum circuit C3 is divided into 10 first barrier intervals, namely A1-A10. First, the first starting barrier interval A1 is used as the second end barrier interval of the second optimized quantum circuit C4, then the next first barrier interval at this time is A2. It can be seen that there is no CZ gate, that is, a two-bit quantum gate, in the second end barrier interval at this time. Therefore, there is no CZ gate in A2 and the CZ gate in A1 acting on the same quantum bit, so it can be determined that the CZ gate in A2 can be moved to the second end barrier interval. It can be found that there is no two-bit quantum gate in A2, so the second end barrier interval at this time is still the second end barrier interval just now.

[0186] Then, compare the next first barrier interval A3 of A2 with the second end barrier interval, and you can find that there is a quantum bit q24 in the quantum bit acted by the CZ gate of A3 at this time, and the quantum bit q24 is also acted by the CZ gate in the second end barrier interval. It is judged that this CZ gate cannot be moved to the second end barrier interval. Because A3 contains only one CZ gate, after the judgment of the CZ gate is completed, it can be judged whether to use this first barrier interval A3 as the new second end barrier interval, or to keep the second end barrier interval unchanged. It can be found that A3 also includes a CZ gate, so at this time, A3 that also includes a CZ gate should be used as the new second end barrier interval.

[0187] The merging process of the first barrier interval A4 is the same as that of A3 and will not be described again here.

[0188] After the first barrier interval A4 is merged, the second end barrier interval is now the second barrier interval B2, including two CZ gates. At this time, the first barrier interval A5 is merged, and the quantum bits acted by the CZ gate in A5 are compared with the quantum bits acted by the two CZ gates in the second end barrier interval in turn. It can be found that the quantum bit q19 used by the CZ gate in A5 is also acted on by the CZ gate in the second end barrier interval. It is judged whether the CZ gate in A5 that acts on q19 and q12 can be merged into the second end barrier interval. Assuming that A5 includes more than one CZ gate, after the judgment of the CZ gate that acts on q19 and q12 is completed, it is necessary to compare the quantum bits acted by the remaining CZ gates in A5 with the quantum bits acted by the CZ gates in the second end barrier interval. Determine whether the remaining CZ gates in A5 can be merged into the second end interval, until all CZ gates, that is, two-bit quantum gates in A5 are judged, and then determine whether to use this first barrier interval A5 as the new second end barrier interval, or to keep the second end barrier interval unchanged.

[0189] The merging process of A6, A7, A8, A9 and A10 is the same as the process of A1-A5 described above, which will not be repeated here. The final second optimized quantum circuit is as follows Fig.13 shown.

[0190] The present application also provides a computer-readable storage medium containing a computer program. When the computer program is executed by one or more processors, the one or more processors execute the quantum circuit optimization method of the present application.

[0191] It is understood that a computer program includes computer program code. The computer program code may be in source code form, object code form, executable file or some intermediate form. Computer readable storage media may include: any entity or device capable of carrying computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution medium.

[0192] In the description of this specification, the descriptions with reference to the terms "specifically", "further", "particularly", "understandably", etc. are intended to mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not intended to refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0193] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0194] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for optimizing quantum circuits based on timing alignment, characterized in that: The method comprises: Determine a first quantum circuit according to the dependency relationship of quantum gates in the quantum circuit; Processing a target quantum gate in the first quantum circuit to obtain a second quantum circuit; A first optimized quantum circuit is obtained by postponing the single-bit quantum gate in the second quantum circuit according to the barrier gate, so as to optimize the quantum circuit, wherein the barrier gate is configured to prevent the quantum gate after the barrier gate in the quantum circuit from running in advance.

2. The optimization method according to claim 1, characterized in that: Determining the first quantum circuit according to the dependency relationship of the quantum gates in the quantum circuit includes: Determine the parallel quantum gates that can be operated in parallel in the quantum circuit according to the dependency relationship; The execution sequence of quantum gates in the quantum circuit is rearranged according to the parallel quantum gates to obtain the first quantum circuit.

3. The optimization method according to claim 1, characterized in that: The method further comprises: The functional equivalence of the first quantum circuit is verified according to the simulation test to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

4. The optimization method according to claim 1, characterized in that: The step of processing the target quantum gate in the first quantum circuit to obtain the second quantum circuit includes: The target quantum gate is processed according to the pre-supported quantum instruction set to obtain the second quantum circuit.

5. The optimization method according to claim 1, characterized in that: The step of postponing the single-bit quantum gate in the second quantum circuit according to the barrier gate to obtain the first optimized quantum circuit includes: Postponing the single-bit quantum gate to before the nearest two-bit quantum gate, the nearest two-bit quantum gate being used to indicate the first two-bit quantum gate after the single-bit quantum gate in the second quantum circuit that acts on the same quantum bit as the single-bit quantum gate; The barrier gate is added before the single-bit quantum gate located before the nearest two-bit quantum gate to obtain the first optimized quantum circuit.

6. The optimization method according to claim 1, characterized in that: The optimization method further comprises: Merging a plurality of first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit, wherein the first barrier interval is used to indicate a quantum circuit between every two barrier gates in the first optimized quantum circuit, and a first starting barrier interval of the first optimized quantum circuit and a first ending barrier interval of the first optimized quantum circuit are respectively determined by one of the barrier gates; The single-bit quantum gates in the first optimized quantum circuit are sequentially embedded in the second optimized quantum circuit to obtain a third optimized quantum circuit.

7. The optimization method according to claim 6, characterized in that: The step of merging the plurality of first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit includes: Using the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit; The second end barrier interval is compared with a plurality of the first barrier intervals to obtain a second optimized quantum circuit.

8. The optimization method according to claim 7, characterized in that: The step of comparing the second end barrier interval with a plurality of the first barrier intervals to obtain a second optimized quantum circuit comprises: Comparing the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval, wherein the next first barrier interval is used to indicate the next first barrier interval in the first optimized quantum circuit that is located in the first barrier interval corresponding to the second end barrier interval; When it is confirmed that the current two-bit quantum gate in the next first barrier interval can be moved to the second end barrier interval, the current two-bit quantum gate in the next first barrier interval is moved to the second end barrier interval to obtain the second optimized quantum circuit.

9. The optimization method according to claim 8, characterized in that: The comparing the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval includes: When the qubit acted by the current two-bit quantum gate in the next first barrier interval is inconsistent with the qubit acted by each two-bit quantum gate in the second last barrier interval, confirming that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval; When at least one of the quantum bits acted by the current two-bit quantum gate in the next first barrier interval and the quantum bits acted by the two-bit quantum gate in the second final barrier interval is consistent, it is confirmed that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second final barrier interval.

10. The optimization method according to claim 8, characterized in that: The step of using the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit comprises: In a case where the next first barrier interval includes a two-bit quantum gate, the next first barrier interval is used as the second last barrier interval of the second optimized quantum circuit.

11. The optimization method according to claim 8, characterized in that: The method further comprises: In a case where the next first barrier interval does not include a two-bit quantum gate, the second end barrier interval is compared with a plurality of the first barrier intervals to obtain a second optimized quantum circuit.

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