Quantum circuit depth optimization method based on heuristic SAT scanning and computer equipment

Abstract

The invention discloses a quantum circuit deep optimization method based on heuristic SAT scanning, computer equipment and a computer readable storage medium. The method comprises the steps that in response to user input, scanning parameters of the quantum circuit are set, and the scanning parameters comprise the number of scanning times of the quantum circuit; and under the condition that the current scanning times of the quantum circuit are smaller than the scanning times of the quantum circuit, processing the quantum circuit according to the scanning parameters, a heuristic sub-circuit scanning method, a cost evaluation method and a Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit so as to realize optimization of the quantum circuit. According to the method, a quantum circuit is processed through a heuristic sub-circuit scanning method, a cost evaluation method and a Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit. Therefore, through the method, the number of the quantum gates is reduced on the premise that the circuit function is not sacrificed, so that the efficiency and the performance of the quantum circuit are improved, and the performability of the quantum circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of quantum computing, and more specifically, to a quantum circuit deep optimization method based on heuristic SAT scanning, a computer device, and a computer-readable storage medium. Background Art

[0002] Quantum computers based on the principles of quantum mechanics can represent multiple states simultaneously by utilizing the superposition and entanglement properties of quantum bits, thereby realizing the ability to process large amounts of data in parallel. However, quantum computers are still in the development stage and face many technical challenges. For example, the quantum hardware of quantum computers has specific limitations, and compilation operations are needed to help quantum circuits adapt to these limitations to ensure that the algorithm can be correctly executed on specific quantum hardware. In addition, quantum computers are limited by their own performance and have strict restrictions on the depth index of the executed quantum circuits. During the compilation process of quantum circuits, a large number of exchange gates are usually introduced near the control NOT gate. In the subsequent execution process, a exchange gate will be decomposed into multiple control NOT gates, thereby increasing the number of quantum gates in the quantum circuit, resulting in the degradation of the depth index of the quantum circuit and affecting the executableness of the quantum circuit. Summary of the invention

[0003] The present application provides a quantum circuit deep optimization method based on heuristic SAT scanning, a computer device, and a computer-readable storage medium.

[0004] The embodiment of the present application provides a quantum circuit deep optimization method based on heuristic SAT scanning, characterized in that the method includes:

[0005] In response to user input, setting scanning parameters of the quantum circuit, the scanning parameters including the number of quantum circuit scans;

[0006] When the current scan number of the quantum circuit is less than the scan number of the quantum circuit, the quantum circuit is processed according to the scan parameter, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit, so as to optimize the quantum circuit.

[0007] Thus, the method of the present application processes the quantum circuit through the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solving algorithm to obtain the Boolean quantum circuit. Thus, through this method, the number of quantum gates is reduced without sacrificing the circuit function, thereby improving the efficiency and performance of the quantum circuit and enhancing the executability of the quantum circuit.

[0008] In certain embodiments, the step of processing the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, the cost evaluation method, and the Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit to optimize the quantum circuit includes:

[0009] When the current scan number is less than the quantum circuit scan number, performing scan evaluation processing on the quantum circuit according to the scan parameter, the heuristic subcircuit scan method and the cost evaluation method to obtain an optimal subcircuit;

[0010] When the optimal subcircuit can be obtained, optimizing the optimal subcircuit according to the Boolean satisfiability solving algorithm to obtain a Boolean subcircuit;

[0011] The subcircuit corresponding to the optimal subcircuit in the quantum circuit is replaced with the Boolean subcircuit to obtain the Boolean quantum circuit, and the quantum circuit is replaced according to the Boolean quantum circuit.

[0012] In this way, when the current number of scans is less than the number of quantum circuit scans, the present application performs scan evaluation processing on the quantum circuit according to the scan parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain the optimal subcircuit. Then, when the optimal subcircuit can be obtained, the present application optimizes the optimal subcircuit according to the Boolean satisfiability solution algorithm to obtain a Boolean subcircuit. Finally, the present application replaces the subcircuit corresponding to the optimal subcircuit in the quantum circuit with a Boolean subcircuit to obtain a Boolean quantum circuit, and replaces the quantum circuit according to the Boolean quantum circuit. In this way, the entanglement and operational complexity between quantum bits can be reduced, thereby improving the overall execution efficiency of the quantum circuit. Moreover, by using the obtained Boolean quantum circuit as a new quantum circuit and performing multiple iterations, the execution efficiency of the quantum circuit can be maximized.

[0013] In some embodiments, the scanning and evaluating the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain the optimal subcircuit includes:

[0014] When the current scan number is less than the quantum circuit scan number, the maximum evaluation value is set to 0;

[0015] A preselected quantum gate in the quantum circuit is scanned and evaluated according to the scanning parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain an optimal subcircuit, wherein the preselected quantum gate is a predetermined 2-bit quantum gate.

[0016] In this way, when the current number of scans is less than the number of quantum circuit scans, the present application sets the maximum evaluation value to 0. Next, the present application performs a scan evaluation process on the pre-selected quantum gates in the quantum circuit according to the scan parameters, the heuristic sub-circuit scanning method and the cost evaluation method to obtain the optimal sub-circuit, and the pre-selected quantum gate is a predetermined 2-bit quantum gate. In this way, by evaluating the pre-selected quantum gates, those parts of the quantum circuit that have the greatest impact on the performance of the quantum circuit can be identified and optimized, thereby improving the performance of the entire quantum circuit. The sub-circuits of the quantum circuit are deeply optimized by the heuristic sub-circuit scanning method, and the sorting is used as the selection basis for the SAT solver to perform deep optimization.

[0017] In some embodiments, the scanning parameters include a maximum number of bits and a number of test cases, and the scanning and evaluating process is performed on the preselected quantum gates in the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, and the cost evaluation method to obtain an optimal subcircuit, including:

[0018] Constructing a first subcircuit and a secondary neighbor set, wherein the first subcircuit includes the preselected quantum gate, and the secondary neighbor set is an empty set;

[0019] constructing a first neighbor set according to the first subcircuit;

[0020] Performing a removal process on the first adjacent set according to the secondary adjacent set to obtain a second adjacent set;

[0021] When the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, the 2-bit quantum gates in the second adjacent set are added to the first subcircuit, and the second subcircuit is obtained by adding the 2-bit quantum gates in the second adjacent set to the first subcircuit, and each of the 2-bit quantum gates includes 2 quantum bits;

[0022] The potential of the second neighbor set is determined to obtain the optimal sub-circuit according to the potential of the second neighbor set and the second sub-circuit.

[0023] In this way, the present application constructs a first subcircuit and a secondary adjacent set, the first subcircuit includes a preselected quantum gate, and the secondary adjacent set is an empty set. The present application then constructs a first adjacent set based on the first subcircuit. Next, the present application removes the first adjacent set according to the secondary adjacent set to obtain a second adjacent set. Then, when the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, the present application adds the 2-bit quantum gate in the second adjacent set to the first subcircuit, and the second subcircuit is obtained by adding the 2-bit quantum gate in the second adjacent set to the first subcircuit, and each 2-bit quantum gate includes 2 quantum bits. Finally, the present application determines the potential of the second adjacent set to obtain the optimal subcircuit based on the potential of the second adjacent set and the second subcircuit. In this way, by gradually expanding the subcircuit and evaluating the impact of each step, the complexity and performance of the circuit can be controlled.

[0024] In some embodiments, determining the potential of the second neighboring set to obtain the optimal subcircuit according to the potential of the second neighboring set includes:

[0025] When the potential of the second neighboring set is not 0, constructing a next first neighboring set according to the second subcircuit;

[0026] Obtaining a next secondary adjacent set according to the union of the second adjacent set and the secondary adjacent set;

[0027] Performing removal processing on the next first adjacent set according to the next secondary adjacent set to obtain a next second adjacent set;

[0028] When the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, the 2-bit quantum gates in the next second adjacent set are added to the first subcircuit, and the second subcircuit is obtained by adding the 2-bit quantum gates in the next second adjacent set to the first subcircuit, and each of the 2-bit quantum gates includes 2 quantum bits;

[0029] The potential of the second neighbor set is determined to obtain the optimal sub-circuit according to the potential of the second neighbor set.

[0030] In this way, when the potential of the second adjacent set is not 0, the present application constructs the next first adjacent set according to the second subcircuit. The present application then obtains the next secondary adjacent set according to the union of the second adjacent set and the secondary adjacent set. Then, the present application removes the next first adjacent set according to the next secondary adjacent set to obtain the next second adjacent set. Then, when the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, the present application adds the 2-bit quantum gate in the next second adjacent set to the first subcircuit, and the second subcircuit is obtained by adding the 2-bit quantum gate in the next second adjacent set to the first subcircuit, and each 2-bit quantum gate includes 2 quantum bits. Finally, the present application determines the potential of the second adjacent set to obtain the optimal subcircuit according to the potential of the second adjacent set. In this way, if the potential of the second adjacent set is not 0, it means that these quantum gates need to continue to be optimized to obtain the optimal subcircuit. And by continuously updating the adjacent set, it is ensured that the same quantum gate will not be repeatedly optimized during the optimization process, thereby improving efficiency. In addition, through such an iterative process, the complexity and performance of the circuit can be controlled.

[0031] In some embodiments, determining the potential of the second neighboring set to obtain the optimal subcircuit according to the potential of the second neighboring set includes:

[0032] When the potential of the second adjacent set is 0, the second subcircuit and the number of test cases are evaluated according to the cost evaluation method to obtain the optimal subcircuit.

[0033] Thus, when the potential of the second adjacent set is 0, the present application evaluates the second subcircuit and the number of test cases according to the cost evaluation method to obtain the optimal subcircuit. Thus, when the potential of the second adjacent set is 0, it means that further iterations may not bring better optimization results. Moreover, the cost evaluation method can obtain the deep redundancy of the second subcircuit and quantify the performance of the second subcircuit.

[0034] In some implementations, the evaluating the second sub-circuit and the number of test cases according to the cost evaluation method to obtain the optimal sub-circuit includes:

[0035] Evaluate the second subcircuit and the number of test cases according to the cost evaluation method to obtain a current evaluation value;

[0036] comparing the current evaluation value with the maximum evaluation value;

[0037] In the case that the current evaluation value is greater than the maximum evaluation value, the current evaluation value is used as the maximum evaluation value to update the maximum evaluation value, and the second sub-circuit is used as the optimal sub-circuit.

[0038] In this way, the present application evaluates the second subcircuit and the number of test cases according to the cost evaluation method to obtain the current evaluation value. Next, the present application compares the current evaluation value and the maximum evaluation value. Finally, when the current evaluation value is greater than the maximum evaluation value, the present application uses the current evaluation value as the maximum evaluation value to update the maximum evaluation value and uses the second subcircuit as the optimal subcircuit. In this way, the deep redundancy of the second subcircuit is obtained through the cost evaluation method, and the performance of the second subcircuit is quantified. In addition, by continuously comparing and updating the maximum evaluation value, the method of the present application can ensure that the optimal subcircuit with the best performance is found, thereby optimizing the performance of the entire quantum circuit.

[0039] In some implementations, the step of evaluating the second sub-circuit and the number of test cases according to the cost evaluation method to obtain a current evaluation value includes:

[0040] Decomposing the second subcircuit to obtain a test subcircuit;

[0041] When the current test number of the quantum circuit is less than the number of test cases, applying a test quantum state randomly selected from a computational base state to the test subcircuit to obtain a test inner product, and obtaining a maximum test inner product according to the test inner product;

[0042] The current evaluation value is obtained according to the maximum test inner product.

[0043] In this way, the present application decomposes the second subcircuit to obtain a test subcircuit. Then, when the current number of tests of the quantum circuit is less than the number of test cases, the present application applies the test quantum state randomly selected from the computational basis state to the test subcircuit to obtain a test inner product, and obtains the maximum test inner product based on the test inner product. Then, the present application obtains the current evaluation value based on the maximum test inner product. In this way, the second subcircuit is simplified or decomposed into smaller parts through decomposition processing to facilitate testing and evaluation. And randomly selecting test quantum states from the computational basis state can simulate different input situations. By comparing different test inner products, the best performance of the subcircuit in all test cases can be found, and the test inner product can reflect the change of the quantum state.

[0044] In some embodiments, when the current test number of the quantum circuit is less than the number of test cases, applying the randomly selected test quantum state to the test subcircuit to obtain a test inner product, and obtaining the maximum test inner product according to the test inner product, comprises:

[0045] Constructing a test inner product set, wherein the test inner product set is used to store the test inner product;

[0046] Applying the test quantum state to the test subcircuit to obtain the test inner product, and storing the test inner product in the test inner product set;

[0047] The maximum test inner product is obtained from the test inner product set.

[0048] In this way, the present application constructs a test inner product set, and the test inner product set is used to store the test inner product. Then, the present application applies the test quantum state to the test subcircuit to obtain the test inner product, and stores the test inner product in the test inner product set. Finally, the present application obtains the maximum test inner product from the test inner product set. In this way, by constructing a test inner product set and obtaining the maximum test inner product therefrom, the performance of different subcircuits in a quantum circuit can be systematically evaluated and compared.

[0049] In some embodiments, applying the test quantum state to the test subcircuit to obtain the test inner product, and storing the test inner product in the test inner product set, comprises:

[0050] When the current test number is less than the number of test cases, the test number is increased by 1;

[0051] Randomly select a quantum state from the calculated base state as the test quantum state;

[0052] Applying the test subcircuit to the test quantum state to obtain an output quantum state;

[0053] Obtaining the test inner product according to the test quantum state and the output quantum state;

[0054] The test inner product is stored in the test inner product set.

[0055] In this way, when the current number of tests is less than the number of test cases, the present application adds 1 to the number of tests. Next, the present application randomly selects a quantum state from the calculation base state as the test quantum state. Then, the present application acts on the test quantum state to obtain the output quantum state. The present application then obtains the test inner product based on the test quantum state and the output quantum state. Finally, the present application stores the test inner product in a test inner product set. In this way, when the number of tests is less than the number of test cases, the present application performs iterative testing and calculates the test inner product to systematically evaluate the performance of the test subcircuit.

[0056] In some embodiments, obtaining the current evaluation value according to the maximum test inner product includes:

[0057] Calculating a test depth of the test sub-circuit;

[0058] The product of the preset parameter and the average number of times is used as the exponent of the Euler number to obtain a first exponent, wherein the average number of times the quantum gate in the test subcircuit is recompiled by the SAT solver;

[0059] A current evaluation value is obtained according to the first index, the maximum test inner product and the test depth.

[0060] In this way, the present application calculates the test depth of the test subcircuit. Next, the present application uses the product of the preset parameter and the average number of times as the exponent of the Euler number to obtain a first exponent, and the average number of times is the average number of times the quantum gate in the test subcircuit has been recompiled by the SAT solver. Then, the present application obtains the current evaluation value based on the first exponent, the maximum test inner product and the test depth. In this way, by calculating the test depth and the first exponent, and combining the maximum test inner product, a comprehensive and quantified current evaluation value is obtained for evaluating and optimizing the subcircuit in the quantum circuit.

[0061] In some embodiments, the step of processing the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, the cost evaluation method, and the Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit to optimize the quantum circuit includes:

[0062] When the current scanning number is greater than or equal to the quantum circuit scanning number, the Boolean quantum circuit is output to achieve optimization of the quantum circuit.

[0063] In this way, when the current scanning number is greater than or equal to the quantum circuit scanning number, the present application outputs a Boolean quantum circuit to optimize the quantum circuit. In this way, the Boolean quantum circuit obtained by multiple iterations is input, and the Boolean quantum circuit has good execution efficiency.

[0064] An embodiment of the present application provides a computer device, which includes a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the above-mentioned deep optimization method is implemented.

[0065] An embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium memory stores a computer program, and when the computer program is executed by one or more processors, the above-mentioned deep optimization method is implemented.

[0066] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0068] Figure 1 It is one of the flow charts of the method of the implementation mode of the present application;

[0069] Figure 2 is a schematic diagram of an example quantum circuit according to an embodiment of the present application;

[0070] Figure 3 This is the second flow chart of the method of the implementation mode of the present application;

[0071] Figure 4 This is the third flow chart of the method of the implementation mode of the present application;

[0072] Figure 5 This is the fourth flow chart of the method of the implementation mode of the present application;

[0073] Figure 6 This is the fifth flow chart of the method of the implementation mode of the present application;

[0074] Figure 7 This is the sixth flow chart of the method of the implementation mode of the present application;

[0075] Figure 8 This is the seventh flow chart of the method of the implementation mode of the present application;

[0076] Fig. 9 This is the eighth flow chart of the method of the implementation mode of the present application;

[0077] Fig.10 This is the ninth flow chart of the method of the implementation mode of the present application;

[0078] Fig.11 This is the tenth flowchart of the method of the implementation mode of the present application;

[0079] Fig.12 This is the eleventh flow chart of the method of the implementation mode of the present application;

[0080] Fig.13 This is the twelfth flow chart of the method of the implementation mode of the present application;

[0081] Fig.14 is a schematic diagram of an example input circuit of an embodiment of the present application;

[0082] Fig.15 is a schematic diagram of an example output circuit of an embodiment of the present application;

[0083] Fig.16 This is the fifteenth flow chart of the method of the implementation method of the present application. DETAILED DESCRIPTION

[0084] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application, and cannot be understood as limiting the embodiments of the present application.

[0085] Quantum computers based on the principles of quantum mechanics use the superposition and entanglement properties of quantum bits to represent multiple states simultaneously, thereby achieving the ability to process large amounts of data in parallel.

[0086] However, quantum computers are still in the development stage and face many technical challenges. For example, quantum computers have specific limitations on their quantum hardware due to the complexity of their physical implementation. In order to ensure that quantum algorithms can be executed correctly and efficiently on these specific hardware, quantum circuits need to be adapted and optimized through the quantum compilation process. Quantum compilation is the process of converting high-level quantum algorithms into low-level physical operations that can be executed on specific quantum hardware. In addition, quantum computers are limited by their own performance, such as the physical properties of quantum bits, the implementation accuracy of quantum gates, the connectivity between quantum bits, and the environmental noise of quantum computers. There are strict restrictions on the depth indicators of the executed quantum circuits. The depth of quantum circuits refers to the length of the sequence of quantum gate operations, which directly affects the execution time and resource consumption of quantum computing.

[0087] However, during the compilation of quantum circuits, a large number of swap gates are usually introduced near the control NOT gates. In the subsequent execution process, a swap gate will be decomposed into multiple control NOT gates. In addition, in quantum circuits, there are more interactions between CNOT gates in some areas, and fewer interactions with quantum bit gates in other areas. These control NOT gates are concentrated in the quantum circuit, increasing the depth of the circuit. This not only increases the number of quantum gates in the quantum circuit, but also leads to the degradation of the depth index of the quantum circuit, affecting the executableness of the quantum circuit.

[0088] Based on the above questions, please refer to Figure 1 The embodiment of the present application provides a quantum circuit deep optimization method based on heuristic SAT scanning, characterized in that the method includes:

[0089] 011: In response to user input, setting scanning parameters of the quantum circuit;

[0090] 012: When the current scan number of the quantum circuit is less than the scan number of the quantum circuit, the quantum circuit is processed according to the scan parameters, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit to achieve the optimization of the quantum circuit.

[0091] The embodiment of the present application also provides a computer device, including a memory and a processor. The method of the embodiment of the present application can be implemented by the computer device of the embodiment of the present application. Specifically, a computer program is stored in the memory, and the processor is used to set the scanning parameters of the quantum circuit in response to user input. And when the current scanning number of the quantum circuit is less than the scanning number of the quantum circuit, the quantum circuit is processed according to the scanning parameters, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit, so as to achieve the optimization of the quantum circuit.

[0092] The embodiment of the present application also provides a deep optimization device. The method of the embodiment of the present application can be implemented by the deep optimization device of the embodiment of the present application. Specifically, the deep optimization device includes a setting module and a processing module. The setting module is used to set the scanning parameters of the quantum circuit in response to user input. The processing module is used to process the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit when the current scanning number of the quantum circuit is less than the scanning number of the quantum circuit, so as to optimize the quantum circuit.

[0093] It should be noted that in the embodiments of the present application, a quantum bit is a basic unit for storing and processing data in a quantum computer. A quantum program implements a specific calculation process by performing corresponding quantum gate operations on a quantum bit.

[0094] Quantum gates are the basic computing units in quantum computing. The effect of quantum gates on quantum bits is achieved by changing the quantum state vector of the quantum bit. According to the number of quantum bits acted on, quantum gates can be divided into single-qubit gates and two-qubit gates. Single-qubit gates only act on a specific quantum bit and can only change the state of that quantum bit. Two-qubit gates act on two quantum bits and can change the states of the quantum bits they act on. In the following, G(i) is used to represent a general single-qubit gate G acting on the i-th quantum bit, G(i,j) is used to represent a general two-qubit gate G acting on the i and j quantum bits, and |G| is used to represent the number of quantum bits acted on by the quantum gate G. The exchange gate used in the embodiment of the present application, that is, the SWAP gate, is a special two-qubit gate that acts on the i-th quantum bit and the j-th quantum bit, usually represented by SWAP(i,j).

[0095] A quantum circuit is a commonly used method for describing quantum programs, usually consisting of quantum bits and a series of quantum gates. A subcircuit is a component of a quantum circuit and is a relatively independent circuit unit that can perform specific quantum operations or algorithms. Figure 2 , Figure 2 This is an example quantum circuit, which contains two quantum bits q0 and q1. Each line represents the corresponding quantum bit, and module A represents G A (q0), module B represents a two-bit CNOT gate G B (q0,q1) or CNOT(q0,q1), module C represents SWAP(q0,q1).

[0096] The depth of a quantum circuit is an important indicator of a quantum circuit, and the depth is determined by the specific layout of quantum gates in the quantum circuit. In some embodiments, the techniques for calculating the depth of a quantum circuit include general techniques such as direct counting method, hierarchical analysis method, and dependency graph method. The embodiments of the present application use the direct counting method to calculate the depth of a quantum circuit.

[0097] Specifically, the number of quantum circuit scans is determined by the user, which indicates the number of times the quantum circuit is repeatedly executed when executing the algorithm.

[0098] When a quantum circuit having a large number of clustered two-bit quantum gates is obtained after compiling the quantum circuit, in response to user input, the computer device sets a scan parameter of the quantum circuit, wherein the scan parameter includes the number of times the quantum circuit is scanned.

[0099] Then, when the current scan number of the quantum circuit is less than the scan number of the quantum circuit, the quantum circuit is processed according to the scan parameters, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit to achieve the optimization of the quantum circuit.

[0100] In summary, in the quantum circuit deep optimization method and computer device based on heuristic SAT scanning of the implementation mode of the present application, for the quantum circuit with a large number of clustered two-bit quantum gates obtained after compilation, the method of the present application processes the quantum circuit through the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solution algorithm to obtain a Boolean quantum circuit. In this way, through this method, the number of quantum gates is reduced without sacrificing the circuit function, thereby improving the efficiency and performance of the quantum circuit and enhancing the executability of the quantum circuit.

[0101] See also Figure 3In some embodiments, step 012 (processing the quantum circuit according to the scanning parameter, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit to optimize the quantum circuit) includes:

[0102] 021: When the current scan number is less than the quantum circuit scan number, the quantum circuit is scanned and evaluated according to the scan parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain the optimal subcircuit;

[0103] 022: When the optimal subcircuit can be obtained, the optimal subcircuit is optimized according to the Boolean satisfiability solution algorithm to obtain a Boolean subcircuit;

[0104] 023: Replace the subcircuit corresponding to the optimal subcircuit in the quantum circuit with a Boolean subcircuit to obtain a Boolean quantum circuit, and replace the quantum circuit according to the Boolean quantum circuit.

[0105] In some embodiments, the scanning evaluation module is used to scan and evaluate the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method and the cost evaluation method when the current scanning number is less than the quantum circuit scanning number, so as to obtain the optimal subcircuit. The optimization module is used to optimize the optimal subcircuit according to the Boolean satisfiability solution algorithm to obtain a Boolean subcircuit when the optimal subcircuit can be obtained. The replacement module is used to replace the subcircuit corresponding to the optimal subcircuit in the quantum circuit with a Boolean subcircuit to obtain a Boolean quantum circuit, and replace the quantum circuit according to the Boolean quantum circuit.

[0106] In some embodiments, the processor is further configured to scan and evaluate the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, and the cost evaluation method to obtain the optimal subcircuit when the current scanning number is less than the quantum circuit scanning number. And when the optimal subcircuit can be obtained, the optimal subcircuit is optimized according to the Boolean satisfiability solution algorithm to obtain a Boolean subcircuit. And the subcircuit corresponding to the optimal subcircuit in the quantum circuit is replaced with a Boolean subcircuit to obtain a Boolean quantum circuit, and the quantum circuit is replaced according to the Boolean quantum circuit.

[0107] Specifically, when the current scan number is less than the quantum circuit scan number, the computer device performs scan evaluation processing on the quantum circuit according to the scan parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain the optimal subcircuit. Then, when the optimal subcircuit can be obtained, the computer device optimizes the optimal subcircuit according to the Boolean satisfiability solution algorithm to obtain a Boolean subcircuit. Finally, the computer device replaces the subcircuit corresponding to the optimal subcircuit in the quantum circuit with a Boolean subcircuit to obtain a Boolean quantum circuit, and replaces the quantum circuit according to the Boolean quantum circuit.

[0108] In this way, computer equipment can reduce the entanglement and operational complexity between quantum bits, thereby improving the overall execution efficiency of quantum circuits. Moreover, by using the obtained Boolean quantum circuit as a new quantum circuit and performing multiple iterations, the execution efficiency of the quantum circuit can be maximized.

[0109] See also Figure 4 In some embodiments, step 021 (scanning and evaluating the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain the optimal subcircuit) includes:

[0110] 031: When the current scan number is less than the quantum circuit scan number, the maximum evaluation value is set to 0;

[0111] 032: Scan and evaluate the pre-selected quantum gates in the quantum circuit according to the scanning parameters, heuristic subcircuit scanning method and cost evaluation method to obtain the optimal subcircuit.

[0112] In some embodiments, the setting module is used to set the maximum evaluation value to 0 and add 1 to the current scan number when the current scan number is less than the quantum circuit scan number. The scan evaluation module is used to perform scan evaluation processing on the preselected quantum gates in the quantum circuit according to the scan parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain the optimal subcircuit.

[0113] In some embodiments, the processor is further configured to set the maximum evaluation value to 0 when the current scan number is less than the quantum circuit scan number. And perform scan evaluation processing on the preselected quantum gates in the quantum circuit according to the scan parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain the optimal subcircuit.

[0114] Specifically, when the current scanning number is less than the quantum circuit scanning number, the computer device sets the maximum evaluation value to 0. Next, the computer device performs scanning and evaluation processing on the pre-selected quantum gates in the quantum circuit according to the scanning parameters, the heuristic sub-circuit scanning method and the cost evaluation method to obtain the optimal sub-circuit, and the pre-selected quantum gate is a predetermined 2-bit quantum gate.

[0115] In this way, by evaluating the pre-selected quantum gates, the computer device can identify those parts of the quantum circuit that have the greatest impact on the performance of the quantum circuit, and optimize them, thereby improving the performance of the entire quantum circuit. In addition, the computer device uses a heuristic subcircuit scanning method to perform deep optimization sorting on the subcircuits of the quantum circuit, and uses the sorting as the selection basis for the SAT solver to perform deep optimization.

[0116] See also Figure 5In some embodiments, the scanning parameters include a maximum number of bits and a number of test cases. Step 032 (scanning and evaluating the preselected quantum gates in the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, and the cost evaluation method to obtain the optimal subcircuit) includes:

[0117] 041: construct the first subcircuit and the secondary neighbor set;

[0118] 042: construct a first adjacent set according to the first subcircuit;

[0119] 043: remove the first adjacent set according to the secondary adjacent set to obtain a second adjacent set;

[0120] 044: When the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, a 2-bit quantum gate in the second adjacent set is added to the first subcircuit, and the second subcircuit is obtained by adding a 2-bit quantum gate in the next second adjacent set to the first subcircuit;

[0121] 045: Determine the potential of the second neighboring set to obtain an optimal subcircuit according to the potential of the second neighboring set and the second subcircuit.

[0122] In some embodiments, the construction module is used to construct a first subcircuit, a secondary adjacent set and a first adjacent set. And the first adjacent set is constructed according to the first subcircuit. The removal module is used to remove the first adjacent set according to the secondary adjacent set to obtain a second adjacent set. The adding module is used to add the 2-bit quantum gate in the second adjacent set to the first subcircuit when the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, and the second subcircuit is obtained by adding the 2-bit quantum gate in the next second adjacent set to the first subcircuit. The determination module is used to determine the potential of the second adjacent set to obtain the optimal subcircuit according to the potential of the second adjacent set and the second subcircuit.

[0123] In some embodiments, the processor is further configured to construct a first subcircuit, a secondary neighbor set, and a first neighbor set. And construct the first neighbor set according to the first subcircuit. And remove the first neighbor set according to the secondary neighbor set to obtain a second neighbor set. The processor is also configured to add a 2-bit quantum gate in the second neighbor set to the first subcircuit when the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, and the second subcircuit is obtained by adding a 2-bit quantum gate in the next second neighbor set to the first subcircuit. And determine the potential of the second neighbor set to obtain the optimal subcircuit according to the potential of the second neighbor set and the second subcircuit.

[0124] Specifically, the computer device constructs a first subcircuit and a secondary adjacent set, the first subcircuit includes a preselected quantum gate, and the secondary adjacent set is an empty set. The present application then constructs a first adjacent set based on the first subcircuit. Next, the computer device removes the first adjacent set according to the secondary adjacent set to obtain a second adjacent set. Then, when the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, the computer device adds the 2-bit quantum gate in the second adjacent set to the first subcircuit, and the second subcircuit is obtained by adding the 2-bit quantum gate in the second adjacent set to the first subcircuit, and each 2-bit quantum gate includes 2 quantum bits. Finally, the computer device determines the potential of the second adjacent set to obtain the optimal subcircuit based on the potential of the second adjacent set and the second subcircuit.

[0125] In this way, the computer device can control the complexity and performance of the circuit by gradually expanding the subcircuit and evaluating the impact of each step.

[0126] See also Figure 6 In some embodiments, step 045 (determining the potential of the second neighbor set to obtain the optimal subcircuit according to the potential of the second neighbor set) includes:

[0127] 051: when the potential of the second neighboring set is not 0, construct a next first neighboring set according to the second subcircuit;

[0128] 052: Obtain the next secondary adjacent set according to the union of the second adjacent set and the secondary adjacent set;

[0129] 053: remove the next first adjacent set according to the next secondary adjacent set to obtain the next second adjacent set;

[0130] 054: When the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, add a 2-bit quantum gate in the next second adjacent set to the first subcircuit;

[0131] 055: Determine the potential of the second neighboring set to obtain the optimal subcircuit according to the potential of the second neighboring set.

[0132] In some embodiments, the construction module is used to construct a next first neighboring set according to the second subcircuit. The processing module is used to obtain a next secondary neighboring set according to the union of the second neighboring set and the secondary neighboring set. The removal module is used to remove the next first neighboring set according to the next secondary neighboring set to obtain the next second neighboring set. The adding module is also used to add the 2-bit quantum gate in the next second neighboring set to the first subcircuit when the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits. The confirmation module is used to determine the potential of the second neighboring set to obtain the optimal subcircuit according to the potential of the second neighboring set.

[0133] In some embodiments, the processor is further configured to construct a first neighboring set according to the second subcircuit when the potential of the second neighboring set is not 0. And obtain a next secondary neighboring set according to the union of the second neighboring set and the secondary neighboring set. And remove the first neighboring set according to the next secondary neighboring set to obtain a next second neighboring set. The processor is also configured to add a 2-bit quantum gate in the next second neighboring set to the first subcircuit when the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits. And determine the potential of the second neighboring set to obtain the optimal subcircuit according to the potential of the second neighboring set.

[0134] Specifically, when the potential of the second adjacent set is not 0, the computer device constructs a first adjacent set according to the second subcircuit. The present application then obtains the next secondary adjacent set according to the union of the second adjacent set and the secondary adjacent set. Then, the computer device removes the first adjacent set according to the next secondary adjacent set to obtain the next second adjacent set. Then, when the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, the computer device adds the 2-bit quantum gate in the next second adjacent set to the first subcircuit, and the second subcircuit is obtained by adding the 2-bit quantum gate in the next second adjacent set to the first subcircuit, and each 2-bit quantum gate includes 2 quantum bits. Finally, the computer device determines the potential of the second adjacent set to obtain the optimal subcircuit according to the potential of the second adjacent set.

[0135] In this way, if the potential of the second adjacent set is not 0, it means that these quantum gates need to be further optimized to obtain the optimal subcircuit. And by continuously updating the adjacent set, it is ensured that the same quantum gate will not be repeatedly optimized during the optimization process, thereby improving efficiency. In addition, through such an iterative process, the complexity and performance of the circuit can be controlled.

[0136] See also Figure 7 In some embodiments, step 045 (determining the potential of the second neighbor set to obtain the optimal subcircuit according to the potential of the second neighbor set) includes:

[0137] 056: When the potential of the second adjacent set is 0, the second subcircuit and the number of test cases are evaluated according to the cost evaluation method to obtain the optimal subcircuit.

[0138] In some implementations, the evaluation module is used to evaluate the second subcircuit and the number of test cases according to a cost evaluation method to obtain an optimal subcircuit when the potential of the second neighboring set is 0.

[0139] In some implementations, the processor is further configured to, when the potential of the second neighboring set is 0, evaluate the second subcircuit and the number of test cases according to a cost evaluation method to obtain an optimal subcircuit.

[0140] Specifically, when the potential of the second adjacent set is 0, the computer device evaluates the second subcircuit and the number of test cases according to the cost evaluation method to obtain the optimal subcircuit.

[0141] Thus, when the potential of the second neighboring set is 0, it means that further iterations may not bring better optimization results. In addition, the deep redundancy of the second subcircuit can be obtained through the cost evaluation method, and the performance of the second subcircuit can be quantified.

[0142] See also Figure 8 In some implementations, step 056 (evaluating the second subcircuit and the number of test cases according to the cost evaluation method to obtain the optimal subcircuit) includes:

[0143] 061: Evaluate the second sub-circuit and the number of test cases according to the cost evaluation method to obtain a current evaluation value;

[0144] 062: Compare the current evaluation value with the maximum evaluation value;

[0145] 063: When the current evaluation value is greater than the maximum evaluation value, the current evaluation value is used as the maximum evaluation value to update the maximum evaluation value, and the second sub-circuit is used as the optimal sub-circuit.

[0146] In some embodiments, the evaluation module is used to evaluate the second subcircuit and the number of test cases according to the cost evaluation method to obtain a current evaluation value. The comparison module is used to compare the current evaluation value with the maximum evaluation value. The processing module is also used to use the current evaluation value as the maximum evaluation value to update the maximum evaluation value and use the second subcircuit as the optimal subcircuit when the current evaluation value is greater than the maximum evaluation value.

[0147] In some embodiments, the processor further evaluates the second subcircuit and the number of test cases according to the cost evaluation method to obtain a current evaluation value, and compares the current evaluation value with the maximum evaluation value, and when the current evaluation value is greater than the maximum evaluation value, uses the current evaluation value as the maximum evaluation value to update the maximum evaluation value, and uses the second subcircuit as the optimal subcircuit.

[0148] Specifically, the computer device evaluates the second subcircuit and the number of test cases according to the cost evaluation method to obtain a current evaluation value. Then, the computer device compares the current evaluation value with the maximum evaluation value. Finally, when the current evaluation value is greater than the maximum evaluation value, the computer device uses the current evaluation value as the maximum evaluation value to update the maximum evaluation value, and uses the second subcircuit as the optimal subcircuit.

[0149] In this way, the computer device obtains the deep redundancy of the second subcircuit through the cost evaluation method and quantifies the performance of the second subcircuit. In addition, by continuously comparing and updating the maximum evaluation value, the method of the present application can ensure that the optimal subcircuit with the best performance is found, thereby optimizing the performance of the entire quantum circuit.

[0150] See also Fig. 9 In some implementations, step 061 (evaluating the second sub-circuit and the number of test cases according to the cost evaluation method to obtain a current evaluation value) includes:

[0151] 071: Decompose the second subcircuit to obtain a test subcircuit;

[0152] 072: When the current test number of the quantum circuit is less than the number of test cases, a test quantum state randomly selected from the self-computation base state is applied to the test subcircuit to obtain a test inner product, and the maximum test inner product is obtained based on the test inner product;

[0153] 073: Get the current evaluation value based on the maximum test inner product.

[0154] In some embodiments, the decomposition module is further used to decompose the second subcircuit to obtain a test subcircuit. The processing module is used to apply a test quantum state randomly selected from the computational basis state to the test subcircuit to obtain a test inner product when the current test number of the quantum circuit is less than the number of test cases, and obtain a maximum test inner product based on the test inner product. The operation module is used to obtain a current evaluation value based on the maximum test inner product.

[0155] In some embodiments, the processor is further configured to decompose the second subcircuit to obtain a test subcircuit. When the current number of tests of the quantum circuit is less than the number of test cases, a test quantum state randomly selected from the computational basis state is applied to the test subcircuit to obtain a test inner product, and a maximum test inner product is obtained based on the test inner product. And a current evaluation value is obtained based on the maximum test inner product.

[0156] Specifically, the computer device decomposes the second subcircuit to obtain a test subcircuit. Then, when the current number of tests of the quantum circuit is less than the number of test cases, the computer device applies a test quantum state randomly selected from the computational basis state to the test subcircuit to obtain a test inner product, and obtains a maximum test inner product based on the test inner product. Then, the computer device obtains a current evaluation value based on the maximum test inner product.

[0157] In this way, the computer device simplifies or decomposes the second subcircuit into smaller parts through decomposition processing to facilitate testing and evaluation. And randomly selecting test quantum states from the computational basis state can simulate different input situations. By comparing different test inner products, the best performance of the subcircuit in all test cases can be found, and the test inner product can reflect the change of the quantum state.

[0158] See also Fig.10 In some embodiments, step 072 (when the current test number of the quantum circuit is less than the number of test cases, applying the randomly selected test quantum state to the test subcircuit to obtain a test inner product, and obtaining the maximum test inner product based on the test inner product) includes:

[0159] 081: Construct a test inner product set, which is used to store the test inner product;

[0160] 082: Apply the test quantum state to the test subcircuit to obtain a test inner product, and store the test inner product in a test inner product set;

[0161] 083: Get the maximum test inner product from the test inner product set.

[0162] In some embodiments, the construction module is further used to construct a test inner product set, and the test inner product set is used to store the test inner product. The storage module is used to apply the test quantum state to the test subcircuit to obtain the test inner product, and store the test inner product in the test inner product set. The acquisition module is used to obtain the maximum test inner product from the test inner product set.

[0163] In some embodiments, the processor is further configured to construct a test inner product set, the test inner product set being used to store the test inner product, and to apply the test quantum state to the test subcircuit to obtain the test inner product, and to store the test inner product in the test inner product set, and to obtain the maximum test inner product from the test inner product set.

[0164] Specifically, the computer device constructs a test inner product set, and the test inner product set is used to store the test inner product. Then, the computer device applies the test quantum state randomly selected from the computational basis state to the test subcircuit to obtain the test inner product, and stores the test inner product in the test inner product set. Finally, the computer device obtains the maximum test inner product from the test inner product set.

[0165] In this way, the computer device can systematically evaluate and compare the performance of different subcircuits in the quantum circuit by constructing a set of test inner products and obtaining the maximum test inner product from them.

[0166] See also Fig.11 In some embodiments, step 082 (applying the test quantum state to the test subcircuit to obtain a test inner product, and storing the test inner product in a test inner product set) includes:

[0167] 091: If the current test count is less than the number of test cases, add 1 to the test count;

[0168] 092: Randomly select a quantum state from the calculated base state as the test quantum state;

[0169] 093: Apply the test subcircuit to the test quantum state to obtain the output quantum state;

[0170] 094: Obtain the test inner product based on the test quantum state and the output quantum state;

[0171] 095: Store the test inner product in the test inner product set.

[0172] In some embodiments, the adding module is further used to increase the number of tests by 1 when the current number of tests is less than the number of test cases. The selecting module is used to randomly select a quantum state from the computational base state as a test quantum state. The processing module is further used to apply the test subcircuit to the test quantum state to obtain an output quantum state. And obtain a test inner product based on the test quantum state and the output quantum state. The storage module is used to store the test inner product in a test inner product set.

[0173] In some embodiments, the processor is further configured to increase the number of tests by 1 when the current number of tests is less than the number of test cases. And randomly select a quantum state from the computational base state as a test quantum state. And apply the test subcircuit to the test quantum state to obtain an output quantum state. The processor is further configured to obtain a test inner product based on the test quantum state and the output quantum state. And store the test inner product in a test inner product set.

[0174] Specifically, when the current number of tests is less than the number of test cases, the computer device adds 1 to the number of tests. Next, the computer device randomly selects a quantum state from the computational basis state as the test quantum state. Then, the computer device applies the test subcircuit to the test quantum state to obtain the output quantum state. The computer device then obtains the test inner product based on the test quantum state and the output quantum state. Finally, the computer device stores the test inner product in the test inner product set.

[0175] In this way, when the number of tests is less than the number of test cases, the computer device performs iterative testing and calculates test inner products to systematically evaluate the performance of the test subcircuit.

[0176] See also Fig.12 In some implementations, step 094 (obtaining a current evaluation value based on the maximum test inner product) includes:

[0177] 0101: Calculate the test depth of the test subcircuit;

[0178] 0102: The product of the preset parameter and the average number is used as the exponent of the Euler number to obtain the first exponent;

[0179] 0103: Get the current evaluation value based on the first index, the maximum test inner product and the test depth.

[0180] In some embodiments, the calculation module is further used to calculate the test depth of the test subcircuit. The processing module is used to use the product of the preset parameter and the average number of times as the exponent of the Euler number to obtain a first exponent. The processing module is also used to obtain a current evaluation value according to the first exponent, the maximum test inner product and the test depth.

[0181] In some embodiments, the processor is further configured to calculate a test depth of the test subcircuit, and to obtain a first index by multiplying a preset parameter and an average number of times as an index of the Euler number, and to obtain a current evaluation value according to the first index, the maximum test inner product, and the test depth.

[0182] Specifically, the computer device calculates the test depth of the test subcircuit. Then, the computer device uses the product of the preset parameter and the average number of times as the exponent of the Euler number to obtain a first exponent, and the average number of times is the average number of times the quantum gate in the test subcircuit has been recompiled by the SAT solver. Then, the computer device obtains the current evaluation value according to the first exponent, the maximum test inner product and the test depth.

[0183] In this way, the computer device calculates the test depth and the first index, and combines them with the maximum test inner product to obtain a comprehensive and quantified current evaluation value for evaluating and optimizing sub-circuits in the quantum circuit.

[0184] See also Fig.13 In some embodiments, step 012 (processing the quantum circuit according to the scanning parameter, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit to optimize the quantum circuit) includes:

[0185] 024: When the current scanning times are greater than or equal to the scanning times of the quantum circuit, a Boolean quantum circuit is output to optimize the quantum circuit.

[0186] In some embodiments, the output module is further configured to output a Boolean quantum circuit when the current scanning number is greater than or equal to the quantum circuit scanning number, so as to optimize the quantum circuit.

[0187] In some embodiments, the processor is further configured to output a Boolean quantum circuit when the current scan number is greater than or equal to the quantum circuit scan number, so as to optimize the quantum circuit.

[0188] Specifically, when the current scanning number is greater than or equal to the quantum circuit scanning number, the present application outputs a Boolean quantum circuit to achieve optimization of the quantum circuit.

[0189] In this way, a Boolean quantum circuit is obtained by inputting multiple iterations, and the Boolean quantum circuit has good execution efficiency.

[0190] The following is an example to illustrate the method of the implementation method of the present application. In the embodiments of the present application, the dependency between quantum gates generally refers to the fact that in a quantum circuit, the execution of certain quantum gates depends on the results or states of other quantum gates. The quantum bits that are acted upon refer to those quantum bits that are directly operated by the quantum gates. In the implementation method of the present application, the method for determining whether there is dependency between quantum gates is as follows:

[0191] In a quantum circuit C, if two quantum gates simultaneously satisfy the following conditions:

[0192] Share at least one quantum bit being acted upon;

[0193] Furthermore, two quantum gates cannot operate on other quantum gates in the shared quantum bit.

[0194] The two quantum gates are said to be dependent on each other in the quantum circuit C. In the embodiment of the present application, the process of using the above conditions to determine whether two quantum gates are dependent on each other is recorded as Dependency (G i , G j ,C).

[0195] The dependency between quantum gates and subcircuits generally refers to the fact that, in the design and execution of quantum circuits, the operation of quantum gates depends on the state or result of subcircuits, or the operation of subcircuits depends on the state or result of quantum gates. In the implementation manner of the present application, the method for determining the dependency between quantum gates and subcircuits is:

[0196] In a quantum circuit C, if one of the subcircuits C i And the quantum gate G satisfies the following conditions:

[0197] C i Shares at least one quantum bit with G;

[0198] And in the shared quantum bit C i There cannot be any other quantum gates between and G.

[0199] Then it is called subcircuit C i The quantum gate G and the subcircuit are mutually dependent in the circuit C. In the embodiment of the present application, the process of using the above conditions to determine whether the quantum gate and the subcircuit are mutually dependent is recorded as Dependency(G, C i , C).

[0200] The proximity of quantum gates and subcircuits refers to the proximity of their relative positions and action sequences in the quantum circuit. Adjacent quantum gates or subcircuits are closely connected in the circuit, and their execution sequence and interaction have an important impact on the function and performance of the entire circuit. In the implementation manner of the present application, the method for determining the proximity of quantum gates and subcircuits is:

[0201] In a quantum circuit C, for a given subcircuit C 1 and quantum gate G0, if there does not exist any non-empty gate sequence Satisfies [(for all i, G i The location is G i-1 Before)∨(for all i, G i The location is G i-1 After)]∧Dependency(G i , G i-1 , C)∧Dependency(G K , C 1 , C), then it is called subcircuit C 1 Adjacency (G0, C 1 , C).

[0202] Decomposition of SWAP gates. In a quantum circuit, a SWAP gate SWAP(i, j) can be decomposed into three CNOT gates, namely CNOT(i, j), CNOT(j, i), and CNOT(i, j). In the implementation of the present application, the process of decomposing a SWAP gate into a CNOT gate is recorded as Decompose(C). After decomposing the SWAP gate, a new quantum circuit that does not contain a SWAP gate is obtained. The number of quantum circuit scans is the number of algorithm subcircuit scans TS, the maximum number of bits is the maximum number of bits TN that the SAT solver can process in a CNOT circuit, and the number of test cases is the number of input-output pairs TP tested by the heuristic evaluation function.

[0203] The potential of a quantum gate set is the number of different quantum gates in the quantum gate set.

[0204] Before the quantum circuit is executed, the quantum needs to be compiled according to the connectivity constraints of the target hardware. This compilation operation will introduce a large number of clustered two-bit quantum exchange gates into the quantum circuit, which will lead to a large number of two-bit quantum gate subcircuits in the output circuit. Fig.14 , Fig.15 , Fig.14 is an input circuit for the quantum circuit compilation process, Fig.15 is a possible output circuit, which contains two sub-circuits, A and B, which only contain two-bit quantum gates.

[0205] Specifically, after compiling the quantum circuit, the heuristic subcircuit scanning technology is first used to obtain the quantum circuit C with a large number of CNOT gates obtained by the compilation operation, and then cut it into multiple small-scale CNOT-SWAP circuits. The specific operation method is as follows:

[0206] The user inputs scanning parameters according to his / her needs. In response to the user's input, the computer device sets the scanning parameters, including the number of algorithm subcircuit scans TS, the maximum number of bits TN of the CNOT circuit that the SAT solver can process, and the number of input-output pairs TP of the heuristic evaluation function test.

[0207] See also Fig.16 , when the current scan number n is less than TS, the quantum circuit C with a large number of CNOT gates obtained after the compilation operation is processed as follows:

[0208] The initial value of the maximum evaluation value Z0 is set to 0, and the value of the current scan number n is increased by 1.

[0209] Next, any two-qubit gate in the quantum circuit C is extracted to construct the first subcircuit C1, and a secondary adjacent set D1 without any elements is constructed temporarily. Then, the first adjacent set D is constructed using the two-qubit gates adjacent to the first subcircuit C1 in the quantum circuit C. Then, all two-qubit gates that exist in both the first adjacent set G and the secondary adjacent set D1 are removed from the first adjacent set D to obtain the second adjacent set D2, that is, the elements in the union of the first adjacent set D and the secondary adjacent set D1 are removed from the first adjacent set D to obtain the second adjacent set D2.

[0210] Then, before adding the two-qubit gate Mi in the first adjacent set to the first subcircuit C1, it is pre-calculated whether the number of qubits in the first subcircuit will exceed the maximum number of bits TN input by the user after adding the two-qubit gate Mi to the first subcircuit C1. The order in which the two-qubit gate Mi in the first adjacent set is added to the first subcircuit C1 is to add them in sequence according to the position order in the first adjacent set. If the number of qubits in the first subcircuit will not exceed the maximum number of bits TN input by the user, the two-qubit gate Mi is added to the first subcircuit C1 to obtain the second subcircuit C2. If the number of qubits in the first subcircuit will exceed the maximum number of bits TN input by the user, the two-qubit gate Mi in the first adjacent set will not be added to the first subcircuit C1, and the second subcircuit C2 is directly obtained.

[0211] Then, the next secondary neighbor set is obtained according to the union of the first neighbor set D and the secondary neighbor set D1. Next, the potential of the second neighbor set D2 is determined. If the potential of the second neighbor set D2 is not 0, the second subcircuit is used as the new first subcircuit, and the first neighbor set is reconstructed according to the new first subcircuit until the potential of the obtained second neighbor set D2 is 0.

[0212] If the potential of the second adjacent set D2 is 0, then the cost evaluation method Evaluate is used to perform cost evaluation on the second subcircuit C2 to obtain the optimal subcircuit. Figure 1 The method of performing cost evaluation processing on the second sub-circuit C2 according to the cost evaluation method Evaluate is as follows:

[0213] First, according to the decomposition of the SWAP gate provided in the above-mentioned embodiment of the present application, the second subcircuit is decomposed to obtain a test subcircuit C3 that does not contain a SWAP gate. Then, the depth S of the test subcircuit C3 is calculated according to the depth calculation method provided in the above-mentioned embodiment of the present application. Next, a test number i is set to 0. When the test number i is less than the number of input-output pairs TP of the heuristic evaluation function test input by the user. Construct a test inner product set D3 for storing test inner products, and randomly select a quantum state from the calculation basis state as the test quantum state |x>. Act the test subcircuit C3 on the test quantum state |x> to obtain the output quantum state |y>. According to the test quantum state |x> and the output quantum state |y>, the test inner product d is obtained, that is<x|y> The test inner product d is stored in the test inner product set D3. When the number of tests i is greater than or equal to the number of input-output pairs TP of the heuristic evaluation function test input by the user, the largest test inner product d-max is selected from the test inner product set D3. Then the average number of times v that the quantum gates in the second subcircuit have been recompiled by the SAT solver is calculated.

[0214] Then preset the parameters γ, depth S and average times v to get the current evaluation value Z1, which is calculated as follows:

[0215] After calculating the current evaluation value Z1, compare the current evaluation value Z1 with the maximum evaluation value Z0. When the current evaluation value Z1 is less than or equal to the maximum evaluation value Z0, do not make any changes to the circuit. When the current evaluation value Z1 is greater than the maximum evaluation value Z0, use the current evaluation value Z1 as the new maximum evaluation value Z0, and use the second subcircuit C2 as the optimal subcircuit. After obtaining the optimal subcircuit, optimize the optimal subcircuit according to the Boolean satisfiability solution algorithm to obtain a Boolean subcircuit. And replace the subcircuit corresponding to the optimal subcircuit in the quantum circuit C with the Boolean subcircuit to obtain a Boolean quantum circuit.

[0216] Determine the size of the current scan number n and the algorithm subcircuit scan number TS input by the user. If the current scan number n is less than the algorithm subcircuit scan number TS, the obtained Boolean quantum circuit is used as a new quantum circuit for scanning and evaluation again. If the current scan number n is not less than the algorithm subcircuit scan number TS, the Boolean quantum circuit is output. At this time, the Boolean quantum circuit reduces the entanglement and operation complexity between quantum bits and improves the overall execution efficiency.

[0217] In this way, by extracting subcircuits containing only CNOT and SWAP gates from the quantum circuit, and then recompiling the heuristic CNOT-SWAP circuit to evaluate the subcircuit deep redundancy to confirm the optimal subcircuit, and then optimizing and sorting the optimal subcircuit through heuristic subcircuit scanning. Then call the SAT solver to deeply optimize the optimal subcircuit obtained by the optimized sorting to obtain a Boolean subcircuit. Finally, the subcircuit corresponding to the optimal subcircuit in the quantum circuit is replaced with a Boolean subcircuit to obtain a Boolean quantum circuit. This solves the problem that the complexity of the SAT problem grows exponentially with the circuit complexity when solving complex quantum circuits with existing SAT technology, which in turn causes a sharp increase in solution time.

[0218] The present application also provides a computer-readable storage medium containing a computer program. When the computer program is executed by one or more processors, the one or more processors execute the depth optimization method of the present application.

[0219] It is understood that a computer program includes computer program code. The computer program code may be in source code form, object code form, executable file or some intermediate form. Computer readable storage media may include: any entity or device capable of carrying computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution medium.

[0220] In the description of this specification, the descriptions with reference to the terms "specifically", "further", "particularly", "understandably", etc. are intended to mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not intended to refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0221] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0222] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A quantum circuit deep optimization method based on heuristic SAT scanning, characterized in that: The method comprises: In response to user input, setting scanning parameters of the quantum circuit, wherein the scanning parameters include the number of quantum circuit scans; When the current scan number of the quantum circuit is less than the scan number of the quantum circuit, the quantum circuit is processed according to the scan parameter, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit, so as to optimize the quantum circuit.

2. The method according to claim 1, characterized in that: The step of processing the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit to optimize the quantum circuit includes: When the current scan number is less than the quantum circuit scan number, performing scan evaluation processing on the quantum circuit according to the scan parameter, the heuristic subcircuit scan method and the cost evaluation method to obtain an optimal subcircuit; When the optimal subcircuit can be obtained, optimizing the optimal subcircuit according to the Boolean satisfiability solving algorithm to obtain a Boolean subcircuit; The subcircuit corresponding to the optimal subcircuit in the quantum circuit is replaced with the Boolean subcircuit to obtain the Boolean quantum circuit, and the quantum circuit is replaced according to the Boolean quantum circuit.

3. The method according to claim 2, characterized in that The step of performing scanning and evaluation processing on the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain the optimal subcircuit includes: When the current scan number is less than the quantum circuit scan number, the maximum evaluation value is set to 0; A preselected quantum gate in the quantum circuit is scanned and evaluated according to the scanning parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain an optimal subcircuit, wherein the preselected quantum gate is a predetermined 2-bit quantum gate.

4. The method according to claim 3, characterized in that The scanning parameters include a maximum number of bits and a number of test cases, and the scanning and evaluation process is performed on the preselected quantum gates in the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method and the cost evaluation method to obtain an optimal subcircuit, including: Constructing a first subcircuit and a secondary neighbor set, wherein the first subcircuit includes the preselected quantum gate, and the secondary neighbor set is an empty set; constructing a first neighbor set according to the first subcircuit; Performing a removal process on the first adjacent set according to the secondary adjacent set to obtain a second adjacent set; When the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, the 2-bit quantum gates in the second adjacent set are added to the first subcircuit, and the second subcircuit is obtained by adding the 2-bit quantum gates in the second adjacent set to the first subcircuit, and each of the 2-bit quantum gates includes 2 quantum bits; The potential of the second neighbor set is determined to obtain the optimal sub-circuit according to the potential of the second neighbor set and the second sub-circuit.

5. The method according to claim 4, characterized in that The determining the potential of the second neighboring set to obtain the optimal subcircuit according to the potential of the second neighboring set includes: When the potential of the second neighboring set is not 0, constructing a next first neighboring set according to the second subcircuit; Obtaining a next secondary adjacent set according to the union of the second adjacent set and the secondary adjacent set; Performing removal processing on the next first adjacent set according to the next secondary adjacent set to obtain a next second adjacent set; When the number of quantum bits in the second subcircuit is less than or equal to the maximum number of bits, the 2-bit quantum gates in the next second adjacent set are added to the first subcircuit, and the second subcircuit is obtained by adding the 2-bit quantum gates in the next second adjacent set to the first subcircuit, and each of the 2-bit quantum gates includes 2 quantum bits; The potential of the second neighbor set is determined to obtain the optimal sub-circuit according to the potential of the second neighbor set.

6. The method according to claim 4 or 5, characterized in that: The determining the potential of the second neighboring set to obtain the optimal subcircuit according to the potential of the second neighboring set includes: When the potential of the second adjacent set is 0, the second subcircuit and the number of test cases are evaluated according to the cost evaluation method to obtain the optimal subcircuit.

7. The method according to claim 6, characterized in that The step of evaluating the second sub-circuit and the number of test cases according to the cost evaluation method to obtain the optimal sub-circuit includes: Evaluate the second subcircuit and the number of test cases according to the cost evaluation method to obtain a current evaluation value; comparing the current evaluation value with the maximum evaluation value; In the case that the current evaluation value is greater than the maximum evaluation value, the current evaluation value is used as the maximum evaluation value to update the maximum evaluation value, and the second sub-circuit is used as the optimal sub-circuit.

8. The method according to claim 7, characterized in that The step of evaluating the second sub-circuit and the number of test cases according to the cost evaluation method to obtain a current evaluation value includes: Decomposing the second subcircuit to obtain a test subcircuit; When the current test number of the quantum circuit is less than the number of test cases, applying a test quantum state randomly selected from a computational base state to the test subcircuit to obtain a test inner product, and obtaining a maximum test inner product according to the test inner product; The current evaluation value is obtained according to the maximum test inner product.

9. The method according to claim 8, characterized in that When the current test number of the quantum circuit is less than the number of test cases, applying the randomly selected test quantum state to the test subcircuit to obtain a test inner product, and obtaining a maximum test inner product according to the test inner product, includes: Constructing a test inner product set, wherein the test inner product set is used to store the test inner product; Applying the test quantum state to the test subcircuit to obtain the test inner product, and storing the test inner product in the test inner product set; The maximum test inner product is obtained from the test inner product set.

10. The method according to claim 9, characterized in that The step of applying the test quantum state to the test subcircuit to obtain the test inner product, and storing the test inner product in the test inner product set, comprises: When the current test number is less than the number of test cases, the current test number is increased by 1; Randomly select a quantum state from the calculated base state as the test quantum state; Applying the test subcircuit to the test quantum state to obtain an output quantum state; Obtaining the test inner product according to the test quantum state and the output quantum state; The test inner product is stored in the test inner product set.

11. The method according to claim 9, characterized in that The obtaining the current evaluation value according to the maximum test inner product includes: Calculating a test depth of the test sub-circuit; The product of the preset parameter and the average number of times is used as the exponent of the Euler number to obtain a first exponent, wherein the average number of times the quantum gate in the test subcircuit is recompiled by the SAT solver; A current evaluation value is obtained according to the first index, the maximum test inner product and the test depth.

12. The method according to claim 1, characterized in that The step of processing the quantum circuit according to the scanning parameters, the heuristic subcircuit scanning method, the cost evaluation method and the Boolean satisfiability solving algorithm to obtain a Boolean quantum circuit to optimize the quantum circuit includes: When the current scanning number is greater than or equal to the quantum circuit scanning number, the Boolean quantum circuit is output to achieve optimization of the quantum circuit.

13. A computer device, characterized in that: The computer device comprises a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the method according to any one of claims 1 to 12 is implemented.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium memory stores a computer program, and when the computer program is executed by one or more processors, the method according to any one of claims 1 to 12 is implemented.

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