Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes: a driving circuit, multiple pixels, multiple first scan lines, and multiple clock lines; the driving circuit includes N cascaded first shift register units; the clock line is electrically connected to the multiple first shift register units; the first shift register unit is used to receive at least an input signal and a clock signal on the clock line, and provide the clock signal of the clock line as a first scan signal to the first scan line; the effective time of the first scan signals of at least some of the first shift register units connected to the same clock line overlaps; the process of the clock signal jumping from an inactive level to an active level is a first voltage edge, and the process of jumping from an active level to an inactive level is a second voltage edge; during at least a portion of the display time of a frame of image, the jumping duration of the second voltage edge of the clock signal is greater than or equal to a second preset duration. The above technical solution can improve the problem of uneven display of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] At present, compared with traditional liquid crystal display (LCD), organic light-emitting diode (OLED) display has the advantages of low energy consumption, fast response, high contrast, and light weight. It has been widely used in many devices such as smartphones, tablets, laptops, TVs, calculators, etc.

[0003] In existing organic light emitting diode display technologies, multi-pulse driving is a commonly used driving method, which significantly improves the response time of the display panel and can alleviate the threshold drift problem of the driving transistor in the pixel circuit.

[0004] However, the existing multi-pulse driving method also causes uneven display of the display panel, that is, abnormal display brightness occurs in some areas of the display panel, for example, abnormal display brightness occurs in areas near the upper edge or lower edge of the display panel. Summary of the Invention

[0005] The present invention provides a display panel and a display device to improve the problem of uneven display of the display panel.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising: a driving circuit, a plurality of pixels arranged in an array, a plurality of first scan lines, and a plurality of clock lines;

[0007] At least part of the pixels in the same row are electrically connected to the same first scan line;

[0008] The driving circuit is electrically connected to each first scan line respectively; the driving circuit includes N cascaded first shift register units; the clock line is electrically connected to the plurality of first shift register units; the first shift register unit is configured to receive at least an input signal and a clock signal on the clock line, and control the clock signal of the clock line to be provided as a first scan signal to the first scan line;

[0009] The effective times of the first scan signals of at least some of the first shift register units connected to the same clock line overlap;

[0010] The process of the clock signal jumping from the invalid level to the valid level is the first voltage edge, and the process of the clock signal jumping from the valid level to the invalid level is the second voltage edge;

[0011] During at least a portion of the display time of a frame of image, the transition duration of the second voltage edge of the clock signal is greater than or equal to the second preset duration.

[0012] According to another aspect of the present invention, a display device is provided, including: the above-mentioned display panel.

[0013] The technical solution of the present invention can reduce the transition speed of the second voltage edge of the clock signal by setting the transition duration of the second voltage edge of the clock signal to be greater than or equal to the second preset duration during at least part of the display time of a frame of picture, so that the process of the first scanning signal jumping from the valid level to the invalid level is slower. When there is parasitic capacitance in the pixel, the coupling effect of the first scanning signal on the node in the pixel is smaller. In this way, the load on the clock line transmitting the clock signal fluctuates, especially when the load decreases, to ensure that the coupling effect of the first scanning signal on the node will not significantly change the potential of the node, which is beneficial to the stability of the potential of the node in the pixel, thereby effectively improving the display unevenness problem caused by the load change of the clock line during part of the display time of a frame of picture.

[0014] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 2 The present invention provides a structural diagram and a timing diagram of a driving circuit;

[0018] Figure 3 1 is a structural diagram of a first shift register unit provided by an embodiment of the present invention;

[0019] Figure 4 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0020] Figure 5 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0021] Figure 6 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 7 1 is a schematic diagram of a circuit structure of a pixel provided by an embodiment of the present invention;

[0023] Figure 8 This is a schematic diagram of the circuit structure of another pixel provided by an embodiment of the present invention.

[0024] Figure 9 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0025] Figure 10 This is a timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0026] Figure 11 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0027] Figure 12 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0028] Figure 13 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0029] Figure 14 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0030] Figure 15 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0031] Figure 16 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0032] Figure 17 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0033] Figure 18 This is a structural diagram and timing diagram of another driving circuit provided by the present invention;

[0034] Figure 19 This is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0035] Figure 20 This is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0036] Figure 21 This is a structural diagram and timing diagram of another driving circuit provided by an embodiment of the present invention;

[0037] Figure 22 This is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0038] Figure 23 This is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0039] Figure 24 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] As described in the background technology, in existing organic light-emitting diode display technology, multi-pulse driving is a commonly used driving method, wherein the driving circuit can receive a clock signal and control the clock signal to be output as a driving signal. During the display time of a frame of picture, the driving signal includes multiple valid pulses, and the driving circuit can output the clock signal as the driving signal in multiple time periods.

[0043] During the display time of a single frame, the driver circuit can output multiple drive signals. The effective times of the active pulses of different drive signals may overlap. This means that the driver circuit can control a single clock signal to be output as multiple drive signals during a given period, which can result in a heavy load on the clock line transmitting the clock signal. The number of drive signals with overlapping effective times may vary during different periods of the display time of a single frame, meaning that the load on the clock line may also vary. When the load on the clock line changes, it affects the signal delay when the driver circuit outputs the drive signal, causing the voltage edge transition speed of the drive signal to change. When the voltage edge transition speed of the drive signal is too fast, the coupling effect on some nodes in the pixel circuit can be significant, causing the drive current provided by the pixel circuit to the organic light-emitting diode to be too high or too low, resulting in uneven display on the display panel.

[0044] To solve the above technical problems, an embodiment of the present invention provides a display panel, comprising: a driving circuit, a plurality of pixels arranged in an array, a plurality of first scan lines and a plurality of clock lines; at least some of the pixels in the same row are electrically connected to the same first scan line; the driving circuit is electrically connected to each of the first scan lines respectively; the driving circuit includes N cascaded first shift register units; the clock line is electrically connected to the plurality of first shift register units; the first shift register unit is used to receive at least an input signal and a clock signal on the clock line, and control the clock signal of the clock line to be provided as a first scan signal to the first scan line; the effective times of the first scan signals of at least some of the first shift register units connected to the same clock line overlap; the process of the clock signal jumping from an invalid level to a valid level is a first voltage edge, and the process of jumping from a valid level to an invalid level is a second voltage edge; during at least part of the display time of a frame of image, the jumping duration of the second voltage edge of the clock signal is greater than or equal to a second preset duration.

[0045] By adopting the above technical solution, by setting the transition time of the second voltage edge of the clock signal to be greater than or equal to the second preset time during at least part of the display time of a frame of picture, the transition speed of the second voltage edge of the clock signal can be reduced, so that the process of the first scanning signal jumping from the valid level to the invalid level is slower. When there is parasitic capacitance in the pixel, the coupling effect of the first scanning signal on the node in the pixel is smaller. In this way, the load on the clock line transmitting the clock signal fluctuates, especially when the load decreases, to ensure that the coupling effect of the first scanning signal on the node will not significantly change the potential of the node, which is beneficial to the stability of the potential of the node in the pixel, thereby effectively improving the display unevenness problem caused by the load change of the clock line during part of the display time of a frame of picture.

[0046] The above is the core concept of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without inventive effort are within the scope of protection of the present invention. The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings.

[0047] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, with reference to Figure 1 The display panel 01 includes a driving circuit 20, a plurality of pixels P arranged in an array, a plurality of first scan lines and a plurality of clock lines CL; at least some of the pixels P in the same row are electrically connected to the same first scan line SL1; the driving circuit 20 is electrically connected to each clock line CL and each first scan line SL1 respectively.

[0048] Figure 2 The present invention provides a schematic diagram of the structure and timing of a driving circuit, with reference to Figure 2 The driving circuit 20 includes a first shift register 21, which includes N cascaded first shift register units 22. The first shift register units 22 are electrically connected to the first scan line SL1. The clock line CL is electrically connected to the plurality of first shift register units 22. The i-th stage first shift register unit 22 is configured to receive at least an input signal and a clock signal (CK1, XCK1) on the clock line CL, and control the clock signal (CK1 or XCK1) of the clock line CL to be provided as a first scan signal Scan1(i) to the first scan line SL1, where i is a positive integer less than or equal to N.

[0049] Continue to refer Figure 1 and Figure 2 The active periods of the first scan signal Scan1 of at least a portion of the first shift register units 22 connected to the same clock line CL overlap; the process of the clock signal (CK1, XCK1) transitioning from an inactive level to an active level is a first voltage edge J1, and the process of the clock signal (CK1, XCK1) transitioning from an active level to an inactive level is a second voltage edge J2. During at least a portion of the display time DF of a single frame, the transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1) is greater than or equal to a second predetermined duration.

[0050] Among them, the second preset duration can be the shortest jump duration of the second voltage edge J2 of the clock signal (CK1, XCK1) during the display time DF of a frame image. In some periods of the display time DF of a frame image, the jump duration of the second voltage edge J2 of the clock signal (CK1, XCK1) can be greater than the jump duration of the second voltage edge J2 in other periods. Alternatively, the second preset duration may also be the conventional transition duration of the second voltage edge of the clock signal (CK1, XCK1) in the prior art. For example, if the conventional transition duration of the second voltage edge of the clock signal (CK1, XCK1) in the prior art is 600ns, then the second preset duration may be 600ns; if the conventional transition duration of the second voltage edge of the clock signal (CK1, XCK1) in the prior art is 500-600ns, then the second preset duration may be 500-600ns. In an optional embodiment, during at least part of the display time DF of a frame, the transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1) may be 600-700ns.

[0051] For example, Figure 3 This is a schematic structural diagram of a first shift register unit provided by an embodiment of the present invention, with reference to Figure 2 and Figure 3 The first shift register unit 22 can receive a first clock signal CK1, a second clock signal XCK1, a first level signal VGH, and a second level signal VGL. The first shift register unit 22 may include eight transistors (MS1, MS2, MS3, MS4, MS5, MS6, MS7, MS8) and two capacitors (CS1, CS2). In an optional embodiment, the first clock signal CK1 and the second clock signal XCK1 have the same clock cycle; and during at least a portion of the same clock cycle, the first clock signal CK1 and the second clock signal XCK1 have opposite polarities.

[0052] The first-stage first shift register unit 22 may receive the first initial signal STV1 as an input signal, and the subsequent-stage first shift register unit 22 may receive the first scan signal Scan1 output by the previous-stage first shift register unit 22 as an input signal.

[0053] For the odd-numbered first shift register unit 22, when the input signal and the first clock signal CK1 are both at the valid level, the first shift register unit 22 is turned on, and the period in which the input signal is at the valid level and the first clock signal CK1 is also at the valid level, as well as the period in which the input signal is at the invalid level and the first clock signal CK1 is also at the invalid level thereafter are the on-periods of the first shift register unit 22. During the on-period, the first shift register unit 22 can output the valid pulse of the second clock signal XCK1 as the valid pulse of the first scan signal Scan1.

[0054] For the first shift register unit 22 of the even-numbered stage, when the input signal and the second clock signal XCK1 are at the valid level at the same time, the first shift register unit 22 is turned on, and the period in which the input signal is at the valid level and the second clock signal XCK1 is also at the valid level, and the period in which the input signal is at the invalid level and the second clock signal XCK1 is also at the invalid level thereafter are the conduction period of the first shift register unit 22. During the conduction period, the first shift register unit 22 can output the valid pulse of the first clock signal CK1 as the valid pulse of the first scan signal Scan1.

[0055] It should be noted that the active levels of the first clock signal CK1 and the second clock signal XCK1 can be either high or low. For N-type transistors, the active level is high, and the inactive level is low. For P-type transistors, the active level is low, and the inactive level is high. For ease of description, unless otherwise specified, the present embodiment of the present invention uses the example of the transistors in the first shift register unit 22 being all P-type transistors and having their active levels all being low as an example to illustrate the technical solutions of the present embodiment.

[0056] When the first initial signal STV1 includes multiple valid pulses, the first shift register unit 22 includes multiple conduction periods, that is, the first shift register unit 22 can output multiple valid pulses of the second clock signal XCK1 or the first clock signal CK1 as multiple valid pulses of the first scan signal Scan1.

[0057] For example, the first shift register 21 is electrically connected to the two clock lines CL, and the first shift register unit 22 can output two valid pulses of the first scan signal Scan1 during the display time DF of one frame. Figure 1-Figure 3 For the first scan signal Scan1 output by the first shift register unit 22 of the first two stages, the second valid pulse of the first scan signal Scan1(i) may overlap with the first valid pulse of the first scan signal Scan1(i+2); for the first scan signal Scan1 output by the first shift register unit 22 of the last two stages, the first valid pulse of the first scan signal Scan1(i) may overlap with the second valid pulse of the first scan signal Scan1(i-2); for the first scan signal Scan1 output by the first shift register unit 22 of other stages, the first valid pulse of the first scan signal Scan1(i) may overlap with the second valid pulse of the first scan signal Scan1(i-2), and the second valid pulse may overlap with the first valid pulse of the first scan signal Scan1(i+2).

[0058] According to the above content, the first scanning signals Scan1 with overlapping effective times all come from the first shift register units 22 of the odd-numbered stages, or all come from the first shift register units 22 of the even-numbered stages, and the effective pulses of the first scanning signals Scan1 output by the first shift register units 22 of the odd-numbered stages all come from the second clock signal XCK1, and the effective pulses of the first scanning signals Scan1 output by the first shift register units 22 of the even-numbered stages all come from the first clock signal CK1. In a part of the display time DF of a frame, for example, the FT0' period, the effective time of the first scanning signal Scan1 exists. The number of first shift register units 22 that overlap and simultaneously control the same clock signal (CK1 or XCK1) as the first scan signal Scan1 is large, which will cause a large load on the clock line CL that transmits the second clock signal XCK1 or the first clock signal CK1. As a result, when the first shift register unit 22 controls the clock signal (CK1, XCK1) to be output as the first scan signal Scan1, a large signal delay is generated. As a result, the level transition process of the first scan signal Scan1 is slow, and the coupling effect on some nodes in the pixel P is also less obvious, which is beneficial to the stability of the potential of the nodes in the pixel P.

[0059] For the case where the effective time of the first scan signal Scan1 does not overlap, such as the FT1' period and the FT2' period, the number of first shift register units 22 that control the same clock signal (CK1, XCK1) as the first scan signal Scan1 is small, so that the load of the clock line CL that transmits the second clock signal XCK1 or the first clock signal CK1 is small, resulting in less signal delay when the first shift register unit 22 controls the clock signal (CK1, XCK1) to be output as the first scan signal Scan1. At least in the FT1' period and the FT2' period, the transition time of the second voltage of the clock signal (CK1, XCK1) along J2 is increased, so that the transition time of the second voltage of the clock signal (CK1, XCK1) along J2 is greater than or equal to the second preset time, which can reduce the transition speed of the second voltage of the clock signal (CK1, XCK1) along J2. In this way, even if the load on the clock line CL is reduced and the signal delay is less, the process of the first scanning signal Scan1 jumping from the valid level to the invalid level can be slower, which can reduce the coupling effect of the first scanning signal Scan1 on the node, which is beneficial to balancing the transition speed of each first scanning signal Scan1 from the valid level to the invalid level under different loads of the clock line CL in the display time DF of a frame of picture, thereby improving the problem of uneven display of the display panel 01.

[0060] The clock signal (CK1, XCK1) can be directly provided by a driver chip (not shown) or a clock controller (not shown). When a large load is connected to the clock line CL used to transmit the clock signal (CK1 or XCK1), the signal delay in the process of the first shift register unit 22 providing the clock signal (CK1 or XCK1) as the first scan signal Scan1(i) to the first scan line SL1 is affected, resulting in a large signal delay, which reduces the level transition speed of the first scan signal Scan1(i). However, the level transition speed of the transmission clock signal (CK1 or XCK1) itself is less affected. Therefore, in some time periods, when the transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1) is set to be less than the second preset duration, the transition of the second voltage edge J2 of the clock signal (CK1, XCK1) can be faster. However, due to the influence of the load connected to the clock line CL for transmitting the clock signal (CK1 or XCK1), the level transition speed of the first scan signal Scan1(i) may be slower.

[0061] The first scan signal Scan1 can control the switching device in the pixel P. When the first scan signal Scan1 is at an active level, it can transmit initialization signals, data signals, compensation signals, reset signals, bias signals, and other signals to the pixel P, thereby changing the potential of the node. Even if the process of the first scan signal Scan1 jumping from an inactive level to an active level has a coupling effect on the node, the node will be rewritten with the corresponding signal when the first scan signal Scan1 jumps to an active level. Therefore, the process of the first scan signal Scan1 jumping from an inactive level to an active level has little effect on the potential of the node. By simply setting the jump duration of the second voltage edge J2 of the clock signal to be greater than or equal to the second preset duration during at least a portion of the time period, the process of the first scan signal Scan1 jumping from an active level to an inactive level can be improved to improve the display unevenness problem.

[0062] In an embodiment of the present invention, by setting the transition duration of the second voltage edge of the clock signal to be greater than or equal to the second preset duration during at least a portion of the display time of a frame of picture, the transition speed of the second voltage edge of the clock signal can be reduced, so that the process of the first scanning signal jumping from the valid level to the invalid level is slower. When there is parasitic capacitance in the pixel, the coupling effect of the first scanning signal on the node in the pixel is smaller. In this way, the load on the clock line transmitting the clock signal fluctuates, especially when the load decreases, to ensure that the coupling effect of the first scanning signal on the node will not significantly change the potential of the node, which is beneficial to the stability of the potential of the node in the pixel, thereby effectively improving the display unevenness problem caused by the load change of the clock line during part of the display time of a frame of picture.

[0063] In an optional embodiment, the second preset time length may be greater than or equal to 600 ns and less than or equal to 700 ns.

[0064] For example, during at least part of the display time DF of a frame, the transition duration of the second voltage edge J2 of the clock signal can be the second preset duration plus 50-100ns, and the transition duration of the second voltage edge J2 of the clock signal can be 650-800ns.

[0065] In another optional embodiment, the second preset duration is greater than or equal to 26% of the duration of the effective level of the clock signal, and less than or equal to 30% of the duration of the effective level of the clock signal.

[0066] Among them, the embodiment of the present invention does not limit how to determine the duration of the effective level. In an optional implementation, the duration of the effective level can be determined by amplifying the waveform and manually or automatically obtaining the duration during which the potential of the clock signal is within ±5% of the effective level.

[0067] For example, the duration of the effective level of a general clock signal may be approximately 2300 ns, 26% of 2300 ns is approximately 600 ns, and 30% of 2300 ns is approximately 700 ns. Thus, the second preset duration may be greater than or equal to 600 ns and less than or equal to 700 ns. However, the duration of the effective level of the clock signal is not limited to 2300 ns. For example, when the duration of the effective level of the clock signal is approximately 3000 ns, the second preset duration may be greater than or equal to 780 ns and less than or equal to 900 ns.

[0068] In yet another optional embodiment, during at least a portion of the display time of a frame of image, the thrust of the second voltage edge J2 of the clock signal is less than the second preset thrust.

[0069] The thrust along the second voltage edge J2 may refer to the output power or charging current of a driver chip (not shown) or a clock controller (not shown) providing the clock signal when the clock signal transitions from an active level to an inactive level. The greater the thrust along the second voltage edge J2, the greater the load that the clock line CL transmitting the clock signal can bear, and the smaller the signal delay caused by the load. The smaller the thrust along the second voltage edge J2, the smaller the load that the clock line CL transmitting the clock signal can bear, and the greater the signal delay caused by the load.

[0070] The second preset thrust may be the maximum thrust of the second voltage edge J2 of the clock signal during the display time DF of a frame. During a portion of the display time DF of a frame, the thrust of the second voltage edge J2 of the clock signal (CK1, XCK1) may be smaller than the thrust of the second voltage edge J2 during other periods. Alternatively, the second preset thrust may be the conventional thrust of the second voltage edge of the clock signal (CK1, XCK1) in the prior art. In an optional embodiment, the second preset thrust may also be the thrust of the first initial signal STV1 received by the first shift register unit of the first stage.

[0071] By reducing the thrust of the second voltage edge J2 of the clock signal during at least part of the display time of a frame of picture, the thrust of the second voltage edge J2 of the clock signal is made less than the second preset thrust, and the signal delay is larger. Under the same load, the speed at which the first scanning signal Scan1 jumps from the valid level to the invalid level can be reduced, thereby avoiding the load of the clock line CL being reduced during part of the time, and the parasitic capacitance coupling caused by the first scanning signal Scan1 jumping too fast to affect the potential of the node in the pixel, which is beneficial to the stability of the potential of the node in the pixel, thereby effectively improving the display unevenness problem caused by the load change of the clock line during part of the display time of a frame of picture.

[0072] In yet another optional embodiment, Figure 4 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 4 , during at least a portion of the display time DF of a frame, the second voltage edge J2 of the clock signal (CK1, XCK1) includes at least two second sub-voltage edges J02;

[0073] Among them, the second sub-voltage edge J02 is the process of the clock signal jumping from the first sub-level to the second sub-level; the first sub-level and / or the second sub-level is between the invalid level and the valid level; the absolute value of the difference between the first sub-level and the valid level is smaller than the absolute value of the difference between the second sub-level and the valid level; the absolute value of the difference between the second sub-level and the invalid level is smaller than the absolute value of the difference between the first sub-level and the invalid level.

[0074] Specifically, the second voltage edge is divided into multiple second sub-voltage edges J02, and the clock signal (CK1, XCK1) can be stepped when jumping from the valid level to the invalid level. When the valid level is low, the first sub-level is less than the second sub-level, wherein the first sub-level is greater than or equal to the valid level, the second sub-level is less than or equal to the invalid level, but the two are not equal at the same time, and at least one is between the valid level and the invalid level; when the valid level is high, the first sub-level is greater than the second sub-level, wherein the first sub-level is less than or equal to the valid level, the second sub-level is greater than or equal to the invalid level, but the two are not equal at the same time, and at least one is between the valid level and the invalid level. By setting the clock signal (CK1, XCK1) to jump from the valid level to the invalid level in steps, the jump time of the second voltage edge of the clock signal (CK1, XCK1) can be increased, and the parasitic capacitance coupling caused by the signal jumping too fast can be reduced to improve the problem of uneven display.

[0075] In yet another optional embodiment, Figure 5 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 5 During at least a portion of the display time DF of a frame, the transition duration of the first voltage of the clock signal (CK1, XCK1) along J1 is greater than or equal to a first preset duration.

[0076] Among them, the first preset duration can be the shortest jump duration of the first voltage edge J1 of the clock signal (CK1, XCK1) during the display time DF of a frame of picture. In some periods of the display time DF of a frame of picture, the jump duration of the first voltage edge J1 of the clock signal (CK1, XCK1) can be greater than the jump duration of the first voltage edge J1 in other periods. Alternatively, the first preset duration may also be the conventional transition duration of the first voltage edge of the clock signal (CK1, XCK1) in the prior art. For example, if the conventional transition duration of the first voltage edge of the clock signal (CK1, XCK1) in the prior art is 600ns, then the first preset duration may be 600ns; if the conventional transition duration of the first voltage edge of the clock signal (CK1, XCK1) in the prior art is 500-600ns, then the first preset duration may be 500-600ns. In an optional embodiment, during at least part of the display time DF of a frame, the transition duration of the first voltage edge J1 of the clock signal (CK1, XCK1) may be 600-650ns.

[0077] By setting the transition time of the first voltage edge J1 of the clock signal to be greater than or equal to the first preset time during at least part of the display time DF of a frame of image, on the one hand, the transition speed of the first scanning signal Scan1 from an invalid level to a valid level can be reduced, and the load on the clock line CL transmitting the clock signal can fluctuate, especially when the load decreases, thereby reducing the coupling effect on the node in the pixel P, which is beneficial to the stability of the potential of the node in the pixel P and improving the problem of uneven display; on the other hand, in at least part of the time period, increasing the transition time of the first voltage edge J1 of the clock signal can reduce the thrust of the first voltage edge J1 of the clock signal, which is beneficial to reducing the power consumption of the display panel 01.

[0078] Based on the above embodiment, the first preset time length is shorter than the second preset time length.

[0079] Specifically, during at least a portion of the display time DF of a single frame, the transition duration of the first voltage edge J1 of the clock signal is less than or equal to the transition duration of the second voltage edge J2. Without affecting the display effect, setting a shorter transition duration of the first voltage edge J1 helps increase the effective duration of the clock signal, thereby increasing the effective duration of the effective pulse of the first scan signal Scan1 and improving the signal charging rate.

[0080] Based on the above embodiments, Figure 6 This is a structural schematic diagram of another display panel provided by an embodiment of the present invention. The display panel 01 includes a first pixel row PR1 and a second pixel row PR2 alternately arranged along a second direction Y. The adjacent first pixel row PR1 and second pixel row PR2 form a pixel row group; pixels P in the same pixel row group can receive the same first pixel Scan1.

[0081] Exemplarily, the first scan signal Scan1 can control switching devices in the pixels P. When the first scan signal Scan1 is at an active level, the same initialization signal, the same compensation signal, the same reset signal, or the same bias signal can be simultaneously transmitted to each pixel P in the same pixel row group. Alternatively, when the first scan signal Scan1 is at an active level, different data signals can be transmitted to each pixel P in the same pixel row group. When the first scan signal Scan1 is used to control the switching devices used to transmit data signals in the pixels P, each column of pixels P can be electrically connected to two data lines DL, one data line DL being used to transmit data signals for the pixels P in the first pixel row PR1 of the column, and the other data line DL being used to transmit data signals for the pixels P in the second pixel row PR2 of the column.

[0082] By setting the pixels P of the same pixel row group to receive the same first pixel Scan1, on the one hand, the effective time of the first scanning signal Scan1 can be increased, thereby increasing the time for the signal to be written into the pixel P when the switching device is turned on, so as to ensure that the signal can be accurately written into the pixel P, which is beneficial to improving the charging rate of the signal and realizing high-frequency driving; on the other hand, the number of first scanning signals Scan1 required in the display panel can be reduced, that is, the number of first shift register units 22 in the first shift register 21 can be reduced. In this way, the number of first shift registers 21 electrically connected to the clock line CL can be significantly reduced, which is beneficial to reducing the load and realizing high-resolution driving.

[0083] Optionally, during the display time of a frame, the first scan signal includes a data write pulse and at least one virtual write pulse; the data write pulse of the first scan signal Scan1(i) output by some first shift register units overlaps with the virtual write pulse of the first scan signal Scan1(j) output by other first shift register units, i and j are both positive integers less than or equal to N, and i≠j.

[0084] Specifically, the first scan signal can be used to control the switching device used to transmit the data signal in the pixel. During the display time of a frame of the picture, the first shift register unit can output at least two valid pulses of the first scan signal, one of which is a data write pulse, and the other valid pulses are virtual write pulses. During the effective time of the data write pulse of the first scan signal Scan1(i), the driving transistors of some pixels can write data signals corresponding to the grayscale, such as the data signal of the current row, so that the light-emitting elements in the pixels can display the corresponding grayscale; during the virtual write pulse phase of the first scan signal Scan1(i), the driving transistors of some pixels can write data signals that do not correspond to the grayscale, such as the data signals of other rows, and the data signals written by the pixels before can be cleared, thereby avoiding the driving transistor in the pixel from being in a certain state for a long time, affecting the performance of the driving transistor. In an optional embodiment, there is no need to set up an additional bias transistor, nor is there any need to set up an additional bias signal and bias control signal, which is conducive to reducing the pixel size and improving the resolution.

[0085] In the display time of one frame, the dummy write pulse of the same first scan signal may be located before or after the data write pulse, which is not limited in the embodiment of the present invention.

[0086] Exemplarily, the pixel P includes a pixel circuit 11 and a light emitting element LED, wherein the pixel circuit 11 can be any combination known in the art, for example, the pixel circuit 11 can be a typical 2T1C circuit, such as Figure 7 Alternatively, the pixel circuit 11 may also be a typical 7T1C circuit, such as Figure 8 As shown, at this time, the pixel circuit 11 may include a first light emission control transistor M1, an initialization transistor M4, a compensation transistor M5, a second light emission control transistor M6, a reset transistor M7, a write transistor M2, a drive transistor M3 and a storage capacitor C.

[0087] The pixel circuit 11 is Figure 8 Take the 7T1C circuit shown as an example, Figure 9 This is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Figure 8 and Figure 9 Pixel circuits 11 arranged in rows along a first direction X can be electrically connected to the same first scan line SL1. The i-th first scan line SL1 can transmit a first scan signal Scan1(i) to the pixel circuit 11 in the i-th row to control the write transistor M2 and the compensation transistor M5 of the pixel circuit 11 in the i-th row. The display panel 01 also includes a plurality of data lines DL. Pixel circuits 11 arranged in columns along a second direction Y can be electrically connected to the same data line DL, where the second direction Y intersects the first direction X. When the first scan signal Scan1(i) transmitted by the i-th first scan line SL1 is at an active level, the plurality of data lines DL can transmit data signals data to pixel circuits 11 located in the i-th row but in different columns.

[0088] The display panel 01 may further include a plurality of second scan lines SL2 and a plurality of emission control lines EL. The drive circuit 20 may further include a second shift register and a third shift register (not shown in the figure). The second shift register includes N cascaded second shift register units, and the third shift register includes N cascaded third shift register units. The second shift register unit is electrically connected to the second scan line SL2, and the third shift register unit is electrically connected to the emission control line EL (not shown in the figure). The pixel circuits 11 arranged in rows along the first direction X can be electrically connected to the same second scan line SL2 and the same emission control line EL. The i-th second scan line SL2 can transmit a second scan signal Scan2(i) to the i-th pixel circuit 11 to control the initialization transistor M4 and reset transistor M7 of the i-th pixel circuit 11; the i-th emission control line EL can transmit a light emission control signal Emit(i) to the i-th pixel circuit 11 to control the first emission control transistor M1 and the second emission control transistor M6 of the i-th pixel circuit 11.

[0089] The pixel circuit 11 is Figure 8 For example, in the 7T1C circuit shown in FIG. 1 , the first scanning signal includes a data write pulse and a dummy write pulse, and the dummy write pulse is located before the data write pulse. Figure 10 This is a timing diagram of a pixel circuit provided by an embodiment of the present invention, referring to Figures 8-10During the display time of one frame, the pixel circuit 11 includes a bias phase t0, an initialization phase t1, a writing phase t2, a reset phase tf and a light emitting phase t3.

[0090] The bias stage t0 may be located before the initialization stage t1, the writing stage t2, and the light-emitting stage t3. In this stage, the virtual writing pulse S0 of the first scanning signal Scan1(i) may control the writing transistor M2 to be turned on, and transmit the data signals of the pixels P in other rows to the driving transistor M3 of the pixels P in this row, so as to eliminate the data signals written by the pixels P in this row in the previous writing stage. In this stage, the virtual writing pulse S0 may also control the compensation transistor M5 to be turned on, and transmit the data signals of the pixels P in other rows to the gate of the driving transistor M3 of the pixels P in this row, so as to avoid the gate of the driving transistor M3 of the pixels P in this row being at a certain potential for a long time when the picture is continuously displayed, thereby affecting the performance of the driving transistor M3.

[0091] The initialization stage t1 is located before the writing stage t2. In this stage, the second scanning signal Scan2(i) can control the initialization transistor M4 to turn on, transmit the initialization signal vref1 to the gate of the driving transistor M3, and control the driving transistor M3 to turn on, which is beneficial to the subsequent writing stage t2 to write the data signal data at the gate of the driving transistor M3.

[0092] The writing stage t2 is located after the initialization stage t1 and before the light-emitting stage t3. In this stage, the data writing pulse S1 of the first scanning signal Scan1(i) can control the writing transistor M2 to turn on, and transmit the data signal data of the pixel circuit 11 of this row to the driving transistor M3 of the pixel circuit 11 of this row; at the same time, the data writing pulse S1 can also control the compensation transistor M5 to turn on, and transmit the data signal data to the gate of the driving transistor M3 of the pixel circuit 11 of this row, and compensate for the threshold voltage of the driving transistor M3.

[0093] The reset phase tf is located before the light emitting phase t3. In this phase, the first scan signal Scan1(i) or the second scan signal Scan2(i) can control the reset transistor M7 to transmit the reset signal to the light emitting element LED to clear the residual electrical signal in the light emitting element LED.

[0094] The light-emitting stage t3 is located after the initialization stage t1, the writing stage t2, and the reset stage t3. In this stage, the first scanning signal Scan1(i) and the second scanning signal Scan2(i) are both at invalid levels, the storage capacitor C stores the data signal, and the light-emitting control signal Emit(i) can control the first light-emitting control transistor M1 to turn on, and transmit the first power signal PVDD to the driving transistor M3; the light-emitting control signal Emit(i) can also control the second light-emitting control transistor M6 to turn on, and control the driving transistor M3 to provide a driving current to the light-emitting element LED, wherein the driving current corresponds to the data signal stored in the storage capacitor C. The light-emitting element LED also receives the second power signal PVEE to form a path in the light-emitting element LED, and the light-emitting element LED can display light according to the data signal stored in the storage capacitor C.

[0095] By setting the transition time of the second voltage along J2 of the clock signal to be greater than or equal to the second preset time during at least part of the time period, the transition speed of at least part of the first scanning signal Scan1 when it jumps from the valid level to the invalid level can be reduced, thereby reducing the coupling effect of the first scanning signal Scan1 on the node, especially the coupling on the gate potential of the driving transistor M3, which is beneficial to improving the stability of the gate potential of the driving transistor M3, thereby improving the accuracy of the data signal stored in the storage capacitor C, and then when the light-emitting element LED displays light according to the data signal stored in the storage capacitor C, it can display the correct grayscale, which can effectively improve the problem of uneven display of the display panel 01.

[0096] It should be noted that the figure only illustrates that all transistors in the pixel circuit 11 are P-type transistors. In other embodiments, at least some of the transistors in the pixel circuit 11 may be N-type transistors. For a P-type transistor, when the signal received by its gate is low, the P-type transistor is turned on, and when the signal received by its gate is high, the P-type transistor is turned off. For an N-type transistor, when the signal received by its gate is high, the N-type transistor is turned on, and when the signal received by its gate is low, the N-type transistor is turned off. For ease of description, the embodiments of the present invention are described by taking the case where all transistors in the pixel circuit 11 are P-type transistors as an example to illustrate the technical solutions of the embodiments of the present invention.

[0097] It should also be noted that the above is only an exemplary description of the specific structure of the pixel and its driving principle provided in the embodiment of the present invention, and the structure of the pixel and its driving principle in the embodiment of the present invention can be designed according to actual needs, and the embodiment of the present invention does not specifically limit this. For the convenience of description, unless otherwise specified, the embodiment of the present invention is based on Figure 8 Taking the structure of the pixel shown in FIG. 1 as an example, the technical solution of the embodiment of the present invention is exemplarily described.

[0098] Optional, Figure 11 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 11 The first scan signal Scan1 includes a data write pulse S1 and a dummy write pulse S0; the data write pulse S1 output by each first shift register unit 22 is shifted sequentially; during the display time DF of a frame, at least one dummy write pulse S0 of the same first scan signal Scan1 precedes the data write pulse S1. The display time DF of a frame includes a first refresh period TF1 and a second refresh period TF2; during the first refresh period TF1, the first shift register unit 22 of the first stage to the first shift register unit 22 of the X-1th stage sequentially outputs the data write pulse S1; during the second refresh period TF2, the first shift register unit 22 of the Xth stage to the first shift register unit 22 of the Nth stage sequentially outputs the data write pulse S1; N / 2<X≤N, and X is an integer; at least during the second refresh period TF2, the transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1, CK2, XCK2) is greater than or equal to the second preset duration.

[0099] Exemplary, reference Figure 11 The first shift register 21 can receive the first clock signal CK1, the second clock signal XCK1, the third clock signal CK2, and the fourth clock signal XCK2. The first-stage first shift register unit 22 can receive the first initial signal STV1 as an input signal. The second-stage first shift register unit 22 can receive the second initial signal STV1 as an input signal. The i-th first shift register unit 22 of the subsequent stage can receive the first scan signal Scan1(i-2) output by the i-2-th first shift register unit 22 as an input signal. At this time, i is a positive integer greater than 2 and less than or equal to N.

[0100] The first shift register unit 22 of the 4x+1 level can output the valid pulse of the first clock signal CK1 as the valid pulse of the first scan signal Scan1(4x+1); the first shift register unit 22 of the 4x+2 level can output the valid pulse of the third clock signal CK2 as the valid pulse of the first scan signal Scan1(4x+2); the first shift register unit 22 of the 4x+3 level can output the valid pulse of the second clock signal XCK1 as the valid pulse of the first scan signal Scan1(4x+3); the first shift register unit 22 of the 4x+4 level can output the valid pulse of the fourth clock signal XCK2 as the valid pulse of the first scan signal Scan1(4x+4); wherein x is a positive integer greater than or equal to 0.

[0101] For example, in the display time DF of one frame, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1, and the first two valid pulses are virtual write pulses S0, and the third valid pulse is a data write pulse S1. Figure 11 , X=N-7, starting from the first level to the X-1 level, the data write pulse S1 of the first scan signal Scan1(i) output by the first shift register unit 22 can overlap with the virtual write pulses S0 of two other first scan signals Scan1, wherein the data write pulse S1 of the first scan signal Scan1(i) can overlap with the second virtual write pulse S0 of the first scan signal Scan1(i+4), and at the same time, can also overlap with the first virtual write pulse S0 of the first scan signal Scan1(i+8), at this time, i is a positive integer less than X.

[0102] Starting from the Xth level to the Nth level, the data write pulse S1 of the first scan signal Scan1(i) output by the first shift register unit 22 only overlaps with the virtual write pulse S0 of one other first scan signal Scan1, or does not overlap with the virtual write pulse S0 of other first scan signals Scan1, wherein a part of the data write pulse S1 of the first scan signal Scan1(i) only overlaps with the second virtual write pulse S0 of the first scan signal Scan1(i+4), and another part of the data write pulse S1 of the first scan signal Scan1(i) does not overlap with the virtual write pulse S0, and at this time, i is an integer greater than or equal to X and less than or equal to N-4.

[0103] It can be seen from the above content that in at least part of the time period of the first refresh phase TF1, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is a first number; in at least part of the time period of the second refresh phase TF2, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is a second number; the first number is greater than the second number.

[0104] Continue to refer Figure 11From the first stage to the X-1 stage, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 can overlap with the two dummy write pulses S0. That is, in the first refresh period TF1, when data is written, a large number of first shift register units 22 control the same clock signal (CK1, XCK1, CK2 or XCK2) as the first scan signal Scan1, which will make the load of the clock signal line CL relatively large. As a result, when the valid pulse of the clock signal output by the first shift register unit 22 is output as the data write pulse S1 of the first scan signal Scan1, a large signal delay is generated, resulting in a slow process of the data write pulse S1 of the first scan signal Scan1 jumping from the valid level to the invalid level, and the coupling effect on some nodes in the pixel P is also less obvious, which is beneficial to the stability of the potential of the nodes in the pixel P.

[0105] Starting from the Xth level to the Nth level, the number of virtual write pulses S0 that overlap with the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 begins to decrease, that is, in the second refresh period TF2, when data is written, the number of first shift register units 22 that control the same clock signal (CK1, XCK1, CK2 or XCK2) as the first scan signal Scan1 is reduced, which will make the load of the signal line CL that transmits the clock signal (CK1, XCK1, CK2 or XCK2) smaller, resulting in less signal delay when the first shift register unit 22 outputs the valid pulse of the clock signal (CK1, XCK1) as the data write pulse S1 of the first scan signal Scan1.

[0106] By setting the transition time of the second voltage edge J2 of the clock signal to be greater than or equal to the second preset time at least in the second refresh period TF2, the transition speed of the second voltage edge J2 of the clock signal can be reduced. In this way, when the load on the clock line CL is reduced, the process of the data write pulse S1 of the first scan signal Scan1 jumping from the valid level to the invalid level can also be made slower, thereby reducing the coupling effect of the first scan signal Scan1 on the node, which is beneficial to balancing the display time DF of a frame of picture. Under different loads on the clock line CL, the transition speed of the data write pulse S1 of each first scan signal Scan1 from the valid level to the invalid level is improved, thereby improving the problem of uneven display of the display panel 01.

[0107] Among them, during the effective time of the virtual write pulse S0, the pixel P writes a data signal that does not correspond to the grayscale, such as the data signal of other rows, which is only used to improve the performance of the driving transistor, that is, when the virtual write pulse S0 jumps, the coupling effect on the node will not affect the data signal stored in the storage capacitor C. Therefore, the jumping process of the virtual write pulse S0 has little effect on the display grayscale of the light-emitting element LED. By setting the jumping time of the second voltage along J2 of the clock signal (CK1, XCK1, CK2, XCK2) to be greater than or equal to the second preset time in at least the second refresh period TF2, the process of the data write pulse S1 of the first scan signal Scan1 jumping from the valid level to the invalid level is improved, which can effectively improve the problem of uneven display.

[0108] In an optional embodiment, Figure 12 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 12 , in at least part of the first refresh period TF1, the transition duration of the second voltage along J2 of the clock signal (CK1, XCK1, CK2, XCK2) is the first transition duration △t1; in the second refresh period TF2, the transition duration of the second voltage along J2 of the clock signal (CK1, XCK1, CK2, XCK2) is the second transition duration △t2; the second transition duration △t2 is greater than the first transition duration △t1.

[0109] Specifically, in the first refresh period TF1, the load of the clock line CL is large, so that the transition process of the first scan signal Scan1 from the valid level to the invalid level is slow, and the coupling effect on the node of the driving transistor M3 is small; in the second refresh period TF2, the load of the clock line CL is small, and it is necessary to increase the transition time of the second voltage of the clock signal (CK1, XCK1, CK2, XCK2) along J2, so that the transition process of the first scan signal Scan1 from the valid level to the invalid level is also slow, so as to reduce the coupling effect on the node of the driving transistor M3.

[0110] Therefore, during at least a portion of the first refresh period TF1, there is no need to increase the first transition duration Δt1 of the second voltage edge J2 of the clock signals (CK1, XCK1, CK2, XCK2). Alternatively, the first transition duration Δt1 of the second voltage edge J2 of the clock signals (CK1, XCK1, CK2, XCK2) can be slightly increased so that the first transition duration Δt1 is shorter than the second transition duration Δt2. Without affecting the display effect, setting a shorter first transition duration Δt1 is beneficial for increasing the effective duration of the clock signals (CK1, XCK1, CK2, XCK2), thereby increasing the effective duration of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0111] In yet another optional embodiment, continue to refer to Figure 12 , the second refresh period TF2 includes a first sub-refresh stage TF01 and a second sub-refresh stage TF02; the first sub-refresh stage TF01 is located before the second sub-refresh stage TF02; in the first sub-refresh stage TF01, the jump duration of the second voltage edge J2 of the clock signal (CK1, XCK1, CK2, XCK2) is a third duration △t3; in the second sub-refresh stage TF02, the jump duration of the second voltage edge J2 of the clock signal (CK1, XCK1, CK2, XCK2) is a fourth duration △t4; the third duration △t3 is less than or equal to the fourth duration △t4.

[0112] For example, in the display time DF of one frame, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1, and the first two valid pulses are virtual write pulses S0, and the third valid pulse is a data write pulse S1. Figure 12 In the first sub-refresh phase TF01, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 only overlaps with a virtual write pulse S0 of another first scan signal Scan1; in the second sub-refresh phase TF02, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 does not overlap with the virtual write pulse S0 of other first scan signals Scan1.

[0113] Continue to refer Figure 12 From the first refresh period TF1 to the first sub-refresh stage TF01, the number of first shift register units 22 connected to the same clock line CL and having overlapping valid times of the first scan signal Scan1 decreases (from three to two); from the first sub-refresh stage TF01 to the second sub-refresh stage TF02, the number of first shift register units 22 connected to the same clock line CL and having overlapping valid times of the first scan signal Scan1 also decreases (from two to one). As a result, the load on the clock line CL gradually decreases from the first refresh period TF1 to the first sub-refresh stage TF01, and from the first sub-refresh stage TF01 to the second sub-refresh stage TF02.

[0114] In addition, in some embodiments, from the first refresh period TF1 to the second refresh period TF2, from the first sub-refresh stage TF01 to the second sub-refresh stage TF02, the distance between the first shift register unit 22 for outputting the first scan signal Scan1 and the driver chip (not shown in the figure) or the clock controller (not shown in the figure) for outputting the clock signal (CK1, XCK1, CK2, XCK2) also gradually decreases.

[0115] The reduced load of the clock line CL and the reduced distance between the first shift register unit 22 and the driver chip (not shown in the figure) or the clock controller (not shown in the figure) will both reduce the signal delay of the first shift register unit 22 outputting the clock signal as the first scanning signal Scan1. By setting the third time length △t3 to be less than or equal to the fourth time length △t4, the transition speed of the data write pulse S1 of each first scanning signal Scan1 from the valid level to the invalid level in the display time DF of a frame of picture can be balanced, which is also beneficial to increase the effective time length of the clock signal, thereby increasing the effective time length of the data write pulse S1 of the first scanning signal Scan1 and improving the charging rate of the data signal.

[0116] In another optional embodiment, the driving circuit 20 includes M clock lines; M≥2, and M is an even number; in the display time DF of a frame, the same first scan signal Scan1, Q virtual write pulses S0 are located before the data write pulse S1; Q≥1, and Q is an integer; N / 2<X≤N+1-Q×M.

[0117] For example, Figure 13 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 11-13 When M=4 and Q=2, starting from the N-7th stage to the Nth stage, the number of first shift register units 22 connected to the same clock line CL and having overlapping effective times of the first scan signal Scan1 is reduced compared with before, and the load of the clock line CL is also reduced compared with before. N / 2<X≤N-7 makes the second refresh period TF2 at least include the data write pulse S1 of the first scan signal Scan1 output by the first shift register units 22 from the N-7th stage to the Nth stage; when M=6 and Q=2, starting from the N-11th stage to the Nth stage, the number of first shift register units 22 connected to the same clock line CL and having overlapping effective times of the first scan signal Scan1 is reduced compared with before, and the load of the clock line CL is also reduced compared with before. N / 2<X≤N-11 makes the second refresh period TF2 at least include the data write pulse S1 of the first scan signal Scan1 output by the first shift register units 22 from the N-11th stage to the Nth stage. It is understandable that the number M of clock lines CL connected to the first shift register 21 of the driving circuit 20 can also be other integers, and the number Q of virtual write pulses S0 located before the data write pulse S1 of the same first scan signal Scan1 can also be other integers, which will not be explained one by one in the embodiments of the present invention.

[0118] By setting in the second refresh period TF2, the transition time of the second voltage edge J2 of the clock signal is greater than or equal to the second preset time, and N / 2<X≤N+1-Q×M, it can be ensured that the transition time of the second voltage edge J2 of the clock signal is increased at least when the load of the clock line CL is small, so as to balance the transition speed of the data write pulse S1 of each first scan signal Scan1 from the valid level to the invalid level under different loads of the clock line CL, thereby improving the problem of uneven display of the display panel 01.

[0119] On the basis of the above embodiment, Q=2; in the first sub-refresh phase TF01, the first shift register unit 22 of the Xth stage to the first shift register unit 22 of the NMth stage sequentially output the data write pulse S1; in the second sub-refresh phase TF02, the first shift register unit 22 of the N-M+1th stage to the first shift register unit 22 of the Nth stage sequentially output the data write pulse S1; the third time length △t3 is less than the fourth time length △t4.

[0120] Exemplary, reference Figure 11-13 When M=4, starting from the N-7th level to the N-4th level, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is 2, and starting from the N-3th level to the Nth level, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is 1. During at least part of the first sub-refresh phase TF01, the load of the clock line CL is less than the load of the clock line CL during at least part of the first sub-refresh phase TF01.

[0121] When M=6, starting from the N-11th level to the N-6th level, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is 2, and starting from the N-5th level to the Nth level, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is 1. During at least part of the first sub-refresh phase TF01, the load of the clock line CL is less than the load of the clock line CL during at least part of the first sub-refresh phase TF01.

[0122] By setting the first sub-refresh stage TF01 to include the data write pulse S1 output by the first shift register unit 22 from the Xth level to the NMth level, and the second sub-refresh stage TF02 to include the data write pulse S1 output by the first shift register unit 22 from the N-M+1th level to the Nth level, and the third time length △t3 is less than the fourth time length △t4, the transition speed of the data write pulse S1 of each first scan signal Scan1 from the valid level to the invalid level under different loads of the clock line CL can be balanced, and it is also beneficial to increase the effective time length of the clock signal, thereby increasing the effective time length of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0123] In another optional embodiment, the display panel also includes multiple second scan lines; at least some of the pixels located in the same row are electrically connected to the same second scan line; the second scan line is used to transmit a second scan signal; the second scan lines correspond one-to-one to the first scan lines, and at least some of the pixels located in the same row are electrically connected to the corresponding second scan line and the first scan line at the same time; the sth first scan line corresponds to the sth second scan line; the sth first scan line is electrically connected to the s+kth second scan line; 1≤s≤Nk, 1≤k≤Ns, and s and k are both integers; wherein, X=NQ×M-k+1.

[0124] For example, Figure 14 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 14 , k=2, starting from the first stage to the N-2 stage, the first shift register unit 22(s) is electrically connected to the s-th first scan line SL1 and the s+2-th second scan line SL2 at the same time, the first shift register units 22 of the first stage to the N-2 stage are all electrically connected to two scan lines (SL1 and SL2), and the loads of the first shift register units 22 of the first stage to the N-2 stage are the same; from the N-1 stage to the N stage, the first shift register unit 22 is all electrically connected to one first scan line SL1, the loads of the first shift register units 22 of the N-1 stage to the N stage are the same, and the loads of the first shift register units 22 of the N-1 stage to the N stage are less than the loads of the first shift register units 22 of the first stage to the N-2 stage.

[0125] Taking k=2, M=6, Q=2 as an example, X=N-13, starting from the N-13th stage to the Nth stage, the data write pulse S1 output by the first shift register unit 22 begins to overlap with the dummy write pulse S0 output by the first shift register unit 22 from the N-1th stage to the Nth stage, and / or, the number of dummy write pulses S0 overlapped by the data write pulse S1 output by the first shift register unit 22 decreases, so that the load of the clock line CL is also reduced. X=N-13 makes the second refresh period TF2 include the N-13th stage. The data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 of the Nth stage is transmitted. In the second refresh period TF2, the transition time length of the second voltage along J2 of the clock signals (CK1, XCK1, CK2, XCK2, CK3, XCK3) is greater than or equal to the second preset time length. This can balance the transition speed of the data write pulse S1 of each first scan signal Scan1 from the active level to the inactive level under different loads of the clock line CL, thereby improving the problem of uneven display on the display panel 01. Wherein, k can also be other integers, which will not be described one by one in the embodiments of the present invention.

[0126] On the basis of the above embodiment, Q=2; the second refresh period TF2 includes a first sub-phase t01, a second sub-phase t02, a third sub-phase t03, a fourth sub-phase t04 and a fifth sub-phase t05; in the first sub-phase t01, the first shift register unit 22 of the Xth stage to the first shift register unit 22 of the N-2×Mth stage sequentially outputs a data write pulse S1; in the second sub-phase t02, the first shift register unit 22 of the N-2×M+1th stage to the first shift register unit 22 of the NMkth stage sequentially outputs Data write pulse S1; in the third sub-stage t03, the first shift register unit 22 of the N-M+1-kth level to the first shift register unit 22 of the NMth level output the data write pulse S1 in sequence; in the fourth sub-stage t04, the first shift register unit 22 of the N-M+1th level to the first shift register unit 22 of the Nkth level output the data write pulse S1 in sequence; in the fifth sub-stage t05, the first shift register unit 22 of the N-k+1th level to the first shift register unit 22 of the Nth level output the data write pulse S1 in sequence.

[0127] In the ath sub-stage, the transition duration of the second voltage edge J2 of the clock signal is the fifth duration; in the bth sub-refresh stage, the transition duration of the second voltage edge of the clock signal is the sixth duration; 1≤a<b≤5, and a and b are both integers; wherein, the fifth duration is less than the sixth duration.

[0128] For example, take k=2, M=6, X=NQ×M-k+1=N-13 as an example, and continue to refer to Figure 14, in the first sub-phase t01, the first shift register unit 22 of the N-13th stage to the first shift register unit 22 of the N-12th stage outputs the data write pulse S1 in sequence; in the first sub-phase t01, the data write pulse S1 output by the first shift register unit 22 overlaps with the dummy write pulse S0 output by the first shift register unit 22 of the N-1th stage to the Nth stage, wherein the load of the first shift register unit 22 of the N-1th stage to the Nth stage is smaller than the load of other first shift register units 22. Therefore, in the first sub-phase t01, the load of the clock line CL is smaller than the load of the clock line CL in the first refresh phase TF1.

[0129] In the second sub-stage t02, the N-11th level first shift register unit to the N-8th level first shift register unit 22 sequentially output the data write pulse S1; in the second sub-stage t02, the data write pulse S1 output by the first shift register unit 22 overlaps with the virtual write pulse S0 output by another first shift register unit 22, and the number of virtual write pulses S0 overlapped by the data write pulse S1 output by the first shift register unit 22 is reduced. Therefore, in the second sub-stage t02, the load of the clock line CL is less than the load of the clock line CL in the first sub-stage t01.

[0130] In the third sub-stage t03, the first shift register unit of the N-7th stage to the first shift register unit 22 of the N-6th stage output the data write pulse S1 in sequence; in the third sub-stage t03, the data write pulse S1 output by the first shift register unit 22 overlaps with a virtual write pulse S0 output by the first shift register unit 22 of the N-1th stage to the Nth stage, therefore, in the third sub-stage t03, the load of the clock line CL is less than the load of the clock line CL in the second sub-stage t02.

[0131] In the fourth sub-stage t04, the N-5th-level first shift register unit to the N-2th-level first shift register unit 22 sequentially output the data write pulse S1; in the fourth sub-stage t04, the data write pulse S1 output by the first shift register unit 22 does not overlap with the virtual write pulse S0 output by other first shift register units 22, and the number of virtual write pulses S0 overlapping with the data write pulse S1 output by the first shift register unit 22 is reduced. Therefore, in the fourth sub-stage t04, the load of the clock line CL is less than the load of the clock line CL in the third sub-stage t03.

[0132] In the fifth sub-stage t05, the N-1th level first shift register unit to the Nth level first shift register unit 22 sequentially output the data write pulse S1; in the fifth sub-stage t05, the data write pulse S1 output by the first shift register unit 22 does not overlap with the virtual write pulse S0 output by other first shift register units 22, and the load of the first shift register unit 22 that outputs the data write pulse S1 is smaller than the loads of the other first shift register units 22. Therefore, in the fifth sub-stage t05, the load of the clock line CL is smaller than the load of the clock line CL in the fourth sub-stage t04.

[0133] By setting the fifth time duration to be smaller than the sixth time duration, it is possible to ensure that, in the first sub-phase t01, the transition time duration of the second voltage edge J2 of the clock signal is smaller than the transition time duration of the second voltage edge J2 of the clock signal in the second sub-phase t02; in the second sub-phase t02, the transition time duration of the second voltage edge J2 of the clock signal is smaller than the transition time duration of the second voltage edge J2 of the clock signal in the third sub-phase t03; and in the third sub-phase t03, the transition time duration of the second voltage edge J2 of the clock signal is smaller than the transition time duration of the second voltage edge J2 of the clock signal in the fourth sub-phase t04. In the fourth sub-stage t04, the transition time of the second voltage edge J2 of the clock signal is shorter than the transition time of the second voltage edge J2 of the clock signal in the fifth sub-stage t05. In this way, the different loads of the clock line CL can be finely divided, which is conducive to better balancing the transition speed of the data write pulse S1 of each first scan signal Scan1 from the valid level to the invalid level under the different loads of the clock line CL. It is also conducive to increasing the effective time of the clock signal, thereby increasing the effective time of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0134] Optional, Figure 15 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 15The first scan signal Scan1 includes a data write pulse S1 and a dummy write pulse S0; the data write pulse S1 output by each first shift register unit 22 is shifted sequentially; during the display time DF of a frame, at least one dummy write pulse S0 of the same first scan signal Scan1 is located after the data write pulse S1. The display time DF of a frame includes a third refresh phase TF3 and a fourth refresh phase TF4; during the third refresh period TF3, the first shift register unit 22 of the first stage to the first shift register unit 22 of the Zth stage sequentially outputs the data write pulse S1; 1≤Z<N / 2, and Z is an integer; during the fourth refresh phase TF3, the first shift register unit 22 of the Z+1th stage to the first shift register unit 22 of the Nth stage sequentially outputs the data write pulse S1; at least during the third refresh period TF3, the transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1, CK2, XCK2) is greater than or equal to the second preset duration.

[0135] For example, in the display time DF of one frame, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1, and the first valid pulse is the data write pulse S1, and the last two valid pulses are virtual write pulses S0. Figure 15 , Z=8, starting from the first level to the Zth level, the data write pulse S1 of the first scan signal Scan1(i) output by the first shift register unit 22 does not overlap with the virtual write pulse S0 of other first scan signals Scan1, or only overlaps with the virtual write pulse S0 of one other first scan signal Scan1, wherein a part of the data write pulse S1 of the first scan signal Scan1(i) does not overlap with the virtual write pulse S0, and another part of the data write pulse S1 of the first scan signal Scan1(i) only overlaps with the second virtual write pulse S0 of the first scan signal Scan1(i-4), at this time, i is an integer greater than or equal to 5 and less than or equal to Z.

[0136] Starting from the Z+1th level to the Nth level, the data write pulse S1 of the first scan signal Scan1(i) output by the first shift register unit 22 can overlap with the virtual write pulses S0 of two other first scan signals Scan1, wherein the data write pulse S1 of the first scan signal Scan1(i) can overlap with the second virtual write pulse S0 of the first scan signal Scan1(i-4), and at the same time, it can also overlap with the first virtual write pulse S0 of the first scan signal Scan1(i-8), at this time, i is an integer greater than or equal to Z+1 and less than or equal to N.

[0137] From the above content, it can be seen that in at least part of the time period of the third refresh stage TF3, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is the third number; in at least part of the time period of the fourth refresh stage TF4, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is the fourth number; the third number is greater than the fourth number.

[0138] Continue to refer Figure 15 From the 1st stage to the Zth stage, the data write pulse S1 output by the first shift register unit 22 for the first scan signal Scan1 overlaps with a small number of dummy write pulses S0. That is, in the third refresh period TF3, when data is written, the number of first shift register units 22 that control the same clock signal (CK1, XCK1, CK2, or XCK2) as the first scan signal Scan1 is small, which results in a relatively small load on the clock signal line CL. From the Z+1th stage to the Nth stage, the data write pulse S1 output by the first shift register unit 22 for the first scan signal Scan1 can overlap with two dummy write pulses S0. That is, in the fourth refresh period TF4, when data is written, the number of first shift register units 22 that control the same clock signal (CK1, XCK1, CK2, or XCK2) as the first scan signal Scan1 is large, which results in a relatively large load on the clock signal line CL.

[0139] By setting the transition time of the second voltage edge J2 of the clock signal clock signal to be greater than or equal to the second preset time length at least in the third refresh period TF3, the transition speed of the second voltage edge J2 of the clock signal clock signal can be reduced, and the transition speed of the data write pulse S1 of each first scan signal Scan1 from the valid level to the invalid level under different loads of the clock line CL can be balanced, thereby improving the problem of uneven display of the display panel 01.

[0140] In an optional embodiment, Figure 16 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 16 In the third refresh period TF3, the transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1, CK2, XCK2) is the seventh duration △t7; in at least part of the fourth refresh period TF4, the transition duration of the second voltage edge J2 of the clock signal (CK1, XCK1, CK2, XCK2) is the eighth duration △t8; the seventh duration △t7 is greater than the eighth duration △t8.

[0141] Specifically, during the third refresh period TF3, the load on the clock line CL is relatively small, and the transition duration of the second voltage edge J2 of the clock signals (CK1, XCK1, CK2, XCK2) needs to be increased, so that the transition process of the first scan signal Scan1 from the active level to the inactive level is slower, thereby reducing the coupling effect on the node of the drive transistor M3. During at least part of the fourth refresh period TF4, it is not necessary to increase the eighth duration Δt8 of the second voltage edge J2 of the clock signals (CK1, XCK1, CK2, XCK2). Alternatively, the eighth duration Δt8 of the second voltage edge J2 of the clock signals (CK1, XCK1, CK2, XCK2) can be slightly increased, so that the eighth duration Δt8 is less than the seventh duration Δt7. This is beneficial for increasing the effective duration of the clock signals (CK1, XCK1, CK2, XCK2), thereby increasing the effective duration of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0142] In another alternative embodiment, continue to refer to Figure 16 , the third refresh period TF3 includes a third sub-refresh stage TF03 and a fourth sub-refresh stage TF04; the third sub-refresh stage TF03 is located before the fourth sub-refresh stage TF04; in the third sub-refresh stage TF03, the jump duration of the second voltage edge J2 of the clock signal (CK1, XCK1, CK2, XCK2) is the ninth time length △t9; in the fourth sub-refresh stage TF04, the jump duration of the second voltage edge J2 of the clock signal (CK1, XCK1, CK2, XCK2) is the tenth time length △t10; the ninth time length △t9 is greater than or equal to the tenth time length △t10.

[0143] For example, in the display time DF of one frame, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1, and the first valid pulse is the data write pulse S1, and the last two valid pulses are virtual write pulses S0. Figure 16 In the third sub-refresh stage TF03, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 does not overlap with the virtual write pulse S0 of other first scan signals Scan1; in the fourth sub-refresh stage TF04, the data write pulse S1 of the first scan signal Scan1 output by the first shift register unit 22 only overlaps with one other virtual write pulse S0 of the first scan signal Scan1.

[0144] Continue to refer Figure 16From the third sub-refresh stage TF03 to the fourth sub-refresh stage TF04, the number of first shift register units 22 connected to the same clock line CL and having overlapping effective times of the first scan signal Scan1 increases (from one to two), and the load of the clock line CL increases; from the fourth sub-refresh stage TF04 to the fourth refresh period TF4, the number of first shift register units 22 connected to the same clock line CL and having overlapping effective times of the first scan signal Scan1 also increases (from two to three), and the load of the clock line CL increases.

[0145] The increase in the load of the clock line CL will increase the signal delay of the clock signal (CK1, XCK1, CK2 or XCK2) output by the first shift register unit 22 as the first scan signal Scan1. The data write pulse S1 of the first scan signal Scan1 in different refresh periods has different transition speeds from the valid level to the invalid level, and the coupling effect on the nodes in the pixel is also different, resulting in different degrees of deviation in the data signals stored in the storage capacitors C in the pixel circuits in different areas. By setting the ninth time duration △t9 to be greater than or equal to the tenth time duration △t10, the transition speed of the data write pulse S1 of each first scan signal Scan1 from the valid level to the invalid level in the display time DF of a frame of picture can be balanced, which is also beneficial to increasing the effective time of the clock signal (CK1, XCK1, CK2, XCK2), thereby increasing the effective time of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0146] In another optional embodiment, the driving circuit 20 includes M clock lines; M≥2, and M is an even number; in the display time DF of a frame, the same first scan signal Scan1, P virtual write pulses S0 are located after the data write pulse S1; P≥1, and P is an integer; P×M≤z<N / 2.

[0147] For example, Figure 17 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 15-17When M=4 and P=2, the number of first shift register units 22 connected to the same clock line CL and overlapping with the effective time of the first scan signal Scan1 in the 9th to Nth stages increases compared with before, and the load of the clock line CL also increases compared with before. 8≤z<N / 2 makes the third refresh period TF3 at least include the data write pulses S1 of the first scan signal Scan1 output by the first shift register units 22 of the first to eighth stages; when M=6 and P=2, the number of first shift register units 22 connected to the same clock line CL and overlapping with the effective time of the first scan signal Scan1 in the thirteenth to Nth stages increases compared with before, and the load of the clock line CL also increases compared with before. 12≤z<N / 2 makes the third refresh period TF3 at least include the data write pulses S1 of the first scan signal Scan1 output by the first shift register units 22 of the first to twelfth stages. It is understandable that the number M of clock lines CL connected to the first shift register 21 of the driving circuit 20 can also be other integers, and the number P of virtual write pulses S0 located after the data write pulse S1 of the same first scan signal Scan1 can also be other integers, which will not be explained one by one in the embodiments of the present invention.

[0148] By setting in the third refresh period TF3, the transition time of the second voltage edge J2 of the clock signal is greater than or equal to the second preset time, and P×M≤z<N / 2, it can be ensured that the transition time of the second voltage edge J2 of the clock signal is increased at least when the load of the clock line CL is small, so as to balance the transition speed of the data write pulse S1 of each first scan signal Scan1 from the valid level to the invalid level under different loads of the clock line CL, thereby improving the problem of uneven display of the display panel 01.

[0149] On the basis of the above embodiment, P=2; in the third sub-refresh phase TF03, the first-level first shift register unit 22 to the M-th-level first shift register unit 22 sequentially output the data write pulse S1; in the fourth sub-refresh phase TF04, the M+1-th-level first shift register unit 22 to the 2×M-th-level first shift register unit 22 sequentially output the data write pulse S1; the ninth time duration △t9 is greater than the tenth time duration △t10.

[0150] Exemplary, reference Figure 15-17 When M=4, from the first stage to the fourth stage, the number of the first shift register units 22 connected to the same clock line CL and having overlapping effective times of the first scan signal Scan1 is 1, and from the fifth stage to the eighth stage, the number of the first shift register units 22 connected to the same clock line CL and having overlapping effective times of the first scan signal Scan1 is 2. During at least a portion of the fourth sub-refresh phase TF04, the load of the clock line CL is greater than the load of the clock line CL during at least a portion of the third sub-refresh phase TF03.

[0151] When M=6, from the first level to the sixth level, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is 1; from the seventh level to the twelfth level, the number of first shift register units 22 connected to the same clock line CL and whose effective times overlap with the first scan signal Scan1 is 2; and during at least part of the fourth sub-refresh stage TF04, the load of the clock line CL is greater than the load of the clock line CL during at least part of the third sub-refresh stage TF03.

[0152] By setting the third sub-refresh stage TF03 to include the data write pulse S1 output by the first shift register unit 22 from the first level to the M-th level, and the fourth sub-refresh stage TF04 to include the data write pulse S1 output by the first shift register unit 22 from the M+1-th level to the 2×M-th level, and the ninth time length △t9 is greater than the tenth time length △t10, the transition speed of the data write pulse S1 of each first scan signal Scan1 from the valid level to the invalid level under different loads of the clock line CL can be balanced, and it is also beneficial to increase the effective time of the clock signal, thereby increasing the effective time of the data write pulse S1 of the first scan signal Scan1 and improving the charging rate of the data signal.

[0153] Optionally, the number of the first shift register units 22 connected to the same clock line CL and outputting the first scan signals Scan1 with overlapping valid times is less than or equal to 2.

[0154] Exemplary, reference Figure 17 For the display time DF of one frame, the first shift register unit 22 can output three valid pulses of the first scan signal Scan1, and the first valid pulse is the data write pulse S1, and the last two valid pulses are both virtual write pulses S0. The maximum number of first shift register units 22 connected to the same clock line CL and having overlapping valid times of the output first scan signal Scan1 is 3, and the minimum is 1. The maximum difference in the load of the clock line CL is large, resulting in more cases where the load of the clock line CL is small, and the refresh time of the clock line CL with uneven load is also long, resulting in more areas where abnormal display brightness is likely to occur.

[0155] In an optional embodiment, Figure 18 This is a structural diagram and timing diagram of another driving circuit provided by the present invention, referring to Figure 18 In the display time DF of a frame, the first scan signal Scan1 includes a data writing pulse S1 and a dummy writing pulse S0.

[0156] For the display time DF of one frame, the first shift register unit 22 can output two valid pulses of the first scan signal Scan1, and the first valid pulse is the data write pulse S1, and the second valid pulse is the dummy write pulse S0, or the first valid pulse is the dummy write pulse S0, and the second valid pulse is the data write pulse S1 (not shown in the figure). When the first shift register unit 22 of the first four stages or the last four stages (not shown in the figure) outputs the data write pulse S1, the number of first shift register units 22 connected to the same clock line CL and whose valid times of the output first scan signal Scan1 overlap is 1; when the first shift register units 22 of other stages output the data write pulse S1, the number of first shift register units 22 connected to the same clock line CL and whose valid times of the output first scan signal Scan1 overlap is 2. The maximum difference in the load of the clock line CL is small, so that the situation where the load of the clock line CL is small is rare, the refresh time of the uneven load of the clock line CL is short, and the number of areas prone to abnormal display brightness is small.

[0157] By setting the maximum number of first shift register units 22 connected to the same clock line CL and having overlapping effective times of the output first scanning signal Scan1 to 2 during the display time DF of a frame, on the one hand, the load of the clock line CL is relatively small, and the signal delay of the first shift register unit 22 outputting the clock signal as the first scanning signal Scan1 is also relatively small. In this way, the thrust of the voltage edge of the clock signal can be set to be relatively small, which is beneficial to reducing power consumption; on the other hand, the maximum difference in the load change of the clock line CL can be reduced, and the situation where the load of the clock line CL is relatively small can also be reduced, thereby shortening the refresh time of the uneven load of the clock line CL and reducing the area where abnormal display brightness is prone to occur; in addition, the period in which the jump time of the second voltage edge J needs to be increased can be shortened, thereby reducing the impact on the clock signal in other periods, which is beneficial to increasing the effective time of the clock signal and the effective time of the data write pulse S1 of the first scanning signal Scan1, thereby improving the charging rate of the data signal.

[0158] On the basis of the above embodiment, the pixel circuit 11 is Figure 8 Taking the 7T1C circuit shown as an example, during the display time DF of a frame, the first shift register unit 22 can output two valid pulses of the first scan signal Scan1, and the first valid pulse is the data write pulse S1, and the second valid pulse is the dummy write pulse S0. In an optional embodiment, the dummy write pulse S0 can be located after the write phase t2 and after the light-emitting phase t3, as shown in FIG. Figure 19 As shown, after the pixel P displays light, the driving transistor M3 is bias-adjusted to improve the performance of the driving transistor M3.

[0159] In another optional embodiment, the dummy write pulse S0 may also be located after the write phase t2 and before the light emitting phase t3, as shown in FIG. Figure 20 As shown, the driving transistor M3 is bias-adjusted before the pixel P displays light emission, wherein this embodiment is applicable to the case where the compensation transistor M5 and the write transistor M2 receive different scanning signals (not shown in the figure). During the effective time of the virtual write pulse S0, when the driving transistor M3 is bias-adjusted before the pixel P displays light emission, the compensation transistor M5 needs to be turned off to avoid the data signals of other rows used for bias adjustment being written into the gate of the driving transistor M3 during the effective time of the virtual write pulse S0, thereby affecting the displayed grayscale.

[0160] Optionally, during the display time DF of a frame, the first scan signal Scan1 includes a first virtual write pulse S01, a data write pulse S1 and a second virtual write pulse S02; wherein, during the display time DF of a frame, the data write pulse S1 is located between the first virtual write pulse S01 and the second virtual write pulse S02.

[0161] For example, Figure 21 This is a structural diagram and timing diagram of another driving circuit provided by an embodiment of the present invention, referring to Figure 21 The driving circuit 20 includes four clock lines CL. When the first shift register unit 22 outputs the data write pulse S1, the maximum number of first shift register units 22 connected to the same clock line CL and having overlapping effective times of the first scan signal Scan1 is 3, and the minimum number is 2. On the one hand, the maximum difference in the load change of the clock line CL can be narrowed, and the situation where the load of the clock line CL is too small can be reduced. Therefore, when increasing the jump duration of the second voltage edge J2 of the clock signal in part of the display time DF of each frame, it does not need to be increased too long, which can reduce the impact on the effective time, increase the charging rate of the data signal, and do not need to design too much jump duration of the second voltage edge J2 based on the situation where the load is too small, which can simplify the timing design; on the other hand, before and after data writing, a bias adjustment is performed, which can better adjust the state of the driving transistor, which is beneficial to extending the service life of the driving transistor and improving the display quality.

[0162] Based on the above embodiment, the pixel circuit 11 is used as Figure 8 Take the 7T1C circuit shown as an example, Figure 22 This is a timing diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 22The first dummy write pulse S01 can be located before the initialization stage t1, and the second dummy write pulse S02 can be located after the light-emitting stage t3. In this way, the driving transistor M3 can be biased and adjusted before the pixel P is initialized, and the driving transistor M3 can be biased and adjusted again after the pixel P displays light, which can prevent the driving transistor M3 of the pixel circuit 11 from being at a certain potential for a long time, affecting the performance of the driving transistor M3.

[0163] In other embodiments, the second dummy write pulse S02 may also be located before the light emitting phase t3, such as Figure 23 As shown, the driving transistor M3 is bias-adjusted again before the pixel P displays light emission, wherein this embodiment is applicable to the case where the compensation transistor M5 and the write transistor M2 receive different scanning signals (not shown in the figure). During the effective time of the second virtual write pulse S02, when the driving transistor M3 is bias-adjusted before the pixel P displays light emission, the compensation transistor M5 needs to be turned off to avoid the data signals of other rows used for bias adjustment being written into the gate of the driving transistor M3 during the effective time of the second virtual write pulse S02, thereby affecting the displayed grayscale.

[0164] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Figure 24 is a structural diagram of a display device provided by an embodiment of the present invention, such as Figure 24 As shown, the display device 02 includes a display panel 01 provided by any embodiment of the present invention. The display device 02 provided by the embodiment of the present invention can be Figure 24 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0165] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: A driving circuit, a plurality of pixels arranged in an array, a plurality of first scanning lines, and a plurality of clock lines; At least part of the pixels in the same row are electrically connected to the same first scanning line; The driving circuit is electrically connected to each of the first scan lines respectively; the driving circuit includes N cascaded first shift register units; the clock line is electrically connected to the plurality of first shift register units; the first shift register unit is configured to receive at least an input signal and a clock signal on the clock line, and control the clock signal of the clock line to be provided as a first scan signal to the first scan line; The effective times of the first scanning signals of at least part of the first shift register units connected to the same clock line overlap; The process of the clock signal jumping from the invalid level to the valid level is a first voltage edge, and the process of the clock signal jumping from the valid level to the invalid level is a second voltage edge; During at least a portion of the display time of a frame of picture, the transition duration of the second voltage edge of the clock signal is greater than or equal to a second preset duration.

2. The display panel according to claim 1, wherein: The second preset time length is greater than or equal to 600 ns and less than or equal to 700 ns.

3. The display panel according to claim 1, wherein: The second preset duration is greater than or equal to 26% of the duration of the effective level of the clock signal, and less than or equal to 30% of the duration of the effective level.

4. The display panel according to claim 1, wherein: During at least a portion of a display time of a frame of picture, the second voltage edge of the clock signal includes at least two second sub-voltage edges; Among them, the second sub-voltage edge is the process of the clock signal jumping from the first sub-level to the second sub-level; the first sub-level and / or the second sub-level is located between the invalid level and the valid level; the absolute value of the difference between the first sub-level and the valid level is smaller than the absolute value of the difference between the second sub-level and the valid level; the absolute value of the difference between the second sub-level and the invalid level is smaller than the absolute value of the difference between the first sub-level and the invalid level.

5. The display panel according to claim 1, wherein: During at least a portion of a display time of a frame of picture, the thrust of the second voltage edge of the clock signal is less than a second preset thrust.

6. The display panel according to claim 1, wherein: During the display time of one frame, the first scanning signal includes a data writing pulse and at least one dummy writing pulse; The data write pulses of the first scan signals Scan1(i) output by some of the first shift register units overlap with the virtual write pulses of the first scan signals Scan1(j) output by other first shift register units, where i and j are both positive integers less than or equal to N, and i≠j.

7. The display panel according to claim 1, wherein: The first scanning signal includes a data write pulse and a dummy write pulse; the data write pulses output by the first shift register units of each stage are shifted in sequence; During the display time of one frame, at least one dummy write pulse of the same first scanning signal is located before the data write pulse; The display time of one frame includes a first refresh period and a second refresh period; In the first refresh phase, the first shift register unit of the first stage to the first shift register unit of the X-1 stage sequentially output the data write pulse; In the second refresh period, the first shift register unit of the Xth stage to the first shift register unit of the Nth stage sequentially output the data write pulse; N / 2<X≤N, and X is an integer; At least in the second refresh period, the transition duration of the second voltage edge of the clock signal is greater than or equal to the second preset duration.

8. The display panel according to claim 7, wherein: During at least a portion of the first refresh phase, the number of the first shift register units connected to the same clock line and having overlapping valid times of the first scan signals is a first number; During at least a portion of the second refresh phase, the number of the first shift register units connected to the same clock line and having overlapping valid times of the first scan signals is a second number; The first number is greater than the second number.

9. The display panel according to claim 7, wherein: During at least a portion of the first refresh period, a transition duration of the second voltage edge of the clock signal is the first transition duration; In the second refresh period, the transition duration of the second voltage edge of the clock signal is a second transition duration; The second jump duration is greater than the first jump duration.

10. The display panel according to claim 7, wherein: The second refresh period includes a first sub-refresh phase and a second sub-refresh phase; the first sub-refresh phase is located before the second sub-refresh phase; In the first sub-refresh phase, a transition duration of the second voltage edge of the clock signal is a third duration; In the second sub-refresh phase, the transition duration of the second voltage edge of the clock signal is a fourth duration; The third duration is less than or equal to the fourth duration.

11. The display panel according to claim 10, wherein: The driving circuit includes M clock lines; M ≥ 2, and M is an even number; During the display time of one frame, for the same first scanning signal, Q dummy write pulses are located before the data write pulse; Q ≥ 1, and Q is an integer; N / 2<X≤N+1-Q×M.

12. The display panel according to claim 11, wherein: Q＝2； In the first sub-refresh phase, the first shift register unit of the Xth stage to the first shift register unit of the NMth stage sequentially output the data write pulse; in the second sub-refresh phase, the first shift register unit of the N-M+1th stage to the first shift register unit of the Nth stage sequentially output the data write pulse; The third duration is shorter than the fourth duration.

13. The display panel according to claim 11, wherein: The display panel further includes a plurality of second scan lines; at least some of the pixels in the same row are electrically connected to the same second scan line; the second scan line is used to transmit a second scan signal; The second scan lines correspond to the first scan lines one-to-one, and at least part of the pixels in the same row are electrically connected to the corresponding second scan lines and the first scan lines at the same time; The sth first scan line corresponds to the sth second scan line; the sth first scan line is electrically connected to the s+kth second scan line; 1≤s≤Nk, 1≤k≤Ns, and s and k are both integers; Where, X = NQ × M-k+1.

14. The display panel according to claim 13, wherein: Q=2; the second refresh period includes a first sub-phase, a second sub-phase, a third sub-phase, a fourth sub-phase and a fifth sub-phase; In the first sub-stage, the first shift register unit of the Xth stage to the first shift register unit of the N-2×Mth stage sequentially output the data write pulse; in the second sub-stage, the first shift register unit of the N-2×M+1th stage to the first shift register unit of the NMkth stage sequentially output the data write pulse; in the third sub-stage, the first shift register unit of the N-M+1-kth stage to the first shift register unit of the NMth stage sequentially output the data write pulse; in the fourth sub-stage, the first shift register unit of the N-M+1th stage to the first shift register unit of the Nkth stage sequentially output the data write pulse; in the fifth sub-stage, the first shift register unit of the N-k+1th stage to the first shift register unit of the Nth stage sequentially output the data write pulse; In the a-th sub-phase, the transition duration of the second voltage edge of the clock signal is a fifth duration; In the bth sub-refresh phase, the transition duration of the second voltage edge of the clock signal is a sixth duration; 1≤a<b≤5, and a and b are both integers; The fifth duration is shorter than the sixth duration.

15. The display panel according to claim 1, wherein The first scanning signal includes a data write pulse and a dummy write pulse; the data write pulses output by the first shift register units of each stage are shifted in sequence; During the display time of one frame, at least one dummy write pulse of the same first scanning signal is located after the data write pulse; The display time of one frame includes the third refresh phase and the fourth refresh phase; In the third refresh period, the first shift register unit of the first stage to the first shift register unit of the Zth stage sequentially output the data write pulse; 1≤Z<N / 2, and Z is an integer; In the fourth refresh phase, the first shift register unit of the Z+1th stage to the first shift register unit of the Nth stage sequentially output the data write pulse; At least in the third refresh period, the transition duration of the second voltage edge of the clock signal is greater than or equal to the second preset duration.

16. The display panel according to claim 15, wherein: During at least a portion of the third refresh phase, the number of the first shift register units connected to the same clock line and having overlapping valid times of the first scan signals is a third number; During at least a portion of the fourth refresh phase, the number of the first shift register units connected to the same clock line and having overlapping valid times of the first scan signals is a fourth number; The third number is smaller than the fourth number.

17. The display panel according to claim 15, wherein: In the third refresh period, the transition duration of the second voltage edge of the clock signal is a seventh duration; During at least a portion of the fourth refresh period, a transition duration of the second voltage edge of the clock signal is an eighth duration; The seventh duration is greater than the eighth duration.

18. The display panel according to claim 15, wherein: The third refresh period includes a third sub-refresh phase and a fourth sub-refresh phase; the third sub-refresh phase is located before the fourth sub-refresh phase; In the third sub-refresh phase, the transition duration of the second voltage edge of the clock signal is a ninth duration; In the fourth sub-refresh phase, the transition duration of the second voltage edge of the clock signal is a tenth duration; The ninth duration is greater than or equal to the tenth duration.

19. The display panel according to claim 18, wherein: The driving circuit includes M clock lines; M ≥ 2, and M is an even number; During the display time of one frame, for the same first scanning signal, the P dummy write pulses are located after the data write pulse; P ≥ 1, and P is an integer; P×M≤z<N / 2.

20. The display panel according to claim 19, wherein P＝2； In the third sub-refresh phase, the first shift register unit of the first stage to the first shift register unit of the Mth stage sequentially output the data write pulse; in the fourth sub-refresh phase, the first shift register unit of the M+1th stage to the first shift register unit of the 2×Mth stage sequentially output the data write pulse; The ninth duration is greater than the tenth duration.

21. The display panel according to claim 1, wherein During at least a portion of the display time of a frame of image, the transition duration of the first voltage edge of the clock signal is greater than or equal to a first preset duration.

22. The display panel according to claim 1, wherein The number of the first shift register units connected to the same clock line and having the first scan signals outputted with overlapping effective times is less than or equal to 2.

23. The display panel according to claim 22, wherein: During the display time of one frame, the first scanning signal includes a data writing pulse and a dummy writing pulse.

24. The display panel according to claim 1, wherein During the display time of one frame, the first scanning signal includes a first dummy write pulse, a data write pulse, and a second dummy write pulse; In the display time of one frame, the data write pulse is located between the first dummy write pulse and the second dummy write pulse.

25. A display device, characterized in that: include: The display panel according to any one of claims 1 to 24.

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