Efficient power scheme for redundancy

Abstract

The invention relates to an efficient power scheme for redundancy. A memory device may include circuitry that stores memory address information related to one or more defective or unreliable memory components and compares the memory address information to a memory address that is a target of a memory access operation. The memory device may selectively allocate a target memory address to one or more circuits within the circuitry based on whether the one or more circuits store memory address information. Additionally or alternatively, the memory device may selectively power one or more circuits within the circuitry based on whether the circuits store memory address information.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with the application date of May 29, 2020, the invention name of which is “High-efficiency power solution for redundancy” and the application number is 202010473217.X.

[0003] Cross Reference

[0004] This patent application claims priority to U.S. patent application No. 16 / 446,457 to Fackenthal et al., entitled “EFFICIENT POWER SCHEME FOR REDUNDANCY,” filed on June 19, 2019, which is assigned to its assignee, and the entire contents of which are expressly incorporated herein by reference.

[0005] The technical field relates to efficient power schemes for redundancy. Background Art

[0006] The following generally relates to a system including at least one memory device, and more particularly, to an efficient power scheme for redundancy.

[0007] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, most commonly, binary devices store one of two states represented by a logical "1" or a logical "0". In other devices, more than two states may be stored. To access stored information, a component of the device may read or sense at least one stored state in the memory device. To store information, a component of the device may write or program a state in the memory device.

[0008] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and other memories. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for an extended period of time even in the absence of an external power source. Volatile memory devices (e.g., DRAM) may lose their stored state when disconnected from an external power source. FeRAM may be able to achieve densities similar to volatile memory, but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices.

[0009] Some memory devices can improve reliability by tracking memory components (e.g., access lines or memory cells) that have been identified as having problems. However, memory devices using circuitry associated with the identified problems may consume excessive power. Techniques for reducing power consumption at memory devices may be needed. Summary of the invention

[0010] An apparatus is described. The apparatus includes: a first latch configured to store an address bit associated with an access line identified as defective; a second latch configured to store at least one bit indicating that the first latch is storing the address bit; a first logic component coupled to the first latch and configured to perform a logic operation on a signal representing the address bit stored at the first latch; and a second logic component coupled to the second latch and configured to send a second signal representing a second address bit associated with an access line selected for a memory access operation to the first logic component based at least in part on the at least one bit stored at the second latch.

[0011] A method is described. The method includes storing at a first latch a first address bit associated with a memory component identified as unreliable, storing at a second latch an enable bit indicating that the first latch is storing the first address bit, performing a logic operation on a signal representing the enable bit and a second address bit associated with a memory component selected for a memory access operation, and outputting, based at least in part on the logic operation, a signal representing the second address bit to a logic component coupled to the first latch.

[0012] An apparatus is described. The apparatus includes: a set of latches configured to store memory address information; a latch configured to store at least one bit indicating whether the set of latches stores a memory address associated with an access line identified as defective; a power supply coupled to the set of latches and the latch; and a switching component coupled to the latch and configured to activate or deactivate based at least in part on the at least one bit stored at the latch.

[0013] A method is described. The method includes storing at a set of latches a memory address associated with a memory component identified as unreliable; storing at least one bit at the latch indicating that the set of latches is storing the memory address; sending a signal representing the at least one bit to a switching component coupled to the set of latches and a power supply; and activating the switching component based at least in part on the signal representing the at least one bit to couple the power supply with the set of latches. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 An example of a system supporting a high-efficiency power scheme for redundancy according to examples disclosed herein is described.

[0015] Figure 2

[0013] An example of a memory die supporting a high efficiency power scheme for redundancy according to examples disclosed herein is illustrated.

[0016] Figures 3 to 7

[00136] An example of circuitry supporting a high-efficiency power scheme for redundancy according to examples disclosed herein is described.

[0017] Figure 8 A block diagram is shown of a device supporting a high-efficiency power scheme for redundancy according to examples disclosed herein.

[0018] Fig. 9 and 10 A flow chart illustrating a method of supporting an efficient power scheme for redundancy according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0019] Some memory devices can increase reliability by tracking memory components (e.g., access lines or memory cells) that have been identified as defective or unreliable. For example, a memory device can include circuitry that stores addresses of defective memory components and indicates when one of the addresses is the target of an upcoming memory access operation. This indication can allow the memory device to avoid using the defective memory component, thereby increasing reliability. However, a memory device using this circuitry may consume too much power. Among other benefits, the present disclosure describes aspects related to reducing power consumption.

[0020] The power consumed by a memory device implementing redundancy can be reduced by selectively assigning memory addresses that are targets of memory access operations. For example, the memory device can provide the target memory addresses to one or more components used for redundancy but not to other components. Additionally or alternatively, the memory device can selectively isolate one or more components of the memory device from power when the components are not in use. For example, the memory device can be connected to power one or more components used for redundancy but not to other components.

[0021] A memory device may implement redundancy to increase the reliability of its operation and data. In a redundancy scheme, a memory device may inspect its memory components (e.g., access lines, memory cells, etc.) and identify defective or unreliable components. The memory device may store the addresses of defective or unreliable components so that when defective or unreliable components are the target of a memory operation, the device may detect as many defective or unreliable components as possible and use different (e.g., non-defective, reliable) components instead.

[0022] To achieve this, the addresses of defective or unreliable memory components may be stored in one or more circuits referred to as repair solutions or repair circuits. For a given region of memory, there may be one or more (e.g., many) repair circuits, and at least some of the repair circuits (if not every repair circuit) may include one or more latches for storing the addresses of defective memory components. When a memory device targets a memory component for an access operation, the memory device may determine whether the memory component is defective by comparing the address of the memory component with the address stored by the repair circuit. Because the device does not know which repair circuit (if any) stores an address that matches the address of the target memory component, the device may provide the target memory address to each repair circuit for comparison. However, providing the target memory address to each repair circuit may waste power because not every repair circuit may be in use (e.g., currently storing a memory address).

[0023] According to the techniques described herein, a memory device can save power by selectively providing a target memory address to one or more sets of repair circuits having at least one repair circuit in use. Thus, the memory device can avoid providing the target memory address to one or more sets of repair circuits that are not in use, which saves power and has other benefits. Additionally or alternatively, the memory device can save power by selectively powering down latches that are not in use (e.g., storing addresses for defective memory components).

[0024] First, refer to Figures 1 to 3 Features of the present invention are described in the context of the memory system and memory die described. Figures 3 to 7 Features of the present invention are described in the context of redundant circuit systems described herein. Figures 8 to 10 These and other features of the present invention are further illustrated and described with reference to a memory controller diagram and flow chart associated with a highly efficient power scheme for redundancy.

[0025] Figure 1 An example of a system 100 utilizing one or more memory devices according to examples disclosed herein is illustrated. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0026] System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop, a tablet, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. Memory device 110 may be a component of the system configured to store data for one or more other components of system 100. In some examples, system 100 is capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0027] At least a portion of system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, or the like. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device.

[0028] In some cases, memory device 110 may be a standalone device or component that is configured to communicate with other components of system 100 and provide a physical memory address / space that is potentially used or referenced by system 100. In some examples, memory device 110 may be configured to work with at least one type of system 100 or multiple different types of systems 100. Signaling between components of system 100 and memory device 110 may operate to support modulation schemes to modulate signals, different pin designs for communicating signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0029] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support the desired or specified data storage capacity. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0030] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may electronically communicate with each other using a bus 140.

[0031] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, processor 120 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a system on a chip (SoC), among other instances.

[0032] BIOS component 125 may be a software component including BIOS operating as firmware that may initialize and run various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100 (e.g., peripheral components 130, I / O controller 135, etc.). BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0033] Peripheral component 130 may be any input device or output device that may be integrated into or with system 100, or an interface for such a device. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components understood by those skilled in the art to be peripherals.

[0034] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input 145, or output 150. I / O controller 135 may manage peripheral devices that are not integrated into or integrated with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0035] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0036] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0037] The components of system 100 may be composed of general or special purpose circuitry designed to perform its functions. This may include various circuit elements, such as wires, transistors, capacitors, inductors, resistors, amplifiers, switching elements, latches, logic elements, or other active or passive elements, which are configured to perform the functions described herein.

[0038] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. At least some of the memory dies 160 (if not every memory die 160) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, each of which is configured to store at least one bit of digital data. Referring to Figure 2 Features of memory array 170 and / or memory cells are described in greater detail.

[0039] Memory device 110 may be an example of a two-dimensional (2D) array of memory cells, or may be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other or stacked next to each other. In some cases, memory die 160 may be divided into regions or areas of memory. For example, memory die 160 may include one or more memory vaults, at least some of which (if not each of which) may be associated with corresponding redundant circuitry.

[0040] In some cases, memory dies 160-N in a 3D memory device may be referred to as a deck, level, layer, or die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). This may increase the number of memory cells that may be positioned on a substrate compared to a single 2D memory device, which in turn may reduce production costs or increase performance of the memory array, or both. In some 3D memory devices, different levels may share at least one common access line, such that some levels may share at least one of a word line, a digit line, and / or a plate line.

[0041] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enables the memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or a processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 is to store certain data on behalf of a component of the system 100 (e.g., the processor 120), or a read command indicating that the memory device 110 is to provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, or the like.

[0042] The local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. In addition, the local memory controller 165 may be configured to communicate with the device memory controller 155 (e.g., receive and transmit data and / or commands). The local memory controller 165 may support the device memory controller 155 in controlling the operation of the memory device 110, as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120. In some examples, the local memory controller 165 may control redundant circuitry for one or more memory regions within the associated memory array 170.

[0043] The external memory controller 105 may be configured to enable communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. For example, when a memory address is the target of an access operation, the external memory controller 105 may facilitate communication of the target memory address to other components of the system 100. The external memory controller 105 may act as a liaison between components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the details of the operation of the memory device. Components of the system 100 may make requests (e.g., read commands or write commands) to the external memory controller 105, which the external memory controller 105 will satisfy. The external memory controller 105 may convert or translate communications exchanged between components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0044] In some cases, the external memory controller 105 or other components of the system 100 or its functions described herein may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functions described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may in some cases be performed by the external memory controller 105 (separate from the processor 120 or as included in the processor 120).

[0045] Components of system 100 may exchange information with memory device 110 using a plurality of channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to function as part of a channel. In some cases, a pin or pad of a terminal may be part of a signal path of channel 115. Additional signal paths may be coupled to the terminals of a channel for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or a component thereof, such as signal paths internal to memory die 160) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0046] The channels 115 (and associated signal paths and terminals) may be dedicated to conveying a particular type of information. In some cases, the channels 115 may be aggregate channels, and thus may include multiple individual channels. For example, the data channels 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), and the like. The signals conveyed through the channels may use a double data rate (DDR) timing scheme. For example, some symbols of the signal may be registered on the rising edge of the clock signal, and other symbols of the signal may be registered on the falling edge of the clock signal. The signals conveyed through the channels may use single data rate (SDR) signaling. For example, one symbol of the signal may be registered for each clock cycle.

[0047] In some cases, channels 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to communicate commands between external memory controller 105 and memory device 110, the commands including control information associated with the commands (e.g., address information). For example, CA channels 186 may include a read command with an address of desired data. In some cases, CA channels 186 may be registered on a rising clock signal edge and / or a falling clock signal edge. In some cases, CA channels 186 may include any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0048] In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channels 188 may be configured to communicate one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal), and the signal path of the CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. The CK channel 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations of the memory device 110 or other system-wide operations of the memory device 110. The clock signal CK may therefore be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, or the like).

[0049] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to communicate data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may communicate information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110.

[0050] In some cases, channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths.

[0051] In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally represent "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference for access operations commonly used for the memory device 110 (e.g., a timing reference for both read operations and write operations). Therefore, the write clock signal WCK may also be referred to as a data clock signal WCK. The WCK channel may be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t signal and WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, or the like).

[0052] In some cases, other channels 192 may include one or more error detection code (EDC) channels. An EDC channel may be configured to convey error detection signals (eg, checksums) to improve system reliability. An EDC channel may include any number of signal paths.

[0053] The channel 115 may use a variety of different architectures to couple the external memory controller 105 with the memory device 110. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer (such as a silicon interposer), or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0054] A variety of different modulation schemes may be used to modulate the signals communicated over the channel 115. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0055] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one digital data bit (e.g., the symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) signal may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

[0056] In some examples, system 100 may include redundant circuitry that stores memory address information. Memory address information may be transmitted (e.g., autonomously sent) from a fuse circuit ("fuse") that stores information related to characteristics of system 100. Memory address information may include a memory address associated with a memory component (e.g., an access line or a memory cell) that is identified as unusable or having a problem. For example, a memory component may be identified as defective or unreliable. A defective memory component may be a component that does not function properly. An unreliable memory component may be a component that behaves inconsistently. In some cases, a component may be both defective and unreliable. For ease of reference in the present invention, one type of memory component (e.g., unreliable or defective) may be referenced in certain examples, however, unless otherwise explicitly indicated, the applicability of the related concepts may be equal (e.g., the same) for both types.

[0057] When selecting a memory address for an access operation, the redundant circuitry may compare the selected memory address to one or more memory addresses stored by circuits within the redundant circuitry. If the selected memory address matches a memory address stored by at least one of the circuits, the redundant circuitry may send a signal indicating as much to one or more other components of system 100. Once notified that the selected memory address is defective or unreliable, system 100 or one or more components of system 100 may take steps to avoid using that memory address.

[0058] In general, redundant circuitry can distribute selected memory addresses (or representations of memory addresses) to all circuits within the redundant circuitry, which can continue to be powered while system 100 is in operation. However, when only some of the redundant circuits are in use (e.g., storing defective memory addresses), providing one or more memory addresses to and powering all circuits within the redundant circuitry may waste power. According to the techniques described herein, redundant circuitry can reduce power consumption of system 100 by selectively powering circuits in use and distributing selected memory addresses to the circuits.

[0059] Figure 2 An example of a memory die 200 according to examples disclosed herein is illustrated. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that can be programmed to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one digital logic bit at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one digital logic bit at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0060] The memory cell 205 may store a state (e.g., a polarization state or a dielectric charge) representing digital data. In a FeRAM architecture, the memory cell 205 may include a capacitor including a ferroelectric material to store a charge and / or polarization representing a programmable state. In a DRAM architecture, the memory cell 205 may include a capacitor including a dielectric material to store a charge representing a programmable state. The techniques described herein may be implemented using any type of memory architecture including FeRAM and DRAM architectures.

[0061] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210, digit line 215, and / or plate line 220. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, digit lines, plate lines, or the like may be interchangeable without loss of understanding or operation. Activating or selecting word line 210, digit line 215, or plate line 220 may include applying a voltage to the corresponding line.

[0062] The memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210, digit lines 215, and / or plate lines 220. By biasing the word lines 210, digit lines 215, and plate lines 220 (e.g., applying voltages to the word lines 210, digit lines 215, and plate lines 220), a single memory cell 205 at its intersection may be accessed.

[0063] Access to the memory cells 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from a local memory controller 265 and activate a word line 210 based on the received row address. The column decoder 230 may receive a column address from a local memory controller 265 and activate a digit line 215 based on the received column address. The plate driver 235 may receive a plate address from a local memory controller 265 and activate a plate line 220 based on the received plate address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M, a plurality of digit lines 215 labeled DL_1 to DL_N, and a plurality of plate lines labeled PL_1 to PL_P, where M, N, and P depend on the size of the memory array. Thus, by activating a word line 210, a digit line 215, and a plate line 220 (e.g., WL_1, DL_3, and PL_1), a memory cell 205 at its intersection can be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of a memory cell 205. In some cases, the intersection of a word line 210, a digit line 215, and a plate line 220 can be referred to as the address of a memory cell 205. The address of a word line 210, a plate line 220, or a digit line 215 can be referred to herein as an access line address.

[0064] Memory cell 205 may include a logic storage component such as capacitor 240 and a switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0065] Selecting or deselecting the memory cell 205 can be accomplished by activating or deactivating the switching component 245. The capacitor 240 can be in electronic communication with the digital line 215 using the switching component 245. For example, when the switching component 245 is deactivated, the capacitor 240 can be isolated from the digital line 215, and when the switching component 245 is activated, the capacitor 240 can be coupled to the digital line 215. In some cases, the switching component 245 is a transistor, and the operation of the transistor is controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source is greater than or less than the threshold voltage of the transistor. In some cases, the switching component 245 can be a p-type transistor or an n-type transistor. The word line 210 can be in electronic communication with the gate of the switching component 245, and the switching component 245 can be activated / deactivated based on the voltage applied to the word line 210.

[0066] The word line 210 may be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of a switching element 245 of the memory cell 205 and may be configured to control the switching element 245 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205 and the memory cell 205 may not include a switching element.

[0067] The digit line 215 can be a conductive line that connects the memory cell 205 to the sensing component 250. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during a portion of an access operation. For example, the word line 210 and the switching component 245 of the memory cell 205 can be configured to selectively couple and / or isolate the capacitor 240 of the memory cell 205 from the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0068] Plate line 220 may be a conductive line in electronic communication with memory cell 205 to perform access operations on memory cell 205. Plate line 220 may be in electronic communication with a node (e.g., the cell bottom) of capacitor 240. During an access operation of memory cell 205, plate line 220 may be configured to cooperate with digit line 215 to bias capacitor 240.

[0069] The sensing component 250 may be configured to determine the state (e.g., polarization state or charge) stored on the capacitor 240 of the memory cell 205, and determine the logic state of the memory cell 205 based on the detected state. In some cases, the charge stored by the memory cell 205 may be very small. Thus, the sensing component 250 may include one or more sense amplifiers to amplify the signal output of the memory cell 205. The sense amplifier may detect a small change in the charge of the digit line 215 during a read operation, and may generate a signal corresponding to a logic 0 or logic 1 based on the detected charge. During a read operation, the capacitor 240 of the memory cell 205 may output a signal (e.g., release the charge) to its corresponding digit line 215. The signal may cause the voltage of the digit line 215 to change. The sensing component 250 may be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 255 (e.g., a reference voltage).

[0070] The sensing component 250 may determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 255, the sensing component 250 may determine that the storage state of the memory cell 205 is a logic 1, and if the digit line 215 has a lower voltage than the reference signal 255, the sensing component 250 may determine that the storage state of the memory cell 205 is a logic 0. The sensing component 250 may include various transistors or amplifiers to detect and amplify the difference in signals. The detected logic state of the memory cell 205 may be provided as an output of the sensing component 250 (e.g., to the input / output 260), and the detected logic state may be indicated to another component of the memory device 110 including the memory die 200, such as the device memory controller 155 (e.g., directly or using a local memory controller 265). In some cases, the sensing component 250 may be in electronic communication with the row decoder 225, the column decoder 230, and / or the plate driver 235.

[0071] The local memory controller 265 may control the operation of the memory cell 205 through various components (eg, the row decoder 225, the column decoder 230, the plate driver 235, and the sensing component 250). The local memory controller 265 may be a reference Figure 1 105 . In some cases, one or more of the row decoder 225, column decoder 230, and plate driver 235 and sensing component 250 may be co-located with the local memory controller 265. The local memory controller 265 may be configured to receive data from the external memory controller 105 (or reference 105). Figure 1The local memory controller 265 may generate row, column, and / or board line address signals to activate the target word lines 210, the target digit lines 215, and the target board lines 220. The local memory controller 265 may also generate and control various voltages or currents used during the operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory die 200.

[0072] In some cases, the local memory controller 265 can be configured to perform a precharge operation on the memory die 200. The precharge operation can include precharging one or more components and / or access lines of the memory die 200 to one or more predetermined voltage levels. In some cases, portions of the memory cells 205 and / or memory die 200 can be precharged between different access operations. In some cases, the digit lines 215 and / or other components can be precharged prior to a read operation.

[0073] In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify a target memory cell 205 on which a write operation is to be performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and / or a target plate line 220 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The local memory controller 265 may apply a specific signal (e.g., voltage) to the digit line 215 and a specific signal (e.g., voltage) to the plate line 220 during a write operation to store a specific state in the capacitor 240 of the memory cell 205, wherein the specific state indicates a desired logic state.

[0074] In some cases, the local memory controller 265 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logic state stored in the memory cell 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 265 may identify a target memory cell 205 on which a read operation is to be performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and / or a target plate line 220 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 250 in response to biasing the access line. The sensing component 250 may amplify the signal. The local memory controller 265 may trigger the sensing component 250 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 255. Based on the comparison, the sensing component 250 may determine the logic state stored on the memory cell 205. As part of the read operation, the local memory controller 265 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or device memory controller).

[0075] Prior to performing an access operation, such as a read or write operation, the local memory controller 265 may check to see if the target memory address is defective or unreliable. For example, the local memory controller 265 may provide the target memory address to the redundant circuitry, which may return a match signal if the memory address is defective. According to the techniques described herein, the redundant circuitry may implement an efficient power scheme by selectively assigning the target memory address to certain groups of its repair circuits based on the usage status of its repair circuits. Additionally or alternatively, the redundant circuitry may also selectively isolate certain groups of repair circuits from power based on the usage status of those repair circuits.

[0076] In some memory architectures, accessing the memory cell 205 may degrade or destroy the logical state stored in the memory cell 205. For example, a read operation performed on a ferroelectric memory cell may destroy the logical state stored in the ferroelectric capacitor. In another example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. The local memory controller 265 may perform a rewrite operation or a refresh operation to return the memory cell to its original logical state. The local memory controller 265 may rewrite the logical state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered as part of the read operation. In addition, activating a single access line such as word line 210 may disturb the state stored in some memory cells that are in electronic communication with that access line. Therefore, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not have been accessed.

[0077] Figure 3 An example of a circuit system 300 supporting an efficient power scheme for redundancy according to examples disclosed herein is illustrated. The circuit system 300 may include redundant circuits 305 and a controller 310 that may be coupled to each other. The controller 310 may control various components of the redundant circuits 305.

[0078] As described herein, redundant circuits 305 can be associated with (e.g., store addresses of) memory regions, such as memory banks. Redundant circuits 305 can include one or more repair circuits 315, which can also be referred to as repair solutions. In one example, redundant circuits 305 can include 128 repair circuits, such as Figure 3 . The repair circuit 315 may be configured to store memory address information. For example, the repair circuit 315 may store one or more addresses corresponding to one or more memory components (e.g., access lines or memory cells) that have been identified as damaged, defective, unreliable, or otherwise unusable. Thus, in some examples, the redundancy circuit 305 may have the capacity to store the addresses of 128 memory components. The one or more addresses stored at the repair circuit 315 may be obtained from one or more fuses (e.g., after activation or reset).

[0079] Redundancy circuit 305 may determine when a defective memory component is the target of a memory access operation and provide an indication of the determination to a memory controller (e.g., controller 310) or other component. For example, redundancy circuit 305 may receive (e.g., from a memory controller such as controller 310) an incoming address (IA) corresponding to a memory component that has been the target (e.g., selected) of a memory access operation. The incoming address may include x+1 bits and may represent the target memory address or a complemented version of the target memory address with an inverted (e.g., flipped) bit.

[0080] The incoming address may be distributed to at least some, if not every, of the repair circuits 315 for comparison. The repair circuits 315 may perform one or more logical operations on the incoming address and the address stored by the repair circuits 315 to compare the incoming address to the stored address. For example, the repair circuits 315 may perform one or more logical operations on the incoming address and the address stored by the repair circuits 315 to determine whether the incoming address and the stored address match (e.g., are the same). If the addresses match, the repair circuits 315 may output a signal indicating the match to an external component or device (e.g., a memory controller, such as controller 310).

[0081] For example, the repair circuit 315 may assert a match signal. If the addresses are different, the redundancy circuit 305 may not output a signal (e.g., may refrain from outputting a relevant signal) or may output a signal indicating the difference to an external component or device. Such an indication may inform a memory device when it has a defective memory component that is the target of an operation, and thus may enable the memory device to avoid using the memory component. For example, instead of accessing the defective memory component, the memory device accesses a spare (or "redundant") memory component corresponding to the repair circuit 315 that asserted the match signal.

[0082] To perform their functions, at least some repair circuits 315 (if not every repair circuit 315) may include a plurality (e.g., x+1) of latches 320 and logic components 325. Latch 320-a may be configured to store memory information such as address bits. Address bits may be portions of a memory address associated with a memory component that has been identified as defective or unreliable. Thus, repair circuit 315 may store a complete memory address by using a plurality of latches, at least some of which (if not each of which) store corresponding bits. The memory addresses stored by repair circuit 315 may be unique relative to other memory addresses stored at redundant circuit 305. For example, a first repair circuit 315 may include a first set of latches configured to store a first memory address, and a second repair circuit 315 may include a second set of latches configured to store a second memory address.

[0083] The latch 320-a can be configured to output (e.g., in response to a prompt or command by a memory controller such as the controller 310) a signal indicating an address bit stored at the latch 320-a. The signal can be output (e.g., provided to) one or more logic components 325-a coupled to the latch 320-a. For example, the signal can propagate through a conductive path coupling an output of the latch 320-a with an input of the logic component 325-a.

[0084] In addition to receiving the stored address bits from latch 320-a, logic component 325-a may also receive corresponding incoming address bits (e.g., from controller 310). Logic component 325-a may perform one or more logic operations on the received bit signals and output the results of the logic operations to another logic component 325-b. Although shown with two inputs, logic component 325-a may include a different number of inputs, such as with additional inputs. For example, logic component 325-a may include four inputs. In such cases, logic component 325-a may also receive complementary versions of the stored and incoming address bits.

[0085] Logic component 325-b can perform logic operations on signals received from logic component 325-a and latch 320-b. Latch 320-b can store information about the content stored by other latches 320-a. For example, latch 320-b can store a bit indicating whether the content stored by latch 320-a is memory address information. Therefore, the bit can indicate the use status of repair circuit 315-a. The bit stored by latch 320-b can be referred to as a "use" bit, a "state" bit, or an "enable" bit in this article, and can be represented as "E" in the diagram. When the target address is consistently matched with the random content stored by latch 320-a, the enable bit can prevent the repair circuit 315 from erroneously asserting a match signal. Therefore, when the enable bit is asserted and the target address matches the stored address, logic component 325-b can assert a match signal.

[0086] The functionality of a single repair circuit 315 is explained above. However, as noted, an incoming address may be provided to multiple (if not every) repair circuit 315 within a redundant circuit 305 to ensure that the incoming address is compared to at least some (if not all) addresses stored in the redundant circuit 305. However, only a portion of the repair circuits 315 may store addresses (e.g., the remaining repair circuits 315 may store random content other than memory address information). In these cases, distributing the incoming address to each repair circuit 315 may waste power. This is because distributing the incoming address may involve charging multiple traces or lines per repair circuit 315.

[0087] In some cases, distributing the incoming address can increase the peak power consumed by the memory device. If the incoming address and its complement are distributed to each repair circuit 315 within a relatively short period of time (e.g., 1 ns), the charging associated with the distribution can result in a large (e.g., 165 mA) alternating current (AC) power spike. This power spike can in turn contribute to the average power consumed by the memory device (e.g., the power consumed by a given y access operation over a period of time). Therefore, providing the incoming address to each repair circuit 315 may tax the battery of the host device.

[0088] According to the techniques described herein, peak and average power consumed by a memory device implementing redundancy may be reduced by selectively assigning incoming addresses to groups of repair circuits 315 that have at least one in-use repair circuit 315. Thus, the memory device may avoid assigning incoming addresses to groups of repair circuits 315 that are not in-use, which may save power.

[0089] But peak and average power may not be the only issues or power issues associated with redundancy. Memory devices may also waste power by powering latches that are not in use (e.g., storing memory addresses). Because powering latches also results in leakage, the power cost of powering latches that are not in use may be twice as high. According to the techniques described herein, a memory device implementing redundancy can reduce power consumption and leakage by selectively powering down unused latches within the repair circuit 315.

[0090] Figure 4 An example of a circuit system 400 that supports an efficient power scheme for redundancy according to examples disclosed herein is illustrated. The circuit system 400 may include a gating circuit system 405, a controller 410, and a repair circuit 415, at least some of which (if not each) may be coupled to each other. The controller 410 may be a reference Figure 3 The controller 310 described above and the repair circuit 415 may be referred to as Figure 3 4. The repair circuit 415 may store the address of an unreliable or defective memory component and indicate when the address is the target of a memory operation. The gating circuit system 405 may selectively provide the incoming address to the repair circuit 415 based on the usage status of the repair circuit 415. The controller 410 may control various signals and components used by the gating circuit system 405 and the repair circuit 415.

[0091] The repair circuit 415 may include a plurality of latches and logic elements, such as XOR elements and AND elements. Figure 3 The example of latch 320-a described above and latch 420-b may be referred to as Figure 3 The XOR element 425 and the AND element 430 may be as described with reference to Figure 3 4. An example of a logic component 325 is depicted. The latches 420-a and the XOR components 425 can be coupled to each other (e.g., in electronic communication with each other). In this example, the repair circuit 415 can include thirteen latches 420 and twelve XOR components 425. Thus, the repair circuit 415 can have one more latch 420 than XOR components 425.

[0092] At least some latches 420-a (if not every latch 420-a) may be configured to store memory address content. For example, each latch 420-a may be configured to store at least one bit (e.g., a single bit, multiple bits) of a memory address associated with a memory component identified as defective or unreliable. The latches 420-a may collectively store a complete memory address (e.g., a memory address of an unreliable or defective access line or memory cell). For example, latch 420-a-11 may store the twelfth bit (bit 11) of a 12-bit address, and latch 420-a-0 may store the first bit (bit 0) of a 12-bit address. The bits stored at latch 420-a may be downloaded from a fuse, for example, after power-up or reset. If the repair circuit 415 does not receive an address bit from the fuse, the repair circuit 415 may be referred to as unused, and the content stored by the repair circuit 415 may be random content (e.g., different from the memory address content).

[0093] In addition to latches 420-a for memory address bits, repair circuit 415 may include latches that store enable bits. For example, repair circuit 415 may include latch 420-b, which may store enable bits for repair circuit 415. The enable bits may indicate when other latches 420-a store memory address bits (as opposed to random bits). This indication may prevent repair circuit 415 from asserting a match signal when the target address consistently matches the random bits stored by unused latches 420-a. Thus, the enable bits may allow repair circuit 415 to distinguish between valid matches and invalid matches. The enable bits may be labeled as "E" bits, and may alternatively be referred to as use bits or status bits.

[0094] At least some of the XOR components 425 (if not every XOR component 425) can be coupled to the output of the corresponding latch 420-a. The XOR component 425 can receive a signal representing an incoming address bit from an external component. As noted, the incoming address bit can be a bit (or a complementary version of the bit) of the memory address that is the target of the access operation.

[0095] exist Figure 4 , the incoming address bits may be complementary versions of the target memory address bits. XOR component 425 may also receive a signal representing an address bit stored at latch 420-a coupled to XOR component 425. For example, XOR component 425-a may receive a signal representing the twelfth bit of the stored address (bit 11) from latch 420-a-11 and a signal representing the twelfth incoming address bit (bit 11) from latch 420-a-11. Figure 4 In the expression <11> ) signal.

[0096] XOR component 425 may perform a logical operation (e.g., a bitwise comparison) on the received signal and output a result. For example, if the input signals represent the same bit, XOR component 425 may output a logical zero, and if the input signals represent different bits, XOR component 425 may output a logical one. Thus, if the stored bit matches the incoming bit, XOR component 425 may output a logical zero, and if the stored bit does not match the incoming bit, XOR component 425 may output a logical one. A logical one may be represented by a signal having a first threshold voltage, and a logical zero may be represented by a signal having a second threshold voltage.

[0097] The outputs of at least some of the XOR components 425 (if not every XOR component 425) may be communicated to an AND component 430. The AND component 430 may perform a logical operation (e.g., an AND operation) on its inputs and output a result. For example, if all of the inputs to the AND component 430 are logical ones, it may output a logical one (e.g., a match signal). In other words, if the address selected for the memory access operation matches the address stored by the repair circuit 415, the AND component 430 may output (or "assert") a match signal.

[0098] Thus, repair circuit 415 may operate on the incoming address to determine if the target address is defective or unreliable. However, in some cases, the content stored by repair circuit 415 may be different from the memory address information. In these cases, providing the incoming address to repair circuit 415 may waste power. According to the techniques described herein, if repair circuit 415 is in use, then the incoming address may be provided to repair circuit 415, but if repair circuit 415 is not in use, then the incoming address may be retained.

[0099] For example, if the enable bit is asserted, the gating circuitry 405 may receive the incoming address and distribute it to the repair circuit 415. If the enable bit is not asserted, the gating circuitry 405 may output a static signal to the repair circuit 415. Thus, the gating circuitry 405 may selectively provide the incoming address to the repair circuit 415 based on the usage state of the repair circuit 415.

[0100] Although shown with two inputs, XOR component 425 may include additional inputs. For example, XOR component 425 may include four inputs. In such cases, XOR component 425 may also receive the incoming address bits and the complement version of the stored address bits.

[0101] Although shown with XOR logic gates and AND logic gates, repair circuit 415 may be implemented using any type or combination of logic components, including OR logic gates, XOR logic gates, NAND logic gates, NOT gates (also known as inverters), XNOR logic gates, etc. For example, repair circuit 415 may be implemented using XNOR logic gates by using an incoming address that represents a target address instead of a complemented version of the target address.

[0102] Figure 5 An example of a circuit system 500 supporting an efficient power scheme for redundancy according to examples disclosed herein is illustrated. The circuit system 500 may include a redundant circuit 505 and a gating circuit 520. The redundant circuit 505 may be as described in reference Figure 3 The redundant circuit 305 described in the example, and the gating circuit 520 can be included in the reference Figure 4 4. An example of circuitry in gated circuitry 405 is depicted. Redundant circuitry 505 may include repair circuits 515 grouped into a plurality of logical groups 510. For example, repair circuits 515 may be divided into eight logical groups 510, each logical group including sixteen repair circuits 515. At least some of the logical groups 510, if not every logical group 510, may be coupled with respective gating circuits 520 that selectively distribute incoming addresses to repair circuits 515 within the logical groups 510. This selective distribution may reduce peak and average power consumed by circuitry 500.

[0103] The gating circuit 520 may include a plurality of logic circuits 525. The number of logic circuits 525 may be equal to the number of bits that make up the incoming address. Thus, there may be one logic circuit 525 per address bit. At least some of the logic circuits 525 (if not every logic circuit 525) may receive a corresponding bit of the incoming address. For example, logic circuit 525-0 may receive a signal representing the first bit (bit 0) of the incoming address, and logic circuit 525-x may receive a signal representing the xth bit (e.g., bit x-1) of the incoming address. Additionally, at least some of the logic circuits 525 (if not every logic circuit 525) may receive a signal representing an enable bit of a repair circuit 515 coupled to an input of the gating circuit 520. For example, logic circuit 525-0 may receive an enable bit from repair circuit 515-a. At least some of the logic circuits 525 (if not every logic circuit 525) may include one or more logic components.

[0104] If at least one of the repair circuits 515 is in use, the logic circuit 525 may distribute the incoming address bits to the repair circuits 515 in its corresponding logical group 510. For example, if the enable bit from the repair circuit 515-a is asserted, the logic circuit 525-0 may distribute the incoming address bits to the repair circuits 515-a through 515-p. In addition to distributing the incoming address bits, the logic circuit 525 may also distribute the complement (e.g., inverted version) of the incoming address bits. However, if none of the repair circuits 515 is in use, the logic circuit 525 may retain the incoming bit address without distributing it to its corresponding logical group 510. For example, if the enable bit from the repair circuit 515-a is not asserted, the logic circuit 525-0 may retain the incoming bit address without distributing it to the repair circuits 515-a through 515-p.

[0105] For clarity, the operation of logic circuit 525 is explained in the context of logic circuit 525-0. However, other components, configurations, and operations of logic circuit 525 are contemplated and fall within the scope of the present invention. For example, logic circuit 525 may not include inverter 535 (e.g., in logic component 325-a as described in reference to FIG. 5B ). Figure 3 described with two inputs instead of four).

[0106] Logic circuit 525-a may include an AND component 530 and an inverter 535. AND component 530 and inverter 535 may be coupled to each other. For example, the output of AND component 530 may be coupled to the input of inverter 535. AND component 530 and inverter 535 may also be coupled to repair circuit 515 in logic group 510-a.

[0107] For example, the output of AND component 530 may be coupled to a first input of repair circuit 515-a (e.g., via conductive path 540-a), and the output of inverter 535 may be coupled to a second input of repair circuit 515-a (e.g., via conductive path 540-b). Various conductive paths may couple other components in circuit system 500. For example, conductive path 540-c may couple the output of a latch storing an enable bit to the input of AND component 530. A conductive path may be a combination of elements (e.g., traces and / or components) that allow current to flow from one end of the conductive path to the other without interruption. For example, a conductive path may include one or more switching components that are disposed along a trace and activated to allow current to flow.

[0108] As noted, the logic components of logic circuit 525-0 can be configured to selectively assign incoming address bits to logic groups 510-a based on an enable bit stored at repair circuit 515-a. In one example, AND component 530 can receive a signal representing the enable bit stored at repair circuit 515-a. AND component 530 can also receive a signal representing the incoming address bit. AND component 530 can perform a logic operation (e.g., an AND operation) on the enable bit and the incoming address bit and output a result.

[0109] When the enable bit is asserted (e.g., is a logical one), the AND component 530 can output the incoming address. When the enable bit is not asserted (e.g., is a logical zero), the AND component 530 can output a logical zero. Thus, the incoming address bit can be provided (e.g., signaled) to the repair circuits 515-a to 515-p when at least one of those repair circuits 515 is in use, but when all repair circuits 515 are not in use, then the incoming address is not provided to the repair circuits 515-a to 515-p. This selective allocation can save power by preventing unnecessary charging of the wires leading to the unused repair circuits 515.

[0110] In some cases (e.g., in logic component 325-a as shown in reference Figure 3 Logic circuit 525-0 may also distribute a complemented version of the incoming address bits to logic group 510-a (as described with four inputs instead of two). For example, when the enable bit is asserted, inverter 535 may invert the incoming address bits output by AND component 530 and send the resulting complemented version to repair circuit 515 in logic group 510-a.

[0111] Thus, incoming address bits (and / or their complement) may be assigned to logical groups 510-a based on the usage status of the logical groups. The address bits that make up the remaining target memory addresses may undergo similar operations and thus may be assigned on a similar basis. In some examples, the incoming address bits may be assigned in parallel (e.g., simultaneously or within a threshold duration) to reduce latency. Once repair circuitry 515 receives all of the address bits of the target memory address, repair circuitry 515 may perform a logical operation (e.g., a bitwise comparison) to detect whether the target memory address matches any of the stored memory addresses identified as defective.

[0112] To ensure that incoming addresses are not accidentally retained without being assigned to the repair circuits 515 in use, the defective addresses stored by the redundant circuits 505 may be loaded into the repair circuits 515 in a specific order rather than randomly. For example, the first defective address stored at the logical group 510 may be stored at the repair circuit 515 coupled to the input of the gating circuit 520. Thus, the defective address may be stored at the repair circuit 515-a before any other defective address is stored at the other repair circuits 515 within the logical group 515-a. This ordering may ensure that any and all repair circuits 515 storing memory addresses receive the incoming address for comparison. In some cases, the storage of defective addresses may be further ordered so that power consumption is reduced. For example, after storing the defective address at the repair circuit 515-a, the host device may choose to store the next fifteen addresses at the other repair circuits in the logical group 510-a instead of storing the next fifteen addresses at the repair circuits 515 in the other logical groups 510. Thus, incoming addresses may be assigned to only one logical group (rather than several logical groups, as would be the case if defective addresses were stored randomly or indiscriminately).

[0113] Figure 6 An example of a circuit system 600 supporting an efficient power scheme for redundancy according to examples disclosed herein is illustrated. The circuit system 600 can be configured to: provide power to a logical group if at least one of the repair circuits in the group is in use; and remove power from the logical group if none of the repair circuits is in use.

[0114] The circuit system 600 may include a logic circuit 605 and a logic group 610, which may be respectively as shown in FIG. Figure 5 605 and logic group 510. Circuit system 600 may also include power supply 625, which may be a local power supply powered by a global power supply. Power supply 625 may also be referred to as a power supply, a voltage source, or a current source. Although shown as coupled to logic circuit 605, logic group 610 may be implemented independently of logic circuit 605.

[0115] The logic group 610 may include a plurality of repair circuits 615 and a switching component 620. At least some of the repair circuits 615, if not every repair circuit 615, may include a set of latches and may be coupled with the switching component 620. The switching component 620 may be configured to selectively provide power to the repair circuit 615 based on the usage status of the repair circuit 615-a. This selectivity may reduce the power consumed and leaked by the circuit system 600.

[0116] The switching component 620 can be coupled to the power supply 625 and the latch that stores the enable bit within the repair circuit 615-a. For example, the input of the switching component 620 can be coupled to the output of the latch. The switching component 620 can be configured to modify its state (e.g., activate or deactivate) based on the enable bit.

[0117] For example, the switching component 620 may receive a signal representing an enable bit from the repair circuit 615-a. If the enable bit is asserted, the switching component 620 may be activated, thereby establishing a conductive path between the power supply 625 and the repair circuit 615. If the enable bit is not asserted, the switching component 620 may be deactivated, thereby isolating the power supply 625 from the repair circuit 615. Because powering an unused repair circuit 615 may be an unnecessary power expenditure that is exacerbated by leakage, powering down the unused repair circuit 615 may reduce power consumption of the circuit system 600.

[0118] Circuit system 600 may be configured to supply the latch storing the enable bit in repair circuit 615-a independently of the enable bit. This configuration may allow circuit system 600 to control power supplied to the rest of logic group 610 even if the enable bit is not asserted.

[0119] Figure 7 An example of a circuit system 700 supporting an efficient power scheme for redundancy according to examples disclosed herein is illustrated. Figure 6 Circuit system 700 may be configured to provide power on a repair circuit basis, as opposed to the logical grouping basis described above. This configuration may enable circuit system 700 to selectively provide power at a greater granularity than circuit system 600, which may increase power savings. However, the configuration of circuit system 700 may have a larger footprint than the footprint of the configuration of circuit system 600.

[0120] The circuit system 700 may include a logic circuit 705 and a logic group 710, which are respectively as shown in FIG. Figure 5 and 6 Examples of described logic circuits and logic groups. Circuit system 700 may also include a plurality of one or more power supplies 725. Logical group 710 may include a plurality of repair circuits 715. At least some of repair circuits 715, if not every repair circuit 715, may be coupled with a respective switching element 720.

[0121] At least some of the switching components 720 (if not every switching component 720) may be configured to selectively provide power to its corresponding repair circuit 715 based on the usage status of the repair circuit 715 (and independently of the usage status of other repair circuits 715). For example, the switching component 720-a may be configured to activate when an enable bit stored at the repair circuit 715-a is asserted, and to deactivate when the enable bit is not asserted. Thus, when the repair circuit 715-a is in use, the switching component 720-a may establish a conductive path from the power supply 725-a to the repair circuit 715-a, and when the repair circuit 715-b is not in use, the switching component 720-a may isolate the power supply 725-a from the repair circuit 715-a. Activating and deactivating the switching component 720-a may be independent of the enable bits stored at other repair circuits 715.

[0122] Similarly, the switching component 720-b can be configured to activate when the enable bit stored at the repair circuit 715-b is asserted, and to deactivate when the enable bit is not asserted. Thus, when the repair circuit 715-b is in use, the switching component 720-b can establish a conductive path from the power supply 725-b to the repair circuit 715-b, and when the repair circuit 715-b is not in use, the switching component 720-b can isolate the power supply 725-b from the repair circuit 715-b. Activating and deactivating the switching component 720-b can be independent of the enable bits stored at other repair circuits 715.

[0123] Circuit system 700 may be configured to supply power to a latch storing an enable bit in each repair circuit 715 independently of the corresponding enable bit. This configuration may allow circuit system 700 to control power supplied to each repair circuit 715 even if the enable bit stored at the repair circuit 715 is not asserted.

[0124] Although multiple power supplies 725 are shown, the power gating techniques described herein may be implemented using a single power supply 725 coupled with each of the switching components 720 .

[0125] Figure 8 A block diagram 800 is shown of a memory controller 805 supporting an efficient power scheme for redundancy according to examples disclosed herein. The memory controller 805 may be as described with reference to Figures 1 to 4 805. The memory controller 805 may include a storage manager 810, a logic manager 815, a signaling manager 820, and a component manager 825. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses). The modules of the memory controller 805 may perform or instruct other components to perform various operations to implement the efficient power schemes described herein.

[0126] For example, the module can be configured to facilitate Figure 5 The operation of the efficient power scheme described in the present invention. In this example, the storage manager 810 may cause or instruct one or more components to store a first address bit associated with a memory component identified as unreliable at a first latch. The storage manager 810 may also cause or instruct one or more components to store an enable bit at a second latch indicating that the first latch is storing the first address bit. The logic manager 815 may cause or instruct one or more components to perform a logic operation on a signal representing the enable bit and a second address bit associated with the memory component selected for the memory access operation. The signaling manager 820 may cause or instruct one or more components to output a signal representing the second address bit to a logic component coupled to the first latch based at least in part on the logic operation.

[0127] In some cases, the logic manager 815 may cause or instruct the logic component to perform a second logic operation on the signals representing the first and second address bits. In such cases, the signaling manager 820 may cause or instruct the one or more components to output a second signal based at least in part on the second logic operation. In some cases, the logic manager 815 may cause or instruct the second logic component to perform a third logic operation on the second signal output by the logic component and a third signal representing an enable bit. In such cases, the signaling manager 820 may cause or instruct the one or more components to output a fourth signal indicating whether the first address bit matches the second address bit based at least in part on the third logic operation.

[0128] In some cases, the signaling manager 820 may cause or instruct the second logic component to receive a signal representing an enable bit from the second latch. In such cases, the signaling manager 820 may cause or instruct the second logic component to receive a signal representing at least one second address bit, wherein the logic component performs a logic operation.

[0129] In some examples, the logic manager 815 may cause or instruct one or more components to invert the second address bit after performing the logic operation. In such cases, the signaling manager 820 may cause or instruct one or more components to signal at least one inverted second address bit to a logic component coupled to the first latch. In addition, the logic manager 815 may cause or instruct one or more components to perform a second logic operation on a signal representing the first address bit, the second address bit, and the inverted second address bit.

[0130] In some cases, the module can be configured to facilitate Figure 6 and 7The operation of the efficient power scheme described in the present invention. For example, the storage manager 810 may cause or instruct one or more components to store a memory address associated with a memory component identified as unreliable at a set of latches. The storage manager 810 may also cause or instruct one or more components to store a bit at a latch indicating that the set of latches is storing a memory address. The signaling manager 820 may cause or instruct one or more components to send a signal representing the bit to a switching component coupled to the set of latches and a power supply. And the component manager 825 may cause or instruct one or more components to activate the switching component based at least in part on the signal representing the bit to couple the power supply to the set of latches.

[0131] In some examples, the storage manager 810 may cause or instruct one or more components to store a second memory address associated with a second memory component identified as unreliable at a second set of latches. In such cases, activating the switching component may couple the power supply to the second set of latches.

[0132] In some examples, the storage manager 810 may cause or instruct one or more components to store a second bit at a second latch that indicates whether the second set of latches is storing a second memory address associated with a second memory component identified as unreliable. In such cases, the component manager 825 may cause or instruct one or more components to modify a state of a second switching component based at least in part on the second bit. In such cases, the second switching component may be coupled to the power supply and the second set of latches.

[0133] In some examples (eg, when the second bit indicates that the second set of latches is storing a second memory address), component manager 825 may cause or instruct one or more components to deactivate a switching component to isolate the power supply from the second set of latches.

[0134] In some instances (e.g., when at least one second bit indicates that the second set of latches is not storing the second memory address), the component manager 825 may cause or instruct one or more components to activate a second switching component to facilitate establishing a conductive path from the power supply to the second set of latches.

[0135] Fig. 9 A flow chart illustrating one or more methods 900 for supporting an efficient power scheme for redundancy according to examples disclosed herein is shown. The operations of the method 900 may be implemented by a memory controller or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory controller or components thereof as described herein. Figure 8 The memory controller described herein performs the functions described herein. In some examples, the memory controller may execute a set of instructions to control the functional elements of the memory controller to perform the functions described herein. Additionally or alternatively, the memory controller may use dedicated hardware to perform the functions described herein.

[0136] At 905, the method may include storing, at a first latch (e.g., latch 420-a-11), a first address bit associated with a memory component identified as unreliable. The operations of 905 may be performed according to the methods described herein. In some examples, the operations of 905 may be performed as described in reference to Figure 8 Describes the storage manager implementation.

[0137] At 910, the method may include storing an enable bit at a second latch (e.g., latch 420-b) indicating that the first latch is storing a first address bit. The operation of 910 may be performed according to the methods described herein. In some examples, the operation of 910 may be performed as described in reference to Figure 8 Describes the storage manager implementation.

[0138] At 915, the method may include performing a logical operation (e.g., an AND operation) on a signal representing an enable bit and a second address bit associated with a memory component selected for a memory access operation. Operation 915 may be performed according to the methods described herein. In some examples, operation 915 may be performed as described in reference to Figure 8 Describes the logic manager execution.

[0139] At 920, the method may include outputting a signal representing the second address bit to a logic component (e.g., XOR component 425-a) coupled to the first latch based on a logic operation. Operation 920 may be performed according to the methods described herein. In some examples, operation 920 may be performed as described in reference to Figure 8 Describes the Signaling Manager implementation.

[0140] In some examples, an apparatus described herein may perform one or more methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: storing at a first latch a first address bit associated with a memory component identified as unreliable; storing at a second latch an enable bit indicating that the first latch is storing the first address bit; performing a logic operation on a signal representing at least one bit and a second address bit associated with a memory component selected for a memory access operation; and outputting a signal representing the second address bit to a logic component coupled to the first latch based on the logic operation.

[0141] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for performing, at a logic component (e.g., XOR component 425-a), a second logic operation on signals representing the first and second address bits; and outputting a second signal based on the second logic operation. In such examples, the method 900 and apparatus described herein may further include operations, features, means, or instructions for performing, at a second logic component (e.g., AND component 430), a third logic operation on the second signal output by the logic component and a third signal representing an enable bit; and outputting a fourth signal (e.g., a match signal) indicating whether the first address bit matches the second address bit based on the third logic operation.

[0142] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for: receiving an enable bit from a second latch (e.g., latch 420-b) at a second logic component (e.g., AND component 530); receiving a second address bit (e.g., from latch 420-a-11) at a second logic component. In such cases, the second logic component may perform a logic operation on the enable bit and the second address bit.

[0143] Some instances of method 900 and apparatus described herein may further include operations, features, components, or instructions for inverting the second address bit (e.g., at inverter 535) after performing the logical operation; and signaling the inverted second address bit to a logic component (e.g., XOR component 425-a) coupled to a first latch (e.g., latch 420-a-11).

[0144] Some examples of method 900 and apparatus described herein may further include operations, features, means, or instructions for performing (eg, at AND component 430) a second logical operation on a signal representing the first address bit, the second address bit, and the inverted second address bit.

[0145] In some examples, method 900 may be performed by an apparatus. The apparatus may include: a first latch (e.g., latch 320-a or latch 420-a-11) configured to store an address bit associated with an access line identified as defective; a second latch (e.g., latch 320-b or latch 420-b) configured to store at least one bit (e.g., an enable bit) indicating that the first latch is storing the address bit; a first logic component (e.g., logic component 325-a or XOR component 425-a) coupled to the first latch and configured to perform a logic operation on a signal representing at least one address bit stored at the first latch; and a second logic component (e.g., AND component 530) coupled to the second latch and configured to send a second signal representing a second address bit associated with an access line selected for a memory access operation to the first logic component based on the at least one bit stored at the second latch.

[0146] Some examples of the apparatus may include a conductive path coupled to an output of the second latch and an input of the second logic component (e.g., conductive path 540-c), and a second conductive path coupled to an output of the second logic component and an input of the first logic component (e.g., conductive path 540-a). In such examples, the apparatus may include an inverter coupled to an output of the second logic component (e.g., inverter 535), and a third conductive path coupled to an output of the inverter and a second input of the first logic component (e.g., conductive path 540-b).

[0147] Some examples of the apparatus may include a third logic component (eg, logic component 325 - b or AND component 430 ) coupled with an output of the first logic component and an output of the second latch.

[0148] In some examples, the first latch may be configured to output a signal representing an address bit to the first logic component, and the second latch may be configured to output a third signal representing at least one bit to the second logic component.

[0149] In some examples (e.g., when the second logic component is an AND component), the apparatus may include an inverter coupled with the AND component and the first logic component (e.g., inverter 535). The inverter may be configured to send a third signal representing a complement version of the second address bit to the first logic component.

[0150] Fig.10 A flowchart illustrating one or more methods 1000 for supporting an efficient power scheme for redundancy according to examples disclosed herein is shown. The operations of the method 1000 may be implemented by a memory controller or components thereof as described herein. For example, the operations of the method 1000 may be implemented by a memory controller or components thereof as described herein. Figure 8The memory controller described herein may perform the described functions. In some examples, the memory controller may execute a set of instructions to control the functional elements of the memory controller to perform the described functions. Additionally or alternatively, the memory controller may use dedicated hardware to perform the described functions.

[0151] At 1005, the method may include storing at a set of latches a memory address associated with a memory component identified as unreliable. For example, the set of latches may be included in a repair circuit such as repair circuit 715-a. Operation 1005 may be performed according to the methods described herein. In some examples, operation 1005 may be performed as described in reference to Figure 8 Describes the storage manager implementation.

[0152] At 1010, the method may include storing at least one bit at a latch indicating that the set of latches is storing a memory address. In some examples, the latch may be included in a repair circuit. Operation 1010 may be performed according to the methods described herein. In some examples, the method may be performed as described in reference to Figure 8 The storage manager is described as performing operation 1010 .

[0153] At 1015, the method may include sending a signal representing at least one bit to a switching component (e.g., switching component 720-a) coupled to the set of latches and a power supply (e.g., power supply 725-a). Operation 1015 may be performed according to the methods described herein. In some examples, operation 1015 may be performed as described in reference to Figure 8 Describes the Signaling Manager implementation.

[0154] At 1020, the method may include activating a switching component based on a signal representing at least one bit to couple a power supply to the set of latches. Operation 1020 may be performed according to the methods described herein. In some examples, the method may be implemented as described in reference to Figure 8 The component manager described performs operation 1020 .

[0155] In some examples, an apparatus as described herein may perform one or more methods, such as method 1000. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: storing at a set of latches a memory address associated with a memory component identified as unreliable; storing at least one bit at the latch indicating that the set of latches is storing the memory address; sending a signal representing at least one bit to a switching component coupled to the set of latches and a power supply; and activating the switching component based on the signal representing at least one bit to couple the power supply with the set of latches.

[0156] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for the following operations: storing a second memory address associated with a second memory component identified as unreliable at a second set of latches. In such cases, activating the switching component may couple the power supply with the second set of latches. The group of latches may be included in a repair circuit (e.g., repair circuit 615-a) included in the logic group 610, or the second set of latches may be included in a repair circuit (e.g., repair circuit 715-a) included in the logic group 710. The method 1000 and apparatus described herein may further include operations, features, components, or instructions for the following operations: storing at a second latch at least one second bit indicating whether the second set of latches may be storing a second memory address associated with a second memory component identified as unreliable; modifying a state of a second switching component (e.g., switching component 720-b) based on the at least one second bit. The second switching component may be coupled to the power supply and the second set of latches.

[0157] In some instances of method 1000 and apparatus described herein, operations, features, components, or instructions for modifying the state of a second switching component may include operations, features, components, or instructions for deactivating the switching component (e.g., when at least one second bit indicates that the second group of latches may be storing a second memory address) to isolate the power supply from the second group of latches.

[0158] In some instances of method 1000 and apparatus described herein, operations, features, components, or instructions for modifying the state of a second switching component may include operations, features, components, or instructions for activating the second switching component (e.g., when at least one second bit indicates that the second group of latches may not be storing a second memory address) to establish a conductive path from a power supply to the second group of latches.

[0159] It should be noted that the methods described above describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more methods may be combined.

[0160] In some examples, method 1000 may be performed by an apparatus. The apparatus may include a set of latches (e.g., in repair circuit 615-a or 715-a) configured to store memory address information, latches (e.g., in the same repair circuit) configured to store at least one bit indicating whether the set of latches stores a memory address associated with an access line identified as defective, a power supply (e.g., power supply 625 or power supply 725-a) coupled to the set of latches and the latches, and a switching component (e.g., switching component 620 or switching component 720-a) coupled to the latches and configured to activate or deactivate based on at least one bit stored at the latches.

[0161] In some examples, a switching component may be coupled to an output of the latch and may be configured to receive a signal representative of at least one bit.

[0162] In some examples, the switching component may be configured to establish a conductive path from a power supply to the set of latches when at least one bit indicates that the set of latches stores a memory address.

[0163] In some examples, the switching component may be configured to isolate a power supply from the set of latches when at least one bit indicates that the set of latches stores information other than a memory address.

[0164] Some instances of the device may include a second set of latches (e.g., in another repair circuit 615 or repair circuit 715-b) configured to store a second memory address associated with a second access line identified as defective; and a second latch configured to store at least one second bit indicating whether the second set of latches stores the second memory address.

[0165] In some examples, a switching component (eg, switching component 620) can be configured to isolate the power supply from the second set of latches and the second latch when at least one bit stored by the latches indicates that the set of latches stores information other than memory address information.

[0166] Some instances of the apparatus may include a second switching component (e.g., switching component 720-b) coupled to the second latch and configured to establish a second conductive path from the power supply to the second set of latches based on at least one second bit stored at the second latch.

[0167] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have various bit widths.

[0168] As used herein, the term "virtual ground" refers to a node of a circuit that is held at a voltage of approximately zero volts (0V) but is not directly coupled to ground. Thus, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V in a steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. "Virtual ground" or "virtual ground" means connected to approximately 0V.

[0169] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device that includes the connected components, the conductive path between the components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, for example, one or more intermediate components (such as switches or transistors) may be used to interrupt the flow of signals between the connected components for a period of time.

[0170] The term "couple" refers to a transition from an open circuit relationship between components (where signals are currently unable to communicate between components via conductive paths) to a closed circuit relationship between components (where signals are able to communicate between components via conductive paths). When a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not allow signal flow.

[0171] The term "isolation" refers to a relationship between components where a signal is currently unable to flow between the components. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between the components are isolated from one another when the switch is open. When a controller isolates two components from one another, the controller brings about a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0172] As used herein, the term "layer" refers to a level or piece of a geometric structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. A layer may include different elements, components, and / or materials. In some cases, a layer may be composed of two or more sub-layers. In some figures, two dimensions of a three-dimensional layer are depicted for illustrative purposes.

[0173] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0174] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated." A transistor may be "turned off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

[0175] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or that may be within the scope of the claims. The term "exemplary" as used herein means "used as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0176] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. When only the first reference label is used in the specification, the description may apply to any of the similar components with the same first reference label, regardless of the second reference label.

[0177] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0178] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0179] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of the software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination of these. The features of the implementation functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations. In addition, as used herein, included in the claims, such as a list of items (e.g., a list of items starting with a phrase such as "at least one" or "one or more"), the "or" used indicates a list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as a reference to a conditional closed set. For example, without departing from the scope of the present invention, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0180] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media that can be accessed by a general or special purpose computer. By way of example but not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory media that can be used to carry or store the desired program code device in the form of an instruction or data structure and can be accessed by a general or special purpose computer or a general or special purpose processor. Also, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server or other remote source using coaxial cable, optical cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then coaxial cable, optical cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0181] The description herein is provided to enable one skilled in the art to make or use the invention. Various modifications of the invention will be readily apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a set of latches configured to store memory address information; latches configured to store at least one bit indicating whether the set of latches stores a memory address associated with an access line identified as defective; a power supply coupled to the set of latches and the latch; and A switching component is coupled to the latch and configured to activate or deactivate based at least in part on the at least one bit stored at the latch. 2 . The apparatus of claim 1 , wherein the switching component is coupled to an output of the latch and is configured to receive a signal representing the at least one bit.

3. The apparatus of claim 1, wherein the switching component is configured to establish a conductive path from the power supply to the set latch when the at least one bit indicates that the set latch stores the memory address.

4. The apparatus of claim 1, wherein the switching component is configured to isolate the power supply from the set latch when the at least one bit indicates that the set latch stores information other than the memory address.

5. The apparatus of claim 1, further comprising: a second set of latches configured to store a second memory address associated with a second access line identified as defective; and Second latches are configured to store at least one second bit indicating whether the second set of latches stores the second memory address.

6. The apparatus of claim 5, wherein the switching component is configured to isolate the power supply from the second set of latches and the second latch when the at least one bit stored by the latch indicates that the set of latches stores information different from the memory address information.

7. The apparatus according to claim 5, further comprising: A second switching component is coupled to the second latch and is configured to establish a second conductive path from the power supply to the second set of latches based at least in part on the at least one second bit stored at the second latch.

8. The apparatus of claim 5, further comprising: a second power supply; and A second switching component is coupled to the second latch and is configured to establish a second conductive path from the second power supply to the second set of latches based at least in part on the at least one second bit stored at the second latch.

9. A method comprising: storing, at a set of latches, memory addresses associated with memory components identified as unreliable; storing at least one bit at a latch indicating that the set of latches is storing the memory address; sending a signal representing the at least one bit to a switching component coupled to the set of latches and a power supply; and The switching component is activated based at least in part on the signal representing the at least one bit to couple the power supply with the set of latches.

10. The method according to claim 9, further comprising: A second memory address associated with a second memory component identified as unreliable is stored at a second set of latches, wherein activating the switching component couples the power supply with the second set of latches.

11. The method according to claim 9, further comprising: storing at least one second bit at the second latch that indicates whether the second set of latches is storing a second memory address associated with a second memory component identified as unreliable; and Based at least in part on the at least one second bit, a state of a second switching component is modified, the second switching component being coupled to the power supply and the second set of latches.

12. The method of claim 11, wherein modifying the state of the second switching component comprises: When the at least one second bit indicates that the second set of latches is storing the second memory address, the switching component is deactivated to isolate the power supply from the second set of latches.

13. The method of claim 11 , wherein modifying the state of the second switching component comprises: When the at least one second bit indicates that the second set of latches is not storing the second memory address, the second switching component is activated to establish a conductive path from the power supply to the second set of latches.

14. The method according to claim 9, further comprising: storing at least one second bit at the second latch that indicates whether the second set of latches is storing a second memory address associated with a second memory component identified as unreliable; and Based at least in part on the at least one second bit, a state of a second switching component is modified, the second switching component being coupled to a second power supply and the second set of latches.

15. A memory system comprising: one or more memory arrays; and One or more controllers coupled to the one or more memory arrays and configured to cause the memory system to: storing, at a set of latches, memory addresses associated with memory components identified as unreliable; storing at least one bit at a latch indicating that the set of latches is storing the memory address; sending a signal representing the at least one bit to a switching component coupled to the set of latches and a power supply; and The switching component is activated based at least in part on the signal representing the at least one bit to couple the power supply with the set of latches.

16. The memory system of claim 15, wherein the one or more controllers are further configured to cause the memory system to: A second memory address associated with a second memory component identified as unreliable is stored at a second set of latches, wherein activating the switching component couples the power supply with the second set of latches.

17. The memory system of claim 15, wherein the one or more controllers are further configured to cause the memory system to: storing at least one second bit at the second latches that indicates whether the second set of latches is storing a second memory address associated with a second memory component identified as unreliable; and Based at least in part on the at least one second bit, a state of a second switching component is modified, the second switching component being coupled to the power supply and the second set of latches.

18. The memory system of claim 17, wherein to modify the state of the second switching component, the one or more controllers are configured to cause the memory system to: When the at least one second bit indicates that the second set of latches is storing the second memory address, the switching component is deactivated to isolate the power supply from the second set of latches.

19. The memory system of claim 17, wherein to modify the state of the second switching component, wherein the one or more controllers are configured to cause the memory system to: When the at least one second bit indicates that the second set of latches is not storing the second memory address, the second switching component is activated to establish a conductive path from the power supply to the second set of latches.

20. The memory system of claim 15, wherein the one or more controllers are further configured to cause the memory system to: storing at least one second bit at the second latches that indicates whether the second set of latches is storing a second memory address associated with a second memory component identified as unreliable; and Based at least in part on the at least one second bit, a state of a second switching component is modified, the second switching component being coupled to a second power supply and the second set of latches.

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