Memory reading circuit offset elimination system based on programmable CTT

Abstract

The invention provides a memory reading circuit offset elimination system based on a programmable CTT. The system comprises the programmable CTT, a memory reading circuit and a time-to-digital converter, the programmable CTT is arranged in the memory reading circuit, and the time-to-digital converter is connected with the memory reading circuit; the time-to-digital converter is configured to obtain read data of the memory read circuit, judge whether the memory read circuit is in imbalance or not according to the read data and generate a judgment result; the memory readout circuit is configured to output the readout data; and judging whether to program the programmable CTT or not according to the judgment result. According to the system, the problem of application limitation of an existing readout circuit offset elimination technology is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a memory readout circuit offset elimination system based on programmable CTT. Background Art

[0002] In the design and operation of electronic systems, the offset elimination of memory readout circuits has always been an important technical challenge. In order to ensure the accuracy and stability of data, the industry has adopted a variety of methods to deal with this problem. Among them, auto-zero technology has become one of the main methods for eliminating the offset of memory readout circuits due to its unique working principle and high precision.

[0003] Auto-zero technology is a time domain modulation method that mainly corrects the offset through sampling. This technology is often combined with a switched capacitor circuit to store the offset voltage on the capacitor during the sampling phase, and then eliminate the offset during the signal operation phase. The offset voltage of this method can exist at the input or output of the op amp, and its working principle relies on the high gain characteristics of the op amp itself.

[0004] In the implementation of auto-zero technology, the circuit will go through two main stages: the offset elimination cycle (AZ stage) and the signal amplification cycle (AMP stage). In the AZ stage, the circuit will disconnect the signal input and connect the input of the op amp to the AC ground (VCM). At this time, the switch capacitor will store the charge generated by the offset voltage (Vos). In the AMP stage, the signal input will be connected to the loop. At this time, the offset voltage charge stored on the capacitor will participate in the operation together with the input signal, but because the offset voltage has been pre-sampled and stored on the capacitor, it will be eliminated during the signal amplification process, thereby achieving offset correction.

[0005] However, auto-zero technology also has some obvious limitations. First, because the technology requires dynamic refreshing, it is not suitable for continuous-time applications. This means that in some occasions that require continuous signal processing, auto-zero technology may not meet the requirements. Secondly, the overall circuit structure of auto-zero technology is relatively complex, which increases the difficulty of design and implementation. In addition, the sampling process may also cause noise to return to low frequencies to produce aliasing, which manifests as higher low-frequency noise. Summary of the invention

[0006] The present application provides a memory readout circuit offset elimination system based on programmable CTT to solve the application limitation problem of existing readout circuit offset elimination technology.

[0007] The system comprises:

[0008] A programmable CTT, a memory readout circuit and a time-to-digital converter; the programmable CTT is arranged in the memory readout circuit, and the time-to-digital converter is connected to the memory readout circuit;

[0009] The time-to-digital converter is configured to obtain readout data of the memory readout circuit, and determine whether the memory readout circuit is out of adjustment according to the readout data, and generate a determination result;

[0010] The memory read circuit is configured to output the read data; and determine whether to program the programmable CTT according to the determination result.

[0011] Preferably, the memory readout circuit includes a positive phase output OUT, a negative phase output OUTB and a clock signal port CLK;

[0012] The memory readout circuit is further configured to:

[0013] Respectively obtaining a first voltage conversion condition of the positive phase output OUT and a second voltage conversion condition of the negative phase output OUTB;

[0014] Obtaining the signal value change of the clock signal port CLK;

[0015] Calculate the first time from the positive phase output OUT starting to have the first voltage conversion to the clock signal port CLK completing the signal value conversion;

[0016] Calculate a second time from when the inverted output OUTB starts to experience the second voltage conversion to when the clock signal port CLK completes the signal value conversion;

[0017] The first time is subtracted from the second time to obtain the read data.

[0018] Preferably, the memory readout circuit further comprises a first circuit input BL and a second circuit input BLB;

[0019] When a voltage difference occurs between the first circuit input BL and the second circuit input BLB, a voltage change occurs at the positive phase output OUT or the negative phase output OUTB, and a signal value change occurs at the clock signal port CLK.

[0020] Preferably, when the voltage difference between the first circuit input BL and the second circuit input BLB is a negative voltage difference, the positive phase output OUT is converted from a high level to a low level; the first voltage conversion condition is process information of the positive phase output OUT being converted from a high level to a low level;

[0021] When the voltage difference between the first circuit input BL and the second circuit input BLB is a positive voltage difference, the inverting output OUTB is converted from a high level to a low level; the second voltage conversion condition is process information of the inverting output OUTB being converted from a high level to a low level.

[0022] Preferably, the programmable CTT includes CTT1 and CTT2; the CTT1 is arranged at one end of the first circuit input BL, and the CTT2 is arranged at one end of the second circuit input BLB;

[0023] The memory readout circuit is further configured to:

[0024] Whether to program the CTT1 or the CTT2 is determined according to the value of the determination result.

[0025] Preferably, the time-to-digital converter is further configured to:

[0026] When the value of the read data is less than zero, a first judgment result is generated;

[0027] When the value of the read data is greater than zero, a second judgment result is generated;

[0028] The memory readout circuit is further configured to:

[0029] Programming the CTT1 according to the first judgment result;

[0030] The CTT2 is programmed according to the second judgment result.

[0031] Preferably, the time-to-digital converter comprises a quantization port STP, the quantization port STP is connected to the positive phase output OUT and the negative phase output OUTB respectively, and the quantization port STP is configured as:

[0032] Acquire first quantized data of the positive phase output OUT and second quantized data of the negative phase output OUTB;

[0033] Subtract the first quantized data from the second quantized data to obtain target quantized data;

[0034] Whether to program the CTT1 or the CTT2 is determined according to the target quantization data.

[0035] Preferably, the signal value conversion condition is process information of the clock signal port CLK changing from a low voltage to a high voltage; the time-to-digital converter further includes a plurality of delay units d, and the frontmost delay unit d is connected to the clock signal port CLK;

[0036] The delay unit d at the front is configured as follows:

[0037] When the voltage of the clock signal port CLK changes, the signal value change of the clock signal port CLK is sent to the next delay unit d after a preset time.

[0038] Preferably, the time-to-digital converter further comprises a plurality of comparators A;

[0039] The comparator A is configured as:

[0040] The first quantized data and the second quantized data are subtracted to obtain target quantized data.

[0041] Preferably, the time-to-digital converter further comprises a plurality of interpolation circuits PI, all of which are connected in parallel, and each group of three interpolation circuits PI are connected in parallel between two delay units d, and the interpolation circuits PI in the same group are connected to the corresponding comparator A;

[0042] The interpolation circuit PI is configured as follows:

[0043] The signal value change condition output by the front delay unit d is sent to the comparator A after half of the preset time.

[0044] As can be seen from the above content, the present application provides a memory read circuit offset elimination system based on programmable CTT, the system includes a programmable CTT, a memory read circuit and a time-to-digital converter; the programmable CTT is arranged in the memory read circuit, and the time-to-digital converter is connected to the memory read circuit; the time-to-digital converter is configured to obtain the read data of the memory read circuit, and judge whether the memory read circuit is offset according to the read data, and generate a judgment result; the memory read circuit is configured to output the read data; and judge whether to program the programmable CTT according to the judgment result. The present application solves the application limitation problem of the existing read circuit offset elimination technology through the above system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 A schematic diagram of a memory readout circuit offset elimination system based on programmable CTT in the present application;

[0047] Figure 2 A schematic diagram of an implementation of a memory readout circuit in a memory readout circuit offset elimination system based on programmable CTT of the present application;

[0048] Figure 3 A schematic diagram of an implementation of a time-to-digital converter in a memory readout circuit offset elimination system based on programmable CTT of the present application;

[0049] Figure 4 This is a schematic diagram of an implementation of an interpolation circuit PI in a memory readout circuit offset elimination system based on a programmable CTT of the present application;

[0050] Figure 5 This is a schematic diagram of an implementation of a comparator A in a memory readout circuit offset elimination system based on a programmable CTT of the present application;

[0051] Figure 6 This is a waveform diagram of quantization processing of a time-to-digital converter in a memory readout circuit offset elimination system based on programmable CTT in the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0054] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0055] Figure 1 A schematic diagram of a memory readout circuit offset elimination system based on programmable CTT according to the present application.

[0056] See also Figure 1It can be seen that this embodiment provides a memory read circuit offset elimination system based on a programmable CTT, the system comprising a programmable CTT, a memory read circuit and a time-to-digital converter; the programmable CTT is arranged in the memory read circuit, and the time-to-digital converter is connected to the memory read circuit; the time-to-digital converter is configured to obtain the read data of the memory read circuit, and judge whether the memory read circuit is offset according to the read data, and generate a judgment result; the memory read circuit is configured to output the read data; and judge whether to program the programmable CTT according to the judgment result.

[0057] Specifically, in this embodiment, this embodiment is used to eliminate the mismatch characteristics (offset voltage) caused by process errors in the memory read circuit. By utilizing the different output delays of reading '1' and '0' caused by the offset voltage in the memory read circuit, the programmable CTT in the memory read circuit is programmed to keep the output delays of reading '1' and '0' consistent, thereby achieving the purpose of eliminating the offset voltage.

[0058] Figure 2 The present invention is a schematic diagram of an implementation of a memory readout circuit in a memory readout circuit offset elimination system based on programmable CTT.

[0059] in, Figure 2 T1 to T12 are all CMOS tubes; CH and CHB are ports when the programmable CTT is programmed; when the programmable CTT is programmed, the voltage of the CH port drops from 0.9V to 0V, and the voltage of the CHB port rises from 0V to 0.9V; when working normally, the voltage of the CH port is 0.9V, and the voltage of the CHB port is 0V; CLK is the clock signal port CLK; OUT is the positive phase output OUT; OUTB is the negative phase output OUTB; BL is the first circuit input BL; BLB is the second circuit input BL Input BLB; HV_CH is the programming port. When the programmable CTT is programmed, the voltage of the HV_CH port drops from 1.8V to 0V. When working normally, the voltage of the HV_CH port is 1.8V; HV_P1 and HV_P2 are both programming signal terminals. If CTT1 is to be programmed, the voltage of HV_P1 is 1.8V and HV_P2 is 0V. If CTT2 is to be programmed, the voltage of HV_P1 is 0V and HV_P2 is 1.8V; P1 and P2 are thick gate oxide tubes that can withstand a voltage of 1.8V.

[0060] See also Figure 2 It can be seen that, further, in some embodiments, the memory readout circuit includes a positive phase output OUT, a negative phase output OUTB and a clock signal port CLK;

[0061] The memory readout circuit is further configured to:

[0062] Respectively obtaining a first voltage conversion condition of the positive phase output OUT and a second voltage conversion condition of the negative phase output OUTB;

[0063] Obtaining the signal value change of the clock signal port CLK;

[0064] Calculate the first time from the positive phase output OUT starting to have the first voltage conversion to the clock signal port CLK completing the signal value conversion;

[0065] Calculate a second time from when the inverted output OUTB starts to experience the second voltage conversion to when the clock signal port CLK completes the signal value conversion;

[0066] The first time is subtracted from the second time to obtain the read data.

[0067] Specifically, in this embodiment, since the clock signal of the clock signal port CLK reaches the positive output OUT and the negative output OUTB at different times, the output delay of the readout '1' and '0' of the clock signal port CLK may be caused by the offset voltage of the memory readout circuit.

[0068] Among them, the first time from the beginning of the first voltage change at the positive phase output OUT to the completion of the signal value change at the clock signal port CLK is the time required for the clock signal to reach the clock signal port CLK from the positive phase output OUT, and the second time from the beginning of the second voltage change at the negative phase output OUTB to the completion of the signal value change at the clock signal port CLK is the time required for the clock signal to reach the clock signal port CLK from the negative phase output OUTB.

[0069] Whether the memory readout circuit has a circuit imbalance problem is determined by using the readout data obtained by subtracting the first time from the second time.

[0070] Wherein, the memory read-out circuit also includes a first circuit input BL and a second circuit input BLB; when a voltage difference occurs between the first circuit input BL and the second circuit input BLB, a voltage change occurs at the positive output OUT or the negative output OUTB, and a signal value change occurs at the clock signal port CLK.

[0071] Since the voltage difference between the first circuit input BL and the second circuit input BLB is not maintained constant, the present embodiment also has the following implementation methods for the voltage difference in different situations:

[0072] When the voltage difference between the first circuit input BL and the second circuit input BLB is a negative voltage difference, the positive phase output OUT is converted from a high level to a low level; the first voltage conversion condition is process information of the positive phase output OUT being converted from a high level to a low level;

[0073] When the voltage difference between the first circuit input BL and the second circuit input BLB is a positive voltage difference, the inverting output OUTB is converted from a high level to a low level; the second voltage conversion condition is process information of the inverting output OUTB being converted from a high level to a low level.

[0074] according to Figure 2 It can be seen that the programmable CTT includes CTT1 and CTT2; the CTT1 is set at one end of the first circuit input BL, and the CTT2 is set at one end of the second circuit input BLB. Since the read data obtained by subtracting the first time from the second time has positive and complex situations, the CTT programming for different situations is also different. Therefore, it is necessary to determine whether to program the CTT1 or the CTT2 through the memory read circuit according to the corresponding judgment result generated by the time-to-digital converter.

[0075] The time-to-digital converter generates the corresponding judgment result by judging the positive and negative values ​​of the judgment result, specifically, when the value of the read data is less than zero, a first judgment result is generated; when the value of the read data is greater than zero, a second judgment result is generated.

[0076] Similarly, when the memory read circuit receives the first judgment result, it programs the CTT1; when the memory read circuit receives the second judgment result, it programs the CTT2.

[0077] For example, when there is a voltage difference of -ΔV between BL and BLB, CLK rises from 0 to 1, and the OUT terminal changes from a high level to a low level. The time from the rise of CLK to the fall of OUT terminal is T C2OUT Similarly, when there is a voltage difference ΔV between BL and BLB, when CLK rises from 0 to 1, OUTB will change from high level to low level. The time from CLK rising to OUTB falling is T C2OUTB . Δt COUT Equal to T C2OUT Subtract T C2OUTB , and Δt COUT is positively correlated with the offset voltage of the readout circuit. Therefore, by reading 0 and 1, we can get Δt COUT , thereby determining whether there is an offset voltage in the circuit.

[0078] The time-to-digital converter is used to determine whether there is an offset voltage, wherein T C2OUT and T C2OUTB The quantization of is achieved by a time-to-digital converter (TDC), which performs the quantization process. Figure 6 .

[0079] Figure 3 This is a schematic diagram of an implementation of a time-to-digital converter in a memory readout circuit offset elimination system based on programmable CTT in the present application.

[0080] Figure 3 In the figure, d is a delay unit; PI is an interpolation circuit; A is a comparator; VDD can be understood as a power supply voltage; STP is a quantization port STP.

[0081] See also Figure 3 It can be seen that, further, in some embodiments, the time-to-digital converter includes a quantization port STP, the quantization port STP is connected to the positive phase output OUT and the negative phase output OUTB respectively, and the quantization port STP is configured as:

[0082] Acquire first quantized data of the positive phase output OUT and second quantized data of the negative phase output OUTB;

[0083] Subtract the first quantized data from the second quantized data to obtain target quantized data;

[0084] Whether to program the CTT1 or the CTT2 is determined according to the target quantization data.

[0085] Specifically, in this embodiment, for the read data generated by the memory read circuit, effective data acquisition can be performed after quantization processing, so it is necessary to quantize the data acquired from the positive phase output OUT and the negative phase output OUTB respectively through the quantization port STP on the time-to-digital converter, and the specific method can be understood as follows:

[0086] The first quantized data of the positive phase output OUT and the second quantized data of the negative phase output OUTB are obtained respectively, and the difference between the two is processed. The difference data obtained is the final data for measuring whether the circuit is out of adjustment, programming CTT1 or programming CTT2.

[0087] Exemplarily, when CLK rises, counting starts. If STP also rises, the time from CLK to STP rise is converted into a 5-bit digital quantity. When 0 is read, STP is the signal of the OUT port; when 1 is read, STP is the signal of the OUTB port. By comparing the 5-bit data D0[4:0] quantized when 0 is read with the 5-bit data D1[4:0] quantized when 1 is read, it can be determined whether there is an offset voltage. If the two 5-bit data values ​​are the same, it is considered that there is no offset voltage; if they are different, CTT1 or CTT2 of the read circuit will be programmed to increase its VTH value.

[0088] When D0[4:0] is less than D1[4:0], it means that ΔtCQ is less than 0, so CTT1 needs to be programmed. The specific operation is as follows: Set the HV_CH and CH voltages to 0V, CHB to 0.9V, and apply a 1.8V voltage pulse through HV_P1 to program CTT1 to increase its VTH. After programming, read out 0 and 1 again to obtain D0[4:0] and D1[4:0], and compare them. If the two are equal, it is considered that the offset voltage has been eliminated; if they are not equal, continue programming until they are equal.

[0089] Further, in some embodiments, the signal value conversion condition is process information of the clock signal port CLK changing from a low voltage to a high voltage; the time-to-digital converter further includes a plurality of delay units d, and the frontmost delay unit d is connected to the clock signal port CLK;

[0090] The delay unit d at the front is configured as follows:

[0091] When the voltage of the clock signal port CLK changes, the signal value change of the clock signal port CLK is sent to the next delay unit d after a preset time.

[0092] Specifically, in this embodiment, if the clock signal CLK rises from a low voltage to a high voltage, after passing through the delay unit d, the signal CLK1 after the delay unit d needs to go through a fixed delay time t1 before it can rise. Subsequently, after another fixed delay time t1, CLK2 can rise.

[0093] Figure 4 This is a schematic diagram of an implementation of an interpolation circuit PI in a memory readout circuit offset elimination system based on a programmable CTT of the present application.

[0094] Figure 5 Schematic diagram of the implementation of comparator A in a memory readout circuit offset elimination system based on programmable CTT in this application

[0095] See also Figure 4 and Figure 5 It can be seen that, further, in some embodiments, the time-to-digital converter further includes a plurality of comparators A;

[0096] The comparator A is configured as:

[0097] Subtract the first quantized data from the second quantized data to obtain target quantized data;

[0098] The time-to-digital converter further comprises a plurality of interpolation circuits PI, all of which are connected in parallel, and each group of three interpolation circuits PI are connected in parallel between two delay units d, and the interpolation circuits PI in the same group are connected to the corresponding comparator A;

[0099] The interpolation circuit PI is configured as follows:

[0100] The signal value change condition output by the front delay unit d is sent to the comparator A after half of the preset time.

[0101] Since the time t1 in the integrated circuit has a minimum value, in order to obtain a smaller time t2, we need to process the CLK1 and CLK2 signals to achieve a smaller delay time t2. Therefore, we design an interpolation circuit PI.

[0102] The interpolation circuit PI divides the delay t1 from CLK1 to CLK2 into two equal delays t2. For example, Figure 3 The outputs of CLK1 and CLK2, O <1> The result is that both inputs of the interpolation circuit PI are CLK1. <3> Both inputs are the result of CLK2, and O <2> is the result of two inputs, CLK1 and CLK2. Since the delay between CLK1 and CLK2 is t1, the interpolation circuit PI can divide t1 into two equal t2, so O <2> O <1> Delay 0.5t1, and than O <3> Faster than 0.5t1.

[0103] It can be understood that the phase interpolation circuit PI can divide the difference t between the rise time of PI1 and the rise time of PI2 into two equal parts. For example, when PI1 changes from a low level to a high level at time t1, and PI2 changes from a high level at time 2t1, OUT will change from a low level to a high level at time 1.5t1.

[0104] Output O of 31 interpolation circuits PI <1> to <31> Connected to the CQ ports of 31 comparators A, the STP ports of these 31 comparators A are connected. When the voltage of the CQ port rises earlier than the voltage of the STP port, the output AOUT of comparator A is high; conversely, when the voltage of the CQ port rises later than the voltage of the STP port, AOUT is low. Therefore, when CLK rises, the CLK signal passes through a series of delay units d, is connected to the interpolation circuit PI, and is finally transmitted to the CQ port of comparator A. When STP also rises, the time between CLK and STP will be converted into a digital signal. For example, if the time from CLK to STP is 6t1, the outputs of the first 12 comparators A will be high, and the outputs from 13 to 31 will be low. Finally, these 31 output levels are converted into 5-bit data D[4:0] through the thermometer code to binary code circuit (T2B).

[0105] It can be understood that, in comparator A, when the rising time of CQ is earlier than STP, the output of AOUT is high level; if the rising time of CQ is later than STP, the output of AOUT is low level.

[0106] This embodiment has the following advantages:

[0107] A simple and efficient method is used to achieve high-precision offset elimination of a memory readout circuit, thereby avoiding the problem that the circuit offset elimination cannot be performed on a continuous time, continuous signal or complex circuit due to the limitations of the auto-zero technology.

[0108] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A memory readout circuit offset elimination system based on programmable CTT, characterized in that: The system includes a programmable CTT, a memory readout circuit and a time-to-digital converter; the programmable CTT is arranged in the memory readout circuit, and the time-to-digital converter is connected to the memory readout circuit; The time-to-digital converter is configured to obtain readout data of the memory readout circuit, and determine whether the memory readout circuit is out of adjustment according to the readout data, and generate a determination result; The memory readout circuit is configured to output the readout data; It is determined whether to program the programmable CTT according to the determination result.

2. The memory readout circuit offset elimination system based on programmable CTT according to claim 1, characterized in that: The memory readout circuit includes a positive phase output OUT, a negative phase output OUTB and a clock signal port CLK; The memory readout circuit is further configured to: Respectively obtaining a first voltage conversion condition of the positive phase output OUT and a second voltage conversion condition of the negative phase output OUTB; Obtaining the signal value change of the clock signal port CLK; Calculate the first time from the positive phase output OUT starting to have the first voltage conversion to the clock signal port CLK completing the signal value conversion; Calculate a second time from when the inverted output OUTB starts to experience the second voltage conversion to when the clock signal port CLK completes the signal value conversion; The first time is subtracted from the second time to obtain the read data.

3. The memory readout circuit offset elimination system based on programmable CTT according to claim 2, characterized in that: The memory readout circuit further includes a first circuit input BL and a second circuit input BLB; When a voltage difference occurs between the first circuit input BL and the second circuit input BLB, a voltage change occurs at the positive phase output OUT or the negative phase output OUTB, and a signal value change occurs at the clock signal port CLK.

4. The memory readout circuit offset elimination system based on programmable CTT according to claim 3, characterized in that: When the voltage difference between the first circuit input BL and the second circuit input BLB is a negative voltage difference, the positive phase output OUT is converted from a high level to a low level; the first voltage conversion condition is process information of the positive phase output OUT being converted from a high level to a low level; When the voltage difference between the first circuit input BL and the second circuit input BLB is a positive voltage difference, the inverting output OUTB is converted from a high level to a low level; the second voltage conversion condition is process information of the inverting output OUTB being converted from a high level to a low level.

5. The memory readout circuit offset elimination system based on programmable CTT according to claim 4, characterized in that: The programmable CTT includes CTT1 and CTT2; the CTT1 is arranged at one end of the first circuit input BL, and the CTT2 is arranged at one end of the second circuit input BLB; The memory readout circuit is further configured to: Whether to program the CTT1 or the CTT2 is determined according to the value of the determination result.

6. The memory readout circuit offset elimination system based on programmable CTT according to claim 5, characterized in that: The time-to-digital converter is further configured to: When the value of the read data is less than zero, a first judgment result is generated; When the value of the read data is greater than zero, a second judgment result is generated; The memory readout circuit is further configured to: Programming the CTT1 according to the first judgment result; The CTT2 is programmed according to the second judgment result.

7. The memory readout circuit offset elimination system based on programmable CTT according to claim 6, characterized in that: The time-to-digital converter comprises a quantization port STP, which is connected to the positive phase output OUT and the negative phase output OUTB respectively, and the quantization port STP is configured as follows: Acquire first quantized data of the positive phase output OUT and second quantized data of the negative phase output OUTB; Subtract the first quantized data from the second quantized data to obtain target quantized data; Whether to program the CTT1 or the CTT2 is determined according to the target quantization data.

8. The memory readout circuit offset elimination system based on programmable CTT according to claim 7, characterized in that: The signal value conversion is the process information of the clock signal port CLK changing from a low voltage to a high voltage; the time-to-digital converter also includes a plurality of delay units d, and the frontmost delay unit d is connected to the clock signal port CLK; The delay unit d at the front is configured as follows: When the voltage of the clock signal port CLK changes, the signal value change of the clock signal port CLK is sent to the next delay unit d after a preset time.

9. The memory readout circuit offset elimination system based on programmable CTT according to claim 8, characterized in that: The time-to-digital converter also includes a plurality of comparators A; The comparator A is configured as: The first quantized data and the second quantized data are subtracted to obtain target quantized data.

10. The memory readout circuit offset elimination system based on programmable CTT according to claim 9, characterized in that: The time-to-digital converter further comprises a plurality of interpolation circuits PI, all of which are connected in parallel, and each group of three interpolation circuits PI are connected in parallel between two delay units d, and the interpolation circuits PI in the same group are connected to the corresponding comparator A; The interpolation circuit PI is configured as follows: The signal value change condition output by the front delay unit d is sent to the comparator A after half of the preset time.

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