Fast battery charging

Abstract

The invention relates to fast battery charging. Some examples provide battery charging techniques that allow for reasonable fast charging while reducing the charging temperature. In some examples, a target temperature limit is actively maintained by a control loop. In some examples, the CC charging phase is interleaved with the CV phase.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of battery powered delivery; and more particularly to techniques for charging rechargeable batteries. Background Art

[0002] Batteries such as lithium-ion (Li-ion) batteries are widely used in electronic systems such as smartphones, laptops, and electric vehicles due to their high energy density, thereby extending battery life / range. There are several different ways to charge batteries. For example, a technique known as constant current constant voltage (CC-CV) charging is widely used. Summary of the invention

[0003] According to one embodiment of the present disclosure, a computer-readable storage medium is provided, having instructions that, when executed, perform a method, the method comprising: causing a charger to apply a first constant current (CC) charging phase to a battery; and interleaving the first CC phase with at least one constant voltage (CV) charging phase.

[0004] According to one embodiment of the present disclosure, a computer-readable storage medium is provided, having instructions that, when executed, perform a method, the method comprising: causing a charger to charge current into a battery; monitoring battery temperature; and controlling the charging current until the temperature reaches a target limit that is lower than a rated maximum operating battery temperature.

[0005] According to one embodiment of the present disclosure, a computing system is provided, comprising: a platform processor; a control unit coupled to the platform processor; and a charger for charging a battery that will provide power to the computing system, wherein the control unit is used to control the charger so that the charger applies a first constant current (CC) charging phase to the battery, and the control unit is used to interleave the first CC phase with at least one constant voltage (CV) charging phase.

[0006] According to one embodiment of the present disclosure, a computing system is provided, comprising: a platform processor; a control unit coupled to the platform processor; and a charger for charging a battery that will provide power to the computing system, wherein the control unit is used to: enable the charger to charge current into the battery; monitor battery temperature; and control the charging current until the temperature reaches a target limit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention may be best understood by referring to the following description and accompanying drawings which illustrate embodiments of the invention. In the drawings:

[0008] Figure 1A and Figure 1BA conventional CC-CV-CC-CV method for fast battery charging is shown.

[0009] Figure 2 is a block diagram illustrating a computing platform with a battery charging system according to some embodiments.

[0010] Figure 3 is a flow chart illustrating a routine for charging a battery according to some embodiments.

[0011] Figure 4 FIG. 2 is a diagram showing a method for charging a battery according to some embodiments. Figure 3 A flowchart of an exemplary implementation of a routine.

[0012] Figure 5A and Figure 5B is a graph showing a representative charging profile according to some embodiments.

[0013] Fig. 6A is a graph showing charging performance characteristics of a conventional fast charging scheme.

[0014] Figure 6B is a graph illustrating charging performance characteristics of an exemplary fast charging scheme according to some embodiments.

[0015] Figure 6C is a graph comparing the life cycle performance of a conventional fast charging method and an exemplary fast charging method according to some embodiments.

[0016] Figure 7 is a flow chart illustrating a routine for implementing a temperature controlled fast charging method according to some embodiments.

[0017] Figure 8 An example computing system is shown in accordance with some embodiments.

[0018] Fig. 9 According to some embodiments Figure 8 Block diagram of an example processor and / or SoC for a system. DETAILED DESCRIPTION

[0019] Batteries such as lithium-ion (Li-ion) batteries are widely used in electronic systems such as smartphones, laptops and electric vehicles due to their high energy density, thereby extending battery life / range. There are several different ways to charge batteries. For example, a technique known as constant current constant voltage (CC-CV) charging is widely used. It involves charging the battery with a constant current until it reaches a predetermined voltage level, after which the charging voltage is kept constant while the current is gradually reduced until the battery is fully charged. This technique works well, but it is relatively slow, and in many mobile systems, it takes more than 2.5 hours to fully charge the battery pack.

[0020] In response to user demand for faster charging, so-called fast charging strategies have been developed, such as the CC-CV-CC-CV method. It involves charging the battery at a constant current until a predetermined voltage level is reached, after which the charge voltage is held constant while the current is gradually reduced. The battery is then charged at a lower constant current until it reaches a higher predetermined voltage level, after which the charge voltage is held constant while the current is gradually reduced. This cycle is repeated as many times as necessary to fully charge the battery. Examples of CC-CV-CC-CV methods are Figure 1A and Figure 1B As shown. It can be seen that when the battery state of charge is low, charging starts with an elevated constant current followed by a temporary constant voltage phase. When the current decreases to a certain level during the temporary constant voltage charging phase, an additional CC-CV phase follows, but with a lower current in the CC phase. From a speed perspective, this approach works very well, with charging times improved over previous single-stage implementations. For example, under similar conditions, the two-stage (CC-CV-CC-CV) approach takes only 1.82 hours, while the single-stage (CC-CV) process takes 2.59 hours. Unfortunately, however, in the case of two-stage charging, the battery typically has a shorter cycle life (the number of charge and discharge cycles before the battery capacity drops significantly). Over time, the decline in battery capacity can affect the performance and expectations of the device. For example, laptop systems typically require at least 80% capacity retention and more than 500 charge and discharge cycles. Unfortunately, it can be difficult to achieve such a goal using conventional two-stage fast charging. For example, it was found that for some representative laptop systems, conventional two-stage fast charging reached 80% in just 220 cycles.

[0021] Therefore, new charging techniques are proposed to address these challenges. One reason why conventional two-stage fast charging has life cycle issues is that it may impose relatively high battery charge temperatures for an excessively long period of time. Therefore, techniques are disclosed for achieving fast charging without causing significant battery charge temperatures over time. In some embodiments, excessive continuous current is mitigated by interleaving CV phases within one or more CC phases, thereby reducing the temperature rise that may occur if the total charge time can be tolerably increased.

[0022] In some other approaches, the battery temperature can be regulated during a charge cycle, e.g., to a target temperature limit (which is set below an authorized high temperature region for the battery), while providing a fast charge current, e.g., the highest charge current that can be achieved while remaining within the target temperature limit.

[0023] Figure 2 is a block diagram illustrating a computing platform 200 including a battery charging system according to some embodiments. A control unit 205, a charger 230, and a battery 250 are shown. Also included in the figure is a platform processor 220 and a power source (e.g., an AC adapter, a DC power source, e.g., from another battery or device, etc.) 240 for providing power to the battery 250 and the platform processor 220, as well as other platform components not shown for convenience.

[0024] The battery 250 may include one or more battery cells made of any suitable material including lithium ion, lithium polymer, iron phosphate, etc. or made of any other suitable material. The battery may also include a battery management system (BMS) 255 (also referred to as a protection circuit). The BMS typically protects the battery from overcharging, overdischarging, and external short circuits. Many battery management systems may also include a fuel gauge that allows the control unit 205 to read battery life information. The control unit 205 may also read other data such as measured temperature, charging current, charging voltage, charging level, etc. from the battery, as well as the maximum ratings and other information of these same parameters, although in other embodiments, it may come from another source or sources. In some embodiments, the values ​​and limits of the low temperature, standard temperature, and high temperature safety areas can be read from the battery pack manager (e.g., BMS) and may also be dynamically reflected in the maximum charging current and voltage values, which are periodically read from the battery and used by the battery management subsystem to configure charging.

[0025] The control unit 205 is coupled to the battery 250 through an interface 215, such as a system management bus (SMBus). It is also coupled to a charger 230, which in turn is coupled to the battery 250. In typical operation, the control unit monitors battery parameters and controls the charger to charge the battery under certain specified conditions (e.g., constant current, CC, at a certain current level, constant voltage, CV, at a certain voltage level, etc.).

[0026] The control unit 205 has a memory 210 and logic and other components for executing code (e.g., firmware) for implementing various charging-related functions. For example, it can measure, calculate and / or receive information about the battery 250, including the above parameters, as well as the cutoff voltage (COV), battery charging impedance (Rb), charge percentage, stored power, and charger-related parameters such as charging voltage (Vb), charging current (Ib), power provided to the battery, etc. The control unit 205 may include a timer (not shown) to measure, for example, charging time or temperature check intervals. The control unit can communicate with and / or control the output of the charger 230, which receives power from the power source 240. The charger 205 can operate in different states, including a CC state with a cutoff voltage threshold and / or a constant voltage state with a cutoff current threshold.

[0027] In some embodiments, the charger 205 operates in a constant current (CC) state, a constant voltage (CV) state, a trickle charge state, and / or a disconnected state. The control unit 205 can monitor a threshold (eg, a CC threshold or a CV threshold) and switch the charger 230 between these states.

[0028] It should be understood that the charging system components can be implemented in any suitable manner. For example, the control unit and / or the charger can be part of an integrated circuit, such as a system on a chip (SOC), a power management integrated circuit (PMIC), or a dedicated charger / control unit device. The charging management components can also be separated, such as between the charging system and the battery system. For example, in some embodiments, the techniques described herein can be performed in a control unit, a charger, a battery (e.g., in a BMS), or any combination thereof. It is also noted that the computing platform can be any device with a battery suitable for the charging techniques described herein. For example, it can be a mobile computer, such as a laptop, a tablet, a smartphone, an electric vehicle or other vehicle with a rechargeable battery, an appliance, etc. In addition, the power supply can come from an AC adapter manufactured for the device, or from a multi-function interconnect device capable of charging, such as a universal serial bus (USB) device. Along these lines, some mobile computers include lithium-ion smart battery packs with a BMS within the battery pack, but the embodiments disclosed herein can be equally applied to other devices, for example, where telemetry and other battery management functions are primarily controlled by the device. In this example, the battery is the source of charge voltage, maximum charge current, state of charge, and battery temperature, voltage, and current measurements, but this and other data may come from other sources.

[0029] Figure 3 is a flow chart illustrating a routine for charging a battery according to some embodiments. Initially, at 302, the routine confirms that the battery is ready for fast charging. In doing so, it reads various battery parameters, such as temperature, state of charge, cut-off voltage, and / or charging voltage level, for example to ensure that the battery is neither undercharged nor overcharged. If conditions are satisfactory for charging, the routine proceeds to 304 and defines (or identifies) one or more decreasing CC level stages, each having a starting voltage value (Vcc) to be executed based on the read parameters and design considerations such as charging time, charging limits, etc. In some embodiments, in addition to the first CC stage, each subsequent stage may have a different (possibly increasing) starting voltage level. This is one way to identify when a CC stage begins or ends.

[0030] (Note that a "phase" as used herein refers to a continuous period of time during which only a single CC or CV charging operation is applied. Phases can have different time periods, but each phase consists of a single CV operation or a single CC operation. As used herein, a "CC phase" or "CC charging phase" refers to a time range that has one or more CC phases that are all at substantially the same current level, or at least they are controlled to be at substantially the same current level. The range may have one or more CC phases, but if it has more than one CC phase, the CC phases are separated by CV phases, which may or may not be at different voltage levels.)

[0031] refer to Figure 5A and Figure 5B , shows example charging curves that illustrate charging profiles that can be used for this routine. In these examples, two CC phases (CC1, CC2) are depicted. In each curve graph, the CC phase start voltage (Vcc2) is indicated for the second CC phase. Next, at 306, the routine identifies the highest qualified CC phase and starts CC charging at that level. Whether a CC phase is qualified at a given time will depend on the charging performance settings and dynamically changing conditions and parameters. In many cases, the first CC phase may be qualified and selected, although this is not absolute. In addition, once charging begins, subsequent CC phases can be skipped or even dynamically expanded or contracted. In any case, within the selected and executed CC phases, the routine interleaves at least one CV charging phase within the CC phase to essentially break up the CC phase and prevent excessive temperature rise.

[0032] When the CC phase has been completed, the routine proceeds to 308 and determines whether the battery charging has been completed. If so, the routine will end when the battery is charged. Otherwise, at 308, it proceeds to 310 to determine if there is another CC phase to be performed. If not, it means that there may be a problem and the routine ends. On the other hand, as previously described, if there is another CC phase to be performed, the routine proceeds to 312 and performs the next highest qualified CC level with interleaved CV phases.

[0033] In some embodiments, as shown in the flowchart, a qualified CC level with staggered CV phases (308, 312) can be performed according to routine actions 314-318. At 314, the routine checks whether the temperature has been sufficiently reduced or is being reduced. If so, it enters 318 and proceeds normally. Otherwise, it enters 316 and takes measures to slow down the temperature rise, ideally reducing the temperature itself. To this end, the routine takes remedial measures. For example, it can increase the CV frequency or width within the CC phase, or it can jump to the next CC phase or skip one or more CC phases to reduce the CC current level more quickly.

[0034] Figure 4 FIG. 2 is a diagram showing a method for charging a battery according to some embodiments. Figure 3 Flowchart of an exemplary implementation of a routine of . At 402, the routine determines whether the battery charge voltage (e.g., initial voltage) is below the battery under voltage (CUV), which would indicate that pre-charging is required before fast charging. If this is the case, the routine performs pre-charging at 404 and returns to 402.

[0035] From here, the routine proceeds to 406 to determine if the charging process has been completed by comparing Vb to the final target (Vdone). If charging has been completed, the routine proceeds to 408, where it switches to the charge maintenance mode and ends. If charging is not complete, the routine proceeds to 410, where it selects a CC charging phase CC(n) that is appropriate for the current charging voltage level (Vb). In particular, it looks for a CC phase CC(n) such that the starting voltage (Vcc) of the next CC phase CC(n+1) is greater than Vb, and the starting voltage of the candidate phase CC(n) is less than Vb. From here, the routine proceeds to 412 and executes the CC(n) phase to perform constant current charging at the CC(n) current level.

[0036] At 414, check if Vb=Vcc(n+1), i.e., check if Vb is at the starting voltage of the next CC phase. If not, go to 416 and check if the CC(n) timer has expired. This timer corresponds to the length of the CC phase before the CV phase should be inserted in the CC phase. If the timer has not expired, the routine returns to 412 and continues to execute the CC(n) charging phase. However, if the timer has expired at 416, proceed to 418 and set the CVx variable to Vb. Then proceed to 420 and perform the CV phase at a constant voltage CVx (here Vb). Then proceed to 422 and check if Ib is less than the charging level of the next CC phase CC(n+1). If not, continue in the CV phase. Once Ib is equal to or lower than the current level of CC(n+1), the routine returns to 406 and continues as discussed. It is worth noting that at 410, if the battery voltage (Vb) is still less than the starting voltage of the next CC phase CC(n+1), then remain in the CC(n) phase from the previous CC phase. This, along with the timer, is how the CV phases are interleaved within the CC phases in this example. If the CV level is equal to or higher than the start voltage of the next CC phase (Vcb), the routine will select the next CC phase that meets the voltage condition for Vb.

[0037] Returning to 414, if Vb is at or above Vcc(n+1), the routine will proceed to 426 and begin the CV phase at the voltage of Vcc(n+1), the starting voltage of the next CC phase. At 428, a check is made to see if the charging current (Ib) is less than the current level of the next CC phase. If not, then continue in the CV phase, but once below the CC(n+1) current level, the loop loops back to 406 and continues as discussed.

[0038] refer to Figure 6A-6C , it can be seen Figure 4 The routine fast charging method ( Figure 6B ) How to achieve good temperature mitigation with reasonable fast charging performance, especially compared to examples using existing methods ( Fig. 6A ) compared. These figures show the charging voltage and current, and the associated charging battery temperature. Since the charging current is intermittently reduced by the CV stage during the high CC current, and the final CV charge becomes shorter, the method disclosed herein can reduce the Joule heating of the battery, resulting in a reduction in the battery temperature rise, while the increase in the total charging time can be ignored. For example, in Figure 6B In the case of , the temperature rise is 7.1℃ and the charging time is 1.90 hours. Fig. 6A The existing two-stage charge in the example is 8.4°C and 1.82 hours. This difference in temperature rise can lead to significant differences in cycle life. Figure 6C is shown in the graph.

[0039] Figure 7 is a flow chart illustrating a routine for implementing another fast charging method according to some embodiments. In this routine, a feedback loop is used to control the temperature to alleviate excessive temperature rise. The routine begins at 702, where various battery charging parameters are read from the battery or from some other location. For example, the values ​​of the battery charging voltage (Vb), the battery charging current (Ib), the battery battery charging temperature (Tb), the maximum battery charging voltage (Vcmax), and the maximum battery charging current (Icmax) can be read. Next, at 704, the routine checks to confirm that Vcmax is not 0, which indicates that the battery is charged. Of course, there are and can also be used to check whether the battery is charged. If the battery is charged, the routine ends. Otherwise, proceed to 706 and set the charging voltage (Vb) to the maximum allowable charging voltage (Vcmax).

[0040] At 708, the routine calculates a target charging current (Ictgt), which should be fast enough for the desired charging speed, but slow enough to avoid excessive temperature rise. In some embodiments, the target current is calculated as the product of the charge rate (Crate) and the design capacity of the battery. For example, Crate can be a scaled charge rate factor, such as Crate=1, 1.2, 0.7, or 1.5. The design capacity is the design capacity of the battery, typically expressed in mAh, such as 5200mAh, 3000mAh, 4000mAh, etc.

[0041] At 710, the routine checks to see if the battery temperature (Tb) is above the starting temperature (Tstart). If not, the routine sets the charging current (Ib) to the target current (Itgt) at 712. On the other hand, if it is above the starting temperature, the routine proceeds to 714 and calculates the charging current value Ic(t) as a function of temperature. In the described embodiment, two temperature-dependent charging current function options are shown, one for an integer-based step method (716) and the other for a continuous method (718). Of course, any suitable function or method may be used to derive a temperature-dependent charging current value. With the options shown, the charging current starts near Itgt and decreases as the battery temperature increases, approaching Itgt / 2. It may be desirable to use a function that reduces the charging current at an appropriate rate as the temperature of the battery increases.

[0042] At 720, the routine checks whether the actual charging current (Ib) is greater than the maximum allowed charging current (Icmax). If so, it proceeds to 722 and sets Ic to Icmax. On the other hand, if the charging current is not higher than Icmax, it proceeds to 724 from 720 and sets Ib to the previously calculated temperature-based charging current Ic(t). Either way, it returns to the beginning and proceeds as described.

[0043] Note that in some embodiments, a timer may be incorporated into the overall routine loop so that the battery temperature may be monitored at a periodic rate (e.g., checked every 1 second), and once the battery temperature rises above a programmed start value (e.g., 30°C), the temperature difference from the programmed limit value (e.g., Tlim=36°C) may be used as feedback to proportionally reduce the charge current until the battery temperature and charge current reach equilibrium at the limit value. From here, the system regulates the battery temperature to the limit value. This forms a temperature control loop that maintains the highest charge current that can be provided without exceeding the temperature limit. In some embodiments, the battery charger circuit operates primarily in CC charging mode using the temperature control loop with voltage limits. The charging system control unit may be used to calculate and program the current limit value of the charger circuit, thereby forming an external control loop to regulate the battery temperature. In some embodiments, the temperature control loop will regulate until the rising battery charge reaches a level where the circuit becomes voltage limited, after which the current and temperature will decay until the battery reaches full charge. The control loop operates at periodic intervals that are sufficient to respond to temperature increases and decreases in the system. In addition to responding to Joule heating in the battery, the control loop can also respond to other platform temperature changes, including changes in ambient temperature and heat from other system components such as the CPU and graphics.

[0044] Figure 8 An example computing system with a battery with a charging system 825 is shown, which can be implemented using any of the techniques described herein. The multiprocessor system 800 is an interface system and includes multiple processors, including a first processor 870 and a second processor 880 coupled via an interface 850 such as a point-to-point (PP) interconnect, structure and / or bus. In some examples, the first processor 870 and the second processor 880 are isomorphic. In some examples, the first processor 870 and the second processor 880 are heterogeneous. Although the example system 800 is shown as having two processors, the system can have three or more processors, or can be a single processor system. In some examples, the computing system is implemented in whole or in part with a system on a chip (SoC) or a multi-chip (or multi-chiplet) module in the same or different packaging combinations.

[0045] Processors 870 and 880 are shown as including integrated memory control unit (IMC) circuits 872 and 882, respectively. Processor 870 also includes interface circuits 876 and 878 and a core set. Similarly, the second processor 880 includes interface circuits 886 and 888 and a core set. A core set generally refers to one or more computing cores that may or may not be grouped into different clusters, hierarchical groups, or common core type groups. The core can be configured differently to perform different functions and / or instructions with different performance and / or power levels. The processor may also include other blocks, such as memory and other processing unit engines.

[0046] Processors 870, 880 may exchange information via interface 850 using interface circuits 878, 888. IMCs 872 and 882 couple processors 870, 880 to respective memories, namely memory 832 and memory 834, which may be portions of main memory locally attached to the respective processors.

[0047] Processors 870, 880 may exchange information with a network interface (NW I / F) 890 via separate interfaces 852, 854 using interface circuits 876, 894, 886, 898, respectively. Network interface 890 (e.g., one or more of an interconnect, bus, and / or fabric, and in some examples a chipset) may optionally exchange information with a coprocessor 838 via interface circuit 892. In some examples, coprocessor 838 is a special-purpose processor, such as a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general-purpose graphics processing unit (GPGPU), a neural network processing unit (NPU), an embedded processor, etc.

[0048] A shared cache (not shown) may be included in processors 870, 880, or may be included outside the two processors but connected to the processors via an interface such as a PP interconnect, so that if the processors are in a low power mode, local cache information of one or both processors may be stored in the shared cache.

[0049] The network interface 890 may be coupled to the first interface 816 via an interface circuit 896. In some examples, the first interface 816 may be an interface such as a peripheral component interconnect (PCI) interconnect, a PCI Express interconnect, or another I / O interconnect. In some examples, the first interface 816 is coupled to a power control unit (PCU) 817, which may include circuits, software, and / or firmware for performing power management operations with respect to the processors 870, 880, and / or the coprocessor 838. The PCU 817 provides control information to one or more voltage regulators (not shown) so that the voltage regulators generate appropriate regulated voltages. The PCU 817 also provides control information to control the generated operating voltage. In various examples, the PCU 817 may include various power management logic units (circuits) for performing hardware-based power management. Such power management may be completely controlled by the processor (e.g., controlled by various processor hardware and may be triggered by workload and / or power, thermal, or other processor constraints) and / or may be performed in response to external sources (e.g., platform or power management sources or system software).

[0050] PCU 817 is illustrated as existing as logic separate from processor 870 and / or processor 880. In other cases, PCU 817 may be executed on a given core or cores (not shown) of processor 870 or 880. In some cases, PCU 817 may be implemented as a microcontroller unit (dedicated or general purpose) or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In other examples, the power management operations to be performed by PCU 817 may be implemented outside the processor, such as by a separate power management integrated circuit (PMIC) or another component external to the processor. In other examples, the power management operations to be performed by PCU 817 may be implemented within BIOS or other system software. Along these lines, power management may be performed in coordination with other power control units implemented autonomously or semi-autonomously, for example, as control units or executing software in cores, clusters, IP blocks, and / or other parts of the overall system.

[0051] Various I / O devices 814 may be coupled to the first interface 816 along with a bus bridge 818, which couples the first interface 816 to the second interface 820. In some examples, one or more additional processors 815, such as a coprocessor, a high-throughput multi-integrated core (MIC) processor, a GPGPU, an accelerator (e.g., a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor, are coupled to the first interface 816. In some examples, the second interface 820 may be a low pin count (LPC) interface. Various devices may be coupled to the second interface 820, including, for example, a keyboard and / or mouse 822, a communication device 827, and a storage circuit 828. The storage circuit 828 may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device, which may include instructions / codes and data 830, and may implement storage in some examples. In addition, an audio I / O 824 may be coupled to the second interface 820. Note that other architectures besides the point-to-point architecture described above are also possible. For example, instead of a point-to-point architecture, a system such as multiprocessor system 800 may implement a multi-point interface or other such architecture.

[0052] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose in-order cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; 3) dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a chip separate from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in this case, such a coprocessor is sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or a dedicated core); and 4) a system on a chip (SoC), which may be included on the same die as the CPU (sometimes referred to as an application core or application processor), the above-mentioned coprocessor, and additional functions. An example core architecture is described next, followed by a description of example processor and computer architectures.

[0053] Fig. 9A block diagram of an example processor and / or SoC 900 that may have one or more cores and an integrated memory control unit is shown. The solid line box shows a processor 900 having a single core 902(A), a system agent unit circuit 910, and a set of one or more interface control unit circuits 916, while the optional addition of the dashed line box shows an alternative processor 900 having multiple cores 902(A)-(N), a set of one or more integrated memory control unit circuits 914 in the system agent unit circuit 910, and dedicated logic 908, and a set of one or more interface control unit circuits 916. Note that the processor 900 may be Figure 8 one of the processors 870 or 880, or the coprocessors 838 or 815.

[0054] Thus, different implementations of processor 900 may include: 1) a CPU, where the specialized logic 908 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 902(A)-(N) are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of both); 2) a coprocessor, where cores 902(A)-(N) are a large number of specialized cores primarily used for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 902(A)-(N) are a large number of general purpose in-order cores. Thus, processor 900 may be a general purpose processor, a coprocessor, or a specialized processor, such as a network or communications processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput multi-integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 900 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0055] The memory hierarchy includes one or more levels of cache unit circuits 904(A)-(N) within the cores 902(A)-(N), a set of one or more shared cache unit circuits 906, and external memory (not shown) coupled to a set of integrated memory control unit circuits 914. The set of one or more shared cache unit circuits 906 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as last level cache (LLC), and / or combinations thereof. While in some examples, an interface network circuit 912 (e.g., a ring interconnect) interfaces with dedicated logic 908 (e.g., integrated graphics logic), the set of shared cache unit circuits 906, and system agent unit circuits 910, alternative examples use any number of well-known techniques to interface these units. In some examples, coherence is maintained between the one or more shared cache unit circuits 906 and the cores 902(A)-(N). In some examples, interface control unit circuit 916 couples core 902 to one or more other devices 918, such as one or more I / O devices, memory, one or more communication devices (e.g., a wireless network, a wired network, etc.), etc.

[0056] In some examples, one or more of the cores 902(A)-(N) are capable of multithreading. System agent unit circuitry 910 includes those components that coordinate and operate the cores 902(A)-(N). System agent unit circuitry 910 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be or may include logic and components required to regulate the power state of the cores 902(A)-(N) and / or the dedicated logic 908 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0057] The cores 902(A)-(N) may be homogeneous in terms of instruction set architecture (ISA). Alternatively, the cores 902(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores 902(A)-(N) may be able to execute an ISA, while other cores may only be able to execute a subset of that ISA or another ISA.

[0058] The following provides illustrative examples of the techniques disclosed herein. Embodiments of these techniques may include any one or more of the examples described below and any compatible combination of these examples.

[0059] A first example is a computer readable storage medium having instructions that, when executed, perform a method comprising causing a charger to apply two or more constant current (CC) charging phases to a battery and interleaving at least some of the two or more CC phases with at least one constant voltage (CV) charging phase.

[0060] Example 2 includes the subject matter of Example 1, and wherein the two or more CC charging phases occur in order of decreasing current levels.

[0061] Example 3 includes the subject matter of any of Examples 1-2, and wherein the method identifies starting voltage values ​​for two or more CC charging stages to define a set of CC charging stage options prior to applying the first CC charging stage.

[0062] Example 4 includes the subject matter of any of Examples 1-3, and wherein the method skips one or more of the defined CC charging phase options to more quickly reduce temperature rise in the battery.

[0063] Example 5 includes the subject matter of any of Examples 1-4, and wherein the method contracts one or more of the defined CC charging phase options to reduce temperature rise in the battery.

[0064] Example 6 includes the subject matter of any of Examples 1-25, and wherein the method increases the number of CV charging phases within the CC charging phase being performed to reduce the temperature in the battery.

[0065] Example 7 includes the subject matter of any of Examples 1-6, and wherein the method reads battery charging data from the battery prior to causing the charger to apply the two or more CC charging stages.

[0066] Example 8 includes the subject matter of any of Examples 1-7, and wherein the method is performed by a control unit in a computing platform.

[0067] Example 9 includes the subject matter of any of Examples 1-8, and wherein the control unit is part of the battery, or the control unit is implemented within a separate IC within the computing platform.

[0068] Example 10 is a computer readable storage medium having instructions that, when executed, perform a method comprising: causing a charger to charge a current into a battery; monitoring a battery temperature; and controlling the charge current until the temperature reaches a target limit that may be below a rated maximum operating battery temperature.

[0069] Example 11 includes the subject matter of Example 10, and wherein controlling includes reducing the charging current until the temperature reaches the target temperature limit.

[0070] Example 12 includes the subject matter of any of Examples 10-11, and wherein reducing the charging current comprises reducing the charging current based on a temperature difference between a current charging temperature and a temperature limit.

[0071] Example 13 includes the subject matter of any of Examples 10-12, and wherein the temperature difference is applied as feedback to proportionally reduce the charging current.

[0072] Example 14 includes the subject matter of any of Examples 10-13, and wherein the method comprises maintaining the battery temperature and the charging current in a balancing mode when the temperature reaches a limit.

[0073] Example 15 includes the subject matter of any of Examples 10-14, and wherein the method comprises charging current primarily in a CC charging mode using a temperature control loop with a voltage limit.

[0074] Example 16 includes the subject matter of any of Examples 10-15, and wherein the method reads the battery charging data from the battery before causing the charger to charge current into the battery.

[0075] Example 17 includes the subject matter of any of Examples 10-16, and wherein the method is performed by a control unit in a computing platform.

[0076] Example 18 includes the subject matter of any of Examples 10-17, and wherein the control unit is part of the battery, or the control unit is implemented within a separate IC within the computing platform.

[0077] Example 19 is a computing system. The system includes a platform processor, a control unit, and a charger. The control unit is coupled to the platform processor. The charger is used to charge a battery that will provide power to the computing system, and the control unit is used to: control the charger to apply two or more constant current (CC) charging phases to the battery, and interleave at least some of the two or more CC phases with at least one constant voltage (CV) charging phase.

[0078] Example 20 includes the subject matter of Example 19, and wherein the two or more CC charging phases occur in decreasing order of current level.

[0079] Example 21 includes the subject matter of any of Examples 19-20, and wherein the control unit is to identify starting voltage values ​​for two or more CC charging stages to define a set of CC charging stage options before the charger applies the first CC charging stage.

[0080] Example 22 includes the subject matter of any of Examples 19-21, and wherein the control unit skips one or more of the defined CC charging phase options to more quickly reduce a temperature rise in the battery.

[0081] Example 23 includes the subject matter of any of Examples 19-20, and wherein the control unit contracts one or more of the defined CC charging phase options to reduce a temperature rise in the battery.

[0082] Example 24 includes the subject matter of any of Examples 19-23, and wherein the control unit increases the number of CV charging phases within the CC charging phase being performed to reduce a temperature in the battery.

[0083] Example 25 includes the subject matter of any of Examples 19-24, and wherein the control unit reads the battery charging data from the battery before causing the charger to apply the two or more CC charging stages.

[0084] Example 26 is a computing system. The system includes a platform processor, a control unit, and a charger. The control unit is coupled to the platform processor. The charger is used to charge a battery that will provide power to the computing system, and the control unit is used to: cause the charger to charge current into the battery, monitor the battery temperature, and control the charging current until the temperature reaches a target limit.

[0085] Example 27 includes the subject matter of Example 26, and wherein the target temperature limit is below a rated maximum operating battery temperature.

[0086] Example 28 includes the subject matter of any of Examples 26-27, and wherein the control unit is to reduce the charging current until the temperature reaches the target temperature limit.

[0087] Example 29 includes the subject matter of any of Examples 26-28, and wherein the control unit is to reduce the charging current based on a temperature difference between a current charging temperature and the temperature limit.

[0088] Example 30 includes the subject matter of any of Examples 26-29, and wherein the temperature difference is applied as feedback to proportionally reduce the charging current.

[0089] Example 31 includes the subject matter of any of Examples 26-30, and wherein the control unit is to maintain the battery temperature and the charging current in a balancing mode when the temperature reaches a limit.

[0090] Example 32 includes the subject matter of any of Examples 26-31, and wherein the control unit is to charge current primarily in CC charging mode using a temperature control loop with voltage limits.

[0091] Example 33 includes the subject matter of any of Examples 26-32, and wherein the control unit is to read the battery charging data from the battery before causing the charger to charge current into the battery.

[0092] Example 34 includes the subject matter of any of Examples 26-33, and wherein the control unit is part of the battery or the control unit is implemented within a separate IC within the computing platform.

[0093] Example 35 includes the subject matter of any of Examples 26-34, and wherein the computing platform is part of an electric vehicle.

[0094] Example 36 includes the subject matter of any of Examples 26-35, and wherein the control unit and the charger are part of a USB charging device.

[0095] Example 37 is a computer-readable storage medium having instructions that, when executed, perform a method comprising causing a charger to apply a first constant current (CC) charging phase to a battery and interleaving the first CC phase with at least one constant voltage (CV) charging phase.

[0096] Example 38 includes the subject matter of Example 37, and wherein the method comprises: causing the charger to apply a second constant current (CC) charging phase, the first CC phase and the second CC phase being at different current levels from each other; and interleaving the second CC phase with at least one constant voltage (CV) charging phase.

[0097] Example 39 includes the subject matter of any of Examples 37-38, and wherein the first CC charging phase and the second CC charging phase occur in decreasing order of current levels.

[0098] Example 40 includes the subject matter of any of Examples 37-39, and wherein the method, before applying either of the first CC charging stage and the second CC charging stage, identifies starting voltage values ​​for the first CC charging stage and the second CC charging stage to define a set of three or more CC charging stage options, the set including the first CC charging stage and the second CC charging stage.

[0099] Example 41 includes the subject matter of any of Examples 37-40, and wherein the method skips one or more of the defined CC charging phase options to more quickly reduce temperature rise in the battery.

[0100] Example 42 includes the subject matter of any of Examples 37-41, and wherein the method contracts one or more of the defined CC charging phase options to reduce temperature rise in the battery.

[0101] Example 43 includes the subject matter of any of Examples 37-42, and wherein the method increases the number of CV charging phases within the CC charging phase being performed to reduce the temperature in the battery.

[0102] Example 44 includes the subject matter of any of Examples 37-43, and wherein the method reads battery charging data from the battery prior to causing the charger to apply the first CC charging stage and the second CC charging stage.

[0103] Example 45 includes the subject matter of any of Examples 37-44, and wherein the method is performed by a control unit in the computing platform.

[0104] Example 46 includes the subject matter of any of Examples 37-45, and wherein the control unit is part of the battery, or the control unit is implemented within a separate IC within the computing platform.

[0105] Example 47 is a computing system, comprising a platform processor, a control unit, and a charger. The control unit is coupled to the platform processor. The charger is used to charge a battery that will provide power to the computing system, wherein the control unit is used to control the charger so that the charger applies a first constant current (CC) charging phase to the battery. The control unit is also used to interleave the first CC phase with at least one constant voltage (CV) charging phase.

[0106] Example 48 includes the subject matter of Example 47, and wherein the control unit is used to cause the charger to apply a second constant current (CC) charging phase, the first CC phase and the second CC phase are at different current levels from each other, and the control unit is used to interleave the second CC phase with at least one constant voltage (CV) charging phase.

[0107] Example 49 includes the subject matter of any of Examples 47-48, and wherein the first CC charging phase and the second CC charging phase occur in decreasing order of current level.

[0108] Example 50 includes the subject matter of any of Examples 47-49, and wherein the control unit is to identify starting voltage values ​​of the first CC charging stage and the second CC charging stage before applying any of the first CC charging stage and the second CC charging stage to define a set of three or more CC charging stage options, the set including the first CC charging stage and the second CC charging stage. The control unit skips one or more of the defined CC charging stage options to more quickly reduce a temperature rise in the battery.

[0109] Example 51 includes the subject matter of any of Examples 47-50, and wherein the control unit contracts one or more of the defined CC charging phase options to reduce temperature rise in the battery.

[0110] Example 52 includes the subject matter of any of Examples 47-51, and wherein the control unit increases the number of CV charging phases within the CC charging phase being performed to reduce a temperature in the battery.

[0111] Example 53 includes the subject matter of any of Examples 47-52, and wherein the control unit is to read the battery charging data from the battery before causing the charger to apply the two or more CC charging stages.

[0112] References in the specification to "an embodiment", "one embodiment", "some embodiments" or "other embodiments" mean that a particular feature, structure or characteristic described in connection with the embodiment is included in at least some embodiments, but not necessarily in all embodiments. Various appearances of "an embodiment", "one embodiment" or "some embodiments" do not necessarily refer to the same embodiment. If the specification provides that a component, feature, structure or characteristic "may", "might" or "could" be included, that particular component, feature, structure or characteristic need not be included. If the specification or claims refer to "a" or "an" element, it does not mean that there is only one of the elements. If the specification or claims refer to "additional" elements, it does not exclude the presence of more than one additional element.

[0113] Throughout the specification and claims, the term "connected" refers to a direct connection, such as an electrical, mechanical or magnetic connection, between the things that are connected without any intervening devices.

[0114] The term "coupled" refers to a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between the connected objects, or an indirect connection through one or more passive or active intermediary devices.

[0115] The term "circuit" or "module" may refer to one or more passive and / or active components that are arranged to cooperate with each other to provide a desired function. Different circuits or modules may share or even consist of common components. For example, a control circuit may be a circuit that performs a first function, while the same control unit circuit may also be a circuit that performs another function that may or may not be related to the first function.

[0116] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on".

[0117] The terms "substantially," "close," "approximately," "near," and "about" generally mean within + / - 10% of a target value.

[0118] Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third," etc., to describe common objects simply indicates that reference is made to different instances of similar objects and does not imply that the objects described are necessarily in a given sequence, whether in time, space, ranking, or in any other manner.

[0119] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0120] It should be noted that those elements in the figures having the same reference numbers (or names) as elements in any other figures may operate or function in any manner similar to that described, but are not limited thereto.

[0121] In addition, specific features, structures, functions or characteristics can be combined in any suitable manner in one or more embodiments. For example, the first embodiment can be combined with the second embodiment at any place where the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0122] Furthermore, for ease of illustration and discussion, and in order not to obscure the present disclosure, well-known power / ground connections of integrated circuit (IC) chips and other components may or may not be shown in the illustrated figures. Furthermore, the arrangements may be shown in block diagram form in order to avoid obscuring the present disclosure, and also in view of the fact that implementation details regarding implementation of such block diagram arrangements depend on the platform in which the present disclosure will be implemented.

[0123] As defined herein, the term "computer-readable storage medium" refers to a storage medium containing or storing program code used by or in conjunction with an instruction execution system, device or apparatus. As defined herein, a "computer-readable storage medium" is not itself a transient, propagating signal. A computer-readable storage medium may be, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. As described herein, a memory element is an example of a computer-readable storage medium. A non-exhaustive list of more specific examples of computer-readable storage media may include: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove with instructions recorded thereon, and any suitable combination of the foregoing.

[0124] As defined herein, the term "output" means stored in a physical storage element such as a device, written to a display or other peripheral output device, sent or transmitted to another system, exported, and the like.

[0125] As defined herein, the term "if" means "when" or "uponce" or "in response to" or "response," depending on the context. Thus, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted, depending on the context, to mean "uponce it is determined" or "in response to determining" or "uponce [described condition / event] is detected" or "in response to detecting [described condition / event]." As defined herein, the term "response" means to react to or be susceptible to reacting to an action or event. Thus, if a second action is performed "in response to" a first action, there is a causal relationship between the occurrence of the first action and the occurrence of the second action. The term "response" indicates a causal relationship.

[0126] As defined herein, the terms "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment described in the present disclosure. Thus, appearances of the phrases "in one embodiment," "in an embodiment," and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment.

[0127] As defined herein, the term "processor" refers to at least one hardware circuit configured to execute instructions contained in a program code. The hardware circuit may be an integrated circuit. Examples of processors include, but are not limited to, a central processing unit (CPU), an array processor, a vector processor, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific integrated circuit (ASIC), a programmable logic circuit, a graphics processing unit (GPU), a control unit, etc.

[0128] The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions for making a processor perform various aspects of the invention arrangement described herein. In the present disclosure, the term "program code" may be used interchangeably with the term "computer-readable program instructions". The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, LAN, WAN and / or wireless network). The network may include a copper transmission cable, an optical transmission fiber, wireless transmission, a router, a firewall, a switch, a gateway computer and / or an edge device including an edge server. The network adapter card or network interface in each computing / processing device receives a computer-readable program instruction from the network, and forwards the computer-readable program instruction to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0129] The computer-readable program instructions for performing the operation of the inventive arrangement described herein can be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​and / or process programming languages). The computer-readable program instructions can include state setting data. The computer-readable program instructions can be executed completely on the user's computer, partly on the user's computer, as an independent software package, partly on the user's computer and partly on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including LAN or WAN), or can be connected to an external computer (for example, by using the Internet of an Internet service provider). In some cases, the electronic circuit including, for example, a programmable logic circuit, FPGA or PLA can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions, to personalize the electronic circuit, thereby executing the various aspects of the inventive arrangement described herein.

[0130] This article describes certain aspects of the present invention arrangement with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products. It should be understood that each block of the flowchart illustration and / or block diagram and the combination of blocks in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions (e.g., program code).

[0131] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, whereby instructions executed by a processor of a computer or other programmable data processing device create a device for implementing the functions / actions specified in the flowchart and / or block diagram block or multiple blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium, which may direct a computer, a programmable data processing device, and / or other equipment to operate in a particular manner, such that a computer-readable storage medium having instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the operations specified in the flowchart and / or block diagram block or multiple blocks.

[0132] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to perform a series of operations on the computer, other programmable apparatus, or other device, thereby producing a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in the flowchart and / or block diagram block or multiple blocks.

[0133] The flow chart and block diagram in the figure illustrate the possible implementation architecture, function and operation of the system, method and computer program product of various aspects arranged according to the present invention.In this regard, each block in the flow chart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for implementing a specified operation.

[0134] In some alternative implementations, the operations noted in the blocks may not occur in the order noted in the figure. For example, two blocks shown in succession may be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functions involved. In other examples, the blocks may generally be executed in increasing numerical order, while in other examples, one or more blocks may be executed in a varying order, with the results stored and used in subsequent or other blocks that do not immediately follow. It will also be noted that each block of the block diagram and / or flowchart illustration and the combination of blocks in the block diagram and / or flowchart illustration may be implemented by a dedicated hardware-based system that performs a specified function or action or a combination of dedicated hardware and computer instructions.

[0135] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements found in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

Claims

1. A computer-readable storage medium having instructions, which when executed perform a method, the method comprising: causing the charger to apply a first constant current (CC) charging phase to the battery; as well as The first CC phase is interleaved with at least one constant voltage (CV) charging phase.

2. The storage medium according to claim 1, wherein: The method includes causing the charger to apply a second constant current (CC) charging phase, the first CC phase and the second CC phase being at different current levels from each other, and interleaving the second CC phase with at least one constant voltage (CV) charging phase.

3. The storage medium according to claim 2, wherein: The first CC charging phase and the second CC charging phase occur in a descending order of current levels.

4. The storage medium according to claim 2, wherein: The method identifies starting voltage values ​​for the first CC charging stage and the second CC charging stage before applying either of the first CC charging stage and the second CC charging stage to define a set of three or more CC charging stage options, the set including the first CC charging stage and the second CC charging stage.

5. The storage medium according to claim 4, wherein: The method skips one or more of the defined CC charging phase options to more quickly reduce temperature rise in the battery.

6. The storage medium according to claim 4, wherein: The method contracts one or more of the defined CC charging phase options to reduce temperature rise in the battery.

7. The storage medium according to any one of claims 4 to 6, wherein: The method increases the number of CV charging phases within an ongoing CC charging phase to reduce the temperature in the battery.

8. The storage medium according to any one of claims 1 to 6, wherein: The method reads battery charging data from the battery before causing the charger to apply the first CC charging stage and the second CC charging stage.

9. The storage medium according to any one of claims 1 to 6, wherein: The method is executed by a control unit in a computing platform.

10. The storage medium according to claim 9, wherein: The control unit is part of the battery, or the control unit is implemented in a separate IC within the computing platform.

11. A computer-readable storage medium having instructions, which when executed perform a method, the method comprising: Allow the charger to charge current into the battery; Monitor battery temperature; as well as The charging current is controlled until the temperature reaches a target limit that is below the rated maximum operating battery temperature.

12. The storage medium according to claim 11, wherein: Controlling includes reducing the charging current until the temperature reaches the target limit.

13. The storage medium according to claim 12, wherein: Reducing the charging current includes reducing the charging current based on a temperature difference between a current charging temperature and the target limit.

14. The storage medium according to claim 13, wherein: The temperature difference is applied as feedback to proportionally reduce the charging current.

15. The storage medium according to any one of claims 11 to 14, wherein: The method includes maintaining the battery temperature and charging current in a balancing mode when the temperature reaches the target limit.

16. The storage medium according to any one of claims 11 to 14, wherein: The method includes charging current primarily in CC charging mode using a temperature control loop in the presence of a voltage limit.

17. A computing system comprising: Platform processor; a control unit, coupled to the platform processor; as well as A charger for charging a battery that will provide power to the computing system, wherein the control unit is used to control the charger so that the charger applies a first constant current (CC) charging phase to the battery, and the control unit is used to interleave the first CC phase with at least one constant voltage (CV) charging phase.

18. The system of claim 17, wherein: The control unit is configured to cause the charger to apply a second constant current (CC) charging phase, the first CC phase and the second CC phase being at different current levels from each other, and the control unit is configured to interleave the second CC phase with at least one constant voltage (CV) charging phase.

19. The system of claim 18, wherein: The first CC charging phase and the second CC charging phase occur in a descending order of current levels.

20. The system of claim 18, wherein: The control unit is configured to identify starting voltage values ​​of the first CC charging stage and the second CC charging stage before applying either of the first CC charging stage and the second CC charging stage to define a set of three or more CC charging stage options, the set including the first CC charging stage and the second CC charging stage.

21. The system of claim 20, wherein: The control unit skips one or more of the defined CC charging phase options to more quickly reduce the temperature rise in the battery.

22. A system according to any one of claims 19 to 21, wherein: The control unit contracts one or more of the defined CC charging phase options to reduce temperature rise in the battery.

23. A system according to any one of claims 19 to 21, wherein: The control unit increases the number of CV charging phases within the CC charging phase being performed to reduce the temperature in the battery.

24. A system according to any one of claims 17 to 23, wherein: The control unit is configured to read battery charging data from the battery before causing the charger to apply two or more CC charging stages.

25. A computing system comprising: Platform processor; a control unit, coupled to the platform processor; as well as A charger for charging a battery that will provide power to the computing system, wherein the control unit is used to: cause the charger to charge current into the battery; monitor the battery temperature; And controlling the charging current until the temperature reaches the target limit.

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