Display panel and display device

Abstract

The application discloses a display panel and a display device; the display panel comprises an anode layer, a first light-emitting functional layer, an N-type charge generation layer, a light-emitting composite layer and a cathode layer; the first light-emitting functional layer is arranged on one side of the anode layer; the N-type charge generation layer is arranged on a side of the first light-emitting functional layer away from the anode layer; the light-emitting composite layer is arranged on a side of the N-type charge generation layer away from the first light-emitting functional layer; the cathode layer is arranged on a side of the light-emitting composite layer away from the N-type charge generation layer; the light-emitting composite layer comprises a plurality of functional layers arranged in a stack; the orthographic projection of the N-type charge generation layer on the cathode layer does not exceed the coverage range of the orthographic projection of at least one functional layer in the light-emitting composite layer on the cathode layer; the application can reduce the probability of short circuit between the N-type charge generation layer and the cathode layer, reduce the probability of short circuit of the light-emitting composite layer between the cathode layer and the N-type charge generation layer, and improve the display uniformity and stability of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) display panel has the characteristics of low power consumption, fast response speed, wide viewing angle, etc., and has a wide application prospect.

[0003] At present, in order to improve the efficiency and service life of the organic light emitting diode display panel, a plurality of light emitting layers are stacked together through a charge generation layer. Compared with a display panel having a single-layer light emitting device, the light emitting efficiency and service life can be greatly improved.

[0004] However, the charge generation layer includes a stacked N-type charge generation layer and a P-type charge generation layer, and the N-type charge generation layer is formed by doping an N-type doping material in an electron transport material. When the cathode layer in the organic light emitting diode display panel contacts the doped part in the N-type charge generation layer, the cathode layer and the doped part in the N-type charge generation layer are easily short-circuited, thereby causing the light emitting unit between the cathode layer and the N-type charge generation layer to be short-circuited, and affecting the display effect of the display panel. SUMMARY

[0005] The embodiments of the present application provide a display panel and a display device, which can reduce the probability of short circuit between the N-type charge generation layer and the cathode layer, and improve the stability and display effect of the display panel.

[0006] The embodiments of the present application provide a display panel, which comprises:

[0007] an anode layer;

[0008] a first light emitting functional layer disposed on one side of the anode layer;

[0009] an N-type charge generation layer disposed on a side of the first light emitting functional layer away from the anode layer;

[0010] a light emitting composite layer disposed on a side of the N-type charge generation layer away from the first light emitting functional layer;

[0011] a cathode layer disposed on a side of the light emitting composite layer away from the N-type charge generation layer;

[0012] The light emitting composite layer comprises a plurality of functional layers stacked together, and the orthographic projection of the N-type charge generation layer on the cathode layer does not exceed the coverage range of the orthographic projection of at least one functional layer in the light emitting composite layer on the cathode layer.

[0013] In an embodiment of the present application, the N-type charge generation layer is distributed with a doped material and an intrinsic material, and the distribution area of the doped material in the N-type charge generation layer is the same as the distribution area of the intrinsic material in the N-type charge generation layer.

[0014] In an embodiment of the present application, the edge of the N-type charge generation layer is inwardly recessed relative to the edge of at least one of the functional layers in the light emitting recombination layer towards the side close to the center of the N-type charge generation layer.

[0015] In an embodiment of the present application, the distance by which the edge of the N-type charge generation layer is inwardly recessed relative to the edge of at least one of the functional layers in the light emitting recombination layer towards the side close to the center of the N-type charge generation layer is greater than or equal to 30 microns.

[0016] In an embodiment of the present application, at least one of the functional layers in the light emitting recombination layer covers the upper surface of the N-type charge generation layer away from the first light emitting functional layer and the plurality of side surfaces of the N-type charge generation layer connected to the upper surface.

[0017] In an embodiment of the present application, the plurality of functional layers comprises a P-type charge generation layer disposed between the N-type charge generation layer and the cathode layer and a second light emitting functional layer disposed between the P-type charge generation layer and the cathode layer.

[0018] The orthographic projection of the N-type charge generation layer on the cathode layer does not exceed the coverage range of the orthographic projection of the P-type charge generation layer on the cathode layer, and / or the orthographic projection of the N-type charge generation layer on the cathode layer does not exceed the coverage range of the orthographic projection of the second light emitting functional layer on the cathode layer.

[0019] In an embodiment of the present application, the first light emitting functional layer comprises a first light emitting layer and a first light emitting auxiliary layer disposed in layers, and the first light emitting auxiliary layer comprises at least one of a first electron injection layer, a first electron transport layer, a first hole injection layer and a first hole transport layer.

[0020] The second light emitting functional layer comprises a second light emitting layer and a second light emitting auxiliary layer disposed in layers, and the second light emitting auxiliary layer comprises at least one of a second electron injection layer, a second electron transport layer, a second hole injection layer and a second hole transport layer.

[0021] The orthographic projection of the N-type charge generation layer on the cathode layer does not exceed the coverage range of the orthographic projection of the P-type charge generation layer on the cathode layer, and / or the orthographic projection of the N-type charge generation layer on the cathode layer does not exceed the coverage range of the orthographic projection of the second light emitting auxiliary layer on the cathode layer.

[0022] In one embodiment of this application, at least one of the functional layers in the light-emitting composite layer is disposed between the N-type charge generation layer and the cathode layer.

[0023] In one embodiment of this application, the display panel includes a display area and a non-display area adjacent to the display area. The non-display area includes a bonding area located on one side of the display area. The display panel includes a substrate and a VDD signal terminal disposed on the substrate and located between the bonding area and the display area. The anode layer is electrically connected to the VDD signal terminal.

[0024] The orthographic projection of the N-type charge generation layer on the substrate and the orthographic projection of the VDD signal terminal on the substrate are spaced apart.

[0025] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display device, the display device including the display panel.

[0026] The beneficial effects of this application are as follows: By setting the orthogonal projection of the N-type charge generation layer on the cathode layer to not exceed the coverage area of ​​the orthogonal projection of at least one functional layer in the light-emitting composite layer on the cathode layer, this application can reduce the probability of short circuit between the N-type charge generation layer and the cathode layer, reduce the probability of short circuit of the light-emitting composite layer located between the cathode layer and the N-type charge generation layer, improve the display uniformity and stability of the display panel, and improve the display effect of the display panel. Attached Figure Description

[0027] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0028] Figure 1 A schematic diagram of the structure of a display panel provided in one embodiment;

[0029] Figure 2 This is a schematic diagram of a first structure of a display panel provided in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of a second structure of the display panel provided in an embodiment of this application;

[0031] Figure 4 This is a schematic diagram of a third structure of the display panel provided in an embodiment of this application;

[0032] Figure 5 A schematic diagram of the coverage area of ​​a light-emitting composite layer in a display panel provided in an embodiment of this application;

[0033] Figure 6A schematic diagram showing the coverage area of ​​another light-emitting composite layer in a display panel provided in an embodiment of this application;

[0034] Figure 7 This is a schematic diagram of a planar distribution structure of a display panel provided in an embodiment of this application;

[0035] Figure 8 A flowchart illustrating the manufacturing method of the display panel provided in this application embodiment. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0037] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0038] Please refer to Figure 1 A tandem display panel typically includes an anode 1, a first light-emitting unit 2 disposed on the anode 1, an N-type charge-generating layer 3 disposed on the first light-emitting unit 2, a second light-emitting unit 4 disposed on the N-type charge-generating layer 3, and a cathode layer 5 disposed on the second light-emitting unit 4. When the N-type charge-generating layer 3 comes into contact with the cathode layer 5, especially when the doped portion of the N-type charge-generating layer 3 comes into contact, it can easily cause a short circuit between the cathode layer 5 and the doped portion of the N-type charge-generating layer 3. This short-circuits the light-emitting unit located between the cathode layer 5 and the N-type charge-generating layer 3, resulting in a short circuit of the second light-emitting unit 4. This directly reduces the start-up voltage by approximately 50%, severely affecting the stability and display uniformity of the display panel. For example, light leakage at the L0 grayscale level is likely to occur, thus affecting the display effect of the display panel.

[0039] Please refer to Figure 2This application provides a display panel, which includes an anode layer 10, a first light-emitting functional layer 20, an N-type charge generation layer 30, a light-emitting composite layer 60, and a cathode layer 50.

[0040] The first light-emitting functional layer 20 is disposed on one side of the anode layer 10; the N-type charge generating layer 30 is disposed on the side of the first light-emitting functional layer 20 away from the anode layer 10; the light-emitting composite layer 60 is disposed on the side of the N-type charge generating layer 30 away from the first light-emitting functional layer 20; and the cathode layer 50 is disposed on the side of the light-emitting composite layer 60 away from the N-type charge generating layer 30.

[0041] Furthermore, the light-emitting composite layer 60 includes multiple functional layers stacked together, and the orthographic projection of the N-type charge generating layer 30 onto the cathode layer 50 does not exceed the coverage area of ​​the orthographic projection of at least one of the functional layers in the light-emitting composite layer 60 onto the cathode layer 50.

[0042] In the implementation process, this embodiment of the application sets the orthographic projection of the N-type charge generation layer 30 onto the cathode layer 50 to not exceed the coverage area of ​​the orthographic projection of at least one functional layer in the light-emitting composite layer 60 onto the cathode layer 50; thereby reducing the probability of short circuit between the N-type charge generation layer 30 and the cathode layer 50, reducing the probability of the light-emitting composite layer 60 located between the cathode layer 50 and the N-type charge generation layer 30 being short-circuited, improving the display uniformity and stability of the display panel, and improving the display effect of the display panel.

[0043] Specifically, please combine Figure 2 , Figure 3 as well as Figure 4 In some embodiments, the display panel may include a substrate, a thin-film transistor array layer disposed on the substrate, a light-emitting device layer disposed on the side of the thin-film transistor array layer away from the substrate, and an encapsulation layer disposed on the side of the light-emitting device layer away from the thin-film transistor array layer.

[0044] It should be noted that the light-emitting device layer includes an anode layer 10, a first light-emitting functional layer 20, an N-type charge generation layer 30, a light-emitting composite layer 60, and a cathode layer 50 as described in the above embodiments. The anode layer 10 includes multiple anodes, and each anode can be connected to a thin-film transistor in the thin-film transistor array layer. Furthermore, the encapsulation layer can cover the side of the cathode layer 50 away from the light-emitting composite layer 60.

[0045] In some embodiments, the first light-emitting functional layer 20 includes a first light-emitting layer 21 and a first light-emitting auxiliary layer stacked together, wherein the first light-emitting auxiliary layer may include at least one of a first hole layer 22 and a first electron layer 23.

[0046] The light-emitting composite layer 60 includes multiple functional layers stacked together, and the multiple functional layers may include a P-type charge generation layer 61 located between the N-type charge generation layer 30 and the cathode layer 50, and a second light-emitting functional layer 40 located between the P-type charge generation layer 61 and the cathode layer 50.

[0047] The second light-emitting functional layer 40 includes a second light-emitting layer 41 and a second light-emitting auxiliary layer stacked together. The second light-emitting auxiliary layer may include at least one of a second hole layer 42 and a second electron layer 43.

[0048] In some embodiments, please combine Figure 3 as well as Figure 4 The first hole layer 22 may include a first hole injection layer 221 and a first hole transport layer 222, and the first electron layer 23 may include a first electron injection layer 231 and a first electron transport layer 232; the second hole layer 42 may include a second hole injection layer 421 and a second hole transport layer 422, and the second electron layer 43 may include a second electron injection layer 431 and a second electron transport layer 432.

[0049] Continuing from the above, the first light-emitting auxiliary layer may include at least one of the first hole injection layer 221, the first hole transport layer 222, the first electron injection layer 231, and the first electron transport layer 232; the second light-emitting auxiliary layer may include at least one of the second hole injection layer 421, the second hole transport layer 422, the second electron injection layer 431, and the second electron transport layer 432.

[0050] In some embodiments, please refer to Figure 4 The first light-emitting functional layer 20 includes a first hole injection layer 221, a first hole transport layer 222, a first light-emitting layer 21, a first electron injection layer 231, and a first electron transport layer 232, which are sequentially stacked on the anode layer 10; the second light-emitting functional layer 40 includes a second hole injection layer 421, a second hole transport layer 422, a second light-emitting layer 41, a second electron injection layer 431, and a second electron transport layer 432, which are sequentially stacked on the P-type charge generation layer 61.

[0051] In some embodiments, the P-type charge generation layer 61 is located between the N-type charge generation layer 30 and the second hole injection layer 421; the material of the P-type charge generation layer 61 includes a hole transport material and a P-type doped material distributed in the hole transport material.

[0052] In some embodiments, the N-type charge generation layer 30 contains intrinsic materials and doped materials; further, the intrinsic materials include electron transport materials, and the doped materials include metallic materials, such as at least one of Yb and Li. It should be noted that, since the doped material is a metallic material and metallic materials are conductive, when the N-type charge generation layer 30 comes into contact with the cathode layer 50, it can easily cause a short circuit between the cathode layer 50 and the N-type charge generation layer 30, thereby short-circuiting the second light-emitting functional layer 40. This results in a direct reduction of the turn-on voltage by approximately 50%, severely affecting the stability and uniformity of the display panel, and consequently affecting the display effect of the display panel.

[0053] In some embodiments, the distribution area of ​​the doped material in the N-type charge generation layer 30 is the same as the distribution area of ​​the intrinsic material in the N-type charge generation layer 30, that is, the N-type charge generation layer 30 is formed by integral doping. Specifically, in the process, the same mask or a mask with the same evaporation opening area can be used to deposit the intrinsic material and the doped material, so that the evaporation area of ​​the intrinsic material and the doped material is the same and the evaporation area overlaps.

[0054] Continuing from the above, in this embodiment, the orthographic projection of the N-type charge generation layer 30 onto the cathode layer 50 does not exceed the coverage area of ​​the orthographic projection of at least one functional layer in the light-emitting composite layer 60 onto the cathode layer 50. That is, this embodiment defines the boundaries of the N-type charge generation layer 30 and the light-emitting composite layer 60 so that the boundary of the N-type charge generation layer 30 does not exceed the boundary of the light-emitting composite layer 60. This effectively reduces the probability of a short circuit between the N-type charge generation layer 30 and the cathode layer 50, reduces the probability of the second light-emitting functional layer 40 being short-circuited, improves the display uniformity of the display panel, improves the L0 grayscale light leakage phenomenon, and improves the display effect and stability of the display panel.

[0055] It should be noted that, since the light-emitting composite layer 60 includes multiple functional layers, the boundary of the N-type charge generation layer 30 does not exceed the boundary of at least one functional layer in the light-emitting composite layer 60. This can effectively block the N-type charge generation layer 30 from the cathode layer 50, thereby reducing the probability of a short circuit between the N-type charge generation layer 30 and the cathode layer 50, reducing the probability of the second light-emitting functional layer 40 being short-circuited, improving the display uniformity of the display panel, improving the L0 grayscale light leakage phenomenon, and improving the display effect and stability of the display panel.

[0056] In some embodiments, the orthogonal projection of the N-type charge generation layer 30 onto the cathode layer 50 does not exceed the coverage area of ​​the orthogonal projection of the P-type charge generation layer 61 onto the cathode layer 50, and / or the orthogonal projection of the N-type charge generation layer 30 onto the cathode layer 50 does not exceed the coverage area of ​​the orthogonal projection of the second light-emitting functional layer 40 onto the cathode layer 50.

[0057] In some embodiments, the orthogonal projection of the N-type charge generation layer 30 onto the cathode layer 50 does not exceed the coverage area of ​​the orthogonal projection of the P-type charge generation layer 61 onto the cathode layer 50, and / or the orthogonal projection of the N-type charge generation layer 30 onto the cathode layer 50 does not exceed the coverage area of ​​the orthogonal projection of the second light-emitting auxiliary layer onto the cathode layer 50.

[0058] In some embodiments, when the second light-emitting auxiliary layer includes the second hole injection layer 421, the second hole transport layer 422, the second electron injection layer 431, and the second electron transport layer 432, the orthogonal projection of the N-type charge generation layer 30 onto the cathode layer 50 does not exceed the coverage of at least one of the orthogonal projections of the P-type charge generation layer 61 onto the cathode layer 50, the second hole injection layer 421 onto the cathode layer 50, the second hole transport layer 422 onto the cathode layer 50, the second electron injection layer 431 onto the cathode layer 50, and the second electron transport layer 432 onto the cathode layer 50.

[0059] Further, please refer to Figure 5 In some embodiments, the edge of the N-type charge generation layer 30 is recessed toward the center of the N-type charge generation layer 30 relative to the edge of at least one of the functional layers in the light-emitting composite layer 60; this can further reduce the probability of contact between the side surface of the N-type charge generation layer 30 and the cathode layer 50.

[0060] It is understood that the edge of the N-type charge generation layer 30 may be recessed towards the center of the N-type charge generation layer 30 relative to the edge of at least one functional layer in the light-emitting composite layer 60, which can reduce the probability of contact between the side surface of the N-type charge generation layer 30 and the cathode layer 50.

[0061] In some embodiments, the edge of the N-type charge generation layer 30 may be recessed toward the center of the N-type charge generation layer 30 relative to at least one of the P-type charge generation layer 61 and the second light-emitting auxiliary layer in the cathode layer 50.

[0062] In some embodiments, when the second light-emitting auxiliary layer includes the second hole injection layer 421, the second hole transport layer 422, the second electron injection layer 431, and the second electron transport layer 432, the edge of the N-type charge generation layer 30 may be recessed toward the center of the N-type charge generation layer 30 relative to at least one of the P-type charge generation layer 61, the second hole injection layer 421, the second hole transport layer 422, the second electron injection layer 431, and the second electron transport layer 432.

[0063] Furthermore, in some embodiments, the edge of the N-type charge generation layer 30 is recessed by a distance L relative to the edge of at least one of the functional layers in the light-emitting composite layer 60 toward the center of the N-type charge generation layer 30, which is greater than or equal to 30 micrometers. For example, the recessed distance of the edge of the N-type charge generation layer 30 can be 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 120 micrometers, 130 micrometers, 140 micrometers, or 150 micrometers.

[0064] In some embodiments, please refer to Figure 6 At least one of the functional layers in the light-emitting composite layer 60 covers the upper surface 301 of the N-type charge generation layer 30 away from the first light-emitting functional layer 20, and the N-type charge generation layer 30 is connected to a plurality of side surfaces 302 of the upper surface 301; that is, at least one of the functional layers in the light-emitting composite layer 60 covers the N-type charge generation layer 30.

[0065] The light-emitting composite layer 60 is disposed between the N-type charge generation layer 30 and the cathode layer 50, and at least one of the functional layers in the light-emitting composite layer 60 is disposed between the N-type charge generation layer 30 and the cathode layer 50, thereby further reducing the probability of contact between the N-type charge generation layer 30 and the cathode layer 50.

[0066] In some embodiments, at least one of the P-type charge generation layer 61 and the second light-emitting auxiliary layer in the cathode layer 50 is spaced between the N-type charge generation layer 30 and the cathode layer 50.

[0067] In some embodiments, when the second light-emitting auxiliary layer includes the second hole injection layer 421, the second hole transport layer 422, the second electron injection layer 431, and the second electron transport layer 432, at least one of the P-type charge generation layer 61, the second hole injection layer 421, the second hole transport layer 422, the second electron injection layer 431, and the second electron transport layer 432 is spaced between the N-type charge generation layer 30 and the cathode layer 50.

[0068] In some embodiments, please combine Figure 2 as well as Figure 7 The display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101. The non-display area 102 includes a bonding area 1021 located on one side of the display area 101. The display panel includes a substrate and a VDD signal terminal 11 disposed on the substrate and located between the bonding area 1021 and the display area 101. The anode layer 10 is electrically connected to the VDD signal terminal 11.

[0069] The orthographic projection of the N-type charge generation layer 30 on the substrate and the orthographic projection of the VDD signal terminal 11 on the substrate are spaced apart, meaning that the coverage of the N-type charge generation layer 30 does not extend to the position of the VDD signal terminal 11, and thus the N-type charge generation layer 30 will not be short-circuited with the anode layer 10.

[0070] Furthermore, in some embodiments, the cathode layer 50 covers the display area 101 and extends beyond the display area 101. The cathode layer 50 is connected to a VSS signal terminal (not shown in the figure) within the non-display area 102. The VSS signal terminal may be distributed around the periphery of the display area 101 and may be located at least in other areas of the non-display area 102 except for the side where the bonding area 1021 is located. The N-type charge generation layer 30 also covers the display area 101 and extends into the non-display area 102. Around the periphery of the display area 101, the orthographic projection of the N-type charge generation layer 30 onto the cathode layer 50 is located within the coverage area of ​​the orthographic projection of the light-emitting composite layer 60 onto the cathode layer 50.

[0071] Continuing from the above, this embodiment of the application sets the orthographic projection of the N-type charge generation layer 30 onto the cathode layer 50 to not exceed the coverage area of ​​the orthographic projection of at least one functional layer in the light-emitting composite layer 60 onto the cathode layer 50; thereby reducing the probability of a short circuit between the N-type charge generation layer 30 and the cathode layer 50, reducing the probability of the light-emitting composite layer 60 located between the cathode layer 50 and the N-type charge generation layer 30 being short-circuited, improving the display uniformity and stability of the display panel, and improving the display effect of the display panel.

[0072] In accordance with the above-mentioned objectives of this application, please refer to Figure 2 , Figure 3 , Figure 4 as well as Figure 8 This application also provides a method for manufacturing a display panel, the method comprising:

[0073] S10, forming the anode layer 10.

[0074] S20, A first light-emitting functional layer 20 is formed on one side of the anode layer 10.

[0075] S30. An N-type charge generation layer 30 is formed on the side of the first light-emitting functional layer 20 away from the anode layer 10.

[0076] S40. A light-emitting composite layer 60 is formed on the side of the N-type charge generation layer 30 away from the first light-emitting functional layer 20. The light-emitting composite layer 60 includes a plurality of functional layers stacked together.

[0077] S50, a cathode layer 50 is formed on the side of the light-emitting composite layer 60 away from the N-type charge generation layer 30, wherein the orthogonal projection of the N-type charge generation layer 30 onto the cathode layer 50 does not exceed the coverage area of ​​the orthogonal projection of at least one of the functional layers in the light-emitting composite layer 60 onto the cathode layer 50.

[0078] Specifically, in step S10, a substrate is first provided, and the substrate can be a rigid substrate or a flexible substrate.

[0079] A thin-film transistor layer is formed on the substrate. The thin-film transistor layer includes a plurality of thin-film transistors arranged in an array on the substrate. The thin-film transistors are part of the driving circuit in the display panel and can be used to control the on / off state of signal transmission. The thin-film transistors include an active layer, a gate, a source, and a drain.

[0080] A planarization layer is formed on the side of the thin-film transistor layer away from the substrate, and an anode layer 10 is formed on the side of the planarization layer away from the thin-film transistor layer. The anode layer 10 includes a plurality of patterned anodes, each of which can be connected to the source or drain of a thin-film transistor and transmits a signal to the anode through the control of the thin-film transistor.

[0081] In step S20, a pixel definition layer is formed on the planarization layer, and a plurality of pixel openings are provided in the pixel definition layer, with each pixel opening corresponding to an exposed anode.

[0082] Next, a first light-emitting functional layer 20 is formed on the pixel definition layer, wherein the first light-emitting functional layer 20 includes a first light-emitting layer 21 and a first light-emitting auxiliary layer formed on the pixel definition layer; further, the first light-emitting functional layer 20 may include a first hole layer 22, a first light-emitting layer 21 and a first electron layer 23 sequentially formed on the pixel definition layer; the first hole layer 22 and the first electron layer 23 continuously cover the side of the pixel definition layer away from the planarization layer and the plurality of pixel openings, and the first light-emitting layer 21 may include a plurality of first light-emitting parts disposed in the plurality of pixel openings, one first light-emitting part being located in one pixel opening and between the first hole layer 22 and the first electron layer 23.

[0083] In some embodiments, the first hole layer 22 may include a first hole injection layer 221 and a first hole transport layer 222, and the first electron layer 23 may include a first electron injection layer 231 and a first electron transport layer 232.

[0084] In step S30, the intrinsic material and the doped material are deposited on the side of the first light-emitting functional layer 20 away from the anode layer 10 using a first mask to form the N-type charge generation layer 30.

[0085] It is understood that the evaporation opening areas corresponding to the intrinsic material and the doped material are the same. Therefore, the distribution area of ​​the doped material in the N-type charge generation layer 30 is the same as the distribution area of ​​the intrinsic material in the N-type charge generation layer 30.

[0086] In some embodiments, the intrinsic material includes an electron transport material, and the doped material includes a metallic material, such as at least one of Yb and Li.

[0087] In step S40, at least one second mask may be used to form the light-emitting composite layer 60 on the side of the N-type charge generation layer 30 away from the first light-emitting functional layer 20.

[0088] In this process, a P-type charge generation layer 61 is formed on the side of the N-type charge generation layer 30 away from the first light-emitting functional layer 20. The material of the P-type charge generation layer 61 includes a hole transport material and a P-type dopant material distributed in the hole transport material.

[0089] A second light-emitting functional layer 40 is formed on the side of the P-type charge generation layer 61 away from the N-type charge generation layer 30. The second light-emitting functional layer 40 includes a second light-emitting layer 41 and a second light-emitting auxiliary layer formed on the side of the P-type charge generation layer 61 away from the N-type charge generation layer 30. Further, the second light-emitting functional layer 40 may include a second hole layer 42, a second light-emitting layer 41, and a second electron layer 43 sequentially formed on the P-type charge generation layer 61. The second hole layer 42 and the second electron layer 43 continuously cover the side of the P-type charge generation layer 61 away from the N-type charge generation layer 30. The second light-emitting layer 41 may include a plurality of second light-emitting parts disposed in a plurality of pixel openings. One second light-emitting part is located in one pixel opening and is located between the second hole layer 42 and the second electron layer 43.

[0090] In some embodiments, the second hole layer 42 may include a second hole injection layer 421 and a second hole transport layer 422, and the second electron layer 43 may include a second electron injection layer 431 and a second electron transport layer 432.

[0091] It should be noted that the P-type charge generation layer 61, the second hole layer 42, and the second electron layer 43 can be formed by vapor deposition using at least one of the second masks. That is, any one or more of the P-type charge generation layer 61, the second hole injection layer 421, the second hole transport layer 422, the second electron injection layer 431, and the second electron transport layer 432 can be formed using the second masks with the same vapor deposition opening area, or using the second masks with different vapor deposition opening areas.

[0092] In some embodiments, when the number of the second mask is one, the vapor deposition opening area of ​​the second mask is greater than or equal to the vapor deposition opening area of ​​the first mask.

[0093] In some embodiments, when there are multiple second masks, the vapor deposition opening areas of each second mask may be the same or different, and the vapor deposition opening area of ​​at least one second mask is greater than or equal to the vapor deposition opening area of ​​the first mask.

[0094] Continuing from the above, by controlling the evaporation opening area of ​​the second mask and the evaporation opening area of ​​the first mask, the boundary of at least one of the functional layers in the light-emitting composite layer 60 can be made greater than or equal to the boundary of the N-type charge generation layer 30, so that the boundary of the N-type charge generation layer 30 does not exceed the boundary of at least one of the functional layers in the light-emitting composite layer 60.

[0095] In step S50, a cathode layer 50 is formed on the side of the light-emitting composite layer 60 away from the N-type charge generation layer 30, and the orthographic projection of the N-type charge generation layer 30 onto the cathode layer 50 does not exceed the coverage area of ​​the orthographic projection of at least one of the functional layers in the light-emitting composite layer 60 onto the cathode layer 50.

[0096] In this embodiment, at least one of the functional layers in the light-emitting composite layer 60 is spaced between the N-type charge generation layer 30 and the cathode layer 50.

[0097] In summary, by setting the orthographic projection of the N-type charge generation layer 30 onto the cathode layer 50 to not exceed the coverage area of ​​the orthographic projection of at least one functional layer in the light-emitting composite layer 60 onto the cathode layer 50, the probability of a short circuit between the N-type charge generation layer 30 and the cathode layer 50 can be reduced, as can the probability of the light-emitting composite layer 60 located between the cathode layer 50 and the N-type charge generation layer 30 being short-circuited. This improves the display uniformity and stability of the display panel and enhances its display effect.

[0098] In addition, this application embodiment also provides a display device, the display device including the display panel described in the above embodiments, or the display panel obtained by the manufacturing method of the display panel described in the above embodiments.

[0099] It is understood that since the display device includes the display panel described in the above embodiments, the display device has the same beneficial effects as the display panel described in the above embodiments, and will not be repeated here.

[0100] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0101] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: Anode layer; A first light-emitting functional layer is disposed on one side of the anode layer; An N-type charge generation layer is disposed on the side of the first light-emitting functional layer away from the anode layer; A light-emitting composite layer is disposed on the side of the N-type charge generation layer away from the first light-emitting functional layer; A cathode layer is disposed on the side of the light-emitting composite layer away from the N-type charge generation layer; The light-emitting composite layer includes multiple functional layers stacked together. The orthogonal projection of the N-type charge generating layer onto the cathode layer does not exceed the coverage area of ​​the orthogonal projection of at least one of the functional layers in the light-emitting composite layer onto the cathode layer. The edge of the N-type charge generating layer is recessed towards the center of the N-type charge generating layer relative to the edge of at least one of the functional layers in the light-emitting composite layer.

2. The display panel according to claim 1, characterized in that, The N-type charge generation layer contains doped materials and intrinsic materials, and the distribution area of ​​the doped materials in the N-type charge generation layer is the same as the distribution area of ​​the intrinsic materials in the N-type charge generation layer.

3. The display panel according to claim 1, characterized in that, The edge of the N-type charge generation layer is recessed by a distance greater than or equal to 30 micrometers relative to the edge of at least one of the functional layers in the light-emitting composite layer toward the center of the N-type charge generation layer.

4. The display panel according to claim 1, characterized in that, At least one of the functional layers in the light-emitting composite layer covers the upper surface of the N-type charge-generating layer away from the first light-emitting functional layer and the multiple side surfaces of the N-type charge-generating layer connected to the upper surface.

5. The display panel according to claim 1 or 2, characterized in that, The plurality of functional layers include a P-type charge generation layer disposed between the N-type charge generation layer and the cathode layer, and a second light-emitting functional layer disposed between the P-type charge generation layer and the cathode layer; The orthogonal projection of the N-type charge generation layer onto the cathode layer does not exceed the coverage area of ​​the orthogonal projection of the P-type charge generation layer onto the cathode layer, and / or the orthogonal projection of the N-type charge generation layer onto the cathode layer does not exceed the coverage area of ​​the orthogonal projection of the second light-emitting functional layer onto the cathode layer.

6. The display panel according to claim 5, characterized in that, The first light-emitting functional layer includes a first light-emitting layer and a first light-emitting auxiliary layer stacked together. The first light-emitting auxiliary layer includes at least one of a first electron injection layer, a first electron transport layer, a first hole injection layer, and a first hole transport layer. The second light-emitting functional layer includes a second light-emitting layer and a second light-emitting auxiliary layer stacked together. The second light-emitting auxiliary layer includes at least one of a second electron injection layer, a second electron transport layer, a second hole injection layer, and a second hole transport layer. Wherein, the orthogonal projection of the N-type charge generation layer on the cathode layer does not exceed the coverage area of ​​the orthogonal projection of the P-type charge generation layer on the cathode layer, and / or the orthogonal projection of the N-type charge generation layer on the cathode layer does not exceed the coverage area of ​​the orthogonal projection of the second light-emitting auxiliary layer on the cathode layer.

7. The display panel according to claim 1, characterized in that, At least one of the functional layers in the light-emitting composite layer is disposed between the N-type charge generation layer and the cathode layer.

8. The display panel according to claim 1, characterized in that, The display panel includes a display area and a non-display area adjacent to the display area. The non-display area includes a bonding area located on one side of the display area. The display panel includes a substrate and a VDD signal terminal disposed on the substrate and located between the bonding area and the display area. The anode layer is electrically connected to the VDD signal terminal. The orthographic projection of the N-type charge generation layer on the substrate and the orthographic projection of the VDD signal terminal on the substrate are spaced apart.

9. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 8.

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