Circuit and method

Abstract

In one embodiment, a circuit includes: an instruction decoder circuit to decode an instruction for execution; processing circuitry to execute the instructions decoded by the instruction decoder circuitry; an interface circuit defining an interface for data communication with the data compression circuit; wherein the processing circuitry is responsive to one or more instructions of a set of instructions defined for the processing circuitry to provide to the interface: input data to be processed by the data compression circuitry; and identification data identifying the compression system used by the data compression circuitry to process the input data; and wherein the processing circuitry is configured to receive from the interface: status data indicating whether a data compression circuitry connected to the interface is capable of processing data using the compression system identified by the identification data; and outputting data, which has been processed by the data compression circuit from the input data using the compression system identified by the identification data, when the status data indicates that the data compression circuit is capable of processing data using the compression system identified by the identification data.

Description

Background Art

[0001] The present disclosure relates to a data processing device, method and virtual machine.

[0002] Some data processing arrangements allow a processing operation (such as neural processing) to be performed using a set of processing values ​​(such as weights or activation values). Summary of the invention

[0003] In one example arrangement, there is provided a circuit comprising:

[0004] an instruction decoder circuit for decoding instructions for execution;

[0005] processing circuitry for executing instructions decoded by the instruction decoder circuitry;

[0006] an interface circuit defining an interface for data communication with the data compression circuit;

[0007] wherein the processing circuit is responsive to one or more instructions in an instruction set defined for the processing circuit to provide to the interface: input data to be processed by the data compression circuit; and identification data identifying a compression system used by the data compression circuit to process the input data; and

[0008] The processing circuit is configured to receive from the interface: status data indicating whether a data compression circuit connected to the interface is capable of processing data using a compression system identified by identification data; and when the status data indicates that the data compression circuit is capable of processing data using a compression system identified by identification data, output data, the output data having been processed from the input data by the data compression circuit using the compression system identified by the identification data.

[0009] In another example arrangement, a method is provided, the method comprising:

[0010] Decode instructions for execution;

[0011] executing, using processing circuitry, the instruction decoded by the instruction decoding step;

[0012] defining an interface for data communication with a data compression circuit;

[0013] In response to one or more instructions in an instruction set defined for the processing circuitry, the processing circuitry provides to the interface: input data to be processed by the data compression circuitry; and identification data identifying a compression system used by the data compression circuitry to process the input data; and

[0014] The processing circuit receives from the interface: status data indicating whether a data compression circuit connected to the interface is capable of processing data using a compression system identified by identification data; and when the status data indicates that the data compression circuit is capable of processing data using a compression system identified by identification data, output data, the output data having been processed from the input data by the data compression circuit using the compression system identified by the identification data.

[0015] Further respective aspects and features of the present disclosure are defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present technology will be further described, by way of example only, with reference to embodiments of the invention as illustrated in the accompanying drawings, in which:

[0017] Figure 1 A data processing apparatus is schematically illustrated;

[0018] Figure 2 The interface of the compression processor is schematically illustrated;

[0019] Figure 3 and Figure 4 is a schematic flow chart illustrating a corresponding method; and

[0020] Figure 5 An example of a simulator is schematically illustrated. DETAILED DESCRIPTION

[0021] Processor Overview

[0022] Now referring to the accompanying drawings, Figure 1 A data processing system 10 is schematically illustrated and includes a processor 20 coupled to a memory 30 storing data values ​​32 and program (or processing) instructions 34. The processor 20 includes an instruction fetch unit 40 for fetching program instructions 34 from the memory 30 and supplying the fetched program instructions to a decoder circuit 50. The decoder circuit 50 decodes the fetched program instructions and generates control signals to control processing circuitry 60 to perform processing operations on registers stored within register circuitry 70 as specified by the decoded vector instruction.

[0023] Processor 20 may optionally access a storage array 90. This is drawn in dashed lines to illustrate that it may or may not be provided as part of processor 20. In an example embodiment, storage array 90 may be a square array portion of a larger or even higher dimensional array or matrix of data items stored in memory. In at least some examples, the storage array may be considered an accumulation array, referred to as a "ZA" in the so-called Scalable Matrix Extension (SME) system provided or specified by Arm Limited.

[0024] In at least some examples, the ZA is implemented as an n×m (square or rectangular) array that stores (or accumulates) elements. In some examples, n and m can be the same and can be equal to the SVL, or in other words, equal to the streaming vector length used within the system (as defined using the so-called Scalable Vector Extensions (SVE) or SVE2 system provided or specified by Arm Limited).

[0025] The SME instruction may refer to various types of matrix operands, including "tiles" that represent subsets of ZA. In some examples, the tiles themselves are square arrays, but this is not required and (for example) rectangular tiles may be used. So-called "tile vectors" represent rows or columns of ZA. An operand called an "accumulator matrix" refers to the entire ZA.

[0026] The processing circuitry 60 may provide or include vector and / or matrix processing circuitry. The general distinction between scalar processing and vector processing is as follows. Vector processing involves applying a single vector processing instruction to a data item of a data vector having multiple data items at corresponding positions in the data vector. Scalar processing operates efficiently on a single data item rather than a data vector. Vector processing is useful in the following situations: processing operations are performed on many different instances of data to be processed. In a vector processing arrangement, a single instruction may be applied to multiple data items (of a data vector) simultaneously. This may improve the efficiency and throughput of data processing compared to scalar processing.

[0027] The processing circuitry may be used to perform operations on matrices. Here, a matrix may be considered to be an array of matrix elements. The array may be two-dimensional or may have higher dimensions.

[0028] Although the present embodiments may involve vector and / or matrix processing, they do not require the use of vector or matrix processors.

[0029] The following discussion refers to example program instructions 34. Embodiments of the present disclosure include, for example, Figure 1 A device of the type shown in is operable or configured to decode and execute such program instructions.

[0030] Register circuit 70 provides a set of physical registers that can be allocated to architectural registers for executing processing instructions. The architectural registers are defined by the processor architecture and its instruction set architecture (ISA). Instructions will define one or more architectural registers to hold source or destination (output) operands, but in actual execution, these architectural registers will be implemented by corresponding physical registers 70. In the case where the registers are vector registers, these may be referred to as "Z" registers. In some examples, these may be scalable vector registers according to the SVE or SVE2 system described above, depending on the primary vector length SVL used.

[0031] In performing such execution, the storage array may act as an accumulation array of the type discussed above as ZA. The processing circuitry may perform a processing operation (such as a matrix processing operation) using the storage array in response to the decoded instruction to accumulate the results of the operation. In other words, the instruction execution circuitry executes the instruction decoded by the instruction decoder circuitry 50, and the instruction execution circuitry is configured to execute the decoded instruction by reference to one or more source operands stored by the set of architectural registers and to maintain one or more values ​​generated by the decoded instruction. This may be an output for storage to an architectural register, or one or more values ​​for storage to a memory, etc.

[0032] Compression circuitry 55 is provided which may provide compression functionality as described below. In some examples, compression circuitry 55 may access at least a subset of registers provided by register circuitry 70. Generally, interface circuitry between compression circuitry 55 and processing circuitry 60 may be provided; although for Figure 1 For clarity, this is not shown in the figure, but will be combined with Figure 2 Have a discussion.

[0033] Neural Processing and Weight Compression

[0034] In certain examples, in some cases, Figure 1 Circuits of this type can be used for neural network processing. In this type of arrangement, the data values ​​to be processed are typically combined with (e.g., multiplied by) a set of weight values. Such processing may involve performing many of these combinations and may therefore be conveniently performed by a vector or matrix processor.

[0035] Weight compression can be a useful technique for neural networks. Compressing weights has the potential advantage of making the overall model smaller and easier to distribute, and also has the potential for higher performance because lower bandwidth is required to load the weight data into the processor for processing.

[0036] Two examples of this are lookup table based clustering and structured sparsity.

[0037] Examples of these techniques are discussed in Gong, Yunchao et al., “Compressing Deep Convolutional Networks using Vector Quantization,” ArXiv abs / 1412.6115 (2014) (https: / / arxiv.org / pdf / 1412.6115.pdf) and https: / / developer.nvidia.com / blog / accelerating-inference-with-sparsity-using-ampere-and-tensorrt / , both of which are incorporated by reference into this application in their entirety.

[0038] Clustering is a technique that forces processed values ​​(usually weights or activations) to be one of a finite number of specific values. Each processed value can then be stored as an index into a codebook of values. Before such processed values ​​can be used for computation, they need to be expanded back to a full-size representation.

[0039] Structured sparsity is a different technique where some of the processed values ​​are forced to be zero. "Structured" means that the sparsity level is enforced at a fine-grained level, e.g. the so-called "2-in-4 sparsity" splits the processed values ​​into 4 blocks, where at least 2 of the blocks must be zero. This allows the data to be represented as an array of half the size of the non-zero data values ​​and some sideband "presence" data that indicates their location in each block.

[0040] Both techniques are attractive because of memory and bandwidth advantages - sparse or clustered representations allow processing values ​​to take up less memory space and consume less bandwidth (or provide higher performance for a given fixed bandwidth) when they are used by operations. The technical literature indicates that this compression can be achieved with little or no impact on the function of the neural network (as measured by accuracy). It is also likely that these techniques are far from the only ones that can be used for this purpose. This poses a challenge to the processor, either to convert the data into a more suitable form before calculation, or to implement specialized operations to directly process the compressed representation.

[0041] Example arrangements involve providing and engaging compression circuitry to handle such decompression, such as decompression of process values ​​(such as weights or activation values) (although these techniques are independent of the nature of the actual data to be decompressed). However, although process value decompression is discussed as a working example of the present technology, the present example is not limited to decompression. Compression circuitry can be used for data compression rather than decompression, such as by applying the 2-in-4 sparsity techniques discussed in this application. In fact, at a basic level, the operation of the compression processor can be considered to provide a process of transforming a data set from one representation to another. In general, "compression" is often used to imply that the destination format provides a representation (whether lossless or otherwise) that uses less data than the input format, while "decompression" is often used to imply that the destination format provides a representation that uses more data than the input format. The term "compression" used herein in conjunction with the data compression circuit 55 or in conjunction with an algorithm, system, parameter set, etc. related to the operation of the compression circuit 55 may include compression or decompression.

[0042] As mentioned above, various compression schemes are in use, and this is an area of ​​ongoing research, which means that more compression schemes may be developed in the future. Given the value of compression but the lack of widespread standardization of compression methods, example embodiments aim to provide a mechanism that can support multiple compression schemes.

[0043] One method of supporting data compression or decompression can be to add extensions to the instruction set (as defined by the instruction set architecture or ISA applicable to the processing circuit). The method will need to modify the ISA in response to the development (or increasing popularity) of compression technology. However, the process of modifying the ISA of the processor may be relatively thorough and tedious. Moreover, this may cause obsolete technology to occupy the ISA encoding space, i.e., the value set that can be used to represent the instruction. Considering that the ISA encoding space is limited, and the existence of obsolete technology in the ISA may require a compatible processor to provide hardware to implement such obsolete technology, this may be undesirable.

[0044] The techniques of the present disclosure may potentially provide one or more of the following: allowing support for multiple compression schemes; allowing new schemes to be included (and / or old schemes to be deprecated) without requiring changes to the operating system or processing circuitry; and avoiding the need to consume more instruction set space for each additional compression scheme.

[0045] Example of compression circuit 55

[0046] Figure 2 A schematic example is provided showing compression circuit 55 (as an example of a data compression processor or circuit), processing circuit 60 , and interface circuit 200 defining an interface for data communication between processing circuit 60 and compression circuit 55 .

[0047] For purposes of discussion, compression circuit 55 may be considered a "compression scheme black box," that is, from the perspective of processing circuit 60, in many respects, it does not matter how compression circuit 55 operates; so long as it is able to receive data and / or parameters in a particular format and output data in another particular format.

[0048] In some examples, compression circuitry may receive clustered processed (e.g., weight or activation) values ​​and / or weight values ​​in a structured sparse format and output decompressed processed values ​​for use by processing circuitry 60 in neural processing.

[0049] The processing circuitry 60 is responsive to one or more instructions in an instruction set defined for the processing circuitry to provide to the interface:

[0050] input data to be processed by the data compression circuit; and

[0051] Identification data identifying the compression system used by the data compression circuitry to process the input data. In other words, in these examples, the ISA provides control over the general ability of the processing circuitry to communicate with the compression circuitry 55 via the interface circuitry 200, but does not require the ISA to provide specific control over a particular compression system or algorithm.

[0052] Specifically, data communications with the compression circuit 55 may include: a scheme ID (identifier) ​​240, which may define or identify a particular compression scheme to be used; a configuration state 250, for example, defining parameters used by the selected compression scheme, such as a lookup table (LUT) used in conjunction with the selected compression scheme; and optionally, a dynamic state 260 to allow operations such as context switching to occur (so that, for example, the dynamic state of the compression processor 55 may be retrieved and stored by the processing circuit at the time of a context switch, and then restored when appropriate at a subsequent context switch). In other words, in conjunction with the dynamic state 260, the processing circuit may be configured to: receive state data defining the current operating state of the data compression circuit from the interface; perform a context switch, including at least storing the state data; and perform a further context switch, including at least providing the stored state data back to the data compression circuit.

[0053] The scheme ID and configuration state (and optionally dynamic state) together allow definition of the compression scheme to be operated by the compression circuit 55. In terms of data to be processed by the compression circuit 55, it may be provided as input data to hundred 10 via a subset of the Z registers (such as 1-4) accessible by the processing circuit and the compression circuit 55, and processed data 220 may be output again by the compression circuit 55 using the subset of the Z registers (such as 1-4).

[0054] The configuration state may be a two-way communication such that the compression circuit 55 may return data to the processing circuit 60 via the interface circuit 200 indicating such things as the ability of the compression circuit 55 to perform the compression scheme defined by the scheme ID. Thus, in these examples, the processing circuit is configured to receive from the interface:

[0055] status data indicating whether data compression circuitry connected to the interface is capable of processing data using the compression system identified by the identification data (eg, via bidirectional communication of a configuration status); and

[0056] When the status data indicates that the data compression circuit is capable of processing the data using the compression system identified by the identification data, outputting data that has been processed from the input data by the data compression circuit using the compression system identified by the identification data (eg, as processed data 220).

[0057] The interface circuit 200 may provide data communication with the compression circuit 55, for example using one or more registers implemented by the register circuit 70, which may be accessible by the processing circuit 60 and the compression circuit 55. In practice, all data communication functions of the interface circuit 200 may be implemented by processor registers, or a separate circuit may be used that is configured to receive data from and provide data to each of the processing circuit 60 and the compression circuit 55. In other words, in an example, the interface circuit includes one or more processor registers that are accessible by the processing circuit and the data compression circuit connected to the interface. For example, the processing circuit may be configured to write at least identification data to one or more processor registers and read at least status data from one or more processor registers.

[0058] The techniques defined herein may be applied to processing circuitry and interface circuitry, whether or not compression circuitry 55 is present. In other words, features of the present disclosure may be defined with respect to the arrangement of processing circuitry and interface circuitry.

[0059] As described above, the arrangement may include a data memory (e.g., memory 30 and / or storage array 90); wherein the processing circuit is configured to: execute instructions defining a neural network in which processing values ​​are applied to data values; read compressed data defining the processing values ​​from the data memory; provide the compressed data as input data to an interface and receive decompressed processing values ​​as output data for use by the instructions defining the neural network.

[0060] Similarly, the arrangement may be used to compress processed values ​​for use by other processors, for example where the processing circuit is configured to: read data defining the processed values ​​from a data memory; provide the data defining the processed values ​​as input data to an interface and receive the compressed processed values ​​as output data.

[0061] Direct processing path

[0062] Also shown is a direct processing path 230, which in this example includes the 1Z register as input and the 1-4Z registers as output. This provides an optional straight-through path if required by the application in use.

[0063] In some examples, at least two modes of operation are supported.

[0064] In one mode, loading input data and extracting output data are separate operations. This may be appropriate, for example, for structured sparsity where it is necessary to provide "sideband" presence bits but not produce output immediately. This may also be useful for more advanced variable rate schemes where there is no fixed relationship between the input and output streams.

[0065] In another mode (so-called direct processing), the operations are combined so that a single operation can provide input data and extract corresponding output data. This can be useful for lookup table schemes where there is a direct correspondence between the two - this reduces the number of instructions required to perform the decompression and simplifies context switching (if separate input and output instructions are being used, the input data becomes part of the state at the same time).

[0066] In practice, a hybrid may be used - for example structured sparsity may use an "input" mechanism to load presence data, and then use a "direct decompression" mode to expand the input vector into an output vector (implicitly consuming some presence data).

[0067] Example Operation

[0068] Figure 3 is a schematic flow chart illustrating an example of operations between the processing circuit 60 (operations shown to the left of the vertical schematic boundary 300) and the compression circuit 55 (operations shown to the right of the boundary 300).

[0069] At step 310, the processing circuitry establishes parameters for processing by compression circuitry 55. As described above, this may be in response to execution of one or more instructions within the ISA of processing circuitry 60, with decoder circuitry 50 decoding the instructions for execution and processing circuitry 60 executing those instructions as decoded by decoder circuitry 50.

[0070] At step 320 , the processing circuitry provides at least the identification data to the compression circuitry 55 via the interface circuitry 200 , and at step 330 , the compression circuitry receives at least the identification data.

[0071] At step 340, compression circuitry 55 compares identification data, e.g., defining at least the scheme ID, to the processing capabilities of compression circuitry 55, and returns a response to processing circuitry 60 by sending status data at step 343 and processing circuitry receiving the status data at step 346. The response may represent the status data discussed above.

[0072] At step 350, the processing circuitry detects whether the status data indicates that the compression circuitry 55 is capable of processing the compression scheme defined by the scheme ID.

[0073] With respect to a negative outcome of step 350 , the processing circuit is configured to execute instructions to control the processing circuit to perform processing on the input data when the status data indicates that the compression circuit 55 cannot process the data using the compression system identified by the identification data.

[0074] If the result is yes, then processing is performed so that the compression circuit 55 processes and returns the data. Specifically, step 360 represents initiating processing of the data using the compression circuit 55. At step 363, depending on the interface technology used, the processing circuit 60 writes the data to be processed to one or more registers and the compression circuit 55 reads the data at step 366. At step 370, the compression circuit 55 processes the data. At step 373, the compression circuit writes the processed data to one or more registers, and at step 376, the processing circuit reads the processed data. When there is more data to be processed in this manner, control then optionally returns to step 360.

[0075] Specific Examples

[0076] Specific examples will now be described.

[0077] The scheme ID (as an example of identification data) identifies the specific compression scheme used. The scheme selected here controls how input data is transformed into output data and how other framework features are used.

[0078] In the overall system defined by the scheme ID, scheme-specific states may be considered. This may define configuration states; for example, as described above, many compression schemes require static states to be configured before processing can proceed. For example, a lookup table (LUT) based scheme requires the LUT itself to be built. This may not be required for all schemes. If the configuration data is only a few bits (e.g., an input / output width selector), it may be incorporated into the scheme ID.

[0079] With reference to the terminology used above, in these examples, the identification data may be configured to define a compression algorithm and one or more parameters used during execution of the compression algorithm. For example, the one or more parameters may include one or more lookup tables used with the compression algorithm defined by the identification data. In some examples, the one or more parameters may include data defining an initial state to be applied to the data compression algorithm defined by the identification data.

[0080] Scenario-specific states can also define dynamic states.

[0081] Most compression schemes will have either dynamic state (such as compressed data that has been loaded but not yet extracted) or "internal" state (such as a dictionary that is derived from the incoming data stream but needs to be maintained to perform decompression).

[0082] Scenarios that support only direct decompression may not require dynamic state.

[0083] Scenario-specific states can also define composite states.

[0084] In order for a general purpose compression system to work, there should be a scheme-agnostic way to switch all the state associated with the scheme at context switch time (and possibly in user code if a mechanism similar to ZA is used to manage it). This can include any configuration state. Furthermore, software that utilizes a particular scheme (that is, instructions for execution by processing circuitry 60) can use scheme-specific knowledge of how to configure and use it.

[0085] With respect to the above reference to a mechanism similar to the ZA, the following further explanation is provided. In user code, an ABI (Application Binary Interface) mechanism may be provided that allows a calling function using the ZA to call a second function (where the second function may or may not use any SME features), thereby leaving a live state in the ZA and storing a pointer to a save area of ​​the ZA state. If the ZA needs to be used at some point during the processing of the second function (which may involve further function calls), the called function checks the relevant status bits and, if necessary, stores the contents of the ZA to a pointer before using the ZA for any requirements defined by the second function or functions called by the second function. When the second function returns, the calling function checks the status bits to see if the ZA contents have been saved, and if so, restores them from the save area before resuming processing.

[0086] This potentially allows lower overhead in cases where the second function does not use ZA (since the calling function does not have to save ZA and restore it later when it has not actually changed), while not incurring as much overhead in cases where it does use it, since the status bit needs to be checked on entry to a function that uses ZA and on return from such a function call.

[0087] A similar scheme can be used to compress state in circuits - so that the code that saves should be able to save data without knowing exactly what is being saved (this is similar to the context switch requirement).

[0088] In other words, in some examples, user functions may need to be saved / restored across function calls.

[0089] As mentioned above, in terms of data input / output, all schemes utilize a mechanism of, for example, passing compressed (or input) data into the scheme and getting decompressed (or processed) data out again. Again, at least two variations are considered.

[0090] Separate input / output instructions. Two different operations are provided: move from register to compressor (1-4Z registers), and move from compressor to register (1-4Z registers). This is well suited for scenarios where there is no simple fixed ratio between input and output, or if multiple slices of data are needed to implement a process (e.g.,

[0091] block or structured sparse schemes).

[0092] Combined input / output instruction. This is a single instruction that consumes a single Z-register and produces 1-4 Z-registers of output.

[0093] In some examples, a register is dedicated or added for selecting a compression scheme. Bits 31:0 of ​​the register identify the compression scheme to be used, with a reserved value of 0 indicating that no scheme is selected. If the value written to the register identifies a scheme that is not supported by the current implementation, the register is set to 0 by the compression circuit 55. Software can read back the register to verify (as status data) whether the scheme is supported.

[0094] Another example may enable multiple compression schemes to be used simultaneously.

[0095] A compression scheme may have associated state, either pre-configured prior to using the scheme, or populated during operation.

[0096] In some examples, a system register is added or dedicated to indicate the amount of state currently stored (or, depending on the scheme, can be set to the amount of state required for configuration). Whether the register is read-only or read-write is defined by the scheme. Some schemes (such as a lookup table) can function without referring to this register.

[0097] Another register may be dedicated or added to indicate the maximum possible live state size for any supported compression scheme. This can be used by the operating system to appropriately determine the size of the fixed context switch buffer.

[0098] Add two new instructions to read and write status:

[0099] MOVCSSR0 - Move from register to compression scheme state

[0100] The syntax can be: MOVCSSR0 Zt,Xn{,# <imm>,MUL VL}

[0101] This instruction loads state into the compressed scheme. The state of the compressed scheme is modeled as a single 1D buffer of a certain length (as described in the previous paragraph). Zt identifies the vector register that holds the state to be loaded, and Xn (possibly plus "imm*VL") indicates the offset into the buffer to be written.

[0102] MOVRCSS0 - Move from Compression Scheme State to Registers

[0103] The syntax can be: MOVRCSS0 Zt,Xn{,# <imm>,MUL VL}

[0104] This is similar to above, but Xn identifies which bit of the buffer to copy, and Zt indicates where to copy it.

[0105] Three new instructions may be provided to actually do the compression, decompression, or both.

[0106] Load compressed data:

[0107] MOVCR0 - Move from register to compression scheme

[0108] The syntax can be: MOVCR0 CRx,Zt{or multiple}

[0109] CRx is the compression register ID, with a scheme-specific meaning, and can be 3-4 bits.

[0110] The use of MOVRCSS0 and MOVCR0 described above provides an example of separate corresponding instructions provided by the ISA to provide identification information to the interface (MOVRCSS0 in this example) and to provide input information to the interface (MOVCR0 in this example).

[0111] Extract the decompressed data:

[0112] MOVRC0 - Move from compression scheme to register

[0113] The syntax can be: MOVRC0 Zt{or multiple},CRx

[0114] Zt defines the Z register. CRx is the register ID - the relationship between MOVCR and MOVRC depends on the compression scheme.

[0115] The use of the MOVRC0 instruction provides an example of another instruction provided by the ISA to retrieve output data from the interface.

[0116] Direct decompression

[0117] DECOMP0 - Decompression using scheme 0.

[0118] The syntax can be: DECOMP0 Zd{or multiple},Zs,{sub ID}

[0119] Here, Zs is the source register and Zd is the destination register. If one Zs decompresses to more than one Zd, a sub-ID may be provided to select portions of the register.

[0120] The direct decompression instruction may provide an example of an instruction (defined by the ISA) to provide input data and identification data to the interface and initiate processing of the input data by the data compression circuitry using a compression system defined by the identification data.

[0121] An example related to a lookup table will now be discussed. In this example, a scheme for expanding a 2-bit or 4-bit compressed value to an 8-bit, 16-bit, or 32-bit value may be implemented.

[0122] The input / output width is encoded into the scheme ID, so there is a 1-bit field for the 2-bit vs. 4-bit encoded value, but in other examples this may leave room for a 1-bit or 8-bit field, with the 2-bit field encoding the output width. The remaining 28-29 bits may have a constant value, identifying this as a lookup table scheme. This provides an example in which one or more parameters are configured to define the corresponding input and output data widths for a compression scheme.

[0123]

[0124] MOVCSSR0 is used to load the lookup table state. Depending on VL and the state size (see table above), this may be one operation or may require several operations.

[0125] The lookup is performed using DECOMP0. The lookup table, input and output widths are configured as described above, providing 1 input and 1-4 output registers. In cases where the ratio is greater than 4:1, a "sub-ID" can be used to indicate which slice of the input is to be consumed.

[0126] Examples related to structured sparsity will now be described.

[0127] This may, for example, support "2-in-4" structural sparsity for 8-bit, 16-bit, or 32-bit data types. The nature of the sparsity scheme (e.g., the number of sparse blocks (such as 2) that define a block group (such as 4 blocks in the example "2-in-4" scheme) and / or the data type used are aspects that may be defined, either individually or collectively, by parameters provided by or associated with the identification data.

[0128] The scheme ID may include a 2-bit width indicator since it affects the rate of register accesses.

[0129] The register indicating the state amount may indicate how much unused sparse data - up to VL bytes - is retained in the sparse data register.

[0130] In terms of compression scheme state, nothing has to be explicitly set up before using the scheme. The context switch code will read the register indicating the amount of state and use the state instructions to save / restore the sparse data.

[0131] When decompressing, it is assumed that the sparse data is stored separately. MOVCR0 is used to load the sparse information. DECOMP0 is then used to convert one packed data register into two unpacked data registers, consuming the appropriate portion of the sparse data. The core needs to maintain the correct ratio between these two operations (i.e., 4:1 for 8-bit data, 8:1 for 16-bit data, or 16:1 for 32-bit data).

[0132] In summary, the example arrangement may provide the following features:

[0133] For each solution, the complete architectural details can be defined in a separate specification. Solution development does not need to be consistent with the rest of the architecture process.

[0134] For the specific implementation where the actual operation is handled by the remote unit, the host CPU can decode the architecture-specified operations and pass them to the remote unit without understanding the details of the scheme used. Therefore, the scheme can be added to the remote unit without contacting the host CPU. This refers to some potential example arrangements for implementing SME, in which there is a host processor and a separate SME unit that processes SME instructions. For non-SME code, the processor operates independently like any other processor. When encountering SME code, the SME instruction is sent to the SME unit via the bus. The SME unit usually has its own memory input / output path and register group. In the context of this example, when the "compression circuit" is part of the SME unit, the host CPU does not necessarily need to know which compression schemes are supported. All accesses can be sent to the SME unit for processing.

[0135] Unused schemes can be deprecated independently of the actual architecture, although if necessary,

[0136] Specific schema versions can mandate support for certain scenarios.

[0137] No need to consume additional instruction set space for each additional scheme.

[0138] Method Example

[0139] Figure 4 is a schematic flow chart of an exemplary method, the method comprising:

[0140] Decoding (at step 400) the instruction for execution;

[0141] executing (at step 410 ) the instruction decoded by the instruction decoding step using the processing circuitry;

[0142] defining (at step 420) an interface for communicating data with the data compression circuit;

[0143] In response to one or more instructions in the instruction set defined for the processing circuitry, the processing circuitry provides (at step 430) to the interface: input data to be processed by the data compression circuitry; and identification data identifying a compression system used by the data compression circuitry to process the input data; and

[0144] The processing circuit receives (at step 440) from the interface: status data indicating whether a data compression circuit connected to the interface is capable of processing data using a compression system identified by the identification data; and when the status data indicates that the data compression circuit is capable of processing data using the compression system identified by the identification data, output data that has been processed from the input data by the data compression circuit using the compression system identified by the identification data.

[0145] Simulator Example

[0146] Figure 5 The simulator that can be used is illustrated. Although the previously described embodiments implement the present disclosure in terms of the apparatus and method for operating the specific processing hardware supporting the technology involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented by using a computer program. Such computer programs are generally referred to as simulators, to a certain extent because such computer programs provide a specific implementation based on software of the hardware architecture. The types of simulator computer programs include emulators, virtual machines, models and binary converters, which include dynamic binary converters. Typically, the simulator is specifically implemented and can be run on a host processor 530 that supports the simulator program 510, optionally running a host operating system 520. In some arrangements, there may be multiple simulation layers between the hardware and the provided instruction execution environment and / or a plurality of different instruction execution environments provided on the same host processor. Historically, a powerful processor is required to provide a simulator that is executed at a reasonable speed, but this method may be reasonable in certain circumstances, such as when it is desired to run another processor local code for compatibility or reuse reasons. For example, the simulator is specifically implemented to provide additional functionality that is not supported by the host processor hardware to the instruction execution environment, or to provide an instruction execution environment that is generally associated with different hardware architectures. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0147] To the extent that embodiments have been previously described with reference to specific hardware constructs or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructs or features. For example, specific circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. One or more of the hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 530), and some simulated embodiments may utilize host hardware where appropriate.

[0148] The simulator program 510 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provide a program interface (instruction execution environment) to the target code 500 (which may include an application, an operating system, and / or a hypervisor), which is the same as the application program interface of the hardware architecture modeled by the simulator program 510. Therefore, the target code 500 (including the code for implementing the above-mentioned functions, such as the reference code) can be executed from within the instruction execution environment using the simulator program 510. Figure 4 The invention also provides program instructions for the functions described above (such as the functions described above) so that a host computer 530 that does not actually have the hardware features of the above-described device 10 can emulate these features.

[0149] General matters

[0150] In this application, the words "configured to..." are used to mean that elements of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the elements of the device need to be changed in any way in order to provide the defined operation.

[0151] Although the exemplary embodiments of the present invention technology have been described in detail herein in conjunction with the accompanying drawings, it should be understood that the present invention technology is not limited to those precise embodiments, and that various changes, additions and modifications may be implemented therein by those skilled in the art without departing from the scope and essence of the present invention technology as defined in the appended claims. For example, the features of the dependent claims may be combined in various ways with the features of the independent claims without departing from the scope of the present invention technology.< / imm> < / imm>

Claims

1. A circuit, comprising: an instruction decoder circuit for decoding instructions for execution; processing circuitry for executing instructions decoded by the instruction decoder circuitry; an interface circuit, the interface circuit defining an interface for data communication with the data compression circuit; wherein the processing circuitry is responsive to one or more instructions in an instruction set defined for the processing circuitry to provide to the interface: input data, the input data to be processed by the data compression circuitry; and identification data, the identification data identifying a compression system used by the data compression circuit to process the input data; and wherein the processing circuit is configured to receive from the interface: status data indicating whether a data compression circuit connected to the interface is capable of processing data using the compression system identified by the identification data; And when the status data indicates that the data compression circuit is capable of processing data using the compression system identified by the identification data, output data, the output data having been processed from the input data by the data compression circuit using the compression system identified by the identification data. 2 . The circuit of claim 1 , wherein the identification data is configured to define a compression algorithm and one or more parameters used during execution of the compression algorithm.

3. The circuit of claim 2, wherein the one or more parameters include at least a portion of one or more lookup tables used with a compression algorithm defined by the identification data. 4 . The circuit of claim 3 , wherein the one or more parameters are configured to define respective input and output data widths for a compression scheme.

5. The circuit of claim 2, wherein the one or more parameters are configured to define one or more aspects of a structured sparse compression algorithm, the one or more aspects comprising one or both of: a number of sparse blocks in a block group and a data type used by the algorithm.

6. A circuit according to any one of claims 2 to 5, wherein the one or more parameters include data defining an initial state to be applied to the data compression algorithm defined by the identification data.

7. A circuit according to any preceding claim, wherein the instruction set defined for the processing circuit comprises: Instructions for providing the input data and the identification data to the interface and for initiating, by the data compression circuit, processing of the input data using a compression system defined by the identification data.

8. A circuit as claimed in any preceding claim, wherein the instruction set defined for the processing circuit comprises separate respective instructions for providing identification data to the interface and for providing input data to the interface.

9. The circuit of claim 8, wherein the instruction set defined for the processing circuit includes a further instruction for retrieving output data from the interface.

10. A circuit according to any of the preceding claims, wherein the processing circuit is configured to: receive state data defining a current operating state of the data compression circuit from the interface; perform a context switch including at least storing the state data; and perform a further context switch including providing at least the stored state data back to the data compression circuit.

11. A circuit as claimed in any preceding claim, wherein the interface circuit comprises one or more processor registers accessible by the processing circuit and a data compression circuit connected to the interface.

12. The circuit of claim 11, wherein the processing circuit is configured to write at least the identification data to the one or more processor registers and to read at least the status data from the one or more processor registers.

13. A circuit according to any of the preceding claims, the circuit comprising a data memory; wherein the processing circuit is configured to: execute instructions defining a neural network in which processing values ​​are applied to data values; read compressed data defining the processing values ​​from the data memory; provide the compressed data as input data to the interface, and receive decompressed processing values ​​as output data for use by the instructions defining the neural network.

14. A circuit according to any one of claims 1 to 12, wherein the processing circuit is configured to: execute instructions defining a neural network in which processing values ​​are applied to data values; read data defining the processing values ​​from the data memory; provide the data defining the processing values ​​as input data to the interface, and receive compressed processing values ​​as output data.

15. A circuit according to any preceding claim, comprising: A data compression circuit is connected to the interface.

16. A circuit according to any one of the preceding claims, wherein the processing circuit is configured to execute instructions to control the processing circuit to perform processing on the input data when the status data indicates that the data compression circuit cannot use the compression system identified by the identification data to process data.

17. A method comprising: Decode instructions for execution; executing, using processing circuitry, the instruction decoded by the instruction decoding step; defining an interface for data communication with a data compression circuit; In response to one or more instructions in an instruction set defined for the processing circuitry, the processing circuitry provides to the interface: input data, the input data to be processed by the data compression circuitry; and identification data, the identification data identifying a compression system used by the data compression circuit to process the input data; as well as The processing circuit receives from the interface: status data indicating whether a data compression circuit connected to the interface is capable of processing data using the compression system identified by the identification data; And when the status data indicates that the data compression circuit is capable of processing data using the compression system identified by the identification data, output data, the output data having been processed from the input data by the data compression circuit using the compression system identified by the identification data.

18. A virtual machine computer program, the virtual machine computer program comprising instructions for controlling a host data processing device to provide an instruction execution environment, the instruction execution environment comprising: an instruction decoder circuit for decoding instructions for execution; processing circuitry for executing instructions decoded by the instruction decoder circuitry; an interface circuit, the interface circuit defining an interface for data communication with the data compression circuit; wherein the processing circuitry is responsive to one or more instructions in an instruction set defined for the processing circuitry to provide to the interface: input data, the input data to be processed by the data compression circuitry; and identification data, the identification data identifying a compression system used by the data compression circuit to process the input data; and wherein the processing circuit is configured to receive from the interface: status data indicating whether a data compression circuit connected to the interface is capable of processing data using the compression system identified by the identification data; And when the status data indicates that the data compression circuit is capable of processing data using the compression system identified by the identification data, output data, the output data having been processed from the input data by the data compression circuit using the compression system identified by the identification data.

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