Storage circuit structure for liquid spraying device

Abstract

The invention provides a storage circuit structure for a liquid spraying device. The storage circuit structure comprises a plurality of programmable memories; the at least one read-write end is used for reading and writing a plurality of programmable memories; the at least one reading loop is used for controlling the current provided by the read-write end to read the plurality of programmable memories; at least one write loop; and when the write-in actuating end receives the write-in actuating signal, the current provided by the read-write end is written into the plurality of programmable memories through the write-in loop. According to the storage circuit structure for the liquid spraying device in the embodiment of the invention, data can be written into the programmable memory in a user-defined manner according to requirements after a chip is packaged or a product is finished, and the written data is not easy to change, so that the data can be protected.

Description

Technical Field

[0001] The invention relates to the field of inkjet printing, and in particular to a storage circuit structure for a liquid jet device. Background Art

[0002] Inkjet printing is one of the printing technologies with the largest market share in the world. In order to record and distinguish various information, various non-volatile memories (NVM or memory) are set in the ink cartridge or liquid cartridge that provides the ink or liquid required for printing, or in the printing inkjet head and other liquid ejecting devices to identify and record the physical properties, electrical parameters, product model, production serial number, ink capacity, ink consumption, effective time and other information of the liquid cartridge or inkjet head. Figure 1 The prior art described in US Pat. No. 6,019,449 discloses the architecture of various systems in a printer 10, including at least one inkjet head 12 for inkjet printing and an ink cartridge 20 for supplying ink. The inkjet head 12 is provided with a nozzle memory 16, and the ink cartridge 20 is also provided with an ink cartridge memory 28. In actual application, these memories are provided on an additional chip of the ink cartridge, an additional chip of the inkjet head, or directly designed in the inkjet head chip. The printer electronic system and control program 34 in the printer 10 read or write information in the nozzle memory 16 and the ink cartridge memory 28 via the inkjet head signal line 18 and the ink cartridge signal line 22, respectively. Such an architecture has been implemented in various commercially available ink cartridges or inkjet head products for inkjet printing for many years and has been widely used.

[0003] Another application in recent years is external circuit boards containing memory, such as Figure 2A and Figure 2B As shown in the prior art described in US Pat. No. 9,421,783 B2 and US Pat. No. 9,573,378 B2, the technology is to design an external circuit board 42 that meets the electrical specifications of the printer for an inkjet head 12. The external circuit board 42 includes at least one external circuit board chip 43 and a plurality of external circuit board electrical contacts 44. The plurality of external circuit board electrical contacts 44 are aligned and attached to the plurality of inkjet head electrical contacts 45 on the inkjet head 12. After alignment and attachment, Figure 2B As shown, after bonding, the memory in the external circuit board chip 43 replaces the memory in the inkjet head 12, so as to achieve the purpose of updating or replacing the data originally recorded in the memory in the inkjet head 12.

[0004] The aforementioned memory, whether it is located in the ink cartridge, inkjet head, or external circuit board, must be non-volatile. In actual application, there are different non-volatile memories such as Mask Read-Only Memory (hereinafter referred to as Mask ROM or Mask Memory), Programmable Read-Only Memory (hereinafter referred to as PROM or Programmable Memory), or Electrically Programmable Read-Only Memory (hereinafter referred to as EPROM) according to the needs. Mask ROM and PROM are both write-after-break type. Mask ROM uses a mask to determine whether to open or short during the wafer manufacturing stage. The advantage of mask memory is that the component area required is small, and the written data is not easy to be changed or destroyed. It is suitable for data that must be protected. However, the disadvantage is that it can only be written during the wafer manufacturing stage, and cannot be written according to the needs after the product is completed. It lacks flexibility in actual production. Programmable memory is just the opposite. If you want to cut off the circuit after writing, you usually use a fuse-type programmable memory. When writing, current is provided to blow the fuse of the bit to be written. The advantage is that it can be customized according to needs after the chip is packaged or the product is completed. However, the disadvantage is that bits that do not need to be written can still be written or destroyed, and cannot be used for data that must be protected. Summary of the invention

[0005] The present invention provides a storage circuit structure for a liquid spraying device, which can customize data writing according to demand after chip packaging or product completion, and the written data is not easy to be changed, so the data can be protected.

[0006] An embodiment of the present invention provides a storage circuit structure for a liquid injection device, which includes: a plurality of programmable memories; at least one read / write end for reading and writing the plurality of programmable memories; at least one read circuit for controlling the current provided by the read / write end to read the plurality of programmable memories; at least one write circuit; and at least one write actuator end, wherein when the write actuator end receives a write actuator signal, the current provided by the read / write end writes to the plurality of programmable memories via the write circuit.

[0007] According to the aforementioned embodiment of the present invention, the at least one read loop and the at least one write loop are connected in parallel between the read / write end and the plurality of programmable memories.

[0008] According to any of the aforementioned embodiments of the present invention, the at least one read circuit comprises at least one read activation transistor, and the read activation transistor is used to control the read current provided by the read / write terminal.

[0009] According to any of the aforementioned embodiments of the present invention, the read actuation transistor is connected between the read / write end and the plurality of programmable memories, and the read actuation transistor is connected to the read / write end.

[0010] According to any of the aforementioned embodiments of the present invention, the at least one read circuit also includes a pull-down transistor and a voltage divider device, the gate of the read actuation transistor is connected to the read-write end via the voltage divider device, the first electrode of the pull-down transistor is connected to the gate of the read actuation transistor, the second electrode of the pull-down transistor is grounded, and the gate of the pull-down transistor is connected to the read-write end.

[0011] According to any of the aforementioned embodiments of the present invention, the voltage divider device is a load resistor.

[0012] According to any of the aforementioned embodiments of the present invention, the voltage divider device is a load transistor, a first electrode of the load transistor is connected to the gate of the read actuation transistor, and a second electrode and the gate of the load transistor are connected to the read / write end.

[0013] According to any of the aforementioned embodiments of the present invention, the at least one write circuit includes at least one write actuation transistor, and the write actuation transistor is turned on by a write actuation signal from the write actuation end, so that a write current provided by the read / write end passes through.

[0014] According to any of the aforementioned embodiments of the present invention, the at least one write circuit also includes at least one write actuation end load resistor, the write actuation transistor is connected between the read-write end and the multiple programmable memories, the gate of the write actuation transistor is connected to the write actuation end, one end of the write actuation end load resistor is connected to the gate of the write actuation transistor, and the other end is grounded.

[0015] According to any of the aforementioned embodiments of the present invention, when the read / write end receives a read current, the write actuator end is configured to be grounded or receive a low potential signal.

[0016] According to an embodiment of the present invention, the storage circuit structure for a liquid spraying device includes at least one read circuit, at least one write circuit and at least one write actuator. When it is necessary to write to multiple programmable memories, the write actuator receives a write actuator signal, and the current provided by the read / write terminal writes to the multiple programmable memories through the write circuit. When it is necessary to read multiple programmable memories, the write actuator no longer receives a write actuator signal, and the current provided by the read / write terminal reads the multiple programmable memories through the read circuit. The storage circuit structure of the liquid spraying device can customize the writing of data to the programmable memory as needed after the chip is packaged or the product is completed, and the data is not easy to be changed after it has been written, so the data can be protected. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0018] Figure 1 is a schematic diagram of the system architecture of a printer;

[0019] Figure 2A It is an application diagram of an external circuit board containing a memory being aligned and attached in front of an inkjet head;

[0020] Figure 2B It is an application diagram after an external circuit board containing a memory is aligned and attached to an inkjet head;

[0021] Figure 3 It is a schematic diagram of a mask storage circuit structure for spraying a liquid crystal sheet in the related art;

[0022] Figure 4 It is a schematic diagram of a programmable storage circuit structure of a liquid crystal chip in another related technology;

[0023] Figure 5 is a schematic diagram of a programmable storage circuit structure according to an embodiment of the present invention;

[0024] Figure 6 FIG. 4 is a schematic diagram of a programmable storage circuit structure according to another embodiment of the present invention.

[0025] Description of reference numerals:

[0026] 10: Printer

[0027] 12: Inkjet head

[0028] 16: Nozzle memory

[0029] 18: Inkjet head signal line

[0030] 20: Cartridge

[0031] 22: Ink cartridge signal line

[0032] 24: Ink supply pipeline

[0033] 28: Cartridge Memory

[0034] 34: Printer electronic system and control program

[0035] 36: Computer host

[0036] 42: External circuit board

[0037] 43: External circuit board chip

[0038] 44: External circuit board electrical contacts

[0039] 45: Inkjet head electrical contacts

[0040] 50a: Open mask memory cell

[0041] 50b: Link mask memory cell

[0042] 51: Mask memory array

[0043] 53: The first transistor

[0044] 54: First logic gate

[0045] 56a: Circuit breaker

[0046] 56b: Link element

[0047] 58: Input terminal first group

[0048] 59: Input terminal second group

[0049] 60: Mask memory reading end

[0050] 66: Fuse programmable memory cell

[0051] 67: Fuse Programmable Memory Array

[0052] 68: Second transistor

[0053] 69: Second logic gate

[0054] 70: Second fuse

[0055] 72: Input terminal third group

[0056] 73: Input terminal group 4

[0057] 74: Fuse programmable memory read and write terminal

[0058] 80: Programmable memory

[0059] 81: Programmable Memory Array

[0060] 82: Transistor

[0061] 83: Logic Gates

[0062] 84: Fuse

[0063] 85: First input component

[0064] 86: Second input component

[0065] 87: Read and write end

[0066] 88: Write loop

[0067] 89: Reading loop

[0068] 90: Write current

[0069] 91: Read current

[0070] 92: Write-actuated transistor

[0071] 93: Write to the actuator end

[0072] 94: Write the actuator load resistance

[0073] 95: Write actuation signal

[0074] 96: Reading the Actuation Transistor

[0075] 97: Low transistor

[0076] 98: Load resistance

[0077] 99: Load transistor

[0078] The purpose, features and advantages of the present invention will be further described in conjunction with the embodiments and with reference to the accompanying drawings.

[0079] illustrate. DETAILED DESCRIPTION

[0080] Embodiments for realizing the features and advantages of the present invention will be described in detail in the following paragraphs. It should be understood that the present invention can be modified in different forms without departing from the scope of the present invention. The descriptions and illustrations are only provided for illustrative purposes to facilitate understanding and are not intended to limit the scope of protection of the present application.

[0081] Before describing the embodiments of the present invention, a storage circuit structure for a liquid ejecting device in the related art is described first. Figure 3 The present invention is a schematic diagram of a mask memory circuit structure of a liquid crystal film in a related art. The mask memory circuit structure is composed of a disconnected mask memory unit 50a and a connected mask memory unit 50b to form a mask memory array 51. Both the disconnected mask memory unit 50a and the connected mask memory unit 50b include a first transistor 53 and a first logic gate 54. In addition to being a switch, the first transistor 53 also provides the required current or loop resistance. The purpose of the first logic gate 54 is to increase the control selection. The biggest difference between the disconnected mask memory unit 50a and the connected mask memory unit 50b is that the disconnected mask memory unit 50a includes a disconnected element 56a, while the connected mask memory unit 50b includes a connected element 56b. The simplest manufacturing method is to use a wire in a wafer process. The disconnected element 56a is designed as an open circuit or disconnected circuit in the mask design, and the connected element 56b is designed as a wire connection in the mask design. The mask memory array 51 composed of the disconnection mask memory unit 50a and the connection mask memory unit 50b preferably uses at least two groups of input terminal groups, such as Figure 3 As shown in the first group of input terminals 58 (a total of n input terminals from A1 to An), and the second group of input terminals 59 (B(j), j=1 to m, a total of m input terminals), the high potential end of the mask memory array 51 can be designed to be connected in parallel to the mask memory reading terminal 60. The printer system can read or detect from the mask memory reading terminal 60 whether each bit of the mask memory is open or connected.

[0082] Depend on Figure 3 As shown and described above, the mask memory array 51 is defined as open circuit or connected circuit during wafer manufacturing, so its characteristic is that its data is determined during the wafer manufacturing stage. The advantage is that the data can be protected from being changed, but the disadvantage is that it cannot be written after the chip is packaged or the product is completed.

[0083] Figure 4 It is a schematic diagram of a programmable storage circuit structure of a liquid crystal chip in another related technology. Figure 4The figure shows a circuit diagram of a fuse programmable read-only memory (Fuse PROM, hereinafter referred to as programmable memory) commonly used in a known inkjet liquid crystal chip. In the fuse programmable read-only memory, a fuse programmable memory array 67 is composed of a plurality of fuse programmable memory cells 66. Each fuse programmable memory cell 66 includes a second transistor 68, a second logic gate 69 and a second fuse 70. The second transistor 68 is used as a switch and also provides the required current or loop resistance. The purpose of the second logic gate 69 is to increase the control selection. If the design purpose is to burn the circuit to be broken when the current passes, the second fuse 70 is a fusible conductor. Usually, the conductor is a thinner wire of a conductor layer in wafer manufacturing. Preferably, one control terminal of the second logic gate 69 in each fuse programmable memory cell 66 is connected to each input terminal in the third input terminal group 72, and the other control terminal is connected to one of the input terminals of the fourth input terminal group 73, so as to form a two-dimensional array to obtain more bits. The high potential end of the fuse programmable memory array 67 can be designed to be connected in parallel to the fuse programmable memory read / write end 74. The printer system can read or detect from the fuse programmable memory read / write end 74 whether each bit of the fuse programmable memory is open or connected.

[0084] The big difference between this fuse programmable memory and mask memory is that mask memory only needs to be read, while fuse programmable memory needs to be written in addition to reading. Figure 4 The reading (Read) and writing (Write) shown are performed at the same end. The voltage or current input for reading and writing must differ by more than 5 times. In order to avoid damaging the fuse, a small current or voltage is used during reading. In order to blow the fuse during writing, a large current or voltage must be used instantly. During writing, in order to have a large enough current in the fuse programmable memory cell 66, the channel width-to-length ratio (ChannelW / L) of the second transistor 68 must be designed to be much larger than the first transistor 53 of the mask memory cell, or the second fuse 70 and the second transistor 68 must be designed to have a low enough loop resistance, so that the second fuse 70 can be blown correctly during writing and become the written bit; while during reading, because the fuse and transistor loop resistance of the fuse programmable memory is low, it is necessary to ensure that the current passing through the second fuse 70 of the unwritten bit is small enough to avoid damaging the unwritten bit.

[0085] The present invention provides a storage circuit structure for a liquid spraying device, which has the dual advantages of being able to be written after chip packaging or product completion like a fuse programmable memory, and being able to protect unwritten bits from subsequent damage like a mask memory.

[0086] Figure 5Schematic diagram of a programmable storage circuit structure of an embodiment of the present invention. The storage circuit structure for a liquid jet device includes a plurality of programmable memories 80, at least one read / write terminal 87, at least one read circuit 89, at least one write circuit 88, and at least one write actuator terminal 93.

[0087] At least one read / write terminal 87 is used to read and write multiple programmable memories 80. At least one read circuit 89 is used to control the current provided by the read / write terminal 87 to read multiple programmable memories 80. When the write actuator terminal 93 receives a write actuator signal, the current provided by the read / write terminal 87 writes to the multiple programmable memories 80 via the write circuit 88.

[0088] According to the storage circuit structure for the liquid spraying device of the embodiment of the present invention, it includes at least one read circuit 89, at least one write circuit 88 and at least one write actuator 93. When it is necessary to write to multiple programmable memories 80, the write actuator 93 receives the write actuator signal, and the current provided by the read / write terminal 87 writes to the multiple programmable memories 80 through the write circuit 88. When it is necessary to read multiple programmable memories, the write actuator 93 no longer receives the write actuator signal, and the current provided by the read / write terminal 87 reads the multiple programmable memories 80 through the read circuit 89. The storage circuit structure of the liquid spraying device can customize the writing of data to the programmable memory 80 according to the needs after the chip is packaged or the product is completed, and the written data is not easy to be changed, so the data can be protected.

[0089] In this embodiment, a programmable memory array 81 including a plurality of programmable memories 80 is used. The programmable memory 80 also includes a transistor 82, a logic gate 83, a fuse 84, a first input component 85, a second input component 86, etc. Different from the mask memory read terminal 60 and the programmable memory read / write terminal 74 in the related art, in the embodiment of the present invention, the memory read / write terminal 87 for the printing device is connected in parallel with two electrical circuits: a write circuit 88 and a read circuit 89. The write circuit 88 provides a relatively large current to write or fuse each programmable memory 80 (hereinafter referred to as the write current (I Write ) 90), the read circuit 89 provides a small current to detect whether each programmable memory 80 is disconnected or connected (hereinafter referred to as the read current (I Read )91).

[0090] That is, in this embodiment, a plurality of programmable memories 80 form a programmable memory array 81. Each programmable memory 80 includes a transistor 82, a logic gate 83, and a fuse 84. The storage circuit structure for the liquid jet device may include a first input component 85 and a second input component 86. The first input component 85 and the second input component 86 each include a plurality of input terminals. In the figure, the first input component 85 includes a total of n input terminals from A1 to An, and the second input component 86 is B(j), where j=1 to m, that is, the second input component includes a total of m input terminals.

[0091] The logic gate 83 is used to increase the control options. One control terminal of the logic gate 83 in each programmable memory 80 is connected to each input terminal in the first input component 85, and the other control terminal is connected to one of the input terminals of the second input component 86, thereby forming more bits. In each programmable memory 80, the first electrode of the transistor 82 is grounded, and the second electrode of the transistor 82 is connected to the read loop 89 and the write loop 88 through the fuse 84, and the fuse 84 can be blown. The fuse 84 is, for example, a thinner wire in a conductor layer in wafer manufacturing. In addition to being a switch, the transistor 82 also provides the appropriate current or loop resistance.

[0092] In this embodiment, at least one read circuit 89 and at least one write circuit 88 are connected in parallel between the read / write terminal 87 and the plurality of programmable memories 80 .

[0093] In some embodiments, at least one write circuit 88 includes at least one write-actuated transistor 92 . The write-actuated transistor 92 is turned on by a write-actuated signal from a write-actuated terminal 93 , so that a write current provided by the read / write terminal 87 passes through the transistor.

[0094] In some embodiments, at least one write circuit 88 further includes at least one write actuation load resistor (R WE )94, a write-actuated transistor 92 is connected between the read-write terminal 87 and a plurality of programmable memories 80, a gate of the write-actuated transistor 92 is connected to a write-actuated terminal 93, one end of a write-actuated terminal load resistor 94 is connected to the gate of the write-actuated transistor 92, and the other end is grounded.

[0095] When the read / write terminal 87 receives a read current, the write actuator terminal 93 is configured to be grounded or receive a low potential signal.

[0096] like Figure 5As shown, in the embodiment of the present invention, both the write current 90 and the read current 91 are still provided by the memory read / write terminal 87. In order to ensure that the write current 90 can enter the programmable memory array 81 only during the writing time, the write circuit 88 includes a write activation transistor 92, and a write activation terminal 93 is connected to the gate of the write activation transistor 92. Preferably, a write activation terminal load resistor (R WE ) 94 to ensure that the input voltage received by the write-actuation terminal 93 can mostly fall on the gate terminal of the write-actuation transistor 92. When the write-actuation terminal 93 receives a sufficiently large input voltage (i.e., the activation signal 95) to turn on the write-actuation transistor 92, the write current 90 can be transmitted to the programmable memory array 81 through the write loop 88.

[0097] In some embodiments, at least one read circuit 89 includes at least one read-activation transistor 96 , and the read-activation transistor 96 is used to control the read current provided by the read / write terminal 87 .

[0098] In some embodiments, the read-actuated transistor 96 is connected between the read-write terminal 87 and the plurality of programmable memories 80, and the read-actuated transistor 96 is connected to the read-write terminal 87. Specifically, the read-actuated transistor 96 is connected between the read-write terminal 87 and the plurality of programmable memories 80, and the gate of the read-actuated transistor 96 is connected to the read-write terminal 87. The gate of the read-actuated transistor 96 may be directly connected to the read-write terminal 87 or indirectly connected.

[0099] For example, in some embodiments, the gate of the read-enable transistor 96 is directly connected to the read / write terminal 87 .

[0100] In some embodiments, at least one read circuit 89 also includes a pull-low transistor 97 and a voltage divider device, the gate of the read actuator transistor 96 is connected to the read-write terminal 87 via the voltage divider device, the first electrode of the pull-low transistor 97 is connected to the gate of the read actuator transistor 96, the second electrode of the pull-low transistor 97 is grounded, and the gate of the pull-low transistor 97 is connected to the read-write terminal 87.

[0101] In some embodiments, the voltage divider device is a load resistor (R RL )98.

[0102] The read circuit 89 includes a read activation transistor 96. When the read / write terminal 87 is reading, the write activation terminal 93 of the write circuit 88 is grounded or at a low potential, so that the write activation transistor 92 is turned off, and the write circuit 88 becomes an open circuit. At this time, the current only passes through the read circuit 89. In addition, there are two major differences between the write activation transistor 92 and the read activation transistor 96: (1) the channel width / length ratio W / L of the write activation transistor 92 needs to be increased to provide a larger write current; (2) the write activation transistor 92 needs to operate in the linear region because it requires a large instantaneous current, while the read activation transistor 96 needs to operate in the saturated region to limit the current because it needs to protect the programmable memory array 81. In order to ensure that the read activation transistor 96 operates in the saturated region, the gate terminal of the read activation transistor 96 is connected to a pull-low transistor 97 and a load resistor (R RL ) 98 to divide the voltage. Preferably, the channel width-length ratio W / L of the low-power transistor 97 should be designed to be smaller than that of the read-actuated transistor 96, or the low-power transistor 97 uses a higher threshold voltage, which is another preferred method. These designs are designed to meet the requirements of low voltage reading and high voltage writing at the read-write end 87: As mentioned above, the read-actuated transistor 96 needs to work in the saturation region. The read current 91 entering the programmable memory array 81 through the read-actuated transistor 96 is as follows: This type V G To read the gate voltage of the actuator transistor 96, firstly, when the read / write terminal 87 is read with a small voltage, the gate terminal of the actuator transistor 97 is also affected by the small voltage and presents a higher impedance or even a disconnection. The read small voltage can start the actuator transistor 96 to work in the saturation region. Secondly, when the memory read / write terminal 87 is written with a large voltage, the gate terminal of the actuator transistor 97 is also affected by the large voltage and presents a low impedance. At this time, the gate voltage V G The voltage can be maintained at a low voltage due to the low impedance of the low-impedance transistor 97 and the voltage division of the load resistor 98, so that the read-actuation transistor 96 cannot provide a large current, thereby protecting the programmable memory array 81. Only when the write-actuation terminal 93 receives a write-actuation signal 95 with a sufficient voltage to turn on the write-actuation transistor 92 can the programmable memory array 81 be written or changed, thereby protecting the data in the programmable memory array 81.

[0103] Figure 61 is a schematic diagram of a programmable storage circuit structure of another embodiment of the present invention. Part of the structure of the other embodiment is the same as that of the aforementioned embodiment. The differences between the two will be described below, and the similarities will not be described in detail. In this embodiment, the voltage divider device is a load transistor 99, a first electrode of the load transistor 99 is connected to the gate of the read-actuating transistor 96, and a second electrode and the gate of the load transistor 99 are connected to the read-write terminal 87.

[0104] Figure 6 Compared with the embodiment Figure 5 In the embodiment involved, a load transistor 99 replaces the original load resistor 98. The load transistor 99 is designed to be a transistor with a longer channel. The desired voltage division of the gate terminal of the read-actuated transistor 96 is achieved by adjusting the channel width-to-length ratio W / L between the pull-down transistor 97 and the load transistor 99. The advantage of such a design is that the pull-down transistor 97 and the load transistor 99 used for voltage division can be manufactured in the same wafer manufacturing process, and the voltage division obtained at the gate terminal of the read-actuated transistor 96 is more accurate.

[0105] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A storage circuit structure for a liquid spraying device, characterized in that: include: Multiple programmable memories; At least one read / write terminal for reading and writing the plurality of programmable memories; At least one read circuit, used to control the current provided by the read / write terminal to read the plurality of programmable memories; at least one write circuit; At least one write-actuation end, when the write-actuation end receives a write-actuation signal, the current provided by the read-write end writes into the plurality of programmable memories via the write loop.

2. The storage circuit structure for a liquid ejecting device according to claim 1, characterized in that: The at least one read loop and the at least one write loop are connected in parallel between the read / write end and the plurality of programmable memories.

3. The storage circuit structure for a liquid ejecting device according to claim 1, characterized in that: The at least one read circuit includes at least one read activation transistor, and the read activation transistor is used to control a read current provided by the read / write terminal.

4. The storage circuit structure for a liquid ejecting device according to claim 3, characterized in that: The read actuation transistor is connected between the read / write terminal and the plurality of programmable memories, and the read actuation transistor is connected to the read / write terminal.

5. The storage circuit structure for a liquid ejecting device according to claim 4, characterized in that: The at least one read circuit also includes a pull-down transistor and a voltage divider device, the gate of the read actuation transistor is connected to the read-write end via the voltage divider device, the first electrode of the pull-down transistor is connected to the gate of the read actuation transistor, the second electrode of the pull-down transistor is grounded, and the gate of the pull-down transistor is connected to the read-write end.

6. The storage circuit structure for a liquid ejecting device according to claim 5, characterized in that: The voltage divider device is a load resistor.

7. The storage circuit structure for a liquid ejecting device according to claim 5, characterized in that: The voltage divider device is a load transistor, a first electrode of the load transistor is connected to the gate of the read actuation transistor, and a second electrode and the gate of the load transistor are connected to the read / write end.

8. The storage circuit structure for a liquid ejecting device according to claim 1, characterized in that: The at least one write circuit includes at least one write activation transistor. The write activation transistor is turned on by a write activation signal from the write activation end, so that a write current provided by the read / write end passes through.

9. The storage circuit structure for a liquid ejecting device according to claim 8, characterized in that: The at least one write circuit also includes at least one write actuation end load resistor, the write actuation transistor is connected between the read-write end and the multiple programmable memories, the gate of the write actuation transistor is connected to the write actuation end, one end of the write actuation end load resistor is connected to the gate of the write actuation transistor, and the other end is grounded.

10. The storage circuit structure for a liquid ejecting device according to claim 8, characterized in that: When the read / write end receives a read current, the write actuation end is configured to be grounded or receive a low potential signal.

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