Storage circuit structure for liquid spraying device

Abstract

This invention provides a storage circuit structure for a liquid spraying device, comprising: a plurality of programmable memories; at least one read / write terminal for reading and writing to the plurality of programmable memories; at least one read circuit for controlling the current provided by the read / write terminal to read the plurality of programmable memories; at least one write circuit; and at least one write actuation terminal, wherein when the write actuation terminal receives a write actuation signal, the current provided by the read / write terminal writes to the plurality of programmable memories via the write circuit. According to the storage circuit structure for a liquid spraying device of this invention, data can be customized and written to the programmable memories as needed after chip packaging or product completion, and the data, once written, is not easily altered, thus protecting the data.

Description

Technical Field

[0001] This invention relates to the field of inkjet printing, and in particular to a storage circuit structure for an inkjet printing device. Background Technology

[0002] Inkjet printing is one of the world's largest printing technologies in terms of market share. In order to record and distinguish various information, non-volatile memory (NVM or memory) is set in ink cartridges or liquid tanks that provide the ink or liquid required for printing, or in inkjet heads and other liquid ejection devices. This memory is used to identify and record information such as the physical and electrical parameters of the liquid tank or inkjet head, product model, production serial number, ink capacity, ink consumption, and effective time. Figure 1 The prior art described in US Patent 6019449 discloses the architecture of various systems within a printer 10, including at least one inkjet head 12 responsible for inkjet printing and an ink cartridge 20 supplying ink. The inkjet head 12 contains a printhead memory 16, and the ink cartridge 20 also contains an ink cartridge memory 28. In practical applications, these memories are located on an external chip in the ink cartridge, on an external chip in the inkjet head, or directly designed into the inkjet head chip. The printer electronics system and control program 34 within the printer 10 read or write information in the printhead memory 16 and the ink cartridge memory 28 via the printhead signal line 18 and the ink cartridge signal line 22, respectively. This architecture has been implemented in various commercially available inkjet printing cartridges or printhead products for many years and is widely used.

[0003] Another application in recent years is the use of external circuit boards containing memory, such as... Figure 2A and Figure 2B As shown, the prior art described in US patents US9421783B2 and US9573378B2 involves designing an external circuit board 42 conforming to printer electrical specifications for an inkjet head 12. The external circuit board 42 includes at least one external circuit board chip 43 and multiple external circuit board electrical contacts 44. These multiple external circuit board electrical contacts 44 are aligned and bonded to multiple inkjet head electrical contacts 45 on the inkjet head 12. After alignment and bonding, as... Figure 2B As shown, after bonding, the memory in the external circuit board chip 43 replaces the memory in the inkjet head 12, which can achieve the purpose of updating or replacing the data originally recorded in the memory in the inkjet head 12.

[0004] The aforementioned memory, whether located in ink cartridges, inkjet heads, or external circuit boards, must be non-volatile. In practical applications, depending on the requirements, different types of non-volatile memory may be used, such as Mask Read-Only Memory (hereinafter referred to as Mask ROM), Programmable Read-Only Memory (hereinafter referred to as PROM), or Electrically Programmable Read-Only Memory (EPROM). Both Mask ROM and PROM are write-on-demand (COP) type. Because Mask ROM uses a photomask to determine whether the circuit is open or short during the wafer manufacturing stage, its advantages are that the component requires a small area and the written data is not easily altered or destroyed, making it suitable for data that must be protected. However, its disadvantage is that it can only be written during the wafer manufacturing stage and cannot be written as needed after the product is completed, which greatly limits its flexibility in actual production. In contrast, programmable memory typically uses fuse-based programmable memory to ensure that the bit to be written is open-circuit after being written. When writing, current is supplied to burn the fuse of the bit to be written. The advantage is that it can be customized to be written after chip packaging or product completion. However, the disadvantage is that bits that do not need to be written can still be written or destroyed, and it cannot be used for data that must be protected. Summary of the Invention

[0005] This invention provides a storage circuit structure for a liquid spraying device, which allows for custom data writing as needed after chip packaging or product completion, and the data is not easily changed after it has been written, thus protecting the data.

[0006] This invention provides a storage circuit structure for a liquid spraying device, comprising: a plurality of programmable memories; at least one read / write terminal for reading and writing the plurality of programmable memories; at least one read circuit for controlling the current provided by the read / write terminal to read the plurality of programmable memories; at least one write circuit; and at least one write actuation terminal, wherein when the write actuation terminal receives a write actuation signal, the current provided by the read / write terminal writes to the plurality of programmable memories through the write circuit.

[0007] According to the foregoing embodiments of the present invention, the at least one read circuit and the at least one write circuit are connected in parallel between the read / write terminal and the plurality of programmable memories.

[0008] According to any of the foregoing embodiments of the present invention, the at least one read circuit includes at least one read actuation transistor, which is used to control the read current provided by the read / write terminal.

[0009] According to any of the foregoing embodiments of the present invention, the read actuation transistor is connected between the read / write terminal and the plurality of programmable memories, and the read actuation transistor is connected to the read / write terminal.

[0010] According to any of the foregoing embodiments of the present invention, the at least one read circuit further includes a low-level transistor and a voltage divider device, the gate of the read actuation transistor is connected to the read / write terminal via the voltage divider device, the first terminal of the low-level transistor is connected to the gate of the read actuation transistor, the second terminal of the low-level transistor is grounded, and the gate of the low-level transistor is connected to the read / write terminal.

[0011] According to any of the foregoing embodiments of the present invention, the voltage divider device is a load resistor.

[0012] According to any of the foregoing embodiments of the present invention, the voltage divider device is a load transistor, the first terminal of the load transistor is connected to the gate of the read actuation transistor, and the second terminal and the gate of the load transistor are connected to the read / write terminal.

[0013] According to any of the foregoing embodiments of the present invention, the at least one write circuit includes at least one write actuation transistor, which is turned on by a write actuation signal from the write actuation terminal, so that a write current provided by the read / write terminal passes through.

[0014] According to any of the foregoing embodiments of the present invention, the at least one write circuit further includes at least one write actuation load resistor, the write actuation transistor is connected between the read / write terminal and the plurality of programmable memories, the gate of the write actuation transistor is connected to the write actuation terminal, one end of the write actuation load resistor is connected to the gate of the write actuation transistor, and the other end is grounded.

[0015] According to any of the foregoing embodiments of the present invention, when the read / write terminal receives a read current, the write actuation terminal is configured to be grounded or receive a low-potential signal.

[0016] According to an embodiment of the present invention, a storage circuit structure for a liquid spraying device includes at least one read circuit, at least one write circuit, and at least one write actuation terminal. When writing to multiple programmable memories is required, the write actuation terminal receives a write actuation signal, and the current provided by the read / write terminal writes to the multiple programmable memories through the write circuit. When reading from multiple programmable memories is required, the write actuation terminal no longer receives a write actuation signal, and the current provided by the read / write terminal reads from the multiple programmable memories through the read circuit. The above-described storage circuit structure for a liquid spraying device allows for custom data writing to the programmable memories as needed after chip packaging or product completion, and the written data is not easily altered, thus protecting the data. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a printer's system architecture.

[0019] Figure 2A This is an application illustration of an external circuit board containing a memory being aligned and bonded to the inkjet head.

[0020] Figure 2B This is an application illustration showing an external circuit board containing memory being aligned and bonded to an inkjet head.

[0021] Figure 3 This is a schematic diagram of a mask storage circuit structure for liquid crystal film spraying in a related technology;

[0022] Figure 4 This is a schematic diagram of a programmable storage circuit structure for liquid crystal wafers in another related technology;

[0023] Figure 5 This is a schematic diagram of a programmable memory circuit structure according to an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of a programmable storage circuit structure according to another embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures:

[0026] 10: Printer

[0027] 12: Inkjet head

[0028] 16: Nozzle memory

[0029] 18: Inkjet head signal cable

[0030] 20: Ink cartridge

[0031] 22: Ink cartridge signal cable

[0032] 24: Ink supply pipeline

[0033] 28: Ink cartridge storage

[0034] 34: Printer electronic systems and control programs

[0035] 36: Computer host

[0036] 42: External circuit board

[0037] 43: External circuit board chip

[0038] 44: External circuit board electrical contacts

[0039] 45: Inkjet head electrical contacts

[0040] 50a: Circuit Breaker Mask Memory Unit

[0041] 50b: Link Mask Memory Unit

[0042] 51: Mask Memory Array

[0043] 53: First transistor

[0044] 54: First Logic Gate

[0045] 56a: Circuit breaker element

[0046] 56b: Connecting element

[0047] 58: Input Terminal First Group

[0048] 59: Input Terminal Second Group

[0049] 60: Mask memory read end

[0050] 66: Fuse-programmable memory unit

[0051] 67: Fuse-programmable memory array

[0052] 68: Second transistor

[0053] 69: Second Logic Gate

[0054] 70: Second fuse

[0055] 72: Input Terminal Third Group

[0056] 73: Input terminal fourth group

[0057] 74: Fuse-programmable memory read / write terminal

[0058] 80: Programmable memory

[0059] 81: Programmable Memory Array

[0060] 82: Transistor

[0061] 83: Logic Gates

[0062] 84: Fuse

[0063] 85: First Input Component

[0064] 86: Second Input Component

[0065] 87: Reading and writing terminal

[0066] 88: Write loop

[0067] 89: Reading loop

[0068] 90: Write current

[0069] 91: Reading the current

[0070] 92: Writing to the actuation transistor

[0071] 93: Write to the actuator

[0072] 94: Write the load resistor to the actuator terminal

[0073] 95: Write the actuation signal

[0074] 96: Reading the actuation transistor

[0075] 97: Low-power transistor

[0076] 98: Load resistance

[0077] 99: Load transistor

[0078] The realization of the objective, functional features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0079] illustrate. Detailed Implementation

[0080] Embodiments that realize the features and advantages of the present invention will be described in detail in the following paragraph. It should be understood that the present invention can be modified in different ways without departing from the scope of the present invention. The descriptions and illustrations therein are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0081] Before describing the embodiments of the present invention, the storage circuit structure for a liquid spraying device in the related art will be described first. Figure 3 This is a schematic diagram of a mask memory circuit structure for spraying liquid crystal wafers in a related technology. The mask memory circuit structure consists of a mask memory array 51 composed of open-circuit mask memory cells 50a and interconnect mask memory cells 50b. Both open-circuit mask memory cells 50a and interconnect mask memory cells 50b include a first transistor 53 and a first logic gate 54. The first transistor 53, in addition to acting as a switch, also provides the appropriate current or loop resistance. The first logic gate 54 aims to increase control selectivity. The biggest difference between open-circuit mask memory cells 50a and interconnect mask memory cells 50b is that open-circuit mask memory cells 50a contain open-circuit elements 56a, while interconnect mask memory cells 50b contain interconnect elements 56b. The simplest manufacturing method is to use wires in a wafer fabrication process. The open-circuit element 56a is patterned as an open circuit or a broken circuit in the photomask design, while the interconnect element 56b is patterned as a wire connection in the photomask design. The mask memory array 51, composed of open-circuit mask memory cells 50a and interconnect mask memory cells 50b, preferably employs at least two groups of input terminals, such as... Figure 3 The first group of input terminals 58 (n input terminals from A1 to An) and the second group of input terminals 59 (m input terminals from B(j), j=1 to m) are shown. The high-potential terminal of the mask memory array 51 can be designed to be connected in parallel to the mask memory read terminal 60. The printer system can read or detect whether each bit of the mask memory is open or connected from this mask memory read terminal 60.

[0082] Depend on Figure 3 As shown and as described above, the mask memory array 51 is defined as either open or connected during wafer fabrication. Therefore, its data is determined during the wafer fabrication stage. The advantage is that the data can be protected from being changed, but the disadvantage is that it cannot be written after chip packaging or product completion.

[0083] Figure 4 This is a schematic diagram of a programmable memory circuit structure for a liquid crystal display (LCD) in another related technology. Figure 4The diagram shows a circuit diagram of a fuse-based programmable read-only memory (FROM, hereinafter referred to as programmable memory) commonly used in known liquid crystal displays. In the fuse-based programmable read-only memory, a fuse-based programmable memory array 67 is composed of multiple fuse-based programmable memory cells 66. Each fuse-based programmable memory cell 66 includes a second transistor 68, a second logic gate 69, and a second fuse 70. The second transistor 68 acts as a switch and also provides the appropriate current or loop resistance. The purpose of the second logic gate 69 is to increase control selection. If the design purpose is to burn out the circuit when current flows through it, the second fuse 70 is a fusible conductor, typically a thin wire made from a conductor layer in wafer fabrication. Preferably, one control terminal of the second logic gate 69 in each fuse-based programmable memory cell 66 is connected to each input terminal in the third group 72 of input terminals, and the other control terminal is connected to one of the input terminals in the fourth group 73 of input terminals, forming a two-dimensional array to obtain a larger number of bits. The high-potential terminal of the fuse programmable memory array 67 can be designed to be connected in parallel to the fuse programmable memory read / write terminal 74. The printer system can read or detect from this fuse programmable memory read / write terminal 74 whether each bit of the fuse programmable memory is open or connected.

[0084] A significant difference between this type of fuse-programmable memory and mask memory is that mask memory only requires reading, while fuse-programmable memory requires both reading and writing. Generally speaking, if... Figure 4 The read and write operations shown are performed on the same terminal. The voltage or current input for reading and writing must differ by more than five times. During reading, a small current or voltage is used to avoid damaging the fuse. During writing, a large current or voltage is required instantaneously to burn the fuse. During writing, in order to have a sufficiently large current, the channel width-to-length ratio (CW / L) of the second transistor 68 in the fuse-programmable memory cell 66 must be designed to be much larger than that of the first transistor 53 in the mask memory cell, or it must be designed to have a sufficiently low circuit resistance between the second fuse 70 and the second transistor 68, so that the second fuse 70 can be burned correctly during writing, becoming the bit to be written. During reading, however, because the fuse and transistor circuit resistance of the fuse-programmable memory are low, it is necessary to ensure that the current through the second fuse 70 of the unwritten bit is small enough to avoid damaging the unwritten bit.

[0085] This invention provides a storage circuit structure for a liquid spraying device, which has the dual advantages of allowing writing to be performed after chip packaging or product completion, similar to a fuse programmable memory, and protecting unwritten bits from subsequent damage, similar to a mask memory.

[0086] Figure 5This is a schematic diagram of a programmable storage circuit structure according to an embodiment of the present invention. The storage circuit structure for the liquid spraying device includes a plurality of programmable memories 80, at least one read / write terminal 87, at least one read circuit 89, at least one write circuit 88, and at least one write actuation terminal 93.

[0087] At least one read / write terminal 87 is used to read and write multiple programmable memories 80. At least one read circuit 89 is used to control the current supplied by the read / write terminal 87 to read the multiple programmable memories 80. When the write actuation terminal 93 receives a write actuation signal, the current supplied by the read / write terminal 87 writes to the multiple programmable memories 80 through the write circuit 88.

[0088] According to an embodiment of the present invention, a storage circuit structure for a liquid spraying device includes at least one read circuit 89, at least one write circuit 88, and at least one write actuation terminal 93. When writing to multiple programmable memories 80 is required, the write actuation terminal 93 receives a write actuation signal, and the current provided by the read / write terminal 87 writes to the multiple programmable memories 80 through the write circuit 88. When reading from multiple programmable memories is required, the write actuation terminal 93 no longer receives a write actuation signal, and the current provided by the read / write terminal 87 reads from the multiple programmable memories 80 through the read circuit 89. The above-described storage circuit structure for a liquid spraying device allows for custom data writing to the programmable memories 80 as needed after chip packaging or product completion, and the data, once written, is not easily altered, thus protecting the data.

[0089] In this embodiment, a programmable memory array 81 comprising multiple programmable memories 80 is used. Each programmable memory 80 also includes transistors 82, logic gates 83, a fuse 84, a first input component 85, and a second input component 86, etc. Unlike the mask memory read terminal 60 and programmable memory read / write terminal 74 in related technologies, in this embodiment, the memory read / write terminal 87 for the printing apparatus has two electrical circuits connected in parallel: a write circuit 88 and a read circuit 89. The write circuit 88 provides a larger current to write to or burn each programmable memory 80 (hereinafter referred to as the write current (I0)). Write )90), the read circuit 89 provides a small current to detect whether each programmable memory 80 is open or closed (hereinafter referred to as the read current (I)). Read )91).

[0090] That is, in this embodiment, multiple programmable memories 80 form a programmable memory array 81. Each programmable memory 80 includes a transistor 82, a logic gate 83, and a fuse 84. The storage circuit structure for the liquid spraying device may include a first input component 85 and a second input component 86. The first input component 85 and the second input component 86 each include multiple input terminals. In the figure, the first input component 85 includes n input terminals from A1 to An, and the second input component 86 is B(j), where j = 1 to m, that is, the second input component includes a total of m input terminals.

[0091] Logic gate 83 is used to increase control selection. One control terminal of logic gate 83 in each programmable memory 80 is connected to each input terminal in the first input component 85, and the other control terminal is connected to one input terminal of the second input component 86, thus forming more bits. In each programmable memory 80, the first terminal of transistor 82 is grounded, and the second terminal of transistor 82 is connected to the read circuit 89 and the write circuit 88 via fuse 84, which is fusible. Fuse 84 is, for example, a thin wire in a conductor layer during wafer fabrication. Transistor 82 acts as a switch and also provides the appropriate required current or loop resistance.

[0092] In this embodiment, at least one read circuit 89 and at least one write circuit 88 are connected in parallel between the read / write terminal 87 and the plurality of programmable memories 80.

[0093] In some embodiments, at least one write circuit 88 includes at least one write actuation transistor 92, which is turned on by a write actuation signal from a write actuation terminal 93, allowing write current supplied by a read / write terminal 87 to pass through.

[0094] In some embodiments, at least one write circuit 88 further includes at least one write actuator load resistor (R). WE )94, write actuation transistor 92 is connected between read / write terminal 87 and multiple programmable memories 80, the gate of write actuation transistor 92 is connected to write actuation terminal 93, one end of write actuation terminal load resistor 94 is connected to the gate of write actuation transistor 92, and the other end is grounded.

[0095] When the read / write terminal 87 receives the read current, the write actuation terminal 93 is configured to be grounded or receive a low-potential signal.

[0096] like Figure 5As shown, in this embodiment of the invention, both the write current 90 and the read current 91 are still provided by the memory read / write terminal 87. To ensure that the write current 90 can only enter the programmable memory array 81 during write operations, the write circuit 88 includes a write actuation transistor 92, which is connected to the gate of the write actuation transistor 92 by a write actuation terminal 93. Preferably, a write actuation terminal load resistor (R) can be provided at the gate terminal of the write actuation transistor 92. WE )94, to ensure that the input voltage received by the write actuation terminal 93 falls mostly on the gate terminal of the write actuation transistor 92. When the write actuation terminal 93 receives a sufficiently large input voltage (i.e., actuation signal 95) to turn on the write actuation transistor 92, the write current 90 can then be transmitted to the programmable memory array 81 through the write circuit 88.

[0097] In some embodiments, at least one read circuit 89 includes at least one read actuation transistor 96, which is used to control the read current provided by the read / write terminal 87.

[0098] In some embodiments, a read actuation transistor 96 is connected between a read / write terminal 87 and a plurality of programmable memories 80, and the read actuation transistor 96 is connected to the read / write terminal 87. Specifically, the read actuation transistor 96 is connected between the read / write terminal 87 and the plurality of programmable memories 80, and the gate of the read actuation transistor 96 is connected to the read / write terminal 87. The gate of the read actuation transistor 96 can be directly connected to the read / write terminal 87 or indirectly connected.

[0099] For example, in some embodiments, the gate of the read actuator transistor 96 is directly connected to the read / write terminal 87.

[0100] In some embodiments, at least one read circuit 89 further includes a pull-low transistor 97 and a voltage divider device, the gate of the read actuation transistor 96 is connected to the read / write terminal 87 via the voltage divider device, the first terminal of the pull-low transistor 97 is connected to the gate of the read actuation transistor 96, the second terminal of the pull-low transistor 97 is grounded, and the gate of the pull-low transistor 97 is connected to the read / write terminal 87.

[0101] In some embodiments, the voltage divider device is a load resistor (R RL )98.

[0102] The read circuit 89 includes a read actuator transistor 96. When the read / write terminal 87 reads, the write actuator terminal 93 of the write circuit 88 is grounded or at a low potential, causing the write actuator transistor 92 to be turned off, making the write circuit 88 an open circuit. At this time, the current only flows through the read circuit 89. In addition, the write actuator transistor 92 and the read actuator transistor 96 have two major differences: (1) the channel width / length ratio of the write actuator transistor 92 needs to be increased to provide a larger write current; (2) the write actuator transistor 92 requires a large instantaneous current and therefore needs to operate in the linear region, while the read actuator transistor 96 needs to operate in the saturated region to limit the current in order to protect the programmable memory array 81. In order to ensure that the read actuator transistor 96 operates in the saturated region, the gate terminal of the read actuator transistor 96 in this embodiment is connected to a pull-low transistor 97 and a load resistor (R). RL To divide the voltage using transistor 98, it is preferable that the channel width-to-length (W / L) ratio of the lowering transistor 97 be designed to be smaller than that of the read actuator transistor 96, or that the lowering transistor 97 uses a higher threshold voltage. These designs aim to address the dual requirements of low-voltage reads and high-voltage writes at the read / write terminal 87: as mentioned above, the read actuator transistor 96 needs to operate in the saturation region, and the read current 91 entering the programmable memory array 81 through the read actuator transistor 96 is as follows: This formula V G To read the gate voltage of actuator transistor 96, firstly, when reading at the read / write terminal 87 with a small voltage, the gate terminal of actuator transistor 97 also experiences a small voltage, resulting in a higher impedance or even an open circuit. The small voltage read can activate actuator transistor 96 to operate in the saturation region. Secondly, when writing at the memory read / write terminal 87 with a large voltage, the gate terminal of actuator transistor 97 also experiences a large voltage, resulting in a low impedance. In this case, the gate voltage V of actuator transistor 96 can be read. G The low voltage caused by the low impedance of transistor 97 and the voltage division of load resistor 98 keeps the programmable memory array 81 at a low voltage, preventing read actuator transistor 96 from providing a large current and thus protecting the programmable memory array 81. Only when write actuator terminal 93 receives a write actuator signal 95 with sufficient voltage to turn on write actuator transistor 92 can the programmable memory array 81 be written or changed, thereby protecting the data in the programmable memory array 81.

[0103] Figure 6This is a schematic diagram of a programmable memory circuit structure according to another embodiment of the present invention. Parts of the structure of this other embodiment are the same as those of the aforementioned embodiment. The differences between the two will be described below, while the similarities will not be detailed further. In this embodiment, the voltage divider is a load transistor 99. The first terminal of the load transistor 99 is connected to the gate of the read actuation transistor 96, and the second terminal and gate of the load transistor 99 are connected to the read / write terminal 87.

[0104] Figure 6 Compared to the embodiments Figure 5 In one embodiment, a load transistor 99 is used instead of the original load resistor 98. The load transistor 99 is designed as a transistor with a longer channel. The desired read voltage division of the gate voltage of the actuator transistor 96 is achieved by the ratio of the channel width-to-length (W / L) between the low-voltage transistor 97 and the load transistor 99. The advantage of this design is that the low-voltage transistor 97 and the load transistor 99 used for voltage division can be manufactured in the same process of wafer fabrication, and the voltage division obtained at the gate of the actuator transistor 96 is more accurate.

[0105] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made under the concept of the present invention using the description and drawings of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A storage circuit structure for a liquid ejection device, characterized by, The application comprises: a plurality of programmable memory cells; at least one read / write terminal for reading and writing the plurality of programmable memory cells; at least one read circuit for controlling the current provided by the read / write terminal to read the plurality of programmable memory cells; at least one write circuit; at least one write activation terminal, when the write activation terminal receives a write activation signal, the current provided by the read / write terminal is passed through the write circuit to write the plurality of programmable memory cells; the at least one read circuit and the at least one write circuit are connected in parallel between the read / write terminal and the plurality of programmable memory cells; the at least one read circuit comprises at least one read activation transistor for controlling the read current provided by the read / write terminal; the read activation transistor is connected between the read / write terminal and the plurality of programmable memory cells, and the read activation transistor is connected to the read / write terminal; the at least one write circuit comprises at least one write activation transistor, which is turned on by the write activation signal of the write activation terminal, so that the write current provided by the read / write terminal is passed through; when the plurality of programmable memory cells need to be written, the write activation terminal receives a write activation signal, and the current provided by the read / write terminal is passed through the write circuit to write the plurality of programmable memory cells; when the plurality of programmable memory cells need to be read, the write activation terminal no longer receives a write activation signal, and the current provided by the read / write terminal is passed through the read circuit to read the plurality of programmable memory cells.

2. The storage circuit structure for a liquid ejecting apparatus according to Claim 1, wherein The at least one read circuit further comprises a pull-down transistor and a voltage dividing device, the gate of the read activation transistor is connected to the read / write terminal through the voltage dividing device, the first electrode of the pull-down transistor is connected to the gate of the read activation transistor, the second electrode of the pull-down transistor is connected to ground, and the gate of the pull-down transistor is connected to the read / write terminal.

3. The storage circuit structure for a liquid ejecting head according to Claim 2, wherein The voltage dividing device is a load resistor.

4. The storage circuit structure for a liquid ejecting head according to Claim 2, wherein The voltage dividing device is a load transistor, the first electrode of the load transistor is connected to the gate of the read activation transistor, and the second electrode and the gate of the load transistor are connected to the read / write terminal.

5. The storage circuit structure for a liquid ejecting head according to Claim 1, wherein The at least one write circuit further comprises at least one write activation terminal load resistor, the write activation transistor is connected between the read / write terminal and the plurality of programmable memory cells, the gate of the write activation transistor is connected to the write activation terminal, one end of the write activation terminal load resistor is connected to the gate of the write activation transistor, and the other end of the write activation terminal load resistor is connected to ground.

6. The storage circuit structure for a liquid ejecting head according to Claim 1, wherein When the read / write terminal receives a read current, the write activation terminal is configured to be grounded or receive a low potential signal.

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