Methods, apparatuses, electronic devices and storage media for handling memory request addresses

Abstract

This application discloses a method, apparatus, electronic device, and storage medium for processing memory request addresses, relating to the field of memory mapping technology. The method includes: for any memory controller, after receiving a memory request address sent by a processing node, detecting the address offset of the memory request address; if an address offset exists, removing the lower-order address space to obtain a shifted address; determining the bits to be removed from the shifted address according to a preset address mapping method, and removing the bits to be removed to obtain the processed memory request address; and mapping the processed memory request address based on the preset address mapping method to obtain the memory row and column addresses. This application, by removing the address offset and address bits before address mapping by the memory controller, avoids repeated readings of the scrubber at empty spaces, thereby improving DDR performance.

Description

Technical Field

[0001] This application relates to the field of memory mapping technology, and in particular to a method, apparatus, electronic device and storage medium for processing memory request addresses. Background Technology

[0002] Because memory requesting nodes segment a requested address and distribute it across different processing nodes during the memory address request process, and each processing node performs a hash operation on the allocated address before mapping the hashed address to a different DDR (Double Data Rate) controller, the addresses received by the DDR are often discontinuous and contain gaps. Therefore, when the DDR controller's address mapping module performs row-to-column address translation, specific address bits are removed from the received address to ensure address contiguousness. The internal scrubber configuration of the DDR controller, located before the DDR controller, periodically reads DDR memory data to determine if ECC (Error Correcting Code) errors exist and takes appropriate action. This scrubber operates by incrementally accessing a range of address spaces based on configured time intervals. Therefore, when the DDR controller receives addresses with gaps, the scrubber will repeatedly read the same address at the gaps, causing read requests from the scrubber to compete for resources with normal DDR read / write requests, thus impacting DDR performance. Summary of the Invention

[0003] The main objective of this application is to provide a memory request address processing method, apparatus, electronic device, and storage medium, which aims to solve the technical problem of poor DDR performance.

[0004] To achieve the above objectives, this application proposes a memory request address processing method, which includes:

[0005] For any memory controller, after receiving the memory request address sent by the processing node, the address offset of the memory request address is detected;

[0006] In the case where there is an address offset, the address of the lower space in the memory request address is offset and removed to obtain the shifted address, wherein the lower space is a preset address range with the smallest corresponding value in the memory request address;

[0007] The bit to be removed in the shift address is determined according to the preset address mapping method, and the bit to be removed in the shift address is removed to obtain the processed memory request address;

[0008] The processed memory request address is mapped based on the preset address mapping method to obtain the memory row and column addresses.

[0009] In one embodiment, the step of offsetting and removing the lower-order space of the memory request address to obtain the shifted address includes:

[0010] Obtain the address in the lower-order space and the address offset of the address;

[0011] The shift address is obtained by subtracting the address offset from the address.

[0012] In one embodiment, the step of determining the bit to be removed in the shift address according to a preset address mapping method includes:

[0013] The bit removal method for the shift address is determined according to the preset address mapping method;

[0014] When the bit removal method is low-order bit removal, the mapping pattern between the processing node and the memory controller is obtained, and the bit to be removed is determined based on the mapping pattern.

[0015] In one embodiment, the step of determining the bit to be removed based on the mapping pattern includes:

[0016] When the mapping mode is scattering mode, based on the corresponding number of processing nodes and memory controllers in the scattering mode, and the preset cross-granularity configured in the memory controller, the first preset address bit removal table is queried to obtain the bit to be removed;

[0017] When the mapping mode is direct mode, the target processing nodes and target memory controllers that have mapping relationships in the direct mode are obtained, and based on the first number of target processing nodes and the second number of target memory controllers, the second preset address bit removal table is queried to obtain the bit to be removed.

[0018] In one embodiment, the memory request address processing method further includes:

[0019] If the bit removal method is high-order bit removal, skip the step of removing the bit to be removed from the shift address, and use the shift address as the processed memory request address.

[0020] In one embodiment, after the step of removing the bit to be removed from the shift address, the method further includes:

[0021] Obtain the original address length of the shifted address;

[0022] Based on the original address length, the high-order bits of the shifted address after the removal of the bit to be removed are padded with zeros.

[0023] In one embodiment, the step of detecting the address offset of the memory request address further includes:

[0024] The memory request address is compared with multiple preset security address ranges to determine the target preset security address range in which the memory request address is located;

[0025] Obtain the reference security attributes configured for the target preset security address range, and perform security verification on the security attributes corresponding to the memory request address based on the reference security attributes;

[0026] If the security attribute verification fails, the step of detecting the address offset of the memory request address is executed, and a preset identifier is attached to the memory request address so that the memory requested by the memory request address can identify the status information of the memory request address according to the preset identifier.

[0027] Furthermore, to achieve the above objectives, this application also proposes a memory request address processing apparatus, which includes:

[0028] The detection module is used to detect the address offset of the memory request address after receiving the memory request address sent by the processing node for any memory controller.

[0029] The shift module is used to offset and remove the address of the lower space in the memory request address when the address offset situation exists, so as to obtain the shift address, wherein the lower space is a preset address range with the smallest corresponding value in the memory request address;

[0030] The bit removal module is used to determine the bit to be removed in the shift address according to a preset address mapping method, and remove the bit to be removed in the shift address to obtain the processed memory request address;

[0031] The mapping module is used to perform address mapping on the processed memory request address based on the preset address mapping method to obtain the memory row and column addresses.

[0032] In addition, to achieve the above objectives, this application also proposes an electronic device, the device comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the memory request address processing method as described above.

[0033] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and which, when executed by a processor, implements the steps of the memory request address processing method described above.

[0034] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the memory request address processing method described above.

[0035] One or more technical solutions proposed in this application have at least the following technical effects:

[0036] This application, for any memory controller, upon receiving a memory request address sent by a processing node, detects the address offset of the memory request address to avoid address overlap during mapping due to address offset in the lower-order space of the memory request address, providing an effective data foundation for timely detection of address overlap. If an address offset exists, the lower-order space of the memory request address is offset and removed to obtain a shifted address, ensuring no address overlap occurs during memory address request. The bits to be removed from the shifted address are determined according to a preset address mapping method and removed to obtain a processed memory request address. This bit removal before address mapping in the memory controller avoids repeated reads when the scrubber reads DDR memory data. Based on the preset address mapping method, the processed memory request address is mapped to obtain a memory row and column address, thus converting the memory request address into a memory-recognizable memory row and column address.

[0037] In summary, this application improves DDR performance by performing offset removal and address bit removal on the address before address mapping in the memory controller, and then mapping the processed continuous, gap-free addresses to memory rows and columns. This ensures that the address data encountered by the scrubber when reading DDR memory data is continuous and gap-free, avoiding the problem of repeated reading at gaps that affects DDR performance. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart illustrating an embodiment of the memory request address processing method of this application.

[0041] Figure 2 This is a schematic diagram illustrating the offset removal of the memory request address processing method provided in Embodiment 1 of this application.

[0042] Figure 3 This is a schematic diagram of the selection process for the memory request address processing method provided in Embodiment 1 of this application;

[0043] Figure 4 This is a flowchart illustrating Embodiment 2 of the memory request address processing method of this application.

[0044] Figure 5 A simplified flowchart illustrating the memory request address processing method provided in Embodiment 2 of this application;

[0045] Figure 6 This is a schematic diagram of the module structure of the memory request address processing device according to an embodiment of this application;

[0046] Figure 7 This is a schematic diagram of the device structure of the hardware operating environment involved in the memory request address processing method in the embodiments of this application.

[0047] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0048] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0049] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0050] The main solution of this application embodiment is as follows: For any memory controller, after receiving a memory request address sent by the processing node, the address offset of the memory request address is detected; if the address offset exists, the address of the lower space in the memory request address is offset and removed to obtain a shifted address, wherein the lower space is a preset address range with the smallest corresponding value in the memory request address; the bit to be removed in the shifted address is determined according to a preset address mapping method, and the bit to be removed in the shifted address is removed to obtain the processed memory request address; the processed memory request address is mapped according to the preset address mapping method to obtain the memory row and column address.

[0051] Because the scrubber configuration inside the DDR controller precedes the DDR controller itself, it periodically reads DDR memory data to determine if ECC errors exist and takes appropriate action. This scrubber operates by incrementally accessing a range of address spaces based on configured time intervals. Therefore, when the DDR controller receives addresses with gaps, the scrubber will repeatedly read the same address at those gaps. The read requests generated by the scrubber will then compete for resources with normal DDR read / write requests, thus impacting DDR performance.

[0052] This application provides a solution that performs offset removal and address bit removal on the address before address mapping in the memory controller, and then performs memory row and column mapping on the processed continuous address without gaps. This ensures that the address data encountered by the scrubber when reading DDR memory data is continuous and without gaps, avoiding the problem of scrubber repeatedly reading at gaps and affecting DDR performance, thus improving DDR performance.

[0053] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device capable of performing the above functions. The following description uses an electronic device as an example to illustrate this embodiment and the subsequent embodiments.

[0054] Based on this, embodiments of this application provide a method for processing memory request addresses, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the memory request address processing method of this application.

[0055] In this embodiment, the memory request address processing method includes steps S10 to S40:

[0056] Step S10: For any memory controller, after receiving the memory request address sent by the processing node, detect the address offset of the memory request address.

[0057] It should be noted that a processing node refers to a node in a CMN (Coherent Mesh Network) mesh that performs hash mapping on the physical address sent by the CPU (Central Processing Unit) for requesting memory; a memory request address refers to an address sent by a processing node that points to a specific location in memory; and address offset refers to whether there is an offset in the address space, such as whether the address space starts from all zeros and increments.

[0058] It is understandable that when there is an address offset in the memory request address, address overlap will occur during the address mapping process, causing some address space to become unusable. Therefore, performing step S10 can avoid the inability to identify address overlap and provide a reliable basis for subsequent address offset correction.

[0059] Step S20: In the case where there is an address offset, the address of the lower space in the memory request address is offset and removed to obtain the shifted address, wherein the lower space is a preset address range with the smallest corresponding value in the memory request address.

[0060] It should be noted that the low-end space refers to the address range representing the smaller data in the memory request address, and this address range has a special identifier; the shifted address refers to the new address after the offset address has been removed.

[0061] It is understandable that address offset will cause address overlap and affect the normal use of part of the address space. Therefore, performing step S20 can avoid the problem of part of the address space being unavailable, thereby avoiding the problem of the address space being segmented too much, which would make it difficult for related hardware to configure resources. This ensures the normal use of the address space while reducing the resource configuration requirements of related hardware.

[0062] In one feasible implementation, the step of offsetting and removing the address of the lower space in the memory request address to obtain the shifted address in step S20 may include steps S21 to S22:

[0063] Step S21: Obtain the address in the low-order space and the address offset of the address;

[0064] It should be noted that the address offset refers to the difference between the memory request address and the base address in the lower memory space.

[0065] For example, when the memory request address is a 128G address space, that is, from 0x0000_8000_0000 to 0x1020_0000_0000, the address in the lower 2G space is obtained, that is, the address in the range from 0x0000_8000_0000 to 0x0000_ffff_ffff. At this time, the address offset of this address is 0x0000_8000_0000.

[0066] Step S22: Subtract the address offset from the address to obtain the shift address.

[0067] For example, please refer to Figure 2 The shift address is obtained through the following calculation logic: addr_in

[44] ? addr_in:(addr_in-0x0000_8000_0000) where addr_in

[44] is the lower 2G part of the memory request address, in order to avoid the address range from 0x0000_8000_0000 to 0x0000_ffff_ffff from overlapping with the address range from 0x1000_8000_0000 to 0x1000_ffff_ffff.

[0068] In this embodiment, by performing low-bit analysis and offset removal on the memory request address, the offset in the memory request address is eliminated, avoiding the problem of some address space being unavailable. This also avoids the problem of excessive segmentation of the address space, which would make it difficult for related hardware to configure resources. This ensures that the address space in the memory request address is used normally, while reducing the resource configuration requirements of related hardware.

[0069] Step S30: Determine the bit to be removed in the shift address according to the preset address mapping method, and remove the bit to be removed in the shift address to obtain the processed memory request address;

[0070] It should be noted that the address mapping method refers to a set of rules or algorithms used in the memory controller to translate physical addresses. This address mapping method is determined by the registers configured in the memory controller and defines the specific method of address translation, including how to handle special bits of the address. The bit to be removed is determined in real time according to the address mapping method and is a specific address bit that needs to be deleted at the shift address.

[0071] Additionally, it should be noted that the preset address mapping method is consistent with the address mapping method used in the processing node to map the physical address issued by the CPU. That is, the register in the memory controller where the preset address mapping method is located is consistent with the register configuration in the processing node. This avoids the bit removal situation in the software calculation of various address mapping modes, improves the efficiency of bit removal in the memory controller, and thus improves the performance of the memory controller.

[0072] Understandably, since the addresses received by the memory controller are discontinuous and have gaps, step S30 is performed to remove the special address bits that need to be removed from the address, ensuring that the address that the scrubber faces when reading DDR memory data is continuous and without gaps. This avoids affecting the normal read and write requests of DDR and improves the read and write performance of DDR.

[0073] In one feasible implementation, the step of determining the bit to be removed in the shift address according to the preset address mapping method in step S30 may include steps S31 to S33:

[0074] Step S31: Determine the bit removal method for the shift address based on the address mapping method;

[0075] For example, the address mapping configured in the registers of the memory controller is as follows:

[0076] SN selection mode 3'b000:1-SN mode(SN0);

[0077] 3'b001:3-SN mode(SN0,SN1,SN2);

[0078] 3'b010:6-SN mode(SN0,SN1,SN2,SN3,SN4,SN5);

[0079] 3'b011:5-SN mode(SN0,SN1,SN2,SN3,SN4);

[0080] 3'b100:2-SN mode(SN0,SN1)power of 2hashing;

[0081] 3'b101:4-SN mode(SN0,SN1,SN2,SN3)power of 2hashing;

[0082] 3'b110:8-SN mode(SN0,SN1,SN2,SN3,SN4,SN5,SN6,SN7)

[0083] power of 2hashing;

[0084] Others: Reserved ，The above configuration indicates that the memory controller needs to remove the low-order bits of the shift address in 1-SN mode, 2-SN mode, 4-SN mode, and 8-SN mode, while the remaining 3 / 6 / 5-SN modes require the removal of the high-order bits.

[0085] Step S32: If the bit removal method is low-order bit removal, obtain the mapping pattern between the processing node and the memory controller, and determine the bit to be removed based on the mapping pattern;

[0086] It should be noted that the mapping mode refers to the correspondence between the processing node and the memory controller. For example, 1-SN mode means that the mapping mode between the processing node and the memory controller is a one-to-one mapping, 2-SN mode means that the mapping mode between the processing node and the memory controller is one processing node mapping two memory controllers, 4-SN mode means that the mapping mode between the processing node and the memory controller is one processing node mapping four memory controllers, and so on.

[0087] In one feasible implementation, the step of determining the bit to be removed based on the mapping pattern in step S32 may include steps S321 to S322:

[0088] Step S321: When the mapping mode is scattering mode, based on the corresponding number of processing nodes and memory controllers in the scattering mode and the preset cross granularity configured in the memory controller, query the first preset address bit removal table to obtain the bit to be removed;

[0089] It should be noted that scattering mode refers to a one-to-many correspondence between processing nodes and memory controllers, such as 2-SN mode, 4-SN mode, and 8-SN mode; the number of correspondences refers to the number of correspondences between processing nodes and memory controllers in scattering mode, for example, the number of correspondences in 2-SN mode is 2-SN, the number of correspondences in 4-SN mode is 4-SN, the number of correspondences in 8-SN mode is 8-SN, and so on; the preset cross granularity refers to the address unit configured in the address mask register in the memory controller.

[0090] For example, when the mapping mode is a scattering mode, i.e., a 2-SN mode, a 4-SN mode, or an 8-SN mode, the corresponding number of 2-SNs, 4-SNs, or 8-SNs is determined. See the table below:

[0091]

[0092] Table 1

[0093] Table 1 shows that the address mask register is configured as 46'h3fff_ffff_ffc0, which means that bits 51 to 6 of the 64-bit address are masked, and the rest are retained. At this time, the cross-granularity configured in the memory controller is 64B, that is, the physical space is in units of 64 bytes.

[0094] The table for removing the first preset address is now retrieved as follows:

[0095]

[0096]

[0097] Table 2

[0098] Table 2 shows that when the corresponding number is 2-SN and the cross-interval granularity is 64B, the bit to be removed is the sixth bit of the address; when the corresponding number is 4-SN and the cross-interval granularity is 64B, the bit to be removed is the sixth to seventh bits of the address, and so on.

[0099] Step S322: When the mapping mode is direct mode, obtain the target processing nodes and target memory controllers that have a mapping relationship in the direct mode, and query the second preset address bit removal table based on the first number of target processing nodes and the second number of target memory controllers to obtain the bit to be removed.

[0100] It should be noted that direct mode refers to a one-to-one correspondence between the processing node and the memory controller, i.e., a 1-SN mode (direct mode) mapping mode.

[0101] For example, the target processing nodes HN-Fs and target memory controllers SN-Fs with mapping relationships in the direct-fire mode are obtained, and the second preset address bit removal table is queried based on the first number of target processing nodes (Number of HN-Fs) and the second number of target memory controllers (Number of SN-Fs) as follows:

[0102]

[0103] Table 3

[0104] Table 3 shows that when the first number is 2 and the second number is 1, no address bits are removed; when the first number is 2 and the second number is 2, the bit to be removed is the sixth bit of the address; when the first number is 4 and the second number is 4, the bits to be removed are the sixth to seventh bits of the address, and so on.

[0105] In this embodiment, by querying the preset address bit removal table based on the actual mapping situation under the two mapping modes, the special address bits that need to be removed from the address are accurately determined. This ensures that the memory request address can be correctly mapped in the memory controller after the address bits are removed, while also removing the address bits before address mapping in the memory controller, thus avoiding repeated reading behavior generated by the scrubber when reading DDR memory data.

[0106] Step S33: If the bit removal method is high-order bit removal, skip the step of removing the bit to be removed from the shift address, and use the shift address as the processed memory request address.

[0107] Understandably, when the removal method is high-order removal, that is, when the corresponding mapping mode is 3 / 6 / 5-SNmode, it is not necessary to remove the low-order bits of the address. Therefore, step S33 is performed. By skipping the bit removal operation on the address, the latency of the memory controller in processing the address is reduced, and the operating efficiency of the memory controller is improved.

[0108] For example, please refer to Figure 3 By using mux, when the removal method is high-order removal, i.e., after performing ofs_ctrl, the step of performing bit removal (bit_ctrl) is skipped. Here, the interconnect network config copy indicates that the address mapping method in the memory controller is consistent with that in the processing node.

[0109] Step S40: Based on the preset address mapping method, the processed memory request address is mapped to obtain the memory row and column addresses.

[0110] For example, in the DDR inner address map module of the memory controller, the processed memory request address is mapped based on a preset address mapping method to obtain the memory row / col address.

[0111] This embodiment provides a memory request address processing method. Before address mapping in the memory controller, the address is processed by offset removal and address bit removal. The processed continuous address without gaps is then mapped to memory rows and columns. This ensures that the address data encountered by the scrubber when reading DDR memory data is continuous and without gaps, avoiding the problem of scrubber repeatedly reading at gaps and affecting DDR performance, thus improving DDR performance.

[0112] In one feasible implementation, after the step of removing the bit to be removed from the shift address in step S30, steps S301 to S302 may also be included:

[0113] Step S301: Obtain the original address length of the shifted address;

[0114] It should be noted that the original address length refers to the number of bits in the address before the bit removal is performed.

[0115] Step S302: Based on the original address length, pad the high-order bits of the shifted address after removing the bit to be removed with zeros.

[0116] It should be noted that padding with zeros at high bits refers to adding 0s to the front of a digital address to keep the address length unchanged.

[0117] For example, when the shift address is 1011, and after the bit to be removed 11 becomes 10, the high-bits of address 10 are padded with zeros based on the original address length of 4 to obtain address 0010.

[0118] In this embodiment, by padding the high-order bits of the address after the removal of the bit with zeros, the problem of address length shortening and address space mismatch caused by the removal of specific address bits is avoided, thus maintaining the integrity of the address space and ensuring the correct addressing of the memory request address in memory, thereby guaranteeing the accuracy of memory access and the stability of system operation.

[0119] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 4 , Figure 4 This is a flowchart illustrating the second embodiment of the memory request address processing method of this application.

[0120] Before step S10, the memory request address processing method further includes steps S01 to S04:

[0121] Step S01: Compare the memory request address with multiple preset security address ranges to determine the target preset security address range in which the memory request address is located;

[0122] It should be noted that the preset safe address range refers to the address range predefined in the memory controller and configured with special security attribute standards; the target preset safe address range refers to the preset safe address range into which the memory request address falls.

[0123] Additionally, it should be noted that performing address security verification before removing address bits from memory request addresses avoids the need for complex configuration adjustments during the security verification process based on the specific removal of address bits. This reduces the complexity of processing memory request addresses and thus improves DDR performance.

[0124] It is understandable that since the memory request address received by the memory controller may be illegal or unsafe, step S01 is performed to determine the range of the memory request address, thereby providing a basis for judging different security attributes. This can prevent illegal or out-of-bounds access to memory, which could lead to system errors, data corruption, or security vulnerabilities. It ensures that only legal address requests are processed, thereby improving the stability and security of the system.

[0125] Step S02: Obtain the reference security attribute configured for the target preset security address range, and perform security verification on the security attribute corresponding to the memory request address based on the reference security attribute;

[0126] It should be noted that reference security attributes refer to a set of security features or identifiers corresponding to the target's preset security address range. These features are used to verify whether the security attributes of the memory request address are consistent with these features. Security attributes refer to a set of security features or identifiers related to the memory request address. These features are used to determine the legality of the request, access permissions, data sensitivity, and other information. This security attribute is part of memory access control.

[0127] Understandably, since there are often specific security requirements during memory access, performing step S02 can prevent security issues such as unauthorized access, data leakage, or malicious operations. By verifying security attributes, the legitimacy and security of memory requests are ensured, thereby protecting the system from security threats and maintaining data integrity and stable system operation.

[0128] Step S03: If the security attribute verification fails, the step of detecting the address offset of the memory request address is executed, and a preset identifier is attached to the memory request address so that the memory requested by the memory request address can identify the status information of the memory request address according to the preset identifier;

[0129] It should be noted that the preset flag is data used to inform the memory of the specific status of the memory request address. For example, when the preset flag indicates that the memory request address for reading memory data is non-compliant, the memory will return zero data or no data after recognizing the preset flag; when the preset flag indicates that the memory request address for writing memory data is non-compliant, the memory will reject the write operation after recognizing the preset flag.

[0130] Step S04: If the security attribute verification is successful, perform the step of detecting the address offset of the memory request address.

[0131] In this embodiment, by comparing the memory request address with the preset address range and verifying the security attributes, it is ensured that only legitimate requests that meet the security requirements are processed, thereby preventing potential memory access errors and security threats and improving the overall security and reliability of the system.

[0132] For example, to help understand the implementation flow of the memory request address processing method obtained by combining this embodiment with the above embodiment one, please refer to... Figure 5 , Figure 5 A simplified flowchart of a memory request address processing method is provided, specifically:

[0133] After multiple CPUs issue requests for physical addresses of memory, these physical addresses are processed by the CMN mesh (processing nodes) and then sent to the memory controller. The memory controller first performs security verification, comparing the address to a preset safe address range and verifying security attributes. After security verification, the address is input into the `addr_ctrl` module for address offset removal and address bit removal. Then, the address after removing specific address bits is mapped to obtain the memory row and column addresses. A `scrubber` module is set before the address mapping module to periodically read DDR memory data to determine if ECC errors exist; if so, appropriate measures are taken. This application, by adding the `addr_ctrl` module before the address mapping module to perform offset removal and address bit removal before address mapping, ensures that the address data encountered by the scrubber when reading DDR memory data is continuous and without gaps. This avoids the problem of repeated readings at gaps affecting DDR performance, thus improving DDR performance.

[0134] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the memory request address processing method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0135] This application also provides a memory request address processing device, please refer to... Figure 6 The memory request address processing device includes:

[0136] The detection module 10 is used to detect the address offset of the memory request address after receiving the memory request address sent by the processing node for any memory controller.

[0137] The shift module 20 is used to offset and remove the address of the low-order space in the memory request address when the address offset situation is that an address offset exists, so as to obtain a shift address, wherein the low-order space is a preset address range with the smallest corresponding value in the memory request address;

[0138] The bit removal module 30 is used to determine the bit to be removed in the shift address according to a preset address mapping method, and remove the bit to be removed in the shift address to obtain the processed memory request address;

[0139] The mapping module 40 is used to perform address mapping on the processed memory request address based on the preset address mapping method to obtain the memory row and column addresses.

[0140] Optionally, the shift module 20 is further configured to:

[0141] Obtain the address in the lower-order space and the address offset of the address;

[0142] The shift address is obtained by subtracting the address offset from the address.

[0143] Optionally, the bit removal module 30 is further configured to:

[0144] The bit removal method for the shift address is determined according to the preset address mapping method;

[0145] When the bit removal method is low-order bit removal, the mapping pattern between the processing node and the memory controller is obtained, and the bit to be removed is determined based on the mapping pattern.

[0146] Optionally, the bit removal module 30 is further configured to:

[0147] When the mapping mode is scattering mode, based on the corresponding number of processing nodes and memory controllers in the scattering mode, and the preset cross-granularity configured in the memory controller, the first preset address bit removal table is queried to obtain the bit to be removed;

[0148] When the mapping mode is direct mode, the target processing nodes and target memory controllers that have mapping relationships in the direct mode are obtained, and based on the first number of target processing nodes and the second number of target memory controllers, the second preset address bit removal table is queried to obtain the bit to be removed.

[0149] Optionally, the bit removal module 30 is further configured to:

[0150] If the bit removal method is high-order bit removal, skip the step of removing the bit to be removed from the shift address, and use the shift address as the processed memory request address.

[0151] Optionally, the bit removal module 30 is further configured to:

[0152] Obtain the original address length of the shifted address;

[0153] Based on the original address length, the high-order bits of the shifted address after the removal of the bit to be removed are padded with zeros.

[0154] Optionally, the verification module 50 in the memory request address processing device is used for:

[0155] The memory request address is compared with multiple preset security address ranges to determine the target preset security address range in which the memory request address is located;

[0156] Obtain the reference security attributes configured for the target preset security address range, and perform security verification on the security attributes corresponding to the memory request address based on the reference security attributes;

[0157] If the security attribute verification fails, the step of detecting the address offset of the memory request address is executed, and a preset identifier is attached to the memory request address so that the memory requested by the memory request address can identify the status information of the memory request address according to the preset identifier.

[0158] The memory request address processing apparatus provided in this application, employing the memory request address processing method in the above embodiments, can solve the technical problem of poor DDR performance. Compared with the prior art, the beneficial effects of the memory request address processing apparatus provided in this application are the same as those of the memory request address processing method provided in the above embodiments, and other technical features in the memory request address processing apparatus are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0159] This application provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the memory request address processing method in Embodiment 1 above.

[0160] The following is for reference. Figure 7 The diagram illustrates a structural schematic of an electronic device suitable for implementing embodiments of this application. The electronic devices in these embodiments may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 7 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0161] like Figure 7 As shown, the electronic device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the electronic device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. While electronic devices with various systems are shown in the figures, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0162] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0163] The electronic device provided in this application, employing the memory request address processing method in the above embodiments, can solve the technical problem of poor DDR performance. Compared with the prior art, the beneficial effects of the electronic device provided in this application are the same as those of the memory request address processing method provided in the above embodiments, and other technical features of this electronic device are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0164] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0165] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0166] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the memory request address processing method in the above embodiments.

[0167] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0168] The aforementioned computer-readable storage medium may be included in an electronic device or may exist independently without being assembled into an electronic device.

[0169] The aforementioned computer-readable storage medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device performs the following actions: For any memory controller, upon receiving a memory request address sent by a processing node, it detects the address offset of the memory request address; if an address offset exists, it removes the address of the lower-order space in the memory request address to obtain a shifted address, wherein the lower-order space is a preset address range with the smallest corresponding value in the memory request address; it determines the bit to be removed in the shifted address according to a preset address mapping method and removes the bit to be removed in the shifted address to obtain a processed memory request address; it performs address mapping on the processed memory request address based on the preset address mapping method to obtain a memory row and column address.

[0170] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0171] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0172] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0173] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described memory request address processing method, thereby solving the technical problem of poor DDR performance. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the memory request address processing method provided in the above embodiments, and will not be repeated here.

[0174] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the memory request address processing method described above.

[0175] The computer program product provided in this application can solve the technical problem of poor DDR performance. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the memory request address processing method provided in the above embodiments, and will not be repeated here.

[0176] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for processing memory request addresses, characterized in that, The memory request address processing method includes: For any memory controller, after receiving the memory request address sent by the processing node, the address offset of the memory request address is detected; In the case where there is an address offset, the address of the lower space in the memory request address is offset and removed to obtain the shifted address, wherein the lower space is a preset address range with the smallest corresponding value in the memory request address; The bit removal method for the shift address is determined according to the preset address mapping method; When the bit removal method is low-order bit removal, obtain the mapping pattern between the processing node and the memory controller; When the mapping mode is scattering mode, based on the corresponding number of processing nodes and memory controllers in the scattering mode, and the preset cross granularity configured in the memory controller, the first preset address bit removal table is queried to obtain the bit to be removed from the shift address; When the mapping mode is direct mode, the target processing nodes and target memory controllers that have a mapping relationship in the direct mode are obtained, and based on the first number of target processing nodes and the second number of target memory controllers, the second preset address bit removal table is queried to obtain the bit to be removed from the shift address; Remove the bit to be removed from the shift address to obtain the processed memory request address; The processed memory request address is mapped based on the preset address mapping method to obtain the memory row and column addresses.

2. The memory request address processing method as described in claim 1, characterized in that, The step of offsetting and removing the lower-order space of the memory request address to obtain the shifted address includes: Obtain the address in the lower-order space and the address offset of the address; The shift address is obtained by subtracting the address offset from the address.

3. The memory request address processing method as described in claim 1, characterized in that, The memory request address processing method further includes: If the bit removal method is high-order bit removal, skip the step of removing the bit to be removed from the shift address, and use the shift address as the processed memory request address.

4. The memory request address processing method as described in claim 1, characterized in that, The step of removing the bit to be removed from the shift address further includes: Obtain the original address length of the shifted address; Based on the original address length, the high-order bits of the shifted address after the removal of the bit to be removed are padded with zeros.

5. The memory request address processing method as described in claim 1, characterized in that, The step of detecting the address offset of the memory request address includes the following before: The memory request address is compared with multiple preset security address ranges to determine the target preset security address range in which the memory request address is located; Obtain the reference security attributes configured for the target preset security address range, and perform security verification on the security attributes corresponding to the memory request address based on the reference security attributes; If the security attribute verification fails, the step of detecting the address offset of the memory request address is executed, and a preset identifier is attached to the memory request address so that the memory requested by the memory request address can identify the status information of the memory request address according to the preset identifier.

6. A memory request address processing device, characterized in that, The memory request address processing device includes: The detection module is used to detect the address offset of the memory request address after receiving the memory request address sent by the processing node for any memory controller. The shift module is used to offset and remove the address of the lower space in the memory request address when the address offset situation exists, so as to obtain the shift address, wherein the lower space is a preset address range with the smallest corresponding value in the memory request address; The bit removal module is used to determine the bit removal method for the shifted address according to a preset address mapping method; when the bit removal method is low-order bit removal, it obtains the mapping mode between the processing node and the memory controller; when the mapping mode is a scattering mode, it queries a first preset address bit removal table based on the corresponding number of processing nodes and memory controllers in the scattering mode and the preset cross-granularity configured in the memory controller to obtain the bits to be removed from the shifted address; when the mapping mode is a direct mode, it obtains the target processing nodes and target memory controllers that have a mapping relationship in the direct mode, and queries a second preset address bit removal table based on a first number of target processing nodes and a second number of target memory controllers to obtain the bits to be removed from the shifted address; and removes the bits to be removed from the shifted address to obtain the processed memory request address; The mapping module is used to perform address mapping on the processed memory request address based on the preset address mapping method to obtain the memory row and column addresses.

7. An electronic device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the memory request address processing method as described in any one of claims 1 to 5.

8. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the memory request address processing method as described in any one of claims 1 to 5.

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