Instruction processing method, apparatus and device, and computer readable storage medium

Abstract

The invention discloses an instruction processing method, device and equipment and a computer readable storage medium, and belongs to the technical field of information. The method comprises the steps that a first storage unit corresponding to a first instruction bundle needing to be processed is determined in a processor, the first instruction bundle comprises a first instruction, the first instruction carries a first identifier of the first instruction bundle, and the processor further comprises a calculation unit corresponding to the first storage unit; under the condition that the number of idle units in the first storage unit is not smaller than the occupied number of the storage units of the first instruction bundle and the calculation units corresponding to the idle units meet the calculation requirement of the first instruction bundle, the first instruction is stored in the idle units, and the calculation units are used for calculating the selected instruction based on the first identifier. When the first instruction needs to be selected for calculation, the first instruction can be selected according to the first identifier, the storage position of the first instruction in the storage unit does not affect instruction selection, different instruction bundles can be stored in a staggered mode, the storage flexibility is high, and the utilization rate of the storage unit is high.

Description

Technical Field

[0001] The present application relates to the field of information technology, and in particular to an instruction processing method, apparatus, device and computer-readable storage medium. Background Art

[0002] In the field of information technology, a processor is often used to load instructions of a program to enable the program to run. The processor includes a storage unit, and the processor stores the instructions to be processed in the storage unit, and then reads the instructions stored in the storage unit to perform subsequent operations to enable the program to run. Therefore, an instruction processing method is needed to process instructions using a processor. Summary of the invention

[0003] The present application provides an instruction processing method, apparatus, device and computer-readable storage medium to process instructions using a processor. The technical solution is as follows:

[0004] In a first aspect, an instruction processing method is provided, the method comprising: determining in a processor a first storage unit corresponding to a first instruction bundle to be processed, wherein the first instruction bundle comprises a first instruction, the first instruction carries a first identifier of the first instruction bundle, and the processor further comprises a computing unit corresponding to the first storage unit; when the number of free cells in the first storage unit is not less than the number of storage cells occupied by the first instruction bundle and the computing unit corresponding to the free cell meets the computing requirements of the first instruction bundle, the first instruction is stored in the free cell, and the computing unit is used to calculate the selected instruction based on the first identifier of the first instruction bundle.

[0005] When it is necessary to select the first instruction included in the first instruction bundle for calculation, the selection of the first instruction can be achieved according to the first identifier of the first instruction bundle, and each first instruction carries the identifier of the first instruction bundle. Therefore, the storage position of the first instruction in the storage unit does not affect the instruction selection. In the process of storing instructions, the instructions included in different instruction bundles can be stored alternately, the storage flexibility is high, and the utilization rate of the storage unit is high.

[0006] In a possible implementation, determining in a processor a first storage unit corresponding to a first instruction bundle to be processed includes: determining a storage index of the first instruction bundle; determining the first storage unit in the processor according to the storage index, wherein the number of rows of the first storage unit in the processor is determined according to the storage index. The storage index is used to clarify in which row of storage units the first instruction bundle needs to be stored, that is, which row of storage units is the first storage unit, so that the first instruction bundle is stored in units of rows, and the efficiency of selecting the first storage unit is higher.

[0007] In a possible implementation, after determining the first storage unit corresponding to the first instruction bundle to be processed in the processor, it also includes: when the number of free units in the first storage unit is less than the number of storage units occupied by the first instruction bundle, or the computing unit corresponding to the free unit does not meet the computing requirements of the first instruction bundle, adjusting the storage index; storing the first instruction included in the first instruction bundle in the storage unit included in the processor according to the adjusted storage index. Even if the first storage unit cannot store the first instruction included in the first instruction bundle, the storage index can be adjusted to achieve storage of the first instruction according to the adjusted storage index. There is also a corresponding storage adjustment strategy for the case of storage failure. Therefore, this method can be applied to a variety of situations, has wide versatility, and is more reliable.

[0008] In a possible implementation, the first instruction bundle includes multiple first instructions, and the multiple free cells where the multiple first instructions are stored are located in the same row of the processor. Storing the multiple first instructions included in the first instruction bundle in the same row of free cells can control the first instructions included in the first instruction bundle to be processed at the same execution time, thereby simplifying the pipeline processing complexity corresponding to the first instruction bundle.

[0009] In a possible implementation, a first instruction included in a first instruction bundle and a second instruction included in a second instruction bundle are interleaved and stored in storage cells in the same row, and a second identifier of the second instruction bundle is different from a first identifier of the first instruction bundle. Instructions included in different instruction bundles can be interleaved and stored, and storage flexibility is high. For storage cells between instructions included in the same instruction bundle that are not occupied by the instruction bundle, other instruction bundles are allowed to occupy them, and the utilization rate of the storage cells is high.

[0010] In a possible implementation, after the first instruction is stored in the idle unit, the method further includes: determining, by a decoding unit included in the processor, the first instruction included in the first instruction bundle that is allowed to be calculated according to the first identifier of the first instruction bundle carried by the first instruction; and calculating, by a computing unit included in the processor, the first instruction included in the first instruction bundle that is allowed to be calculated to obtain result data. Regardless of how the first instruction bundle is stored in the storage unit, the decoding unit can determine the first instruction included in the first instruction bundle that is allowed to be calculated according to the first identifier, so as to ensure that the instructions calculated by the computing unit are all the first instructions included in the first instruction bundle that is currently allowed to be calculated, thereby ensuring the accuracy of instruction processing.

[0011] In a possible implementation, determining the first instruction included in the first instruction bundle that is allowed to be calculated according to the first identifier of the first instruction bundle carried by the first instruction includes: obtaining a reference identifier, the reference identifier being the first identifier of the first instruction bundle that is allowed to be calculated; obtaining a matching result between the first identifier carried by the first instruction and the reference identifier, and determining the first instruction included in the first instruction bundle that is allowed to be calculated according to the matching result. The first instruction can be determined by the reference identifier and the first identifier carried by the first instruction, and the determination process is simple and low-cost.

[0012] In a second aspect, an instruction processing device is provided, which includes: a determination module, used to determine in a processor a first storage unit corresponding to a first instruction bundle to be processed, the first instruction bundle including a first instruction, the first instruction carrying a first identifier of the first instruction bundle, and the processor also including a computing unit corresponding to the first storage unit; a storage module, used to store the first instruction in the idle unit when the number of idle units in the first storage unit is not less than the number of storage units occupied by the first instruction bundle and the computing unit corresponding to the idle unit meets the computing requirements of the first instruction bundle, and the computing unit is used to calculate the selected instruction based on the first identifier of the first instruction bundle.

[0013] In a possible implementation, the determination module is used to determine a storage index of the first instruction bundle; determine a first storage unit in the processor according to the storage index, and the number of rows of the first storage unit in the processor is determined according to the storage index.

[0014] In one possible implementation, the storage module is also used to adjust the storage index when the number of free cells in the first storage unit is less than the number of storage cells occupied by the first instruction bundle, or the computing units corresponding to the free cells do not meet the computing requirements of the first instruction bundle; and store the first instruction included in the first instruction bundle in the storage unit included in the processor according to the adjusted storage index.

[0015] In a possible implementation, the first instruction bundle includes multiple first instructions, and the multiple free cells where the multiple first instructions are stored are located in the same row of the processor.

[0016] In a possible implementation, a first instruction included in the first instruction bundle and a second instruction included in the second instruction bundle are stored alternately in storage units in the same row, and a second identifier of the second instruction bundle is different from a first identifier of the first instruction bundle.

[0017] In one possible implementation, the device also includes: a processing module, used to determine the first instruction included in the first instruction bundle that is allowed to be calculated based on the first identifier of the first instruction bundle carried by the first instruction through a decoding unit included in the processor; and calculate the first instruction included in the first instruction bundle that is allowed to be calculated through a computing unit included in the processor to obtain result data.

[0018] In one possible implementation, a processing module is used to obtain a reference identifier, where the reference identifier is a first identifier of a first instruction bundle that is allowed to be calculated; obtain a matching result between the first identifier of a first instruction bundle carried by a first instruction and the reference identifier, and determine a first instruction included in the first instruction bundle that is allowed to be calculated based on the matching result.

[0019] In a third aspect, an instruction processing device is provided, the device comprising a processor; the processor is used to load and execute at least one instruction so that the instruction processing device implements the instruction processing method in the first aspect or any possible implementation manner of the first aspect.

[0020] In a possible implementation, the device further includes a memory, which is coupled to the processor and is used to store at least one instruction.

[0021] In a fourth aspect, a computer-readable storage medium is provided, in which at least one instruction is stored, and the instruction is loaded and executed by a processor to implement the instruction processing method in the first aspect or any possible implementation manner of the first aspect.

[0022] In a fifth aspect, a computer program (product) is provided, which includes a computer program / instructions, and the computer program / instructions are executed by a processor to enable a computer to implement the instruction processing method in the first aspect or any possible implementation of the first aspect.

[0023] In a sixth aspect, a communication device is provided, the device comprising: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path, the memory is used to store instructions, the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals, and when the processor executes the instructions stored in the memory, the processor executes the method in the first aspect or any possible implementation of the first aspect.

[0024] Optionally, there are one or more processors and one or more memories.

[0025] Optionally, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0026] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or can be set on different chips. This application does not limit the type of memory and the setting method of the memory and the processor.

[0027] In a seventh aspect, a chip is provided, comprising a processor for calling and executing program instructions or codes stored in a memory, so that a communication device equipped with the chip executes the methods in the above aspects.

[0028] In an eighth aspect, another chip is provided, comprising: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute the methods in the above aspects.

[0029] It should be understood that the beneficial effects achieved by the technical solutions of the second to eighth aspects of the present application and the corresponding possible implementation methods can be referred to the above-mentioned technical effects of the first aspect and its corresponding possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of an implementation environment provided for an embodiment of the present application;

[0031] Figure 2 A flowchart of an instruction processing method provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the structure of an instruction provided in an embodiment of the present application;

[0033] Figure 4 A schematic diagram of a process of instruction storage provided by an embodiment of the present application;

[0034] Figure 5 A schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0035] Figure 6 A flowchart of an instruction storage provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of another instruction storage process provided by an embodiment of the present application;

[0037] Figure 8 A schematic diagram of another instruction storage process provided in an embodiment of the present application;

[0038] Fig. 9 A schematic diagram of another instruction storage process provided in an embodiment of the present application;

[0039] Fig.10 A schematic diagram of the structure of an instruction processing device provided in an embodiment of the present application;

[0040] Fig.11A schematic diagram of the structure of a network device provided in an embodiment of the present application;

[0041] Fig.12 A schematic diagram of the structure of another network device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The terms used in the implementation method of this application are only used to explain the specific embodiments of this application, and are not intended to limit this application. In order to make the purpose, technical solution and advantages of this application clearer, the implementation method of this application will be further described in detail below with reference to the accompanying drawings.

[0043] In the field of information technology, the processor is the computing and control core of network devices and the execution unit of program operation. The processor loads the instructions of the application program to enable the application program to run. Among them, the processor includes a storage unit, which is used to store the instructions to be loaded. The processor needs to store the instructions in the storage unit first, and then read the instructions stored in the storage unit for subsequent operations, thereby realizing the loading of instructions.

[0044] In the related art, an instruction bundle includes multiple instructions, and the instruction bundle is, for example, a very long instruction word (VLIW). Each instruction in the multiple instructions included in the instruction bundle carries boundary information, and the boundary information is used to identify the boundary of the instruction bundle. The boundary information is, for example, a boundary bit. After obtaining the instruction bundle to be processed, the instructions included in the instruction bundle to be processed are stored in the storage unit of the same row included in the processor. In addition, since the instruction is determined by the boundary information to determine the instruction bundle in which the instruction is located, it is necessary to store the multiple instructions included in the same instruction bundle continuously in the storage unit. The above processing method stores the multiple instructions included in the instruction bundle continuously in the storage unit, and the instructions included in different instruction bundles need to be stored separately, which has poor storage flexibility. When an unoccupied idle unit appears between the instructions included in an instruction bundle, the idle unit cannot be occupied by other instruction bundles, and the utilization rate of the storage unit is low.

[0045] Please refer to Figure 1 , which shows a schematic diagram of an implementation environment of the instruction processing method provided in an embodiment of the present application, the implementation environment includes a processing device 1, the processing device 1 includes a processor 11, and the processor 11 includes multiple storage units. Among them, the processing device 1 is used to store the instructions included in the instruction bundle to be processed in the storage unit included in the processor 11 according to the instruction processing method provided in an embodiment of the present application.

[0046] Exemplarily, the processor 11 may be any module for loading instructions, for example, the processor 11 may be a programmable processor, an accelerator or a coprocessor, etc., the processing device 1 may be any device having an instruction processing function, and the processing device 1 may be a server, for example, the processing device 1 may be a central server, an edge server, or a local server in a local data center. The server may be a physical server, or a cloud server that provides cloud computing services in a cloud scenario. In some embodiments, the processing device 1 may also be a terminal device such as a desktop, a laptop or a smart phone, or a switch, a router and a gateway (GW), etc.

[0047] The flowchart of the instruction processing method provided in the embodiment of the present application is as follows Figure 2 As shown, including S201-S202.

[0048] S201, determining in a processor a first storage unit corresponding to a first instruction bundle to be processed, wherein the first instruction bundle includes a first instruction, the first instruction carries a first identifier of the first instruction bundle, and the processor further includes a computing unit corresponding to the first storage unit.

[0049] Exemplarily, an instruction refers to a command for commanding a processing device to work after compiling an application program, and the processing device is, for example, a personal computer (PC), and the application program corresponding to the instruction can be any application program with operation requirements, such as game applications, video applications, and social applications. In a possible implementation, the multiple instructions obtained by compilation can be divided into different instruction bundles, and the instruction bundle is, for example, a very long instruction word (VLIW). The instructions included in VLIW can be divided according to the functions corresponding to the instructions, or according to the applications corresponding to the instructions, or according to other methods, and the embodiments of the present application are not limited to this. Multiple instructions are connected together through VLIW to achieve instruction-level parallelism and improve the processing speed of the processing device on the instructions.

[0050] Optionally, the instruction carries an identifier of an instruction bundle corresponding to the instruction, and the instruction bundle corresponding to the instruction refers to an instruction bundle including the instruction. Figure 3 A schematic diagram of the structure of an instruction provided in an embodiment of the present application, see Figure 3In the figure below, an instruction includes operation information and an identifier of an instruction bundle. The operation information is used to control the operation of the computing unit. In some cases, the operation information can be configured in the computing unit profile (arithmetic and logic unit profile, ALU profile). For example. The computing unit is a unit included in the processor, which is used to calculate the instruction, and the computing unit corresponds to the storage unit. If the instruction bundle is VLIW, the identifier of the instruction bundle is the VLIW identity document (VLIW ID). If the VLIW ID of the VLIW corresponding to the instruction is 1, it means that the identifier of the instruction bundle carried by the instruction is 1. The embodiment of the present application does not limit the way in which the identifier of the instruction bundle is carried. It can be to add a new field in the instruction to carry the identifier of the instruction bundle, or to replace the information originally carried in the instruction, for example Figure 3 As shown, the boundary bit originally carried in the instruction is replaced with the identifier of the instruction bundle, so that the identifier of the instruction bundle is carried without increasing the data size of the instruction or changing the original structure of the instruction.

[0051] In the process of processing instructions, the processing device processes multiple instructions included in the instruction bundle in parallel, taking the instruction bundle as a unit, so as to improve the processing efficiency. In a possible implementation, the processing device calls the configured processor to process the instruction bundle. For example, after receiving the instruction bundle, the processing device stores the instructions included in the instruction bundle to be processed in the storage unit included in the storage module, and then the processor can read the instructions stored in the storage unit to load the instructions, for example Figure 4 shown.

[0052] The embodiment of the present application does not limit the number of instruction bundles to be processed, which can be 1 or more. Figure 4 The number of instructions included in different instruction bundles may be the same or may be Figure 4 Since the processes of storing different instruction bundles in the processing device are similar, the first instruction bundle is taken as an example to illustrate the storage of the first instruction included in the first instruction bundle.

[0053] In one possible case, a storage unit is provided in the processor through a storage module for instruction storage, for example Figure 5As shown, the storage module for storing instructions includes a plurality of storage units, and the plurality of storage units are divided into a plurality of rows, and a row includes a plurality of storage units. In some embodiments, the instructions stored in the first row of storage units may be processed first, and then the instructions stored in the second row of storage units may be processed. Therefore, the instructions included in the same instruction bundle may be stored in the storage units in the same row, and the execution time of each function of the program corresponding to the control instruction bundle is 1 beat, so as to simplify the pipeline logic. Among them, 1 beat refers to the time of sampling an external signal once.

[0054] Therefore, before storing the first instruction included in the first instruction bundle, the processing device first determines the first storage unit corresponding to the first instruction bundle in the processor to clarify the storage unit in which row the first instruction bundle needs to be stored, that is, the first before the first storage unit is intended to identify the storage unit located in a certain row, rather than to indicate a certain storage unit. Optionally, the process of determining the first storage unit corresponding to the instruction bundle includes: determining the storage index of the first instruction bundle; determining the first storage unit in the processor according to the storage index, and the number of rows of the first storage unit in the storage module is determined according to the storage index.

[0055] The embodiment of the present application does not limit the method for determining the storage index of the first instruction bundle. The processing device may determine the initial index as the storage index of the first instruction bundle. The initial index may be any integer not less than 0 set based on experience. For example, if the initial index is set to 0, the processing device determines that the storage index of the first instruction bundle is the initial index 0 when the first instruction bundle needs to be written into the processor.

[0056] After determining the storage index of the first instruction bundle, the processing device determines the first storage unit among the multiple storage units included in the storage module. The first storage unit corresponding to the first instruction bundle refers to the storage unit whose row number identifier is determined according to the storage index, and the storage index can be determined as the row number identifier. Taking the storage index as 0 as an example, the first storage unit is the storage unit with the row number identifier of 0 in the storage module. For example Figure 5 As shown, the storage units with a row number identifier of 0 are a plurality of storage units in the first row from top to bottom, and the plurality of storage units are all first storage units.

[0057] S202, the number of free cells in the first storage unit is not less than the number of storage cells occupied by the first instruction bundle, and the computing units corresponding to the free cells meet the computing requirements of the first instruction bundle, the first instruction is stored in the free cells, and the computing units are used to calculate the selected instruction based on the first identifier of the first instruction bundle.

[0058] After determining the first storage unit, the processing device needs to determine whether the first storage unit can store the first instruction bundle, that is, whether the first instruction bundle can be stored in this row of storage units. The processing device determines whether the number of free units is not less than the number of storage units occupied by the first instruction bundle, wherein the free unit refers to a storage unit that does not store instructions.

[0059] The number of storage units occupied refers to the number of storage units required for the first instruction, and the number of storage units occupied is not less than the number of first instructions included in the first instruction bundle. A first instruction included in the first instruction bundle can be stored in one storage unit or in multiple storage units. For example, in some cases, the compressed data size of the first instruction included in the first instruction bundle is still larger than the capacity of a storage unit, and multiple adjacent storage units need to be called to store the first instruction. The processing device counts the number of storage units that each first instruction included in the first instruction bundle needs to occupy, and adds the number of storage units that each first instruction needs to occupy to obtain the number of storage units occupied by the first instruction bundle. Taking the example that the number of first instructions included in the first instruction bundle is 3 and one first instruction needs to occupy one storage unit, the number of storage units occupied is 3.

[0060] Exemplarily, in the process of determining whether the number of free cells is not less than the number of storage cells occupied by the first instruction bundle, the processing device may perform the following steps: Figure 6 As shown, after executing S601-S602, when there is a first instruction bundle to be processed and the first storage unit corresponding to the first instruction bundle is determined, it is determined whether there is a free (nop) unit in the first storage unit corresponding to the first instruction bundle.

[0061] Processing equipment can be Figure 6 As shown in S603, count whether the number of first storage cells stored in the first storage cell is less than the maximum storable value, wherein the maximum storable value is equal to the total number of first storage cells. When the number of first storage cells stored is not less than the maximum storable value, it is determined that the first storage cells are all occupied and there are no free cells. Optionally, the processing device may also count whether the number of instructions stored in the first storage cell is less than the maximum storable value when an instruction is stored in a first storage cell, and when the number of stored instructions is not less than the maximum storable value, it is determined that the first storage cell is all occupied. The processing device thus determines that the number of free cells existing in the first storage cell is 0, which is less than the number of storage cells occupied by the first instruction bundle.

[0062] In the case where there are free cells in the first storage unit, the processing device can further determine whether the number of free cells is not less than the number of storage cells occupied by the first instruction bundle. For example, the difference between the maximum value that can be stored and the number of first storage cells that have been stored is calculated, the difference is used as the number of free cells, and then the relationship between the number of free cells and the number of storage cells occupied is compared. Taking the example that the number of instructions included in the instruction bundle is 3 and the number of storage cells occupied is 3, when the number of free cells in the first storage unit is 3, one first instruction occupies one free cell, which can satisfy the requirement of storing multiple first instructions included in the first instruction bundle in the first storage unit, so as to satisfy the requirement of storing multiple first instructions included in the first instruction bundle in the same row of storage cells of the storage module.

[0063] In one possible case, the processor further includes a computing unit for performing calculations according to the instruction, and the instruction may be the first instruction included in the first instruction bundle, or may be other instructions. In some cases, multiple computing units may be included in a computing module in the processor, and the computing module may be, for example, a parallel arithmetic and logic unit (parallel ALU). The computing unit for calculating the instruction has a constraint relationship with the storage unit of the instruction, and the constraint relationship is, for example, that the number of columns of the storage unit is the same as the number of columns of the computing unit. For example Figure 5 As shown in the structural diagram of the processor, the instructions stored in the storage units in the first column from left to right will be sent by the decoding module to the computing units in the first column from left to right, the instructions that the computing units in the first column are responsible for calculating are the instructions stored in the storage units in the first column, and the instructions that the computing units in the second column are responsible for calculating are the instructions stored in the storage units in the second column.

[0064] In one possible case, different computing units can perform different calculations. For example, computing unit A is used to execute the move_byte (move_byte, MOV_B) instruction, which moves the input byte to the output byte through calculation to achieve byte movement; computing unit B is used to execute the move_float (MOV_R) instruction, which moves the input floating-point number to the output floating-point number through calculation to achieve floating-point number movement. Different instructions will limit the operations performed by the computing units. For example, instruction A belongs to the MOV_B instruction, which is used to limit the computing unit to perform byte movement, and instruction B belongs to the MOV_R instruction, which is used to limit the computing unit to perform floating-point number movement. Instruction A needs to be stored in the storage unit corresponding to computing unit A to ensure that instruction A can be successfully calculated by computing unit A, and instruction B needs to be stored in the storage unit corresponding to computing unit B to ensure that instruction B can be successfully calculated by computing unit B.

[0065] Therefore, when the processing device stores the first instruction bundle in the first storage unit, it also needs to consider the computing requirements of the first instruction bundle. That is, in addition to performing the operation of determining whether the number of unstored free cells in the first storage unit is greater than the number of occupied storage cells in S604, the processing device also determines whether the computing unit corresponding to the free cell meets the computing requirements of the first instruction bundle.

[0066] Optionally, the processing device obtains hardware parameters of the computing unit corresponding to each idle unit in the first storage unit, obtains functional information of the computing unit according to the hardware parameters, and determines a matching result of the operating information and the functional information according to the operating information included in the first instruction. When the operating information of any first instruction included in the first instruction bundle successfully matches the functional information of the computing unit, and different computing units matched by different first instructions are different, the processing device determines that the computing unit corresponding to the idle unit meets the computing requirements of the first instruction bundle.

[0067] Continuing with the example of the first instruction bundle including three first instructions, the operation information of the first instruction 1 is to control the computing unit to perform operation A, the operation information of the first instruction 2 is to control the computing unit to perform operation A, and the operation information of the first instruction 3 is to control the computing unit to perform operation B. The three computing units corresponding to the three idle units in the first storage unit include computing unit 1, computing unit 2, and computing unit 3. Among them, computing unit 1 and computing unit 2 are used to perform operation A, and computing unit 3 is used to perform operation B. Since computing unit 1 and computing unit 2 can execute first instruction 1 and first instruction 2, and computing unit 3 can execute first instruction 3. Therefore, the computing units corresponding to the idle units in the first storage unit meet the computing requirements of the first instruction bundle. That is Figure 6 The type and number of computing units used by the first instruction bundle summarized in S605 satisfy the type and number of computing units corresponding to the idle units, wherein the type refers to the function of the computing unit and can be determined according to the functional information of the computing unit.

[0068] When the processing device determines that the first storage unit can store the first instruction included in the first instruction bundle, it will execute Figure 6 The first instruction included in the first instruction bundle is stored in the free unit in S606 operation. Taking the storage unit in the processor as a unit included in the storage module as an example, the processing device sends the first instruction bundle and the storage address of the first instruction bundle to the storage module of the processor. The storage address can be an address of the storage module, such as an instruction memory entry address (IMEM entry address).

[0069] After receiving the first instruction bundle and the storage address of the first instruction bundle, the storage module will write the first instruction included in the first instruction bundle into the free cell in the first storage unit included in the storage module according to the storage address, so as to realize the storage of the first instruction bundle. In the case where the first instruction bundle includes multiple first instructions, one first instruction will be stored in at least one free cell, that is, multiple first instructions will be stored in multiple free cells, and the multiple free cells are located in the same row of the processor. Because the processing device stores the first instruction included in the first instruction bundle in the free cell, it stores it according to the computing unit corresponding to the free cell. Therefore, when the computing units capable of executing the first instruction included in the first instruction bundle are not adjacent, the first instruction included in the first instruction bundle will not be stored adjacently.

[0070] Figure 7 A schematic diagram of an instruction storage process provided in an embodiment of the present application shows two instruction storage situations. Figure 7 (1) is the first storage situation. The instruction bundles to be processed are instruction bundle 0 and instruction bundle 1. Instruction bundle 0 corresponds to the first instruction bundle, and instruction bundle 1 corresponds to the second instruction bundle. Instruction bundle 0 includes mov_1B(0) instruction and mov_2B(0) instruction. Instruction bundle 1 includes mov_2B(1) instruction and mov_1B(1) instruction. The number before the letter B in mov_1B(0) and mov_2B(0) indicates the number of bytes moved. The number in the brackets is used to distinguish the instruction bundles to which the instructions correspond. Taking mov_1B(0) as an example, it is represented by the mov_1B instruction included in instruction bundle 0. The functional information of each computing unit included in the processor is as follows: Figure 7 As shown, all support general_1byte (general_1B) operations, that is, support all operations on instruction calculations, including mov_1B and mov_2B. In addition, different computing units have different corresponding data bit widths, and the corresponding data bit width positions are also different. For example, the data bit width position is Figure 7 The high position (high, H) and low position (low, L) in.

[0071] According to the above instruction storage operation, the processing device stores the mov_1B(0) instruction and the mov_2B(0) instruction included in the instruction bundle 0 to be processed in the respective Figure 7 In the storage unit shown in (1). There is a storage unit between the mov_1B(0) instruction and the mov_2B(0) instruction, and the mov_1B(0) instruction and the mov_2B(0) instruction are not stored adjacent to each other. For the storage unit with a gap, other instruction bundles can be stored if they can store instructions included in other instruction bundles. For example Figure 7The storage unit between the mov_1B(0) instruction and the mov_2B(0) instruction in (1) can be used to store the mov_1B(1) instruction included in instruction bundle 1. Figure 7 The second storage case shown in (2) and Figure 7 The storage situation in (1) is similar, and the instructions included in instruction bundle 2 and instruction bundle 3 are also interleaved. Figure 7 It can be seen that the first instruction included in the first instruction bundle and the second instruction included in the second instruction bundle can be stored alternately in the storage units of the same row, and the second identifier of the second instruction bundle is different from the first identifier of the first instruction bundle.

[0072] The above is a process of storing the first instruction when the first storage unit is capable of storing the first instruction included in the first instruction bundle. In one possible case, Figure 6 As shown, when the number of free cells in the first storage unit is less than the number of storage units occupied by the first instruction bundle, or the computing unit corresponding to the free cell does not meet the computing requirements of the first instruction bundle, the processing device will also perform the operation of S607 to adjust the storage index; store the first instruction included in the first instruction bundle in the storage unit included in the processor according to the adjusted storage index. Among them, the number of free cells less than the number of storage unit occupancy includes the absence of free cells, and the relevant description of the absence of free cells can refer to the relevant description in the above embodiments. When the number of free cells and the computing unit corresponding to the free cells meet any of the above conditions, the processing device determines that the first storage unit cannot store the first instruction included in the first instruction bundle, and adjusts the storage index, for example, by adding one to the storage index. After that, a row of storage cells that can store the first instruction bundle is re-determined according to the adjusted storage index, and the above instruction storage method is executed to store the first instruction included in the first instruction bundle in the processor.

[0073] Regardless of the first instruction included in the first instruction bundle stored in the processor, the processing device can call the processor to process the stored first instruction after completing the instruction storage. The processing process is, for example, determining the first instruction included in the first instruction bundle that is allowed to be calculated according to the first identifier of the first instruction bundle carried by the first instruction by the decoding unit included in the processor; and calculating the first instruction included in the first instruction bundle that is allowed to be calculated by the calculation unit included in the processor to obtain result data. Optionally, the decoding unit is a unit in a decoding module included in the processor, and the decoding module is, for example, a parallel decoding module (parallel decoder). The storage module sends multiple instructions to multiple decoding units included in the processor, and the multiple instructions include the first instruction included in the first instruction bundle that needs to be processed, and the multiple instructions are instructions stored in a row of storage units of the storage module.

[0074] Optionally, the instructions stored in a row of storage units sent by the storage module may be instructions stored in a whole row of storage units. Since a whole row of instructions may be instructions included in multiple instruction bundles, there may be instruction bundles that are allowed to be calculated and instruction bundles that are not allowed to be calculated in different instruction bundles. For example, there are differences in the execution times of multiple instruction bundles. Among the multiple instruction bundles, there is a first instruction bundle that is allowed to be calculated at the current time, and there is a second instruction bundle that is not allowed to be calculated after the current time. Therefore, after receiving the instruction, the decoding unit needs to process the received instruction to determine whether the received instruction is the first instruction included in the first instruction bundle that is allowed to be calculated.

[0075] Exemplarily, a decoding unit is used to process instructions stored in a storage unit, and the process of the decoding unit processing instructions includes: obtaining a reference identifier, the reference identifier is a first identifier of a first instruction bundle allowed to be calculated; obtaining a matching result between the first identifier of a first instruction bundle carried by the first instruction and the reference identifier, and determining the first instruction included in the first instruction bundle allowed to be calculated based on the matching result.

[0076] In a possible implementation, the processing device determines the instruction bundle that is allowed to be calculated according to the instruction loading situation inside the device, and determines the reference identifier according to the identifier of the instruction bundle that is allowed to be calculated, and sends the reference identifier to multiple decoding units included in the processor, and each of the multiple decoding units obtains the reference identifier. Optionally, the processing device can be in the process of sending the instruction bundle to the storage module according to the IMEM entry address, synchronously sending the reference identifier to the decoding module, the reference identifier clearly identifies the instruction bundle to be processed, and when the instruction bundle to be processed is the first instruction bundle, the reference identifier is the first identifier. After receiving the reference identifier, the decoding module synchronizes the reference identifier to each decoding unit included. Afterwards, the decoding unit determines the matching result between the identifier of the instruction bundle carried by the received instruction and the reference identifier.

[0077] For example Figure 5 As shown, the decoding unit reads the stored instructions from the connected storage unit, and then parses the acquired instructions, determines the identifier of the instruction bundle carried by the instruction according to the parsing result, and matches the identifier of the instruction bundle with the reference identifier. When the identifier of the instruction bundle is the same as the reference identifier, for example, the reference identifier is 0 and the identifier of the instruction bundle is also 0, it is determined that the identifier of the instruction bundle and the reference identifier match successfully, and the instruction belongs to the first instruction included in the first instruction bundle currently allowed to be calculated, and can be processed at the current moment. When the identifier of the instruction bundle and the reference identifier are different, for example, the reference identifier is 0 and the identifier of the instruction bundle is 1, it is determined that the identifier of the instruction bundle and the reference identifier match failed, and the instruction does not belong to the first instruction included in the first instruction bundle currently allowed to be calculated, that is, the instruction cannot be processed at the current moment.

[0078] In the process of calling the processor to determine the first instruction included in the first instruction bundle that is allowed to be calculated, it is executed in parallel by multiple decoding units. Even if the first instruction bundle and other instruction bundles are interleaved and stored in the same row of storage units, it will not affect the decoding unit's determination of the first instruction included in the first instruction bundle, thereby achieving flexible storage of instructions and efficient use of storage units. In addition, parallel filtering has low timing requirements for the processor and is more versatile.

[0079] In addition, after determining the first instruction included in the first instruction bundle that is allowed to be calculated, the decoding unit will send the first instruction included in the first instruction bundle that is allowed to be calculated to the computing unit included in the processor. Optionally, the computing unit that receives any instruction corresponds to the storage unit of any instruction. In the case where the processor includes multiple decoding units, the multiple decoding units and the computing unit are connected. For example Figure 7 As shown, after the decoding unit matches the identifier and reference identifier of the instruction bundle carried by the instruction, if the matching result is a successful match, the decoding unit sends the instruction to the connected computing unit. If the matching result is a failed match, the decoding unit suspends sending instructions to the computing unit. Since the suspension of sending may be sent after a period of time, Figure 7 The dashed arrow in the figure indicates the situation of suspending sending. The decoding unit is controlled to send instructions to the computing unit to ensure that the instructions received by the computing unit are all the first instructions included in the first instruction bundle currently allowed to be calculated, and then the computing unit calculates the first instructions included in the first instruction bundle allowed to be calculated to obtain result data.

[0080] In a possible implementation, the first instruction sent by the decoding unit to the computing unit refers to operation information included in the first instruction. The operation information is, for example, Figure 3 The decoding unit sends the parsed operation information to the connected computing unit, and the computing unit parses the received operation information, thereby determining the operation to be performed, and starts to perform, thereby obtaining multiple result data, and determining the result data as the result of the program running.

[0081] The embodiments of the present application do not limit the modules included in the processing device, and may include other modules besides the processor. For example, the processing device also includes a compiler, and a communication connection is established between the compiler and the processor. A control relationship is realized through the communication connection. The compiler is used to execute operations such as storing the instructions included in the instruction bundle in the storage unit included in the processor and determining the reference identifier in the above embodiments S201-S202.

[0082] In summary, the instruction processing method provided in the embodiment of the present application carries the first identifier of the first instruction bundle in the first instruction. Therefore, the processing device can store the first instruction and the instructions included in other instruction bundles in an interleaved manner during the storage of the first instruction, which has high storage flexibility and can also avoid wasting storage space. Figure 8 and Fig. 9 As shown, Figure 8 and Fig. 9 Description of instruction bundles and computational units in Figure 7 The description of the instruction bundle and computation unit in is similar, please refer to Figure 7 The relevant description will not be repeated here. Figure 8 and Fig. 9 (1) in the figure is an instruction bundle stored using the related technology. Since multiple decoding units in the related technology serially identify the boundary information included in the instruction, when the boundary information is set, the instruction is determined to be the boundary of the instruction bundle, and the multiple instructions previously identified are determined to be the instructions included in the instruction bundle. Therefore, the instructions included in the same instruction bundle need to be stored continuously to avoid the recognition error of the instructions included in the instruction bundle. Figure 8 When the storage unit between the mov_1B(0) instruction and the mov_2B(0) instruction included in the instruction bundle 0 in (1) cannot store the instructions included in the instruction bundle 0, if the storage unit is used to store the instructions included in the instruction bundle 1, the instructions stored in the storage unit will be recognized as the instructions included in the instruction bundle 0, resulting in an instruction recognition error. Therefore, the storage unit cannot be used to store the instructions included in the instruction bundle 1, resulting in a waste of storage units. Figure 8 and Fig. 9 (2) is an instruction stored by the instruction processing method provided in the embodiment of the present application. Figure 8 and Fig. 9 It can be seen that the instruction processing method provided in the embodiment of the present application can avoid the waste of storage units and effectively improve the space utilization of storage units.

[0083] In addition, the instruction processing method provided in the embodiment of the present application can be adapted to different computing units. Even if the application program changes, resulting in changes in the functions and number of computing units required by the instructions corresponding to the application program, the instructions can still be stored in the storage unit by comparing the number of free units and the computing requirements of the first instruction bundle, thereby ensuring efficient storage efficiency. In the process of determining the first instruction included in the first instruction bundle from multiple instructions, the decoding unit can achieve the determination of the instruction bundle by matching the identifier carried by the instruction with the reference identifier, and the decoding logic is simpler. Multiple decoding units determine multiple instructions in parallel, and the parallel determination takes less time and is more efficient than the serial determination of the related art, and reduces the timing requirements for the processor, and can be applied to more processors with high versatility.

[0084] The above describes the instruction processing method of the embodiment of the present application. Corresponding to the above method, the embodiment of the present application also provides an instruction processing device. Fig.10 Schematic diagram of the structure of an instruction processing device provided in an embodiment of the present application. Fig.10 As shown in the following multiple modules, the Fig.10 The instruction processing device shown is capable of executing the above Figure 2 It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown, and the embodiments of the present application are not limited to this. Fig.10 As shown, the device comprises:

[0085] A determination module 1001 is used to determine in a processor a first storage unit corresponding to a first instruction bundle to be processed, where the first instruction bundle includes a first instruction, the first instruction carries a first identifier of the first instruction bundle, and the processor further includes a computing unit corresponding to the first storage unit;

[0086] Storage module 1002 is used to store the first instruction in the idle unit when the number of idle units in the first storage unit is not less than the number of storage units occupied by the first instruction bundle and the computing unit corresponding to the idle unit meets the computing requirements of the first instruction bundle. The computing unit is used to calculate the selected instruction based on the first identifier of the first instruction bundle.

[0087] In a possible implementation, the determination module 1001 is used to determine a storage index of the first instruction bundle; determine a first storage unit in the processor according to the storage index, and the number of rows of the first storage unit in the processor is determined according to the storage index.

[0088] In one possible implementation, the storage module 1002 is also used to adjust the storage index when the number of free units in the first storage unit is less than the number of storage units occupied by the first instruction bundle, or the computing units corresponding to the free units do not meet the computing requirements of the first instruction bundle; and store the first instruction included in the first instruction bundle in the storage unit included in the processor according to the adjusted storage index.

[0089] In a possible implementation, the first instruction bundle includes multiple first instructions, and the multiple free cells where the multiple first instructions are stored are located in the same row of the processor.

[0090] In a possible implementation, a first instruction included in the first instruction bundle and a second instruction included in the second instruction bundle are stored alternately in storage units in the same row, and a second identifier of the second instruction bundle is different from a first identifier of the first instruction bundle.

[0091] In one possible implementation, the device also includes: a processing module, used to determine the first instruction included in the first instruction bundle that is allowed to be calculated based on the first identifier of the first instruction bundle carried by the first instruction through a decoding unit included in the processor; and calculate the first instruction included in the first instruction bundle that is allowed to be calculated through a computing unit included in the processor to obtain result data.

[0092] In one possible implementation, a processing module is used to obtain a reference identifier, where the reference identifier is a first identifier of a first instruction bundle that is allowed to be calculated; obtain a matching result between the first identifier of a first instruction bundle carried by a first instruction and the reference identifier, and determine a first instruction included in the first instruction bundle that is allowed to be calculated based on the matching result.

[0093] Since the above-mentioned device can realize instruction selection according to the first identifier of the first instruction bundle when it is necessary to select the first instruction included in the first instruction bundle for calculation, and each first instruction carries the first identifier, therefore, the storage position of the first instruction in the storage unit does not affect the selection of the first instruction, and the instructions included in different instruction bundles can be stored alternately during the instruction storage process, the storage flexibility is high, and the utilization rate of the storage unit is high.

[0094] It should be understood that the above Fig.10 When the device provided realizes its functions, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0095] See also Fig.11 , Fig.11 A schematic diagram of the structure of a network device 1100 provided by an exemplary embodiment of the present application is shown. Fig.11 The network device 1100 shown is used to perform the above Figure 2 The operations involved in the instruction processing method shown. The network device 1100 is, for example, a switch, a router, etc. The network device 1100 can be implemented by a general bus architecture.

[0096] like Fig.11 As shown, the network device 1100 includes at least one processor 1101 , a memory 1103 , and at least one communication interface 1104 .

[0097] Processor 1101 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing units (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, processor 1101 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present application. The processor can also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0098] Optionally, the network device 1100 further includes a bus. The bus is used to transmit information between the components of the network device 1100. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.11 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0099] The memory 1103 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1103 is, for example, independent and connected to the processor 1101 via a bus. The memory 1103 can also be integrated with the processor 1101.

[0100] The communication interface 1104 uses any transceiver-like device for communicating with other devices or communication networks, and the communication network can be Ethernet, a radio access network (RAN) or a wireless local area network (WLAN), etc. The communication interface 1104 may include a wired communication interface and may also include a wireless communication interface. Specifically, the communication interface 1104 may be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface or a combination thereof. The Ethernet interface may be an optical interface, an electrical interface or a combination thereof. In an embodiment of the present application, the communication interface 1104 may be used for the network device 1100 to communicate with other devices.

[0101] In a specific implementation, as an embodiment, the processor 1101 may include one or more CPUs, such as Fig.11 0 and CPU1 shown in FIG. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0102] In a specific implementation, as an embodiment, the network device 1100 may include multiple processors, such as Fig.11 1 and 1105. Each of these processors may be a single-CPU or a multi-CPU. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0103] In a specific implementation, as an embodiment, the network device 1100 may also include an output device and an input device. The output device communicates with the processor 1101 and can display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 1101 and can receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0104] In some embodiments, the memory 1103 is used to store the program code 1110 for executing the solution of the present application, and the processor 1101 can execute the program code 1110 stored in the memory 1103. That is, the network device 1100 can implement the instruction processing method provided by the method embodiment through the processor 1101 and the program code 1110 in the memory 1103. The program code 1110 may include one or more software modules. Optionally, the processor 1101 itself can also store the program code or instruction for executing the solution of the present application.

[0105] In a specific embodiment, the network device 1100 of the embodiment of the present application may correspond to the processing device in each of the above method embodiments. Optionally, the network device 1100 may also include a compiler, and the compiler is used to control the processor 1101.

[0106] in, Figure 2Each step of the instruction processing method shown is completed by an integrated logic circuit of hardware or an instruction in software form in the processor of the network device 1100. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in the processor for execution. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory, and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0107] Fig.12 It is a structural diagram of another network device provided in an embodiment of the present application. The network device is, for example, a server. The server may have relatively large differences due to different configurations or performances. It may include one or more processors 1201 and one or more memories 1202, wherein at least one computer program is stored in the one or more memories 1202, and the at least one computer program is loaded and executed by the one or more processors 1201, so that the server implements the instruction processing method provided by the above-mentioned various method embodiments. The processor 1201 is, for example, a central processing unit (CPU). Of course, the network device may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The network device may also include other components for implementing device functions, such as a compiler, etc., which will not be repeated here.

[0108] The embodiment of the present application also provides a communication device, which includes: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path, the memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals, and when the processor executes the instructions stored in the memory, the processor executes the instruction processing method.

[0109] It should be understood that the processor may be a CPU, or other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting an advanced RISC machines (ARM) architecture.

[0110] Further, in an optional embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0111] The memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile memory may be a ROM, a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an EEPROM or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (static RAM, SRAM), dynamic random access memory (dynamic random access memory, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) and direct memory bus random access memory (direct rambus RAM, DR RAM).

[0112] The embodiment of the present application also provides an instruction processing device, the device includes a processor, the processor is used to load and run at least one instruction, so that the instruction processing device implements the instruction processing method provided by the embodiment of the present application. Optionally, the device also includes a memory, the memory is coupled to the processor, and the memory is used to store at least one instruction.

[0113] An embodiment of the present application also provides a computer-readable storage medium, in which at least one instruction is stored. The instruction is loaded and executed by a processor so that the computer implements any of the instruction processing methods described above.

[0114] The embodiments of the present application also provide a computer program (product), which, when executed by a computer, can enable a processor or a computer to execute the corresponding steps and / or processes in the above method embodiments.

[0115] An embodiment of the present application also provides a chip, which includes a processor for calling and executing instructions stored in a memory from the memory, so that a communication device equipped with the chip executes any of the instruction processing methods described above.

[0116] An embodiment of the present application also provides another chip, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute any of the instruction processing methods described above.

[0117] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk), etc.

[0118] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions. For example, the first instruction bundle involved in this application is obtained with full authorization.

[0119] Those of ordinary skill in the art will appreciate that, in conjunction with the various method steps and modules described in the embodiments disclosed herein, they can be implemented in software, hardware, firmware, or any combination thereof. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0120] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0121] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiment of the present application can be described in the context of a machine executable instruction, and the machine executable instruction is such as included in the program module executed in the device on the real or virtual processor of the target. Generally speaking, a program module includes a routine, a program, a library, an object, a class, a component, a data structure, etc., which performs a specific task or realizes a specific abstract data structure. In various embodiments, the function of the program module can be merged or divided between the described program modules. The machine executable instruction for the program module can be executed in a local or distributed device. In a distributed device, the program module can be located in both a local and a remote storage medium.

[0122] The computer program code for realizing the method for the embodiment of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable instruction processing device, so that the program code, when executed by a computer or other programmable instruction processing device, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on a computer, partially on a computer, as an independent software package, partially on a computer and partially on a remote computer or completely on a remote computer or server.

[0123] In the context of the embodiments of the present application, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like.

[0124] Examples of signals may include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0125] A machine-readable medium may be any tangible medium that contains or stores a program for or related to an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0126] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0127] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0128] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0129] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0130] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0131] In the present application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various described examples, a first image may be referred to as a second image, and similarly, a second image may be referred to as a first image. Both the first image and the second image may be images, and in some cases, may be separate and different images.

[0132] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0133] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple second messages means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0134] It should be understood that the terms used in the description of the various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0135] It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and / or" is a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0136] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0137] It should also be understood that the terms "if" and "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrases "if it is determined that ..." or "if [a stated condition or event] is detected" may be interpreted to mean "upon determining that ..." or "in response to determining that ..." or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0138] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0139] It should also be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. A command processing method, characterized in that: include: Determine in a processor a first storage unit corresponding to a first instruction bundle to be processed, wherein the first instruction bundle includes a first instruction, the first instruction carries a first identifier of the first instruction bundle, and the processor further includes a computing unit corresponding to the first storage unit; The number of free cells in the first storage unit is not less than the number of storage cells occupied by the first instruction bundle, and the computing unit corresponding to the free cell meets the computing requirements of the first instruction bundle, the first instruction is stored in the free cell, and the computing unit is used to calculate the selected instruction based on the first identifier of the first instruction bundle.

2. The method according to claim 1, characterized in that The determining in the processor a first storage unit corresponding to the first instruction bundle to be processed includes: determining a storage index of the first instruction bundle; The first storage unit is determined in the processor according to the storage index, and the number of rows of the first storage unit in the processor is determined according to the storage index.

3. The method according to claim 2, characterized in that After determining in the processor the first storage unit corresponding to the first instruction bundle to be processed, the method further includes: When the number of free cells in the first storage unit is less than the number of storage cells occupied by the first instruction bundle, or the computing units corresponding to the free cells do not meet the computing requirements of the first instruction bundle, adjusting the storage index; The first instruction included in the first instruction bundle is stored in a storage unit included in the processor according to the adjusted storage index.

4. The method according to any one of claims 1 to 3, characterized in that: The first instruction bundle includes a plurality of first instructions, and a plurality of free cells where the plurality of first instructions are stored are located in a same row of the processor.

5. The method according to any one of claims 1 to 4, characterized in that: The first instruction included in the first instruction bundle and the second instruction included in the second instruction bundle are stored alternately in the storage unit of the same row, and the second identifier of the second instruction bundle is different from the first identifier of the first instruction bundle.

6. The method according to any one of claims 1 to 5, characterized in that: The storing of the first instruction after the free unit, the method further comprises: Determining, by a decoding unit included in the processor, a first instruction included in the first instruction bundle that is allowed to be calculated according to a first identifier of the first instruction bundle carried by the first instruction; The first instruction included in the first instruction bundle allowed to be calculated is calculated by a calculation unit included in the processor to obtain result data.

7. The method according to claim 6, characterized in that The determining, according to the first identifier of the first instruction bundle carried by the first instruction, the first instruction included in the first instruction bundle that is allowed to be calculated comprises: Acquire a reference identifier, where the reference identifier is a first identifier of a first instruction bundle that allows calculation; A matching result between the first identifier of the first instruction bundle carried by the first instruction and the reference identifier is obtained, and the first instruction included in the first instruction bundle allowed to be calculated is determined according to the matching result.

8. An instruction processing device, characterized in that: include: a determination module, configured to determine, in a processor, a first storage unit corresponding to a first instruction bundle to be processed, wherein the first instruction bundle includes a first instruction, the first instruction carries a first identifier of the first instruction bundle, and the processor further includes a computing unit corresponding to the first storage unit; A storage module, used to store the first instruction in the idle cell when the number of idle cells in the first storage cell is not less than the number of storage cells occupied by the first instruction bundle and the computing unit corresponding to the idle cell meets the computing requirements of the first instruction bundle; the computing unit is used to calculate the selected instruction based on the first identifier of the first instruction bundle.

9. The device according to claim 8, characterized in that The determination module is used to determine a storage index of the first instruction bundle; determine the first storage unit in the processor according to the storage index, and the number of rows of the first storage unit in the processor is determined according to the storage index.

10. The device according to claim 9, characterized in that The storage module is further configured to adjust the storage index when the number of free cells in the first storage unit is less than the number of storage cells occupied by the first instruction bundle, or the computing unit corresponding to the free cell does not meet the computing requirement of the first instruction bundle; The first instruction included in the first instruction bundle is stored in a storage unit included in the processor according to the adjusted storage index.

11. The device according to any one of claims 8 to 10, characterized in that: The first instruction bundle includes a plurality of first instructions, and a plurality of free cells where the plurality of first instructions are stored are located in a same row of the processor.

12. The device according to claims 8-11, characterized in that The first instruction included in the first instruction bundle and the second instruction included in the second instruction bundle are stored alternately in the storage unit of the same row, and the second identifier of the second instruction bundle is different from the first identifier of the first instruction bundle.

13. The device according to any one of claims 8 to 12, characterized in that: The device also includes: a processing module, which is used to determine the first instruction included in the first instruction bundle that is allowed to be calculated according to the first identifier of the first instruction bundle carried by the first instruction through a decoding unit included in the processor; and calculate the first instruction included in the first instruction bundle that is allowed to be calculated through a calculation unit included in the processor to obtain result data.

14. The device according to claim 13, characterized in that The processing module is used to obtain a reference identifier, where the reference identifier is the first identifier of a first instruction bundle that is allowed to be calculated; obtain a matching result between the first identifier of the first instruction bundle carried by the first instruction and the reference identifier, and determine the first instruction included in the first instruction bundle that is allowed to be calculated based on the matching result.

15. An instruction processing device, characterized in that: The device comprises a processor, and the processor is used to load and execute at least one instruction, so that the instruction processing device implements the instruction processing method as described in any one of claims 1-7.

16. The device according to claim 15, characterized in that The device further includes a memory, which is coupled to the processor and stores at least one instruction.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one instruction, and the instruction is loaded and executed by the processor to implement the instruction processing method according to any one of claims 1 to 7.

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