A Memory Management Method, Device, Computer Device, and Storage Medium

Abstract

The present invention relates to the technical field of memory management, and discloses a memory management method, device, computer device and storage medium. Among them, the method includes: generating a status information matrix according to the usage status of each atomic memory block in the physical memory information; each element in the status information matrix is used to respectively indicate whether each atomic memory block is used, generating an index table array based on the status information matrix, the index table array includes an in-row index table array and a cross-row index table array, determining a target memory block corresponding to the memory application request based on the index table array, and updating the status information matrix and the index table array based on the target memory block. The present invention confines the memory management operation to a relatively small local range through the status information matrix and the index table array, without having to traverse the entire memory information linked list, effectively reducing the time overhead of memory search and improving the efficiency of memory management.

Description

Technical Field

[0001] The present invention relates to the technical field of memory management, and in particular, to a memory management method, device, computer device, and storage medium. Background Art

[0002] The types of computer services are increasing day by day, and the required memory sizes for running various services are also different. As the number of operations for memory application and release increases, the memory becomes fragmented, resulting in a situation where there is a lot of free memory but a continuous block of memory cannot be allocated.

[0003] Currently, the memory buddy algorithm is usually used for memory management to avoid the above-mentioned memory fragmentation as much as possible. This algorithm divides all free memory blocks into multiple block linked lists, and each linked list contains continuous memory blocks of a specific size, thereby achieving fine-grained management of memory. Specifically, when applying for memory, the memory buddy algorithm allocates and deletes the free pages in the memory block linked list of the same size as the application. If there is no memory block of the same size, it checks the upper level, and at the same time adds the remaining unallocated part to the lower-level free linked list. Memory release is the reverse process of the application.

[0004] However, in the above-mentioned memory management method, during the process of memory application and release, the iterative split / merge operation of memory and the traversal of the linked list will generate a large time overhead, which not only affects the efficiency and performance of memory application / release, but also, the memory merge operation of the above method has the limitation that the address of the first memory block needs to be an integer multiple of 2. Summary of the Invention

[0005] In view of this, the present invention provides a memory management method, device, computer device, and storage medium to solve the problem of low efficiency of the current memory management method based on the buddy algorithm.

[0006] In a first aspect, the present invention provides a memory management method, and the method includes:

[0007] Generating a status information matrix according to the usage status of each atomic memory block in the physical memory information; each element in the status information matrix is used to respectively indicate whether each atomic memory block is used;

[0008] Generating an index table array based on the status information matrix; the index table array includes an in-row index table array and an across-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; the memory blocks of different specifications are used to indicate continuous unused atomic memory blocks of different lengths in the status information matrix;

[0009] Determining a target memory block corresponding to the memory application request based on the index table array;

[0010] Update the status information matrix and the index table array based on the target memory block.

[0011] The memory management method provided by the embodiments of the present invention forms a status information matrix corresponding to the usage status of each atomic memory block, and generates an index table array based on the information status matrix. The design of the index table array enables the quick finding and allocation of consecutive unused memory blocks, reduces memory fragmentation, and thus improves the overall memory utilization rate. That is, through the index table, the system can quickly locate memory blocks of appropriate specifications without traversing the entire memory space, which greatly shortens the time for memory allocation and recycling and improves the system performance.

[0012] In an alternative embodiment, generating the index table array based on the status information matrix includes:

[0013] Generate an in-row index table array and an across-row index table array based on the status information matrix; the number of columns of both the in-row index table array and the across-row index table array is the number of memory block specifications, the number of rows of the in-row index table array is equal to the number of rows of the status information matrix, and the number of rows of the across-row index table array is 1 less than the number of rows of the in-row index table array.

[0014] The memory management method provided by the embodiments of the present invention can quickly locate memory blocks of appropriate specifications by converting the status information matrix into an index table array, including an in-row index table array and an across-row index table array. The index table array not only records the usage situation of memory blocks but also classifies them according to the specifications of memory blocks, thereby reducing the time for searching for unused memory blocks in the entire status information matrix. This indexing method accelerates the memory allocation process, improves the response speed and overall performance of the system. At the same time, by simplifying the complex memory status information into a structured index table array, the logic of memory management is also made clearer and easier to maintain.

[0015] In an alternative embodiment, determining the target memory block corresponding to the memory application request based on the index table array includes:

[0016] Based on the memory application request, determine the target area in the status information matrix in the index table array;

[0017] Select a target memory block corresponding to the size of the memory application request in the target area.

[0018] The memory management method provided by the embodiments of the present invention can quickly locate the area of the target memory block, that is, the area where there may be consecutive unused memory blocks that meet the requested size, in the status information matrix by setting the in-row index table array and the across-row index table array. This quick positioning mechanism avoids aimless or linear searching in the entire physical memory space, thus significantly improving the efficiency of memory allocation.

[0019] In an alternative embodiment, determining a target area in the status information matrix in the index table array based on a memory application request includes:

[0020] If there is an idle status memory block in the index table array with the same size as the memory application request, the area in the status information matrix corresponding to the idle status memory block is identified as the target area;

[0021] If there is no idle status memory block in the index table array with the same size as the memory application request, the area in the status information matrix corresponding to the idle status memory block with the smallest specification larger than the memory application request is identified as the target area.

[0022] The memory management method provided by the embodiments of the present invention first checks whether there is an idle memory block in the index table array with exactly the same size as the memory application request. If so, the target area is directly determined for the allocation of this memory block, which can maximize the satisfaction of the memory request requirements and reduce the generation of memory fragmentation. If there is no exactly matching memory block, the memory block with the smallest specification larger than the request size is selected to determine the target area. This strategy ensures the effective utilization of memory and avoids unnecessary memory waste.

[0023] In an alternative embodiment, selecting a target memory block with a size corresponding to the memory application request in the target area includes:

[0024] Selecting the target memory block with the smallest address in the target area and having a size corresponding to the memory application request.

[0025] The memory management method provided by the embodiments of the present invention selects the memory block with the smallest address for allocation, which helps to maintain the continuity of the memory space. At the same time, selecting the memory block with the smallest address for allocation can simplify the complexity of memory management.

[0026] In an alternative embodiment, the method further includes:

[0027] If the memory application request is successful, reply to the service layer with a memory application success message and the address of the target memory block; otherwise, reply to the service layer with a memory application failure message.

[0028] The memory management method provided by the embodiments of the present invention enables the service layer to immediately know the processing result of the memory request by replying to the service layer with the success or failure information of the memory application. If the memory application is successful, the service layer can obtain the address of the target memory block and continue to execute subsequent operations; if the memory application fails, the service layer can take timely remedial measures, such as releasing some memory that is no longer needed, attempting a smaller memory request, or notifying the user of insufficient memory resources. This immediate feedback helps to enhance the stability of the program and the user experience.

[0029] In an alternative embodiment, the method further includes:

[0030] In response to a memory release request, update the status information matrix and the index table array.

[0031] For the memory management method provided by the embodiments of the present invention, when a memory block is released, the status information matrix and the index table array are updated in a timely manner, which can ensure that these memory blocks are correctly marked as free and reused in subsequent memory allocation requests. This helps to improve the reuse rate of memory resources and reduce memory waste.

[0032] In an alternative embodiment, the method further includes:

[0033] If the memory release request is successful, reply to the service layer with a memory release success message; otherwise, reply to the service layer with a memory release failure message.

[0034] For the memory management method provided by the embodiments of the present invention, when the service layer receives a reply indicating successful memory release, it can release relevant resources more quickly. If the memory release fails, the service layer can take corresponding remedial measures, such as retrying the release operation, recording error logs, or notifying the user, which helps to enhance the stability of the program and the user experience.

[0035] In a second aspect, the present invention provides a memory management device, including:

[0036] A matrix generation module, configured to generate a status information matrix according to the usage status of each atomic memory block in the physical memory information; each element in the status information matrix is used to indicate whether each atomic memory block is in use;

[0037] An array generation module, configured to generate an index table array based on the status information matrix; the index table array includes an in-row index table array and a cross-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; memory blocks of different specifications are used to indicate different lengths of consecutive unused atomic memory blocks in the status information matrix;

[0038] A determination module, configured to determine a target memory block corresponding to a memory application request based on the index table array;

[0039] An update module, configured to update the status information matrix and the index table array based on the target memory block.

[0040] In a third aspect, the present invention provides a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to execute the memory management method according to the first aspect or any corresponding embodiment thereof.

[0041] Fourthly, the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to make a computer execute the memory management method according to the first aspect or any corresponding embodiment thereof.

[0042] Fifthly, the present invention provides a computer program product, including computer instructions, and the computer instructions are used to make a computer execute the memory management method according to the first aspect or any corresponding embodiment thereof. Description of the Drawings

[0043] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required to be used in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0044] Figure 1 is a schematic flowchart of a memory management method according to an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of the conversion process of the status information matrix and the in-row index table array according to an embodiment of the present invention;

[0046] Figure 3 is a schematic flowchart of another memory management method according to an embodiment of the present invention;

[0047] Figure 4 is a schematic flowchart of yet another memory management method according to an embodiment of the present invention;

[0048] Figure 5 is a structural block diagram of a memory management device according to an embodiment of the present invention;

[0049] Figure 6 is a schematic hardware structure diagram of a computer device according to an embodiment of the present invention. Detailed Embodiments

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0051] Currently, the memory buddy algorithm is usually used to meet various memory size requirements and minimize memory fragmentation. This algorithm divides all free memory blocks into multiple block linked lists, each containing consecutive memory blocks of a specific size, thus achieving fine-grained management of memory. However, in the above memory management method, according to the memory application and release process, memory iterative split / merge operations and traversing the linked list incur significant time overhead, which will affect the performance of memory application / release.

[0052] According to an embodiment of the present invention, an embodiment of a memory management method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0053] In this embodiment, a memory management method is provided. Figure 1 It is a flowchart of the memory management method according to an embodiment of the present invention, as Figure 1 shown, and this process includes the following steps:

[0054] Step S101, generate a status information matrix according to the usage status of each atomic memory block in the physical memory information.

[0055] Specifically, first, obtain all the information of the current physical memory, including the total capacity, available capacity, allocated capacity, etc. Then, divide the physical memory into multiple atomic memory blocks of equal size. The size of the atomic memory blocks can be customized in advance, for example, it can be 4KB. These atomic memory blocks are the basic units for memory allocation and recycling.

[0056] Furthermore, divide the entire memory into several smaller atomic memory blocks. The status information of each atomic memory block is mapped to 1 bit to represent its current status information, so as to create a two-dimensional matrix status information matrix with M rows and N columns. Each element in the status information matrix is used to indicate whether each atomic memory block is in use. An atomic memory block has two states: free and in use. Specifically, the free state means after the memory block management module is initialized, or the memory block has been released by the business layer, and the in-use state means the memory block has been applied by the business layer and has not been released yet.

[0057] Optionally, use 0 to represent that the usage status of the atomic memory block is "not in use", and use 1 to represent that the usage status of the atomic memory block is "in use".

[0058] Step S102, generate an index table array based on the status information matrix.

[0059] Specifically, the index table array includes an in-row index table array and an across-row index table array. The index table array is used to indicate the distribution of consecutive elements with the same status and different lengths in the status information matrix. Memory blocks of different specifications are used to indicate consecutive unused atomic memory blocks of different lengths in the status information matrix, where the minimum specification is 1 free atomic memory block and the maximum specification is K consecutive free atomic memory blocks, and K can be customized in advance.

[0060] Furthermore, the higher the memory block specification, the longer the consecutive length of free atomic memory blocks. One free atomic memory block can only belong to one memory block specification.

[0061] In some alternative embodiments, step S102 includes:

[0062] Generating an in-row index table array and an across-row index table array based on the status information matrix; the number of columns of both the in-row index table array and the across-row index table array is the number of memory block specifications, the number of rows of the in-row index table array is equal to the number of rows of the status information matrix, and the number of rows of the across-row index table array is 1 less than the number of rows of the in-row index table array.

[0063] Specifically, for the in-row index table, determine the number of rows of the in-row index table array according to the number of rows of the status information matrix. That is, when the information status matrix is M rows and N columns, the in-row index table is also M rows. At the same time, determine the number of memory block specifications, that is, how many kinds of consecutive lengths of unused atomic memory blocks there are, to determine the number of columns of the in-row index table array.

[0064] Furthermore, in order to ensure the boundary continuity between M rows, that is, between two adjacent rows in the status matrix, an across-row index table is designed as a supplement to the in-row index table. Its number of rows is 1 less than that of the in-row index table array. Therefore, the across-row index table matrix corresponding to the M-row status information matrix should be M - 1 rows, and the number of columns of the across-row index table is also equal to the number of memory block specifications.

[0065] Furthermore, through the above in-row index table array and across-row index table array, the entire memory is divided into 2M - 1 local memories. Each time memory management only needs to select one or two of these local memories for operation, and the global continuity of the entire memory is ensured.

[0066] Step S103, based on the index table array, determine the target memory block corresponding to the memory application request.

[0067] Specifically, first, by parsing the memory application request, the size of the memory block required by the request is obtained. Next, according to the size of the memory block applied for, available free-state memory blocks are searched in the column of the corresponding specification, and the row where the first available free-state memory block exists is confirmed as the valid row. Since each row of the index table array corresponds to a row in the status information matrix, the specific position of the target memory block can be determined in the information status matrix based on this.

[0068] Furthermore, if no available free-state memory block is found in the row of the index table array, the search continues to the next row until all columns and rows of the index table array are traversed.

[0069] In some alternative embodiments, the above step S103 includes:

[0070] Step S1031, based on the memory application request, determine the target area in the status information matrix in the index table array;

[0071] Step S1032, select a target memory block corresponding to the size of the memory application request in the target area.

[0072] Specifically, according to the memory application request, parallel searches are performed on the in-row index table array and the cross-row index table array. If a free-state memory block that can meet the current memory application is found through the index table array, the exact position of the memory block is detected in the local status information matrix according to the index value obtained from the index table to determine the corresponding target area in the status information matrix. Then, according to the memory application request, a memory block of the required size is selected as the target memory block in the target area of the information status matrix, and the address of this memory block is obtained.

[0073] Step S104, based on the target memory block, update the status information matrix and the index table array.

[0074] Specifically, when the target memory block is determined through step S103, in the status information matrix, the starting position and length of the target memory block are found, and the elements at the corresponding positions are changed from the "free" state (usually represented by 0 or False) to the "used" state (usually represented by 1 or True).

[0075] Furthermore, update the in-row index table array and the cross-row index table array based on the updated status information matrix.

[0076] In summary, for the memory management method provided by the embodiments of the present invention, to facilitate memory management, the entire physical memory is divided into several smaller atomic memory blocks, and the status information of each atomic memory block is mapped to 1 bit to represent its current status information. The mappings are aggregated into a status information matrix (bitmap matrix) with M rows and N columns. In the bitmap matrix, continuous representation means continuous physical addresses in memory, including two possibilities: continuous within a row and continuous across rows. If the free atomic memory blocks are continuous within a row, a possible status information matrix is shown in Table 1:

[0077] Table 1: Example Table of Status Information Matrix

[0078] 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

[0079] If the free atomic memory blocks are continuous across rows, a possible status information matrix is shown in Table 2:

[0080] Table 2: Example Table of Status Information Matrix

[0081] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

[0082] Therefore, corresponding to the two possible distributions of continuous free atomic blocks, an in - row index table array and a cross - row index table array are respectively generated. Among them, the in - row index table array is as shown in Figure 2 . The memory is divided into M local memories, and the status of each in - row local memory is represented by the in - row index table. The cross - row index table array, as a supplement to the in - row index table array, is to ensure the boundary continuity between the M in - row local memories. Therefore, a group of cross - row index table arrays with M - 1 rows is formed to represent the status of these M - 1 cross - row local memories. The number of columns of the cross - row index table array is the same as that of the in - row index table.

[0083] When a memory application is made, parallel searches are performed on the in - row index table array and the cross - row index table array according to the size of the applied memory block. Specifically, according to the size of the applied memory, searches are performed in the corresponding columns of the index table array, and the first valid row in the column of the index table array is selected. The area of the status information matrix corresponding to this row is used as the target area, and then the target memory block is selected according to the memory application request. If the search fails in a certain column of the index table array and the current searched memory block specification is not the maximum memory specification, the memory specification is upgraded and the search is performed again in the index table until the target memory block is determined according to the above process. If the search fails in a certain column of the index table array and the current searched memory block specification is the maximum memory specification, it indicates that the memory block required by the service layer cannot be allocated currently, and a direct response is made.

[0084] After determining the target memory block, change the status information corresponding to the target memory block in the status information matrix from "idle" to "in use", and update the index table array based on the updated status information matrix.

[0085] In some alternative embodiments, determining the target area in the status information matrix in the index table array includes:

[0086] If there is an idle status memory block in the index table array with the same size as the memory application request, then the area in the status information matrix corresponding to the idle status memory block is determined as the target area;

[0087] If there is no idle status memory block in the index table array with the same size as the memory application request, then the area in the status information matrix corresponding to the idle status memory block with the smallest specification larger than the memory application request is determined as the target area.

[0088] First, parallelly search in the in-row index table array and the cross-row index table array for the column where the memory block specification that exactly matches the memory application request is located, find the first valid row in this column of the index table array, and use the row in the corresponding information status matrix of this column as the target area. If optional idle status memory blocks are found in both the in-row index table and the cross-row index table, then preferentially use the idle status memory block in the in-row index table to determine the corresponding row in the status information matrix as the target area.

[0089] If there is no idle status memory block with the same size as the memory application request, and the currently searched memory block specification is not the maximum memory specification, then upgrade the memory specification and search in the index table again. If the memory block specification at this time is already the maximum memory block specification in the index table array, it indicates that the memory block required by the service layer cannot be allocated currently, and the memory application request fails.

[0090] In some alternative embodiments, selecting a target memory block with a size corresponding to the memory application request in the target area includes:

[0091] Select the target memory block with the smallest address in the target area and with a size corresponding to the memory application request.

[0092] When determining a certain row in the status information matrix as the target area according to the index table array, if there is more than one optional target memory block corresponding to the memory application request in this row of the status information matrix, as shown in Table 3, assume that the atomic memory block is 4KB and the memory application request is 12KB. Then, according to the index table array, locate the 3rd row of this status information matrix as the target area. However, there are two optional target memory blocks in this target area. Then, at this time, select the memory block with a smaller memory address as the target memory block.

[0093] Table 3: Example Table of Target Area

[0094]

[0095]

[0096] In some alternative embodiments, the method further includes:

[0097] If the memory application request is successful, reply to the service layer with a memory application success message and the address of the target memory block; otherwise, reply to the service layer with a memory application failure message.

[0098] Please refer to Figure 3 , the memory application process further includes a reply to the service layer. If the target memory block is found according to the index table array and the status information matrix, and after updating the status information matrix and the index table array based on the target memory block, reply to the service layer with a memory application success message and the address of the target memory block; if the target memory block corresponding to the memory application request cannot be found, reply to the service layer with a memory application failure message.

[0099] In some alternative embodiments, the method further includes:

[0100] In response to a memory release request, update the status information matrix and the index table array.

[0101] Please refer to Figure 4 , after receiving the memory release operation sent by the service layer, obtain the row of the memory block in the status information matrix according to the address decoding of the released memory, update the status information of the position of the corresponding atomic memory block in the row of the released atomic memory block in the status information matrix, and update the index information in the index table array based on the updated status information matrix.

[0102] In some alternative embodiments, the method further includes:

[0103] If the memory release request is successful, reply to the service layer with a memory release success message; otherwise, reply to the service layer with a memory release failure message.

[0104] In this embodiment, a memory management device is further provided. The device is used to implement the above embodiments and preferred implementation manners, and those that have been described will not be repeated. As used hereinafter, the term "module" may be a combination of software and / or hardware that can implement a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0105] This embodiment provides a memory management device, as Figure 5 shown, including:

[0106] A generation matrix module 501, configured to generate a status information matrix according to the usage status of each atomic memory block in the physical memory information; each element in the status information matrix is used to indicate whether each atomic memory block is used;

[0107] A generation array module 502, configured to generate an index table array based on the status information matrix; the index table array includes an in-row index table array and an across-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; memory blocks of different specifications are used to indicate different lengths of consecutive unused atomic memory blocks in the status information matrix;

[0108] A determination module 503, configured to determine a target memory block corresponding to a memory application request based on the index table array;

[0109] An update module 504, configured to update the status information matrix and the index table array based on the target memory block.

[0110] In some alternative embodiments, the generation array module 502 includes:

[0111] An index table generation subunit, configured to generate an in-row index table array and an across-row index table array based on the status information matrix; the number of columns of the in-row index table array and the across-row index table array is the number of memory block specifications, the number of rows of the in-row index table array is equal to the number of rows of the status information matrix, and the number of rows of the across-row index table array is 1 less than the number of rows of the in-row index table array.

[0112] In some alternative embodiments, the determination module 503 includes:

[0113] A target area determination sub-module, configured to determine a target area in the status information matrix in the index table array based on the memory application request.

[0114] A selection sub-module, configured to select a target memory block corresponding to the size of the memory application request in the target area.

[0115] In some alternative embodiments, the target area determination sub-module includes:

[0116] A first target area determination unit, configured to, when there is an idle state memory block in the index table array with the same size as the memory application request, confirm the area in the status information matrix corresponding to the idle state memory block as the target area;

[0117] A second target area determination unit, when there is no idle state memory block in the index table array with the same size as the memory application request, confirm the area in the status information matrix corresponding to the idle state memory block with the smallest specification greater than the memory application request as the target area.

[0118] In some alternative embodiments, the sub-module selection includes:

[0119] Select the smallest address unit for selecting a target memory block with the smallest address in the target area and having a size corresponding to the memory application request.

[0120] In some alternative embodiments, the apparatus further includes:

[0121] A response module, configured to, when the memory application request is successful, respond to the service layer with a memory application success message and the address of the target memory block, and vice versa, respond to the service layer with a memory application failure message.

[0122] In some alternative embodiments, the apparatus further includes:

[0123] A release and update module, configured to, in response to a memory release request, update the status information matrix and the index table array.

[0124] The further function descriptions of the above-mentioned various modules and units are the same as those in the corresponding foregoing embodiments, and will not be elaborated herein.

[0125] The memory management apparatus in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0126] This embodiment of the present invention further provides a computer device having the above-mentioned Figure 5 shown memory management apparatus.

[0127] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of a computer device provided by an alternative embodiment of the present invention. As shown in Figure 6 , the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi-processor system). Figure 6Taking a processor 10 as an example.

[0128] The processor 10 can be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 can further include a hardware chip. The above-mentioned hardware chip can be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above-mentioned programmable logic device can be a complex programmable logic device, a field-programmable gate array, a generic array logic, or any combination thereof.

[0129] Among them, the memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiments.

[0130] The memory 20 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 can optionally include a memory remotely set relative to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0131] The memory 20 can include a volatile memory, for example, a random access memory; the memory can also include a non-volatile memory, for example, a flash memory, a hard disk, or a solid-state drive; the memory 20 can also include a combination of the above types of memories.

[0132] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30, and the output device 40 can be connected through a bus or other means. Figure 6 Taking the connection through a bus as an example.

[0133] The input device 30 can receive input digital or character information, and generate key signal inputs related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (for example, an LED), and a tactile feedback device (for example, a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some alternative embodiments, the display device can be a touch screen.

[0134] Embodiments of the present invention also provide a computer-readable storage medium. The methods according to the embodiments of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the methods described herein can be stored as such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0135] A part of the present invention can be applied as a computer program product, for example, computer program instructions. When executed by a computer, through the operation of the computer, the methods and / or technical solutions according to the present invention can be called or provided. Those skilled in the art should be able to understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.

[0136] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A memory management method, characterized in that: The method comprises: Generate a state information matrix according to the usage status of each atomic memory block in the physical memory information; each element in the state information matrix is ​​used to indicate whether each atomic memory block is used; Generate an index table array based on the state information matrix; the index table array includes an intra-row index table array and an inter-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; the memory blocks of different specifications are used to indicate the continuous unused atomic memory blocks of different lengths in the state information matrix; Based on the index table array, determining a target memory block corresponding to the memory application request; Based on the target memory block, the state information matrix and the index table array are updated.

2. The method according to claim 1, characterized in that The step of generating an index table array based on the state information matrix comprises: An in-row index table array and an inter-row index table array are generated based on the state information matrix; the number of columns of the in-row index table array and the inter-row index table array are both the number of memory block specifications, the number of rows of the in-row index table array is equal to the number of rows of the state information matrix, and the number of rows of the inter-row index table array is 1 less than the number of rows of the in-row index table array.

3. The method according to claim 2, characterized in that The step of determining a target memory block corresponding to a memory application request based on the index table array includes: Based on the memory application request, determining a target area in the state information matrix in the index table array; A target memory block having a size corresponding to the memory application request is selected in the target area.

4. The method according to claim 3, characterized in that The step of determining a target area in a state information matrix in an index table array based on a memory application request includes: If there is an idle memory block with the same size as the memory application request in the index table array, confirming the area in the state information matrix corresponding to the idle memory block as the target area; If there is no idle memory block with the same size as the memory application request in the index table array, the area in the state information matrix corresponding to the idle memory block larger than the minimum size of the memory application request is confirmed as the target area.

5. The method according to claim 4, characterized in that The step of selecting a target memory block having a size corresponding to the memory application request in the target area includes: The target memory block with the smallest address in the target area and a size corresponding to the memory application request is selected.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: If the memory application request is successful, a memory application success message and the address of the target memory block are responded to the business layer; otherwise, a memory application failure message is responded to the business layer.

7. The method according to claim 6, characterized in that The method further comprises: In response to a memory release request, the state information matrix and the index table array are updated.

8. A memory management device, characterized in that: The device comprises: A matrix generation module, used to generate a state information matrix according to the use status of each atomic memory block in the physical memory information; each element in the state information matrix is ​​used to indicate whether each atomic memory block is used; A generation array module, used for generating an index table array based on the state information matrix; the index table array includes an intra-row index table array and an inter-row index table array; the index table array is used for indicating the usage of memory blocks of different specifications; the memory blocks of different specifications are used for indicating the continuous unused atomic memory blocks of different lengths in the state information matrix; A determination module, configured to determine a target memory block corresponding to a memory application request based on the index table array; An update module is used to update the state information matrix and the index table array based on the target memory block.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the memory management method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the memory management method according to any one of claims 1 to 7.

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