A display panel and display device

Abstract

This disclosure provides a display panel and display device, relating to the field of display technology. Pixel driving lines and data lines are electrically connected to a pixel driving circuit, respectively, for transmitting control signals and data signals to the pixel driving circuit. A shift register circuit transmits control signals to the pixel driving lines, and a gating circuit transmits data signals to the data lines. The shift register circuit includes multiple cascaded shift registers, namely multiple cascaded first shift registers and a second shift register cascaded with the first shift registers. The first shift registers are located in the area where the pixel driving circuit array is located, and the second shift registers are located on the side of the pixel driving circuit array facing the edge of the display panel. The gating circuit is located between the pixel driving circuit array and the second shift registers. This design helps reduce signal interference between the shift register circuit and the data lines, thus improving the display accuracy of the display product.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] Existing display products typically contain various circuits. How to arrange them rationally to reduce interference between different signals has become one of the urgent technical problems to be solved at present. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a display panel and display device that helps reduce signal interference between the shift register circuit and the data line, thereby improving the display accuracy of the display product.

[0005] In a first aspect, this disclosure provides a display panel, including a pixel driving circuit array, a shift register circuit and a gating circuit, as well as pixel driving lines and data lines, wherein the pixel driving circuit array includes a plurality of pixel driving circuits;

[0006] The pixel driving line and the data line are electrically connected to the pixel driving circuit, respectively. The pixel driving line is used to transmit control signals to the pixel driving circuit, and the data line is used to transmit data signals to the pixel driving circuit.

[0007] The shift register circuit is configured to transmit the control signal to the pixel drive line, and the gating circuit is configured to transmit the data signal to the data line;

[0008] The shift register circuit includes multiple cascaded shift registers, each including multiple cascaded first shift registers and a second shift register cascaded with the first shift registers. The first shift registers are located in the area where the pixel driving circuit array is located, and the second shift registers are located on the side of the pixel driving circuit array facing the edge of the display panel. The gating circuit is located between the pixel driving circuit array and the second shift registers.

[0009] In a second aspect, this disclosure provides a display device, including the display panel provided in the first aspect of the present invention.

[0010] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0011] This disclosure adjusts the positional relationship between the shift register and the gating circuit relative to the pixel driving circuit array. Specifically, multiple first shift registers in the shift register circuit are placed in the area where the pixel driving circuit array is located, and a second shift register cascaded with the first shift register is placed in an area outside the pixel driving circuit array, that is, on the side of the pixel driving circuit array facing the edge of the display panel. In this embodiment, the edge of the display panel refers to the lower edge of the display panel. At this time, both the second shift register and the gating circuit are located on the side of the pixel driving circuit array facing the edge of the display panel, and the second shift register is located between the edge of the gating circuit and the edge of the display panel. That is to say, the gating circuit is closer to the pixel driving circuit array than the second shift register, which means that the gating circuit will be closer to the end of the data line. At this time, when connecting the end of the data line to the gating circuit, the connection can be achieved without passing through the second shift register, thereby avoiding the signal interference problem of the second shift register on the data line and improving the accuracy of the data signal transmitted on the data line. Meanwhile, by placing the gating circuit between the second shift register and the pixel driving circuit array, there is no interference from other lines between the data line and the gating circuit. The data line can be connected to the gating circuit without being replaced, thus avoiding the risk of wire breakage or short circuit when replacing the data line, which helps to improve the display stability of the display panel. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0013] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 The figure shown is a planar structural diagram of a display panel provided in an embodiment of this disclosure;

[0015] Figure 2 The figure shown is a planar structural diagram of a display panel provided in an embodiment of this disclosure;

[0016] Figure 3 The diagram shown is a planar structure of a display panel provided in the related art;

[0017] Figure 4 The diagram shown is a connection schematic of a shift register circuit provided in an embodiment of this disclosure;

[0018] Figure 5 The diagram shown is a layout of the pixel driving circuit, gating circuit, and shift register circuit.

[0019] Figure 6 The diagram shown is a connection diagram between the data line and the gating circuit.

[0020] Figure 7 The diagram shown is a connection layout diagram of the data line and the gating circuit;

[0021] Figure 8 The diagram shows the relative positions of the pixel driving circuit, the gating circuit, and the shift register circuit.

[0022] Figure 9 The diagram shows a connection schematic of the pixel driving circuit and the data line;

[0023] Figure 10 The diagram shown illustrates the relative positional relationship between the transmission signal line and the gating control line.

[0024] Figure 11 The diagram shown is a schematic diagram of a film layer of a display panel provided in an embodiment of this disclosure;

[0025] Figure 12 The diagram shown illustrates the relative positional relationship between the switching element group and the gating control line in the gating circuit provided in this embodiment of the present disclosure.

[0026] Figure 13 The diagram shown illustrates another relative positional relationship between the switching element group and the gating control line in the gating circuit provided in this embodiment of the present disclosure.

[0027] Figure 14 The diagram shows a layout of the gating control line and the first signal line that intersects with it.

[0028] Figure 15 The diagram shown is another planar structural diagram of the display panel provided in an embodiment of this disclosure;

[0029] Figure 16 The diagram shown is a layout of the pixel driving circuit array in the display panel provided in an embodiment of this disclosure, facing the edge of the display panel.

[0030] Figure 17 The diagram shown is a reference layout of the pixel driving circuit array facing the edge of the display panel.

[0031] Figure 18 The diagram shown is a schematic diagram of the layout of the light-emitting element in an embodiment of this disclosure;

[0032] Figure 19 The image shown is a partial layout diagram of the display panel;

[0033] Figure 20 The diagram shown is a structural schematic of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0034] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0035] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0036] Figure 1 The diagram shown is a plan view of a display panel provided in an embodiment of this disclosure. Please refer to it. Figure 1 The display panel 100 provided in this disclosure includes a pixel driving circuit array 10, a shift register circuit 20, and a gating circuit 30, as well as pixel driving lines GL and data lines DL. The pixel driving circuit array 10 includes a plurality of pixel driving circuits 11. It should be noted that... Figure 1 The relative positions of the pixel driving circuit array 10, the shift register circuit 20, and the gating circuit 30 are only shown in the illustration. The number and arrangement of the pixel driving circuits 11 actually contained in the pixel driving circuit array 10 are not limited, nor is the number of shift registers actually contained in the shift register circuit 20.

[0037] In the display panel 100 provided in this disclosure, the pixel driving line GL and the data line DL are electrically connected to the pixel driving circuit 11. The pixel driving line GL is used to transmit control signals to the pixel driving circuit 11. These control signals can be, for example, a reset signal to control the pixel driving circuit 11 to reset, a control signal to control the pixel driving circuit 11 to write data, or a light emission control signal to control the pixel driving circuit 11 to emit light. It should be noted that... Figure 1 Only one pixel driving line GL connected to the pixel driving circuit 11 is shown, but the number of pixel driving lines GL actually connected to the pixel driving circuit 11 is not limited. In this disclosure, the data line DL is used to transmit data signals to the pixel driving circuit 11; the shift register circuit 20 is configured to transmit control signals to the pixel driving line GL, which in turn further transmits the control signals to the pixel driving circuit 11; the gating circuit 30 is configured to transmit data signals to the data line DL, which in turn further transmits the data signals to the pixel driving circuit 11.

[0038] In this disclosure, the shift register circuit 20 includes multiple cascaded shift registers, including multiple cascaded first shift registers 21 and second shift registers 22 cascaded with the first shift registers 21. The first shift registers 21 are located in the area where the pixel driving circuit array 10 is located, and the second shift registers 22 are located on the side of the pixel driving circuit array 10 facing the edge B of the display panel. The gating circuit 30 is located between the pixel driving circuit array 10 and the second shift registers 22. Figure 1 The illustrated embodiment uses a pixel driving circuit array 10 comprising a matrix arrangement of multiple pixel driving circuits 11 as an example. In this case, the area where the pixel driving circuit array 10 is located can be considered as a rectangular area formed by all the pixel driving circuits 11. In this disclosure, the first shift register 21 is located within the rectangular area formed by the pixel driving circuit array 10, and the second shift register 22 is located outside the rectangular area. It should be noted that... Figure 1 The rectangular area formed by the pixel driving circuit array 10 in the diagram is merely illustrative and is not intended to be limiting. In some other embodiments of this disclosure, the area where the pixel driving circuit array 10 is located may also be other non-rectangular shapes. It should also be noted that... Figure 1 Only one set of shift register circuits 20 in the display panel is shown, but the actual number of shift register circuits 20 included in the display panel is not limited. For example, please refer to... Figure 2 , Figure 2 The figure shown is a plan view of a display panel provided in an embodiment of this disclosure. Figure 2 The illustrated embodiment shows two sets of shift register circuits 20 in the display panel. The first shift register 21 of each shift register circuit 20 is located in the area where the pixel driving circuit array 10 is located, and the second shift register 22 is located on the side of the pixel driving circuit array 10 facing the edge B of the display panel. It should be noted that the two sets of shift register circuits 20 can transmit control signals to the same pixel driving line GL to improve the driving capability of the control signal, or they can transmit control signals to different pixel driving lines GL respectively. This disclosure does not specifically limit this.

[0039] In the process of designing the display panel, the inventors came up with one implementation method as follows: Figure 3 All shift registers in shift register circuit 20' are located in the area where pixel driving circuit array 10' is located, and gating circuit 30' is located outside pixel driving circuit array 10'. That is, gating circuit 30' is located on the side of shift register circuit 20' facing edge B' of display panel. Figure 3 The diagram shown is a planar structural diagram of a display panel provided in related technologies. However, the inventors discovered that... Figure 3In the current design, the data signal on the data line DL' is subject to interference from other signals. This is because when the end of the data line DL' connects to the gating circuit 30', it needs to pass through the shift register closest to the gating circuit 30'. If the data line DL' and the signal line corresponding to the shift register are placed on the same layer, signal interference will occur. Further research by the inventors revealed that to reduce signal interference from the shift register to the data line DL', the data line DL' located closest to the gating circuit 30' can be redesigned to avoid being placed on the same layer as the signal line corresponding to the shift register. However, since the data line DL' is relatively thin, redesigning it increases the risk of breakage or short circuit, affecting the display effect.

[0040] Based on the above issues, this disclosure adjusts the positional relationship between the shift register and the gating circuit 30 relative to the pixel driving circuit array 10. Please refer to the following for details. Figure 1 and Figure 2 In this embodiment, multiple first shift registers 21 in the shift register circuit 20 are located in the area where the pixel driving circuit array 10 is located, and a second shift register 22 cascaded with the first shift registers 21 is located in an area outside the pixel driving circuit array 10, specifically on the side of the pixel driving circuit array 10 facing the edge B of the display panel. The edge B of the display panel mentioned in this embodiment refers to the lower edge of the display panel. At this time, both the second shift register 22 and the gating circuit 30 are located on the side of the pixel driving circuit array 10 facing the edge B of the display panel, and the second shift register 22 is located between the gating circuit 30 and the edge B of the display panel. That is, the gating circuit 30 is closer to the pixel driving circuit array 10 than the second shift register 22, making the gating circuit 30 closer to the end of the data line DL. Therefore, when connecting the end of the data line DL to the gating circuit 30, the connection can be achieved without passing through the second shift register 22, thereby avoiding signal interference from the second shift register 22 to the data line DL and improving the accuracy of the data signal transmitted on the data line DL. Meanwhile, by placing the gating circuit 30 between the second shift register 22 and the pixel driving circuit array 10, there is no interference from other lines between the data line DL and the gating circuit 30. The data line DL can be connected to the gating circuit 30 without changing the cable, thereby avoiding the risk of wire breakage or short circuit when changing the data line DL, which is conducive to improving the display stability of the display panel.

[0041] Figure 4 The diagram shown is a connection schematic of the shift register circuit 20 provided in an embodiment of this disclosure. Please refer to it. Figure 1 , Figure 2 and Figure 4In one optional embodiment of this disclosure, the output terminal OUT of the first shift register 21 is electrically connected to the pixel driving circuit 11 via the pixel driving line GL. The display panel also includes a bonding pad P1, and the output terminal OUT of the second shift register 22 is electrically connected to the bonding pad P1. That is, the first shift register 21 mentioned in the embodiments of this disclosure is a shift register connected to the pixel driving line GL and used to provide control signals to the pixel driving circuit 11 via the pixel driving line GL, while the second shift register 22 can be regarded as a virtual shift register. Its output terminal OUT is not connected to the pixel driving line GL, but is connected to the bonding pad P1 in the display panel. The second shift register 22 does not need to provide control signals to the pixel driving line GL in the display panel.

[0042] Alternatively, please refer to Figure 1 , Figure 2 and Figure 4 The display panel also includes a test signal line CL, and the output of the second shift register 22 is also electrically connected to the test signal line CL.

[0043] The bonding pad P1 introduced in the display panel is used to bond with the control chip or flexible circuit board, realizing the electrical connection between the control chip or flexible circuit board and the bonding pad P1, and thus realizing the electrical connection with the circuit in the display panel. The display panel is formed by cutting a motherboard. Before cutting, a test pad VT-P is set on the motherboard. The test pad VT-P is used to electrically connect with the test signal line CL in the display panel for detecting the corresponding signal. For example, the output terminal OUT of the second shift register 22 is electrically connected to the test signal line CL. The signal of the second shift register 22 can be tested before cutting. During the test, the test probe is inserted into the test pad VT-P, and the signal at the output terminal of the second shift register 22 can be detected, thereby determining whether there is an abnormality in the control signal output by the shift register circuit 20. The test pad VT-P does not need to be bonded to the control chip or flexible circuit board. Optionally, the test pad VT-P will be removed when cutting to form the display panel.

[0044] Figure 5 The diagram shown is a layout of the pixel driving circuit, gating circuit, and shift register circuit. Figure 6 The diagram shown is a connection circuit diagram between the data line DL and the gating circuit 30. Figure 7 The diagram shown is a possible connection layout between the data line DL and the gating circuit 30. Please refer to it. Figure 5 , Figure 6 and Figure 7 In one optional embodiment of this disclosure, the selection circuit 30 includes a plurality of switching element groups 31, each group including at least two switching elements T, the output terminals of which are electrically connected to the data line DL; please refer to Figure 1 and Figure 2 The data line DL includes a first part X1 and a second part X2 that are electrically connected. The first part X1 is located at least in the area where the pixel driving circuit array 10 is located, and the second part X2 is located on the side of the pixel driving circuit array 10 facing the edge B of the display panel. The first part X1 is electrically connected to the switching element T through the second part X2, and the first part X1 and the second part X2 are arranged on the same layer.

[0045] Figure 6 and Figure 7 The illustrated embodiment uses the switching element group 31 in the gating circuit 30, which includes three switching elements T, as an example, but is not limited to this. In the display panel, the output terminals of the switching elements T in the switching element group 31 are electrically connected to the data lines DL one-to-one, for transmitting data signals to the data lines DL. In this embodiment, the first part X1 of the data line DL can be regarded as a line segment of the data line DL located in the area where the pixel driving circuit array 10 is located, and the second part X2 can be regarded as a line segment used to electrically connect the first part X1 with the switching elements T in the gating circuit 30. When the switching element group 31 is not located directly below the first part X1 in the data line DL, the electrical connection between the first part X1 and the switching elements T in the gating element group 31 can be achieved by introducing the second part X2 located directly above the switching element group 31. The extension direction of at least some of the line segments in the second part X2 is different from the extension direction of at least some of the line segments in the first part X1. In this embodiment, the first part X1 extends along the second direction D2, and at least some of the line segments in the second part X2 extend along the first direction D1 as an example. In this embodiment, when the first part X1 and the second part X2 of the data line DL are set on the same film layer, the data line DL can be electrically connected to the switch element group 31 without changing the data line DL. This helps to avoid the risk of wire breakage or short circuit caused by changing the wire. Moreover, setting the first part X1 and the second part X2 of the data line DL on the same layer also helps to avoid the drilling and other processes introduced when they are set on different layers, thereby simplifying the manufacturing process of the data line DL.

[0046] Please continue to refer to this. Figure 5 , Figure 6 and Figure 7 In one optional embodiment of this disclosure, the gating circuit 30 includes at least two gating control lines K. This embodiment uses three gating control lines K (a first gating control line K1, a second gating control line K2, and a third gating control line K3) as an example. The number of gating control lines K is the same as the number of switching elements included in a single switching element group 31. In the same switching element group 31, the gates of different switching elements are connected to different gating control lines K. The gating control lines K extend along a first direction D1, and the first part X1 extends along a second direction D2. The first direction D1 and the second direction D2 intersect. Please refer to [the relevant documentation / reference]. Figure 1and Figure 2 Along the second direction D2, the switching element group 31 is located between the gating control line K and the pixel driving circuit array 10. The three gating control lines K in the gating circuit 30 send enable signals in a time-division manner, turning on the switching element T connected to them. When the switching element T is turned on, the data signal can be transmitted to the corresponding data line DL through the turned-on switching element.

[0047] Please combine Figure 1 , Figure 2 , Figure 5 , Figure 6 and Figure 7 In this embodiment, the gating control line K is set on the side of the switch element group 31 away from the pixel driving circuit array 10. That is, the switch element group 31 is closer to the pixel driving circuit array 10 than the gating control line K. In this way, when the data line DL is electrically connected to the switch element T in the switch element group 31, it does not need to pass through the gating control line K. The gating control line K will not affect the connection between the data line DL and the switch element T. The data line DL can achieve electrical connection with the switch element T without changing the wire, avoiding the risk of wire breakage or short circuit caused by wire replacement.

[0048] Please combine Figure 1 , Figure 2 , Figure 5 , Figure 6 and Figure 7 In the gating circuit 30, the gating control line K extends along the first direction D1, occupying almost the entire width of the display panel along the first direction D1. In the shift register circuit 20, a single shift register occupies a smaller portion of the display panel's width along the first direction D1. In related technologies, for example... Figure 3 If the gating circuit 30' is positioned on the side of each shift register facing the edge B' of the display panel, in the area between the pixel driving circuit array 10' and the gating circuit 30', some space other than the shift registers (e.g.) Figure 3The space on both sides of the second shift register 22' along the first direction D1 cannot be effectively utilized, resulting in wasted space. However, in this disclosure, when the gating circuit 30 is placed between the second shift register 22 and the pixel driving circuit array 10, the space on both sides of the second shift register 22 along the first direction D1 on the side of the gating circuit 30 facing the edge B of the display panel can be effectively utilized. For example, some traces that were originally placed below the second shift register 22 can be moved up, and wiring can be done in the space on both sides of the second shift register 22 (this will be described in detail in subsequent embodiments), thereby reducing the space occupied by the second shift register 22 and the aforementioned traces along the second direction D2. This allows structures such as the electrostatic protection circuit that were originally placed below the second shift register 22 to move towards the pixel driving circuit array 10, thereby moving some transistors in the display panel (such as transistors in the electrostatic protection circuit) away from the edge B of the display panel. Considering that the display panel is formed by cutting the motherboard, the edge B of the display panel can be regarded as the cutting edge. When the transistors in the display panel are set away from the edge B of the display panel, it is beneficial to reduce the influence of the laser on the transistors during the laser cutting process and reduce the risk of laser damage to the transistors.

[0049] Figure 8 The diagram shows a relative positional relationship between the pixel driving circuit 11, the gating circuit 30, and the shift register circuit 20. Figure 9 The diagram shows a connection schematic of the pixel driving circuit and the data line. Figure 10 The diagram shown illustrates the relative positional relationship between the transmission signal line X0 and the gating control line K. Please refer to the diagram for further details. Figure 8 and Figure 10 In one optional embodiment of this disclosure, the second shift register 22 and the first shift register 21 are electrically connected through a transmission signal line X0. Along the direction perpendicular to the plane where the display panel is located, the transmission signal line X0 and the gating control line K overlap to form a first overlap area Q1. In the first overlap area Q1, the transmission signal line X0 and the gating control line K are arranged in different layers.

[0050] Please combine Figure 5 , Figure 8 , Figure 9 and Figure 10When the second shift register 22 is positioned on the side of the gating circuit 30 facing the edge B of the display panel, it is equivalent to introducing the gating circuit 30 between the first shift register 21 and the second shift register 22. Since the gating control line K extends along the first direction D1 and the cascading signal line X0 connecting the first shift register 21 and the second shift register 22 extends along the second direction D2, the cascading signal line X0 will overlap with the gating control line K to form a first overlap area Q1. In this embodiment, the cascading signal line X0 and the gating control line K in the first overlap area Q1 are placed in different film layers, which helps to reduce signal interference between the two. Optionally, in the first overlap area Q1, the gating control line K is located in the first metal layer M1 of the display panel, and the cascading signal line is located in the second metal layer M2 of the display panel. The specific setting of the gating control line K and the film layer structure of the display panel will be described in subsequent embodiments.

[0051] In this embodiment of the disclosure, when the gating circuit 30 is set between the first shift register 21 and the second shift register 22, the stage transmission signal line X0 led out from the first shift register 21 will pass through the gating control line K in the gating circuit 30 and be electrically connected to the second shift register 22. At this time, it is necessary to switch the connection between the gating control line K and the stage transmission signal line X0. Figure 10 The illustrated embodiment shows a method for switching the gating control line K. Please refer to [the example provided]. Figure 10 Optionally, the gate control line K includes a main body K01 and a bridge portion K02 connected to the main body K01. The main body K01 and the bridge portion K02 are disposed on different layers and both extend along the first direction D1. The bridge portion K02 is at least partially located in the first overlap area Q1, and the cascaded signal line X0 is disposed on the same layer as the main body K01. For the gate control line K, the main body K01 accounts for a larger proportion of the entire gate control line K, while the bridge portion K02 is a cross-line structure arranged to facilitate the passage of other signal lines through the gate control line K. The proportion of the bridge portion K02 in the entire gate control line K is smaller than that of the main body K01. Optionally, the main body K01 is located in the second metal layer M2, and the bridge portion K02 is located in the first metal layer M1.

[0052] In this embodiment, a main body K01 and a bridge part K02 connected to the main body K01 are introduced into the gating control line K. The bridge part K02 and the main body K01 are located in different film layers and are electrically connected through the connection hole LK. When the stage transmission signal line X0 passes through the gating control line K, the stage transmission signal line X0 overlaps with the bridge part K02 in the first overlap area Q1. At this time, the stage transmission signal line X0 can be set in the same film layer as the main body K01 in the gating control line K. This can avoid interference with the gating control line K, make reasonable use of the film layer structure in the display panel, and also avoid the stage transmission signal line X0 from being replaced.

[0053] Optionally, the line width of the gating control line K is greater than the line width of the first part X1 in the data line DL. If the second shift register 22 is set between the gating circuit 30 and the pixel driving circuit array 10, in order to realize the electrical connection between the data line DL and the gating circuit 30, the data line DL needs to pass through the second shift register 22. Since there are many data lines DL and the setting space is small, their line width is small. If the data lines DL are reconnected to reduce signal interference, it will cause the risk of short circuit or wire breakage. If the gating circuit 30 is placed between the second shift register 22 and the pixel driving circuit array 10, the data line DL can be connected to the gating circuit 30 without crossing a wire. Considering that the first shift register 21 and the second shift register 22 need to be connected by the cascading signal line X0, the cascading signal line X0 will pass through the gating control line K. Therefore, in this embodiment, the line width of the gating control line K is set to be larger, making it larger than the line width of the data line DL. Thus, the method of connecting the main body K01 and the bridge part K02 of the gating control line K across a wire is beneficial to reducing the risk of changing the wire.

[0054] Figure 11 The diagram shown is a schematic representation of a film layer of a display panel provided in an embodiment of this disclosure. In an optional embodiment of this disclosure, the display panel includes a substrate 00 and a first metal layer M1 and a second metal layer M2 disposed on the substrate 00. The resistivity of the second metal layer M2 is less than the resistivity of the first metal layer M1. Please refer to... Figure 10 The main body K01 of the selection control line K and the stage transmission signal line X0 are located in the second metal layer M2, and the bridge part K02 of the selection control line K is located in the first metal layer M1.

[0055] Display panels typically contain multiple transistors, such as transistors in the pixel driving circuit 11, transistors corresponding to the switching elements of the gating circuit 30, transistors in the shift register circuit 20, etc. In the film layer structure of the display panel, optionally, the gate of the transistor is disposed in the first metal layer M1, and the source and drain of the transistor are disposed in the second metal layer M2. Optionally, the material of the first metal layer M1 is mainly Mo, and the material of the second metal layer M2 is Ti-Al-Ti. Due to the inherent properties of the materials, the impedance of the first metal layer M1 is greater than that of the second metal layer M2; that is, the resistivity of the first metal layer M1 is greater than that of the second metal layer M2, and the conductivity of the second metal layer M2 is better than that of the first metal layer M1. In this disclosure, by disposing the main body K01 of the gating control line K in the second metal layer M2, it is beneficial to reduce the overall impedance of the gating control line K, reduce the voltage drop of the control signal transmitted on the gating control line K, and thus improve the accuracy of the signal transmitted by the gating control line K. Furthermore, when the stage transmission signal line X0 is also disposed in the second metal layer M2 in the embodiments of this disclosure, it is also beneficial to reduce the impedance of the stage transmission signal line X0 and the voltage drop of the transmitted signal, thereby improving the accuracy of the stage transmission signal transmitted by the stage transmission signal.

[0056] Optionally, the data line DL provided in this embodiment is also located in the second metal layer M2 to reduce the impedance of the data line DL, which helps to reduce the voltage drop of the data signal transmitted on the data line DL and improve the accuracy of the data signal transmitted on the data line DL.

[0057] Optionally, the display panel provided in this embodiment further includes a semiconductor layer poly disposed on the side of the first metal layer M1 facing the substrate 00, and an auxiliary metal layer M0 disposed on the side of the semiconductor layer poly facing the substrate. It should be noted that the display panel may include a dual-gate transistor, in which case one gate of the transistor may be located on the first metal layer M1, and the other gate may be located on the auxiliary metal layer M0. Along a direction perpendicular to the plane of the substrate 00, both the first metal layer M1 and the auxiliary metal layer M0 overlap with the semiconductor layer poly. The auxiliary metal layer M0 also has a light-shielding function, preventing light from affecting the semiconductor layer poly. Optionally, a capacitor metal layer MC is further included between the first metal layer M1 and the second metal layer M2, and the capacitor metal layer MC can form a capacitor structure with the second metal layer M2. Optionally, a third metal layer M3 and a fourth metal layer M4 are further included on the side of the second metal layer M2 facing away from the substrate, and signal lines can be laid out in both the third metal layer M3 and the fourth metal layer M4.

[0058] Please refer to Figure 5 , Figure 8 and Figure 10In one optional embodiment of this disclosure, along the first direction D1, the bridge portion K02 is located between adjacent switch element groups 31; along the second direction D2, the second shift register 22 and the switch element group 31 overlap; along the first direction D1, the cascade signal line X0 connected to the second shift register 22 is located on the same side of the second shift register 22 and the switch element group 31 corresponding to the second shift register 22. In this embodiment, the cascade signal line X0 is located on the right side of the switch element group 31 and the corresponding second shift register 22 as an example. Specifically, when a bridge section K02 is introduced into the gating control line K, the bridge section K02 can be set in the area between adjacent switching element groups 31. The cascade signal line X0 is routed on the same side of the second shift register 22 and the switching element group 31 adjacent to the second shift register 22. The cascade signal line X0 led out from the first shift register 21 passes through the bridge section K02 of the gating control line K and is connected to the second shift register 22. In this way, interference between the cascade signal line X0 and the gating control line K can be avoided, and the routing structure of the cascade signal line X0 can be simplified.

[0059] Please refer to Figure 8 and Figure 10 and combined Figure 5 In one optional embodiment of this disclosure, the transmission signal line X0 includes a main portion X01 and a winding portion X02 electrically connected to the main portion. The main portion X01 is located in the area where the pixel driving circuit array 10 is located, along the second direction D2. The winding portion X02 is located on the side of the pixel driving circuit array 10 facing the edge B of the display panel. The winding portion X02 is electrically connected to the second shift register 22. The main portion X01 extends along the second direction D2. The winding portion X02 includes a first winding X21, a connecting portion X23, and a second winding X22 that are electrically connected in sequence. The first winding X21 and the second winding X22 extend along the first direction D1. The connecting portion X23 extends along the second direction D2. The first winding X21 is connected to the main portion X01, and the second winding X22 is connected to the second shift register 22.

[0060] It should be noted that this embodiment shows a scheme in which the bridge portion K02 in the gating control line K and the main portion X01 of the cascade signal line X0 are staggered in the second direction D2. That is, the bridge portion K02 in the gating control line K is not located directly below the extension direction of the main portion X01 of the cascade signal line X0. Therefore, it is necessary to introduce a winding portion X02 for the main portion X01 of the cascade signal line X0 so as to realize the electrical connection between the main portion X01 and the second shift register 22 through the winding portion X02. Taking the diagram as an example, when the bridge portion K02 of the selector control line K is located in the lower right region of the main portion X01 of the cascade signal line X0, the main portion X01 first connects to the first winding X21 extending along the first direction D1 in the winding portion X02. The first winding X21 extends to the right side of the main portion X01 and connects to the connecting portion X23 extending along the second direction D2. This is equivalent to the connecting portion X23 extending downwards from the first winding X21, passing through the bridge portion K02 of the selector control line K, and continuing downwards to connect with the second winding X22. The second winding X22 extends along the second direction D2 to the region where the second shift register 22 is located, thus achieving connection with the second shift register 22. In this way, by introducing the winding portion X02, the switching of the cascade signal line X0 is avoided, which helps to simplify the film layer setting of the display panel. At the same time, if the cascade signal line X0 is set as a whole in the second metal layer M2, it also helps to reduce the impedance of the cascade signal line X0 and improve the transmission efficiency of the cascade signal. It should be noted that when the bridge section K02 is located directly below the main section X01 of the transmission signal line X0, there is no need to introduce a winding section.

[0061] Please continue to refer to this. Figure 8 and Figure 10In one optional embodiment of this disclosure, the pixel driving circuit array 10 includes a plurality of pixel circuit column groups Z0 arranged along a first direction D1. Each pixel circuit column group includes at least two pixel circuit columns. This embodiment describes a single pixel circuit column group including three pixel circuit columns as an example, but this is not a limitation. Adjacent pixel circuit column groups Z0 are separated by a gap region Q0. Along the second direction D2, a bridge portion K02 overlaps with the gap region Q0. This is equivalent to placing the bridge portion K02 in the selection control line K directly below the gap region Q0 along the second direction D2. Considering that signal lines extending along the second direction D2 are provided between the pixel circuit arrays Z0, some of these signal lines (the type of these signal lines will be specifically described in subsequent embodiments) need to extend to the side of the pixel driving circuit array 10 facing the edge B of the display panel and be electrically connected to the bonding pad P1. Therefore, when the bridge portion K02 of the selection control line K is set in the area directly below the interval Q0, the aforementioned signal lines can pass through the bridge portion K02 for further extension. These signal lines can be set in the second metal layer M2. When passing through the area where the bridge portion K02 is located, there is no need to change or rewind the lines. The original routing layout can be maintained. Therefore, it is beneficial to simplify the wiring difficulty of the display panel after the introduction of the bridge portion K02 and simplify the manufacturing process.

[0062] Please refer to Figure 4 , Figure 8 and Figure 10 In one optional embodiment of this disclosure, the display panel further includes a plurality of first signal lines 51 extending along the second direction D2. The first signal lines 51 are configured to provide signals to the shift register circuit 20. The first signal lines 51 are located on at least one side of the shift register circuit 20 along the first direction D1 and are located in the interval region Q0. Along the plane perpendicular to the light-emitting surface of the display panel, the first signal lines 51 overlap with the bridge portion K02 but do not overlap with the main body portion K01. The first signal lines 51 and the main body portion K01 are disposed on the same layer.

[0063] The first signal line 51 mentioned in this embodiment is a trace that connects to the shift register circuit 20 and provides signals to the shift register circuit 20. Examples include a constant high-level signal line VGH that provides a high-level signal to the shift register circuit 20, a constant low-level signal line VGL that provides a low-level signal to the shift register circuit 20, and a first clock signal line XCK and a second clock signal line CK that provide clock signals to the shift register circuit 20. Optionally, the above four signal lines can be distributed in pairs on both sides of the corresponding shift register circuit 20 along the first direction D1. For example, the first clock signal line XCK and the second clock signal line CK are located on the left side of the shift register circuit 20, and the constant high-level signal line VGH and the constant low-level signal line VGL are located on the right side of the shift register circuit 20. This facilitates the connection between the shift register circuit 20 and these signal lines while making the routing of these signal lines more uniform. When the aforementioned first signal line 51 extends to the side of the pixel driving circuit array 10 facing the edge B of the display panel, it will overlap with the bridge portion K02 of the gating control line K and be disposed on a different layer than the bridge portion K02. For example, it can be disposed on the same layer as the main body portion K01 of the gating control line K. In this way, the first signal line 51 can be wired according to the original wiring method without the need for wire replacement. Therefore, even if the gating unit is placed between the second shift register 22 and the pixel driving circuit array 10, it will not affect the wiring structure of the first signal line 51. Optionally, both the first signal line 51 and the main body portion K01 of the gating control line K are located on the second metal layer M2 of the display panel. The resistivity of the second metal layer M2 is low, which is more conducive to reducing the voltage drop during signal transmission and improving signal transmission efficiency.

[0064] Please continue to refer to this. Figure 8 and Figure 10In one optional embodiment of this disclosure, the stage transmission signal line X0 is located in the interval Q0 and on the side of the first signal line 51 facing the shift register circuit 20. In addition to the first signal line 51 mentioned in the aforementioned embodiments, the signal line connected to the shift register circuit 20 also includes the stage transmission signal line X0. The stage transmission signal line X0 is used to connect shift registers of adjacent stages. For example, for the first shift register 21, in addition to being electrically connected to the pixel driving line GL, the output terminal of the first shift register 21 of this stage is also connected to the input terminal of the next-stage shift register through the stage transmission signal line X0. The first signal line 51 is a signal line shared by multiple shift registers in the shift register circuit 20. For example, the high-level signals required by multiple shift registers in the shift register circuit 20 are all provided by the same constant high-level signal line VGH, while the stage transmission signal line X0 transmits the output signal of the current stage shift register to the next-stage shift register. In this embodiment, when both the stage transmission signal line X0 and the first signal line 51 are located in the interval region Q0, the stage transmission signal line X0 is positioned on the side of the first signal line 51 facing the shift register circuit 20. That is, the stage transmission signal line X0 is closer to the shift register circuit 20 than the first signal line 51, which facilitates the connection of the stage transmission signal line X0 to the shift registers of the two adjacent stages. Optionally, the stage transmission signal line X0 is located in the second metal layer M2.

[0065] Please continue to refer to this. Figure 8 and Figure 10 In one optional embodiment of this disclosure, the data line DL includes a first type of data line DL1 and a second type of data line DL2 corresponding to the pixel circuit column group Z0. Both the first type of data line DL1 and the second type of data line DL2 are electrically connected to the pixel driving circuit 11. The first type of data line DL1 is also electrically connected to the gating circuit 30. Along the first direction D1, the first type of data line DL1 and the second type of data line DL2 are located on opposite sides of the corresponding pixel circuit column group Z0. The transmission signal line X0 and the second type of data line DL2 corresponding to the pixel driving circuit column group Z0 which is in the same column as the shift register circuit are located in the same interval area Q0.

[0066] Optionally, please combine Figure 5 , Figure 9 and Figure 10The display panel provided in this embodiment is a Micro LED display panel, and the light-emitting element in the display panel is a Micro LED. A pixel driving circuit 11 is used to connect to the light-emitting element and drive the light-emitting element to emit light. The pixel driving circuit 11 includes a pulse width modulation circuit (PWM) and a pulse amplitude modulation circuit (PAM) (the specific structures of the PWM and PAM can refer to existing structures, and this disclosure does not specifically limit them). The PWM and PAM are electrically connected, and the output terminal of the PAM is electrically connected to the light-emitting element to provide a driving current to the light-emitting element. The PAM is configured to control the amplitude of the driving current, and the PWM is configured to control the pulse width of the driving current. The pulse width of the driving current is understood as the duration of the driving current, and the amplitude of the driving current is understood as the magnitude of the driving current value. The first type of data line DL1 mentioned in this embodiment is a signal line that transmits data signals to the PWM circuit, and the second type of data line DL2 is a signal line that transmits data signals to the PAM circuit. To achieve uniform arrangement of signal lines, the first type of data line DL1 and the second type of data line DL2 are respectively disposed on both sides of the pixel driving circuit 11 along the first direction D1. Optionally, the second type of data line DL2 is a global signal line. For example, the second type of data line DL2 that provides data signals to light-emitting elements of the same color is electrically connected, thus eliminating the need for a gating circuit 30 for the second type of data line DL2. The first type of data line DL1 is connected to the gating circuit 30 on the side of the pixel driving circuit array 10 facing the edge B of the display panel. During connection, the first part X1 of the first type of data line DL1 is wound through the second part X2 to the top of the gating circuit 30 and electrically connected to it. The transmission signal line X0 is electrically connected to the second shift register 22 through the winding part X02. If the transmission signal line X0 and the first type of data line DL1 are placed in the same interval, the second part X2 of the first type of data line DL1 will interfere with the winding part X02 of the transmission signal line X0, requiring wire replacement to achieve electrical connection with the second shift register 22. In this embodiment, when the cascade signal line X0 and the second type data line DL2 are placed in the same interval area Q0 on one side of the pixel driving circuit 11, the second part X2 in the first type data line DL1 and the winding part X02 in the cascade signal line X0 do not interfere with each other, which is more conducive to simplifying the wiring of the first type data line DL1 and the cascade signal line X0.

[0067] Please continue to refer to this. Figure 8 and Figure 10 In one optional embodiment of this disclosure, with Figure 8 and Figure 10Taking the left-side pixel driving circuit column group Z0 as an example, the shift register circuit is located in the same column as the pixel driving circuit column group Z0. When the stage transmission signal line X0 and the second type data line DL2 are set in the same interval area Q0, the second type data line DL2 is located between the stage transmission signal line X0 and the first signal line 51.

[0068] This embodiment defines the relative positional relationship of the transmission signal line X0, the first signal line 51, and the second type of data line DL2 when they are simultaneously set in the same interval area Q0. It should be noted that the interval area Q0 mentioned in this embodiment is the interval area Q0 located on both sides of the same shift register circuit 20 and adjacent to the shift register circuit 20, and is also the interval area Q0 located on both sides of the same pixel circuit column group Z0 and adjacent to the pixel circuit column group Z0. The aforementioned cascade signal line X0 and the first signal line 51 are both connected to the shift register circuit 20, and the second type of data line DL2 is electrically connected to the pixel driving circuit 11. In this embodiment, the cascade signal line X0 is closest to the shift register circuit 20, the second type of data line DL2 is located between the cascade signal line X0 and the first signal line 51, and the first signal line 51 is furthest from the shift register circuit 20. This makes it easier to route the cascade signal line X0 used to connect the first shift register 21 and the second shift register 22, avoiding wire wrapping. At the same time, when the winding portion X02 in the cascade signal line X0 and the first signal line 51 both extend to the bridge portion K02 of the gating control line K, the cascade signal line X0 and the first signal line 51 will not interfere with each other, thereby reducing the difficulty of wiring.

[0069] In one alternative embodiment of this disclosure, please refer to Figure 8 and Figure 10 In the same switching element group 31, the input terminals of different switching elements T are connected to the same input line 60. Along the direction perpendicular to the light-emitting surface of the display panel, at least some of the input lines 60 corresponding to the switching element group 31 overlap with the bridge portion K02 of the gating control line K, and the input line 60 and the main body portion K01 of the gating control line K are arranged on the same layer.

[0070] To facilitate the connection between the data line DL and the switching elements in the switching element group 31 and avoid data line DL replacement, in the gating circuit 30 provided in this disclosure, the switching elements are located between the pixel driving circuit array 10 and the gating control line K. The input terminals of the switching elements in the same switching element group 31 are electrically connected to the same input line 60. This input line 60 is used to electrically connect to the bonding pad P1 in the display panel. The bonding pad P1 is usually located on the side of the gating circuit 30 away from the pixel driving circuit array 10. Therefore, when the input line 60 is electrically connected to the bonding pad P1, the input line 60 will pass through the gating control line K. In this embodiment, please refer to... Figure 8 and Figure 10The input line 60, corresponding to the switching element group 31 located on the left, is disposed on the same layer as the main body K01 of the selection control line K. The input line 60 passes through the selection control line K from the bridge portion K02. In this configuration, the input line 60 does not require a wire-changing operation, simplifying the wiring process. Furthermore, the input line 60 can be placed on the second metal layer M2 of the display panel to reduce its impedance and signal transmission voltage drop, thereby increasing the signal transmission rate on the input line 60.

[0071] When a first shift register 21 is introduced into the region where the pixel circuit array is located, a first signal line 51 connected to the shift register circuit 20 and a cascading signal line X0 are set in the interval Q0 adjacent to the first shift register 21. To avoid interference of the selection control line K in the selection circuit 30 with these signal lines, a bridge section K02 is introduced in the selection control line K. The aforementioned signal lines pass through the selection control line K at the position of the bridge section K02. For the input line 60 connected to the switching element in the selection circuit 30, if a bridge section K02 is provided on the selection control line K in the region, the input line 60 can pass through the selection control line K from the position of the bridge section K02. Considering that each pixel circuit group Z0 is provided with a selection circuit 30 on the side facing the edge B of the display panel, and only a few pixel circuit groups Z0 are provided with a shift register circuit 20, not every adjacent switching element group 31 will have a bridge section K02 introduced between them. For example, Figure 8 and Figure 10 In the illustrated embodiment, no shift register circuit is provided at the position corresponding to the pixel driving circuit column group Z0 on the right. In the switching element group 31 corresponding to the pixel driving circuit column Z0, when no bridge is provided on the gating control line K in the area corresponding to the input line 60, the input line 60 can also be switched when passing through the bridge section K02. For example, please refer to... Figure 10 The input line 60 corresponding to the switch element group 31 on the right side is connected to the same input line 60. At this time, the input terminals of different switch elements in the same switch element group 31 are connected to the same input line 60. Along the direction perpendicular to the light-emitting surface of the display panel, at least part of the input line 60 corresponding to the switch element group 31 overlaps with the main body K01 of the gating control line K to form a second overlap area Q2. In the second overlap area Q2, the input line 60 and the bridge part K02 of the gating control line K are arranged on the same layer.

[0072] This embodiment shows that when the input line 60 of the switching element group 31 passes through the gating control line K, and no bridge portion K02 is provided at the position corresponding to the gating control line K, the input line 60 can be arranged to overlap with the main body portion K01 of the gating control line K. In the second overlap area Q2 formed by the overlap of the two, the input line 60 and the main body portion K01 of the gating control line K are arranged in different layers, and the input line 60 can be arranged in the same layer as the bridge portion K02 in other areas of the gating control line K. This makes reasonable use of the existing film layer in the display panel to avoid interference between the input line 60 and the gating control line K.

[0073] Figure 12 and Figure 13 The diagrams shown below illustrate another relative positional relationship between the switching element group 31 and the selection control line K in the selection circuit 30 provided in this embodiment. Please refer to diagram 8. Figure 12 and Figure 13 In one optional embodiment of this disclosure, the line width of the main body portion K01 in the second overlapping area Q2 is less than or equal to its line width in other areas; and / or, the main body portion K01 further includes a first opening 91, which is located at least in the second overlapping area Q2 along a direction perpendicular to the plane of the display panel.

[0074] When the input line 60 overlaps with the main body K01 of the gating control line K using a switching method, Figure 12 The illustrated embodiment shows a scheme to narrow the width of the line segment of the main body K01 located in the second overlap region Q2. This reduces the overlap area between the input line 60 and the gating control line K in the second overlap region Q2, thereby reducing the coupling capacitance between the two and reducing or avoiding interference from the coupling capacitance on the signals on the input line 60 and the gating control line K. In addition, other methods can also be used... Figure 13 In the illustrated embodiment, a first opening 91 is formed on the line segment of the main body K01 located in the second overlapping region Q2, so that the first opening 91 overlaps with the input line 60. This also reduces the actual overlap area between the input line 60 and the selection control line K, thus also helping to reduce the coupling capacitance between them. It should be noted that, to further reduce the coupling capacitance between the input line 60 and the selection control line K, in the second overlapping region Q2, while narrowing the line width of the main body K01, a first opening 91 can also be formed on the narrower main body K01, for example... Figure 13 The scheme shown.

[0075] Please continue to refer to this. Figure 12 and Figure 13In one optional embodiment of this disclosure, the gate of the switching element is electrically connected to the gating control line K via a gate connection line 70, which extends along the second direction D2; at least one gate connection line 70 overlaps with the main body portion K01 in a direction perpendicular to the plane where the light-emitting surface of the display panel is located to form a third overlap region Q3; the linewidth of the main body portion K01 in the third overlap region Q3 is less than or equal to its linewidth in other regions; and / or, the main body portion K01 further includes a second opening 92, which is located at least in the third overlap region Q3 in a direction perpendicular to the plane where the display panel is located.

[0076] Please combine Figure 1 , Figure 2 , Figure 12 and Figure 13 To facilitate the connection between the switching elements in the selection circuit 30 and the data line DL, and to avoid the risk of short circuits or breaks caused by changing the data line DL, in this embodiment, the switching element group 31 in the selection circuit 30 is arranged on the side of the selection control line K facing the pixel driving circuit array 10. Considering that the gate of the switching element in the switching element group 31 is connected to the selection control line K, Figure 12 For example, the three switching elements in the same switching element group 31 are electrically connected to the three gating control lines K one by one. The three gating control lines K are arranged along the second direction D2. When the switching element is connected to the gating control line K that is not adjacent to the switching element, the gate connection line 70 will pass through one or two other gating control lines K and overlap with other gating control lines K to form a third overlap region Q3. The gate connection line 70 can be set in the same layer as the gate of the switching element, so that the gate connection line 70 and the main body K01 of the gating control line K are located in different film layers. In this way, the gate connection line 70 can achieve electrical connection with the corresponding gating control line K without changing the line, which helps to simplify the wiring complexity of the gate connection line 70.

[0077] Considering that when the gate connection line 70 overlaps with the gating control line K, a coupling capacitance may be generated between the gate connection line 70 and the gating control line K, causing signal interference, the linewidth of the main body K01 of the gating control line K can be reduced in the third overlap region Q3. For example, please refer to... Figure 12 and Figure 13 This reduces the actual overlap area between the gate connection line 70 and the gating control line K, thereby reducing the coupling capacitance between them. Alternatively, please refer to... Figure 13Alternatively, a second opening 92 can be formed on the main body K01 of the third overlapping region Q3, so that the second opening 92 overlaps with the gate connection line 70. This can also reduce the actual overlap area between the gate connection line 70 and the gating control line K, thereby reducing the coupling capacitance between them. Alternatively, in the third overlapping region Q3, while reducing the linewidth of the main body K01, a second opening 92 can be formed on the main body K01. This is even more beneficial for reducing the actual overlap area between the gate connection line 70 and the gating control line K, reducing or avoiding signal interference between them.

[0078] Optionally, the gate connection line 17 can be electrically connected to the gating control line K by wiring on the left side of the corresponding transistor along the first direction, or by wiring on the right side of the corresponding transistor along the first direction. This disclosure does not specifically limit this.

[0079] Figure 14 The diagram shows a layout of the gating control line K and its overlapping first signal line 51. When the gating control line K extending along the first direction D1 overlaps with the first signal line 51 extending along the second direction D2, the first signal line 51 can be arranged on the same layer as the main body K01 of the gating control line K and overlap with the bridge portion K02 of the gating control line K. To reduce signal interference between the two, the line width of the first signal line 51 can be reduced in the overlapping area, making the line width of the first signal line 51 in the overlapping area smaller than the line width in other areas. It should be noted that... Figure 14 Taking the signal line overlapping with the gating control line K as an example, this explanation uses the first signal line 51 as an example. In some other embodiments of this disclosure, when the signal line overlapping with the gating control line K is another signal line, the same approach can be used. Figure 14 The design reduces the linewidth of the signal line extending along the second direction D2 in the overlapping area.

[0080] It should also be noted that when the main body K01 and the bridging part K02 are introduced into the gating control line, the main body K01 and the bridging part K02 located in different membrane layers can be electrically connected through one or more connecting holes LK. When there are multiple connecting holes LK, for example, please refer to... Figure 14 The multiple connection holes LK are essentially connected in parallel, which helps to reduce the overall impedance of the selection control line K.

[0081] Please refer to Figure 1 and Figure 2 and combined Figure 8In one optional embodiment of this disclosure, the pixel driving circuit array 10 includes a plurality of pixel circuit column groups Z0 arranged along a first direction D1. Each pixel circuit column group Z0 includes at least two pixel circuit columns, and there is a gap Q0 between adjacent pixel circuit column groups Z0. Along the second direction D2, the shift register circuit 20 and the gating circuit 30 overlap with the pixel circuit column group Z0. The first direction D1 and the second direction D2 intersect, and the second direction D2 is the direction in which the pixel driving circuit array 10 points to the second shift register 22.

[0082] In this embodiment, the first shift register 21 in the shift register circuit 20 is located in the area where the pixel driving circuit array 10 is located. Typically, the display area includes the area where the aforementioned pixel driving circuit array 10 is located. Therefore, it is equivalent to placing at least most of the shift registers in the shift register circuit 20 in the display area, without occupying the space of the bezel area of ​​the display panel, which is beneficial for realizing a narrow bezel or bezel-less design of the display panel. When the shift register circuit 20 and the gating circuit 30 are introduced into the display panel, this disclosure sets the shift register circuit 20 and the gating circuit 30 to overlap with the pixel circuit column group Z0 along the second direction D2. Specifically, the shift registers in the shift register circuit 20 and the switching element group 31 in the gating circuit 30 overlap with the pixel circuit column group Z0. This can reduce the space occupied by the shift registers or the switching element group 31 in the interval area Q0 between the pixel circuit column groups Z0, and avoid the shift registers or the switching element group 31 affecting the original wiring structure in the interval area Q0.

[0083] Please refer to Figure 8 In one optional embodiment of this disclosure, along the second direction D2, neither the first shift register 21 nor the second shift register 22 overlaps with the spacing region Q0. Thus, the first shift register 21 does not occupy the space of the spacing region Q0 between the columns of the pixel driving circuit 11, and the second shift register 22 does not occupy the space in the extending direction of the spacing region Q0, thereby not affecting the original wiring structure of the spacing region Q0.

[0084] Figure 15 The diagram shown is another planar structural diagram of the display panel provided in this embodiment. Please refer to... Figure 15 In one optional embodiment of this disclosure, the display panel includes an electrostatic discharge (ESD) protection circuit 70. The ESD protection circuit 70 is located on the side of the pixel driving circuit array 10 facing the edge B of the display panel, and at least a portion of the ESD protection circuit 70 is electrically connected to the second shift register 22. It should be noted that... Figure 15 Only the electrostatic discharge (ESD) protection circuit 70 connected to the second shift register 22 is shown. In reality, other ESD protection circuits 70 can be provided on the side of the pixel drive circuit array 10 facing the edge B of the display panel, for example, please refer to [reference needed]. Figure 5It can be electrically connected to other signal lines that require electrostatic protection, but this disclosure does not specifically limit this.

[0085] This embodiment illustrates a scheme in which an electrostatic discharge (ESD) protection circuit 70 is introduced on the side of the pixel driving circuit array 10 facing the edge B of the display panel. This ESD protection circuit 70 is disposed on the side of the display panel near its edge and is used to connect to some signal lines in the display panel near its edge to prevent ESD from affecting the display panel. For example, part of the ESD protection circuit 70 can be electrically connected to the output terminal of the second shift register 22, thereby preventing ESD from affecting the shift register circuit 20. It should be noted that the ESD protection circuit 70 can adopt a structure from related technologies, and this disclosure does not specifically limit it.

[0086] Figure 16 The diagram shown is a layout of the pixel driving circuit array 10 in a display panel according to an embodiment of this disclosure, facing the edge B of the display panel. It should be noted that... Figure 16 This illustration only shows a portion of the film layers in the display panel; not all film layers are shown. Please refer to [the original text]. Figure 16 In one optional embodiment of this disclosure, the display panel further includes a second signal line 52 disposed between the electrostatic protection circuit 70 and the pixel driving circuit array 10. On the side of the pixel driving circuit array 10 facing the edge B of the display panel, the second signal line 52 extends in a first direction D1 and has a broken line in some areas. For example, the second signal line 52 includes a first line segment 521, a connecting line segment 520 and a second line segment 522 that are electrically connected in sequence and disposed on the same layer. The first line segment 521 and the second line segment 522 both extend along the first direction D1, and the connecting line segment 520 extends along the second direction D2. The first direction D1 and the second direction D2 intersect. Along the first direction D1, at least part of the first line segment 521 and the connecting line segment 520 overlaps with the second shift register 22, while the second line segment 522 does not overlap with the second shift register 22.

[0087] Optionally, the second signal line 52 includes a power signal line that provides a power signal to the electrostatic discharge (ESD) protection circuit, and may also include a detection signal line for connecting the second shift register circuit and the test pad. The aforementioned power signal line can also be used to provide a power signal to the pixel driving circuit; that is, the power signal of the ESD protection circuit can be multiplexed with the power signal of the pixel driving circuit. It should be noted that... Figure 16 Only the wiring structure of the second signal line 52 is illustrated; the actual number of second signal lines 52 is not limited. In this embodiment, when the second signal line 52 is laid out on the side of the pixel driving circuit array facing the edge B of the display panel, compared to setting the second signal line 52 as a straight line, the space on both sides of the second shift register 22 along the first direction D1 is utilized more effectively. For example, please refer to the comparison reference. Figure 16 and Figure 17 , Figure 17 The diagram shows a reference layout of the pixel driving circuit array facing the edge B of the display panel. The gating circuit 30 is located on the side of the shift register circuit 20 facing the edge of the display panel. The gating control line and the second signal line 52 are both located on the side of the switching element group 31 facing the edge B of the display panel. Both the gating control line and the second signal line 52 are straight lines extending along the first direction D1, and they occupy a relatively large space. When the minimum distance d0 between the second signal line 52 and the edge B of the display panel is fixed, Figure 17 In the wiring method, the electrostatic protection circuit 70 is set on the side of the second signal line 52 facing the edge B of the display panel, which makes the distance d2 between the electrostatic protection circuit 70 and the edge B of the display panel smaller. This increases the risk of the transistor in the electrostatic protection circuit 70 being damaged by the cutting laser when the display panel is cut. In this embodiment, the arrangement of the gating circuit 30 and the second shift register 22 is adjusted. The second shift register 22 is set on the side of the gating control line K in the gating circuit 30 facing the edge B of the display panel. On the side of the gating control line K facing the edge B of the display panel, the second shift register 22 is arranged along the first direction D1, and there is a gap between adjacent second shift registers 22. This gap can be used to arrange part of the line segment in the second signal line 52. For example, moving the first line segment 521 and the connecting line segment 520 into this space is equivalent to moving part of the line segment of the second signal line 52 upward. After the line segment of the first signal line 52 is moved upward, the electrostatic protection circuit 70 located on the side of the second signal line 52 facing the edge B of the display panel also has space to move upward. In this way, when the minimum distance between the second signal line 52 and the edge B of the display panel is fixed at d0, the distance d1 between at least part of the electrostatic protection circuit 70 and the edge B of the display panel can be increased, so that d1 > d2, thereby helping to reduce the risk of the transistor in this part of the electrostatic protection circuit 70 being damaged by the cutting laser.

[0088] It should be noted that the distance between different electrostatic protection circuits 70 and the edge B of the display panel can be set to different values. The distance between different electrostatic protection circuits 70 and the edge B of the display panel can be adjusted according to the actual wiring situation. This disclosure does not make specific limitations in this regard.

[0089] Please continue to refer to this. Figure 15In one optional embodiment of this disclosure, the pixel driving circuit array 10 includes a plurality of pixel circuit columns Z0 arranged along a first direction D1. Each pixel circuit column Z0 includes at least two pixel circuit columns, and there is a gap Q0 between adjacent pixel circuit column groups Z0. Along the second direction D2, at least a portion of the electrostatic protection circuit 70 overlaps with the pixel circuit column group Z0, but does not overlap with the gap Q0. The first direction D1 and the second direction D2 intersect, and the second direction D2 is the direction in which the pixel driving circuit array 10 points to the second shift register 22.

[0090] Considering that some signal lines in the interval area between the pixel circuit arrays Z0 need to extend to the edge B area of ​​the display panel and be electrically connected to the bonding pad P1, this part of the signal lines is equivalent to penetrating most of the length direction of the display panel along the second direction D2. When an electrostatic discharge (ESD) protection circuit 70 is introduced on the side of the pixel driving circuit array 10 facing the edge B of the display panel, in this embodiment of the present disclosure, at least part of the ESD protection circuit 70 along the second direction D2 is not overlapped with the interval area Q0. Instead, the ESD protection circuit 70 is placed directly below the pixel driving circuit array 11. In this way, this part of the ESD protection circuit 70 will not occupy the space in the extension direction of the interval area Q0, thereby avoiding interference of the ESD protection circuit 70 with the signal lines in the interval area that originally need to extend to the edge B area of ​​the display panel and be electrically connected to the bonding pad P1. This avoids the need for this part of the signal lines to be wound around the ESD protection circuit 70, thus simplifying the wiring process of the signal lines in the interval area Q0.

[0091] Figure 18 The diagram shown is a layout schematic of the light-emitting element (LD) in an embodiment of this disclosure. Figure 19 The image shown is a partial layout diagram of the display panel. Please refer to it. Figure 18 and Figure 19 In one optional embodiment of this disclosure, the display panel further includes light-emitting elements (LDs) electrically connected to the pixel driving circuit 11. Optionally, the light-emitting elements (LDs) are uniformly arranged in the display panel, and at least some of the light-emitting elements (LDs) are located on the side of the pixel driving circuit array 10 facing the edge B of the display panel. It should be noted that... Figure 18 This description only illustrates one arrangement of light-emitting elements (LDs) in a display panel and does not limit the actual number of LDs included in the display panel, nor the relative positional relationship or quantity correspondence between the LDs and the pixel driving circuits. It should also be noted that the light-emitting elements can include various different colors, such as red, green, and blue light-emitting elements, and this disclosure does not limit them.

[0092] In a display panel, the area where light-emitting elements (LDs) are located can be considered the display area. When the LDs are positioned on the side of the pixel driving circuit array 10 facing the edge B of the display panel, this means that the side of the pixel driving circuit array 10 facing the edge B of the display panel also belongs to the display area. This arrangement helps to increase the proportion of the display area in the display panel, improve the screen-to-body ratio, and achieve an extremely narrow bezel or even a bezel-less design. Since the pixel driving circuit 11 connected to the LDs is located in the area of ​​the pixel driving circuit array 10, the LDs located on the side of the pixel driving circuit array 10 facing the edge B of the display panel can be electrically connected to the corresponding pixel driving circuit 11 via signal lines led out from the pixel driving circuit array 10.

[0093] Please continue to refer to this. Figure 18 and Figure 19 In one optional embodiment of this disclosure, at least a portion of the light-emitting elements (LDs) overlap with the gating circuit 30 along a direction perpendicular to the plane of the display panel. This is equivalent to placing the light-emitting elements (LDs) on the side of the gating circuit 30 facing the light-emitting surface of the display panel. The area where this portion of the light-emitting elements (LDs) is located is reused with the area where the gating circuit 30 is located, which facilitates the rational use of the display panel space for arranging the light-emitting elements (LDs) and improves the space utilization rate of the display panel. Furthermore, since the area where this portion of the light-emitting elements (LDs) is located is reused with the area where the gating circuit 30 is located, it is equivalent to placing the gating circuit 30 in the display area of ​​the display panel, avoiding the gating circuit 30 occupying space in the non-display area. Therefore, it is beneficial to achieve an extremely narrow bezel or bezel-less design for the display panel.

[0094] Please continue to refer to this. Figure 18 and Figure 19 In one optional embodiment of this disclosure, the display panel further includes an electrostatic discharge (ESD) protection circuit 70 disposed on the side of the pixel driving circuit array 10 facing the edge B of the display panel, with at least a portion of the light-emitting elements (LDs) located on the side of the ESD protection circuit 70 facing the edge B of the display panel. This embodiment illustrates a scheme in which the light-emitting elements (LDs) are disposed on the side of the ESD protection circuit 70 away from the pixel driving circuit array 10, which is equivalent to also disposing of the light-emitting elements (LDs) in the area near the lower edge of the display panel. In this way, the ESD protection circuit 70 is also integrated into the display area, without occupying space in the non-display area, which is also beneficial for achieving an extremely narrow bezel or bezel-less design of the display panel.

[0095] Please combine Figure 11 and Figure 18In one optional embodiment of this disclosure, the display panel further includes a first electrode P01 and a second electrode P02 electrically connected to the light-emitting element LD. Along a direction perpendicular to the light-emitting surface of the display panel, the first electrode P01 and the second electrode P02 are located on the side of the pixel driving circuit 11 facing the light-emitting surface of the display panel. The first electrode P01 is electrically connected to the pixel driving circuit 11, and the second electrode P02 is electrically connected to a constant-level signal line. When the pixel driving circuit 11 provides a driving current to the first electrode P01, it drives the corresponding light-emitting element LD to emit light. Optionally, the first electrode P01 and the second electrode P02 can be located on the same film layer of the display panel, or they can be disposed on different layers of the display panel depending on the actual situation; this disclosure does not specifically limit this. When the light-emitting element LD is not located directly above the corresponding pixel driving circuit 11, the pixel driving circuit 11 and the first electrode P01 can be electrically connected via signal traces.

[0096] Based on the same inventive concept, this disclosure also provides a display device. Figure 20 The diagram shown is a structural schematic of a display device provided in an embodiment of this disclosure. Please refer to it. Figure 20 The display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in this disclosure can be any electronic device with display function, such as a tablet computer with touch and display functions, a display cabinet product, a television, or an in-vehicle display device, and is particularly suitable for display devices with extremely narrow bezels or no bezels. The display device 200 provided in this disclosure has the beneficial effects of the display panel 100 provided in this disclosure. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments; these will not be repeated here.

[0097] Understandable Figure 20 The rectangular structure is used to illustrate the display device. In some other embodiments of this disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it.

[0098] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0099] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, It includes a pixel driving circuit array, a shift register circuit and a gating circuit, as well as pixel driving lines and data lines, wherein the pixel driving circuit array includes multiple pixel driving circuits; The pixel driving line and the data line are electrically connected to the pixel driving circuit, respectively. The pixel driving line is used to transmit control signals to the pixel driving circuit, and the data line is used to transmit data signals to the pixel driving circuit. The shift register circuit is configured to transmit the control signal to the pixel drive line, and the gating circuit is configured to transmit the data signal to the data line; The shift register circuit includes multiple cascaded shift registers, each including multiple cascaded first shift registers and a second shift register cascaded with the first shift registers. The first shift registers are located in the area where the pixel driving circuit array is located, and the second shift registers are located on the side of the pixel driving circuit array facing the edge of the display panel. The gating circuit is located between the pixel driving circuit array and the second shift registers.

2. The display panel according to claim 1, characterized in that, The output of the first shift register is electrically connected to the pixel driving circuit through the pixel driving line, and the display panel also includes bonding pads. The output of the second shift register is electrically connected to the bonding pads.

3. The display panel according to claim 2, characterized in that, The display panel also includes a test signal line, and the output of the second shift register is electrically connected to the test signal line.

4. The display panel according to claim 1, characterized in that, The gating circuit includes multiple groups of switching elements, each group of switching elements includes at least two switching elements, and the output terminal of each switching element is electrically connected to the data line. The data line includes a first part and a second part that are electrically connected. The first part is located at least in the area where the pixel driving circuit array is located, and the second part is located on the side of the pixel driving circuit array facing the edge of the display panel. The first part is electrically connected to the switching element through the second part, and the first part and the second part are arranged on the same layer.

5. The display panel according to claim 4, characterized in that, The gating circuit includes at least two gating control lines. In the same group of switching elements, the gates of different switching elements are connected to different gating control lines. The gating control lines extend along a first direction, and the first part extends along a second direction. The first direction and the second direction intersect. Along the second direction, the group of switching elements is located between the gating control lines and the pixel driving circuit array.

6. The display panel according to claim 5, characterized in that, The width of the gating control line is greater than the width of the first part.

7. The display panel according to claim 5, characterized in that, The second shift register is electrically connected to the first shift register via a cascade signal line. Along a direction perpendicular to the plane where the display panel is located, the cascade signal line and the gating control line overlap to form a first overlap area. In the first overlap area, the cascade signal line and the gating control line are arranged on different layers.

8. The display panel according to claim 7, characterized in that, The selection control line includes a main body and a bridge section connected to the main body. The main body and the bridge section are disposed on different layers and both extend along the first direction. The bridge section is at least partially located in the first overlap area, and the transmission signal line is disposed on the same layer as the main body.

9. The display panel according to claim 8, characterized in that, The display panel includes a substrate and a first metal layer and a second metal layer disposed on the substrate. The resistivity of the second metal layer is less than that of the first metal layer. The main body of the gating control line and the transmission signal line are located on the second metal layer, and the bridge portion of the gating control line is located on the first metal layer.

10. The display panel according to claim 8, characterized in that, Along the first direction, the bridge portion is located between adjacent groups of switching elements; along the second direction, the second shift register and the groups of switching elements overlap. Along the first direction, the cascading signal line connected to the second shift register is located on the same side of the second shift register and the switching element group corresponding to the second shift register.

11. The display panel according to claim 10, characterized in that, The transmission signal line includes a main part and a winding part electrically connected to the main part. The main part is located in the area where the pixel driving circuit array is located along the second direction. The winding part is located on the side of the pixel driving circuit array facing the edge of the display panel. The winding part is electrically connected to the second shift register. The main part extends along the second direction, and the winding part includes a first winding, a connecting part, and a second winding that are electrically connected in sequence. The first winding and the second winding extend along the first direction, and the connecting part extends along the second direction. The first winding is connected to the main part, and the second winding is connected to the second shift register.

12. The display panel according to claim 8, characterized in that, The pixel driving circuit array includes a plurality of pixel circuit columns arranged along the first direction, each pixel circuit column group including at least two pixel circuit columns, with a gap between adjacent pixel circuit columns, and the bridge portion overlapping the gap along the second direction.

13. The display panel according to claim 12, characterized in that, The display panel further includes a plurality of first signal lines extending along the second direction, the first signal lines being configured to provide signals to the shift register circuit; the first signal lines are located on at least one side of the shift register circuit along the first direction and within the interval region; along a plane perpendicular to the light-emitting surface of the display panel, the first signal lines overlap with the bridge portion but do not overlap with the main body portion; the first signal lines are disposed on the same layer as the main body portion.

14. The display panel according to claim 13, characterized in that, The cascade signal line is located in the interval region and on the side of the first signal line facing the shift register circuit.

15. The display panel according to claim 13, characterized in that, The data lines include a first type of data line and a second type of data line corresponding to the pixel circuit array. Both the first type of data line and the second type of data line are electrically connected to the pixel driving circuit. The first type of data line is also electrically connected to the gating circuit. Along the first direction, the first type of data line and the second type of data line are located on opposite sides of the corresponding pixel circuit array. The transmission signal line and the second type of data line are located in the same interval area.

16. The display panel according to claim 15, characterized in that, The second type of data line is located between the transmission signal line and the first signal line.

17. The display panel according to claim 8, characterized in that, In the same group of switching elements, the input terminals of different switching elements are connected to the same input line. Along the direction perpendicular to the light-emitting surface of the display panel, at least a portion of the input lines corresponding to the switching element groups overlap with the bridge portion of the gating control line, and the input lines and the main body portion of the gating control line are arranged on the same layer.

18. The display panel according to claim 8, characterized in that, In the same group of switching elements, the input terminals of different switching elements are connected to the same input line. Along the direction perpendicular to the light-emitting surface of the display panel, at least a portion of the input lines corresponding to the switching element groups overlap with the main body of the gating control line to form a second overlap area. In the second overlap area, the input lines and the bridge portion of the gating control line are arranged on the same layer.

19. The display panel according to claim 18, characterized in that, The line width of the main body portion in the second overlapping area is less than or equal to its line width in other areas; and / or, the main body portion further includes a first opening along a direction perpendicular to the plane of the display panel, the first opening being located at least in the second overlapping area.

20. The display panel according to claim 8, characterized in that, The gate of the switching element is electrically connected to the gating control line via a gate connection line, the gate connection line extending along the second direction; at least one of the gate connection lines overlaps with the main body portion to form a third overlap area along a direction perpendicular to the plane where the light-emitting surface of the display panel is located; the line width of the main body portion in the third overlap area is less than or equal to its line width in other areas; and / or, the main body portion further includes a second opening, along a direction perpendicular to the plane where the display panel is located, the second opening being at least located in the third overlap area.

21. The display panel according to claim 1, characterized in that, The pixel driving circuit array includes multiple pixel circuit columns arranged along a first direction, each pixel circuit column including at least two pixel circuit columns, with a gap between adjacent pixel circuit columns; along a second direction, the shift register circuit and the gating circuit both overlap with the pixel circuit columns, the first direction and the second direction intersect, and the second direction is the direction in which the pixel driving circuit array points to the second shift register.

22. The display panel according to claim 21, characterized in that, Along the second direction, neither the first shift register nor the second shift register overlaps with the interval region.

23. The display panel according to claim 1, characterized in that, The display panel includes an electrostatic discharge (ESD) protection circuit located on the side of the pixel driving circuit array facing the edge of the display panel, and at least a portion of the ESD protection circuit is electrically connected to the second shift register.

24. The display panel according to claim 23, characterized in that, The display panel further includes a second signal line disposed between the electrostatic protection circuit and the pixel driving circuit array. The second signal line includes a first line segment, a connecting line segment, and a second line segment that are electrically connected in sequence and disposed on the same layer. The first line segment and the second line segment both extend along a first direction, and the connecting line segment extends along a second direction. The first direction and the second direction intersect. Along the first direction, at least a portion of the first line segment and the connecting line segment overlap with the second shift register, while the second line segment does not overlap with the second shift register.

25. The display panel according to claim 24, characterized in that, The second signal line includes a power signal line and at least one detection signal line. The power signal line is used to provide a power signal to the pixel driving circuit, and the detection signal line is used to be electrically connected to the output of the second shift register.

26. The display panel according to claim 24, characterized in that, The pixel driving circuit array includes a plurality of pixel circuit columns arranged along a first direction, each pixel circuit column including at least two pixel circuit columns, with a gap between adjacent pixel circuit columns; along a second direction, at least a portion of the electrostatic protection circuit overlaps with the pixel circuit columns, but does not overlap with the gap; the first direction and the second direction intersect, the second direction being the direction in which the pixel driving circuit array points to the second shift register.

27. The display panel according to claim 1, characterized in that, It also includes light-emitting elements electrically connected to the pixel driving circuit, with at least a portion of the light-emitting elements located on one side of the pixel driving circuit array facing the edge of the display panel.

28. The display panel according to claim 27, characterized in that, Along a direction perpendicular to the plane of the display panel, at least a portion of the light-emitting element overlaps with the gating circuit.

29. The display panel according to claim 27, characterized in that, It also includes an electrostatic discharge (ESD) protection circuit disposed on the side of the pixel driving circuit array facing the edge of the display panel, with at least some of the light-emitting elements located on the side of the ESD protection circuit facing the edge of the display panel.

30. The display panel according to claim 27, characterized in that, It also includes a first electrode and a second electrode electrically connected to the light-emitting element; along a direction perpendicular to the light-emitting surface of the display panel, the first electrode and the second electrode are located on the side of the pixel driving circuit facing the light-emitting surface of the display panel.

31. A display device, characterized in that, Includes the display panel described in any one of claims 1 to 30.

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