Driving circuit, display panel and display device

Abstract

The present application discloses a driving circuit, a display panel, and a display device, belonging to the field of liquid crystal display technology, comprising: a driving module that receives a first control signal to output a first driving signal; a common voltage line that transmits a common voltage; a first control module connected to the driving module, the first control module having a first output terminal and a first input terminal, the first input terminal being connected to the common voltage line; in response to the driving module outputting the first driving signal, the first control module is turned on to connect the first output terminal to the first input terminal so that the potential output by the first output terminal is equal to the potential of the common voltage. The driving circuit provided in the present application sends a first driving signal to the first control module through the driving module to connect the first output terminal of the first control module to the common voltage line, thereby reducing the voltage difference between the voltage output by the first output terminal and the common voltage, thereby improving the white flickering phenomenon of the display panel and further improving the display effect of the display panel.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of liquid crystal display technology, and in particular to a driving circuit, a display panel, and a display device. Background Art

[0002] Liquid crystal displays (LCDs) are currently the most popular display device, widely used in a variety of electronic devices, including computer monitors, televisions, smartphones, and tablets. With their high-quality image display and convenient user experience, they have become an indispensable part of modern society. However, when an LCD is powered on, the internal voltage input to the display is in a floating state, causing the LCD screen to flicker white. Summary of the Invention

[0003] The purpose of an embodiment of the present application is to provide a driving circuit to solve the technical problem in the prior art that a liquid crystal display screen may flash white when powered on. Another embodiment of the present application is to provide a display panel to solve the technical problem in the prior art that a liquid crystal display screen may flash white when powered on. Another embodiment of the present application is to provide a display device to solve the technical problem in the prior art that a liquid crystal display screen may flash white when powered on.

[0004] In order to solve the above technical problems, the embodiments of the present application disclose the following technical solutions:

[0005] In a first aspect, a driving circuit is provided, comprising:

[0006] a driving module configured to receive a first control signal to output a first driving signal;

[0007] a common voltage line configured to transmit a common voltage;

[0008] a first control module, the first control module having a first control end, a first output end, and a first input end, the first control end being connected to the driving module, the first input end being connected to the common voltage line, the first output end being connected to the display panel, and the first output end being configured to input a display signal into the display panel;

[0009] In response to the driving module outputting the first driving signal, the first output terminal is connected to the first input terminal, so that the potential output by the first output terminal is equal to the potential of the common voltage.

[0010] In combination with the first aspect, the device further includes a second control module, the second control module is connected between the driving module and the first control module, and the second control module is configured to receive the first driving signal to send a second control signal to the first control module;

[0011] The second control signal is configured to turn on the first control module.

[0012] In combination with the first aspect, the second control module has a second control end, a second input end, and a second output end;

[0013] The first control end is connected to the second output end, the second control end is connected to the driving module, the second input end is connected to a third control signal line, and the third control signal line is configured to transmit an AVDD voltage.

[0014] In combination with the first aspect, the first control module has multiple first control modules, and the first input terminals and the first output terminals of the multiple first control modules are cascade-connected to each other to form a cascade logic circuit, and the first control terminals of the multiple first control modules are commonly connected to the second output terminal.

[0015] In combination with the first aspect, the driving module includes a first driver, the first driver having a first driving input terminal, a second driving input terminal and a first driving output terminal, the first driving output terminal is connected to the second control module, the second driving input terminal is grounded, and the first driving input terminal is configured to receive a second driving signal to output the first driving signal.

[0016] In combination with the first aspect, the driving module also includes a second driver, the second driver having a third driving input terminal, a fourth driving input terminal and a second driving output terminal, the third driving input terminal is connected to the working voltage line, the second driving output terminal is connected to the first driving input terminal, and the fourth driving input terminal is configured to receive a third driving signal to output the second driving signal.

[0017] In combination with the first aspect, the driving module also includes a third driver, the third driver having a fifth driving input terminal, a sixth driving input terminal and a third driving output terminal, the fifth driving input terminal is connected to the working voltage line, the third driving output terminal is connected to the fourth driving input terminal, and the sixth driving input terminal is configured to receive the first control signal to output the third driving signal.

[0018] In combination with the first aspect, the first control signal includes a clock signal.

[0019] In a second aspect, a display panel is provided, which is driven by a driving circuit and includes:

[0020] substrate;

[0021] a liquid crystal layer connected to the substrate;

[0022] a signal connection terminal connected to the substrate to input a display signal into the liquid crystal layer;

[0023] In which, the driving circuit has a first output end and a first input end, the signal connection end is connected to the first output end, the first output end is connected to the common voltage line through the first input end, the common voltage line is configured to transmit a common voltage, and after the first output end is connected to the first input end, the potential output by the first output end is equal to the potential of the common voltage.

[0024] In a third aspect, a display device is provided, comprising:

[0025] The driving circuit according to any one of the first aspects; and a power integrated circuit, wherein the power integrated circuit is configured to generate a common voltage, and the common voltage is transmitted to the driving circuit through a common voltage line; or

[0026] A display panel as described in the second aspect; and a power integrated circuit, wherein the power integrated circuit is configured to generate a common voltage, the common voltage is transmitted to a driving circuit through a common voltage line, and the display panel is connected to the driving circuit to receive a display signal.

[0027] One of the above technical solutions has the following advantages or beneficial effects:

[0028] An embodiment of the present application provides a driving circuit, comprising: a driving circuit, comprising: a driving module, the driving module being configured to receive a first control signal to output a first driving signal; a common voltage line, the common voltage line being configured to transmit a common voltage; a first control module, the first control module having a first control terminal, a first output terminal, and a first input terminal, the first control terminal being connected to the driving module, the first input terminal being connected to the common voltage line, the first output terminal being connected to a display panel, and the first output terminal being configured to input a display signal into the display panel; wherein, in response to the driving module outputting the first driving signal, the first output terminal and the first input terminal are conductively connected so that the potential output by the first output terminal is equal to the potential of the common voltage. The driving circuit provided in the present application sends a first driving signal to the first control module via the driving module to connect the first output terminal of the first control module to the common voltage line, thereby reducing the voltage difference between the voltage output by the first output terminal and the common voltage, thereby improving the white flickering phenomenon of the screen of the display device and further improving the display effect of the display device.

[0029] An embodiment of the present application provides a display panel driven by a driving circuit, comprising: a substrate; a liquid crystal layer connected to the substrate; and a signal connection terminal connected to the substrate for inputting a display signal into the liquid crystal layer. The driving circuit has a first output terminal and a first input terminal, the signal connection terminal being connected to the first output terminal, the first output terminal being connected to a common voltage line via the first input terminal, the common voltage line being configured to transmit a common voltage, and when the first output terminal is connected to the first input terminal, the potential output by the first output terminal is equal to the potential of the common voltage. Driven by the driving circuit, the display panel provided by the present application can reduce the voltage difference between the voltage input to the display panel and the common voltage, thereby improving the white flickering phenomenon of the display panel and further enhancing the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0031] Figure 1 A schematic diagram of module connections of a drive circuit provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of the connection structure of the driving circuit provided in an embodiment of the present application;

[0033] Figure 3 A schematic structural diagram of a pixel electrode provided in some embodiments of the present application;

[0034] Figure 4 A schematic diagram of signal timing provided for some embodiments of the present application;

[0035] Figure 5 A schematic diagram showing the connection between the display panel and the driving circuit provided in an embodiment of the present application;

[0036] Figure 6 A schematic diagram of a display device provided in an embodiment of the present application.

[0037] The reference numerals are as follows:

[0038] 100 - substrate, 101 - signal connection end, 200 - liquid crystal layer, 300 - driving circuit, 301 - first output end, 302 - first input end, 400 - voltage signal line. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0040] In some embodiments, the relevant technical personnel of this application have noticed that in an active matrix LCD (Liquid Crystal Display), on the same horizontal scan line, the gates of all TFTs (Thin-Film Transistors) are connected together, and the applied voltages are linked. Due to the existence of parasitic capacitance Cgs between the data line and the gate line (such as Figure 3 As shown in Figure 2), the coupling effect of the parasitic capacitance Cgs causes the gate line to be coupled and raised by the data line when the LCD is powered on. When the voltage coupled to the gate line is greater than the threshold voltage Vgs of the TFT, the TFT will be turned on and the data line will leak to the pixel electrode. At this time, since the output channel is still in a floating state, that is, the voltage output by the output channel is uncertain, there is a certain voltage difference with the common voltage Vcom (as shown in Figure 2). Figure 4 Therefore, the entire screen will flash white when the LCD is powered on.

[0041] To solve the above problem, the present application proposes short-circuiting all output channels input to the LCD surface when the LCD is powered on, reducing the voltage difference between the voltage output by the output channel and the common voltage Vcom when the LCD is powered on, thereby improving the white flickering phenomenon of the startup screen, and releasing the short-circuit state until the timing controller normally sends the data signal to the driving circuit.

[0042] The specific implementation of this application is described below through examples:

[0043] like Figure 1 and Figure 2 As shown, an embodiment of the present application provides a driving circuit, comprising: a driving module, the driving module being configured to receive a first control signal to output a first driving signal; a common voltage line, the common voltage line being configured to transmit a common voltage Vcom; a first control module, the first control module having a first control terminal, a first output terminal, and a first input terminal, the first control terminal being connected to the driving module, the first input terminal being connected to the common voltage line, the first output terminal being connected to the display panel, and the first output terminal being configured to input a display signal to the display panel; wherein, in response to the driving module outputting the first driving signal, the first output terminal and the first input terminal are conductively connected, so that the potential output by the first output terminal is equal to the potential of the common voltage; wherein the first output terminal is configured to input the display signal to the display panel. Specifically, the conductive state of the first input terminal and the first output terminal of the first driving module is controlled by the first driving signal output by the driving module, so that when the LCD is powered on, the voltage output by the first output terminal and the common voltage Vcom are at the same potential, or the voltage difference between the two is reduced, so that the voltage output by the first output terminal can be unified, thereby improving the white flickering phenomenon of the LCD startup screen and enhancing the display effect of the LCD.

[0044] like Figure 1 and Figure 2 As shown, in an embodiment of the present application, a second control module is further included, the second control module is connected between the driving module and the first control module, the second control module is configured to receive the first driving signal to send a second control signal to the first control module; the second control signal is configured to turn on the first control module. Specifically, the conduction of the first control module is controlled by controlling the second control signal output by the second control module. At this time, the first input terminal and the first output terminal are turned on, and the voltage output by the first output terminal is the same as the potential of the common voltage Vcom, thereby improving the white flashing phenomenon of the LCD startup screen. When the second control module outputs other than the second control signal, the first control module is cut off, that is, the connection between the first input terminal and the first output terminal is disconnected. At this time, the first output terminal outputs a normal video signal to the LCD, thereby realizing the display of the video or image screen.

[0045] like Figure 2 As shown, in the embodiment of the present application, the second control module has a second control terminal, a second input terminal and a second output terminal; wherein the first control terminal is connected to the second output terminal, that is, Figure 2The first control module is connected to the driving module, the second input terminal is connected to the third control signal line, and the third control signal line is configured to transmit the third control signal AVDD. Specifically, the first control module includes a P-type MOS transistor Ts, the gate of which is the first control terminal, the source is the first input terminal, and the drain is the first output terminal. The third control signal AVDD generally refers to an analog power supply voltage (Analog VDD), which is used to supply the power supply voltage of the analog circuit. When the first control module is a P-type MOS transistor Ts, the third control signal AVDD is generally a high-level voltage. Therefore, when the second control module is turned on, the third control signal AVDD raises the potential at the gate of the P-type MOS transistor Ts, thereby enabling the source and drain of the P-type MOS transistor Ts to conduct, i.e., making the voltage at the drain equal to the potential of the common voltage Vcom connected to the source, thereby improving the display effect of the screen when the LCD is powered on.

[0046] In some embodiments, the first control module may also include an N-type MOS transistor. In this case, the third control signal AVDD may be a low-level voltage. Therefore, when the second control module is turned on, the third control signal AVDD lowers the potential at the gate of the N-type MOS transistor, thereby enabling the source and drain of the N-type MOS transistor to be turned on, i.e., the voltage of the drain is equal to the potential of the common voltage Vcom connected to the source, thereby improving the display effect of the picture when the LCD is powered on.

[0047] like Figure 2 As shown, in an embodiment of the present application, the first control module has multiple first input terminals and first output terminals of the multiple first control modules are cascade-connected to each other to form a cascade logic circuit, and the first control terminals of the multiple first control modules are commonly connected to the second output terminal. Specifically, the first control module includes multiple MOS tubes, the source and drain of adjacent MOS tubes are connected in sequence, and the gates of all MOS tubes are commonly connected to form a first control terminal to form a cascade logic circuit. The first output terminal still receives the second control signal output by the second control module. Under the drive of the second control signal, all MOS tubes are turned on, so that the source and drain of all MOS tubes are connected to the common voltage line. Therefore, at this time, the potential of the output voltage of the first output terminal is equal to the potential of the common voltage Vcom, or the error is less than the threshold voltage Vgs of the TFT. Therefore, the cascade logic circuit can improve the white flickering phenomenon of the LCD screen when it is powered on, and improve the display effect of the LCD. It can be understood that the first control module may include multiple N-type MOS transistors or multiple P-type MOS transistors Ts. When the first control module is a cascade of multiple P-type MOS transistors Ts, the second control signal AVDD is a high-level signal; when the first control module is a cascade of multiple N-type MOS transistors, the second control signal AVDD is a low-level signal.

[0048] like Figure 2As shown, in the embodiment of the present application, the second control module includes an N-type MOS transistor Tm, the gate of which is the first control terminal, the source of which is the first input terminal, and the drain of which is the first output terminal. When the second control module is the N-type MOS transistor Tm, the first drive signal is generally a low-level voltage. Therefore, when the drive module outputs the first drive signal, the first drive signal pulls down the potential at the gate of the N-type MOS transistor Tm, thereby enabling the source and drain of the N-type MOS transistor Tm to be conductive. That is, the third control signal AVDD in the third control signal line connected to the source can be transmitted to the first control terminal of the first control module, thereby enabling the first input terminal and the first output terminal of the first control module to be conductive, so that the voltage output by the first output terminal is equal to the potential of the common voltage Vcom, thereby improving the display effect of the screen when the LCD is powered on.

[0049] like Figure 1 and Figure 2 As shown, in an embodiment of the present application, the driver module includes a first driver F1, which has a first drive input terminal S, a second drive input terminal R, and a first drive output terminal Q3. The first drive output terminal Q3 is connected to the second control module, and the second drive input terminal R is grounded. The first drive input terminal S is configured to receive a second drive signal and output a first drive signal. Specifically, the first driver F1 determines the first drive signal output by the first drive output terminal Q3 based on the relationship between the second drive signal input by the first input terminal S and the ground signal. In an embodiment of the present application, the level of the output first drive signal can be determined by the level of the second drive signal. When the second drive signal changes from 0 to 1, the first drive input terminal S and the second drive input terminal R are grounded, and the first drive signal output by the first drive output terminal Q3 is high. At this time, the second control module, i.e., the N-type MOS transistor, is turned on under the drive of the first drive signal, and further causes the third control signal AVDD to turn on the first input terminal and the first output terminal of the first control module, so that the voltage output by the first output terminal is equal to the potential of the common voltage Vcom, thereby improving the display effect of the screen when the LCD is powered on. When the second drive signal changes from 1 to 0, the first drive input terminal S and the second drive input terminal R are grounded, and the first drive signal output by the first drive output terminal Q3 is at a low level. At this time, the second control module is cut off, and the first control module is also cut off. That is, the first input terminal and the first output terminal of the first control module are not connected. At this time, the first output terminal can output a normal video signal to the LCD, thereby realizing the display of video or image screen.

[0050] In some embodiments, the first driver F1 includes an RS flip-flop. The RS flip-flop is a basic digital circuit component. The RS flip-flop can be used to store a bit of data (such as 0 or 1). By setting or resetting the input signal, the corresponding state (such as 0 or 1) can be maintained at the output of the flip-flop; alternatively, the RS flip-flop can memorize the previous state and maintain the current output state when there is no input. Therefore, the above function can be used to design an RS flip-flop to control the level of the output signal at the output end according to the signal relationship between the two input ends. Generally speaking, the high level is 1 and the low level is 0. The characteristic equation of the RS flip-flop is: Q n+1 =R'Q n +SQ' n , where R' represents the reset signal, S represents the set signal, and Q n+1 is the output state of the flip-flop, Q n It is the current state of the trigger. The initial state of the trigger is 0.

[0051] It should be noted that in addition to the functions described above, the RS flip-flop also has several other main functions, such as timing control, data synchronization, and logical operations. Because the RS flip-flop has two control inputs, these inputs can be used to control the operating state of the flip-flop. By changing the combination of the two input signals, various timing control functions, such as state transfer, clock synchronization, and data latching, can be achieved. The RS flip-flop can also be used to synchronize input data and the trigger clock signal to ensure that the input signal is stable and correctly transmitted to the output at a specific clock edge. This synchronization capability is crucial for data stability and accuracy in timing circuits. The RS flip-flop can also be used in combinational logic circuits. By connecting the input signal and the output signal through logic gates, different logical functions, such as AND gates, OR gates, and NOT gates, can be achieved. Therefore, in some embodiments, the functions of the RS flip-flop described above can be used to control the level of the signal at the output based on the relationship between the second drive signal and the ground signal.

[0052] like Figure 1 and Figure 2As shown, in an embodiment of the present application, the driving module also includes a second driver F2, the second driver F2 having a third driving input terminal T2, a fourth driving input terminal CLK2 and a second driving output terminal Q2, the third driving input terminal T2 being connected to the working voltage line, the second driving output terminal Q2 being connected to the first driving input terminal S, and the fourth driving input terminal CLK2 being configured to receive a third driving signal to output a second driving signal. Specifically, the second driver F2 determines the second driving signal outputted from the second driving output terminal Q2 by the relationship between the third driving signal inputted by the fourth driving input terminal CLK2 and the working voltage VDD inputted by the third driving input terminal T2. In an embodiment of the present application, the level of the outputted second driving signal can be determined by the level of the third driving signal. When the fourth driving input terminal CLK2 receives the third driving signal and changes from 0 to 1, the third driving input terminal T2 and the fourth driving input terminal CLK2 are connected to the working voltage VDD, and the outputted second driving signal is a high level. When the fourth driving input terminal CLK2 receives the third driving signal and changes from 1 to 0, the third driving input terminal T2 and the fourth driving input terminal CLK2 are connected to the working voltage VDD, the second driver F2 is latched and maintains the original state, and the output maintains the original high level.

[0053] like Figure 1 and Figure 2As shown, in an embodiment of the present application, the driving module includes a third driver F3, which has a fifth driving input terminal T1, a sixth driving input terminal CLK1, and a third driving output terminal Q1. The fifth driving input terminal T1 is connected to the working voltage line, the third driving output terminal Q1 is connected to the fourth driving input terminal CLK2, and the sixth driving input terminal CLK1 is configured to receive a first control signal to output a third driving signal. Specifically, the third driver F3 determines the third driving signal outputted by the third driving output terminal Q1 based on the relationship between the first driving signal inputted by the sixth driving input terminal CLK1 and the working voltage VDD inputted by the fifth driving input terminal T1. In an embodiment of the present application, the level of the outputted third driving signal can be determined by the level change of the first control signal. When the first control signal changes from 0 to 1, the fifth driving input terminal T1 and the sixth driving input terminal CLK1 are connected to the working voltage VDD, and the outputted third driving signal is at a high level. At this point, the second control module is turned off, and similarly, the first control module is also turned off. That is, the first input terminal and the first output terminal of the first control module are disconnected. At this point, the first output terminal can output a normal video signal to the LCD, thereby displaying a video or image. When the first control signal changes from 0 to 1 again, the fifth drive input terminal T1 and the sixth drive input terminal CLK1 are connected to the operating voltage VDD, and the output third drive signal is low. At this point, the second control module, namely the N-type MOS transistor, is turned on by the first drive signal, and further causes the third control signal AVDD to connect the first input terminal and the first output terminal of the first control module, so that the voltage output by the first output terminal is equal to the potential of the common voltage Vcom, thereby improving the display quality of the image when the LCD is powered on.

[0054] In some embodiments, the second driver F2 and the third driver F3 comprise a T flip-flop, a commonly used type of flip-flop consisting of two cross-coupled latches. A T flip-flop is used in sequential control circuits, controlling the state of an output signal via a continuous pulse signal at its input. When the pulse signal at the input is high, the output is inverted on each rising edge of the clock pulse, implementing sequential logic control.

[0055] In the embodiment of the present application, when the first driver F1 is an RS trigger, the second driver F2 and the third driver F3 are both T triggers (the third driver F3 is a T1 trigger, and the second driver F2 is a T2 trigger). The characteristic equation of the T trigger is: Q n+1 =T⊕Q n , where Q n+1 is the output state of the T flip-flop, Q nis the current state of the trigger, and T is the input signal. When the input signal T=0, the trigger maintains the current state; when the input signal T=1, the trigger state flips. When the sixth drive input terminal CLK1 of the third driver F3 inputs the first TP signal, the T1 trigger flips, and the third drive signal output by the third drive output terminal Q1 is 1, that is, the signal received by the fourth drive input terminal CLK2 is 1, then the T2 trigger flips, and the second drive signal output by the second drive output terminal Q2 is 1, that is, the signal received by the first drive input terminal S is 1. At this time, the characteristic equation of the RS trigger is: Q n+1 =R'Q n +SQ' n =Q' n , the first driving signal output by the first driving output terminal Q3 is 1, the N-type MOS transistor Tm is turned on at a high level, and the potential at point p is high. At this time, the source and drain of the P-type MOS transistor Ts can be turned on, that is, the voltage of the drain is equal to the potential of the common voltage Vcom connected to the source.

[0056] When the sixth driving input terminal CLK1 of the third driver F3 inputs the second TP signal, the T1 trigger flips over, and the third driving signal output by the third driving output terminal Q1 is 0, that is, the signal received by the fourth driving input terminal CLK2 is 0. The T2 trigger remains, and the second driving signal output by the second driving output terminal Q2 is 1, that is, the signal received by the first driving input terminal S is 1. At this time, the characteristic equation of the RS trigger is: Q n+1 =Q' n When the first drive signal outputted by the first drive output terminal Q3 is 0, the N-type MOS transistor Tm is turned off at a low level, and the potential at point p is low. At this point, the source and drain of the P-type MOS transistor Ts are disconnected, meaning that the voltage at the drain is not equal to the common voltage Vcom connected to the source. Simultaneously, the output channel outputs a given display voltage signal.

[0057] It should be noted that in addition to the functions mentioned above, the T flip-flop also has the following main functions: frequency division, data storage, and timing transmission. Specifically, the T flip-flop can be used as a frequency divider or divider, reducing the frequency of the clock signal to the desired frequency. By providing an appropriate clock signal to the input of the T flip-flop and setting appropriate logic conditions, the flip-flop output can generate the corresponding divided frequency signal. The T flip-flop can also be used in data storage applications to temporarily store input data and keep it unchanged until the next clock pulse arrives. When the clock signal edge changes (such as the rising or falling edge), the T flip-flop latches the input data and outputs the latched data at the clock edge. Accordingly, the T flip-flop can be used in timing transmission circuits to transfer data to the next stage according to the clock signal edge. When the clock signal arrives, the input data is transferred according to the state of the T flip-flop and output to the next stage at the clock edge, achieving timing data transmission.

[0058] Therefore, the on and off states of the second and third control modules can be controlled based on the level of the first control signal. When the first control signal is high, the second control module is turned on by the first drive signal, and further causes the third control signal AVDD to connect the first input terminal and the first output terminal of the first control module, making the voltage output by the first output terminal equal to the potential of the common voltage Vcom, thereby improving the display quality when the LCD is powered on. When the first drive signal is low, both the second and first control modules are turned off. At this time, the first output terminal can output a normal video signal to the LCD, thereby displaying a video or image.

[0059] like Figure 2 As shown, in the embodiment of the present application, the first control signal includes a clock signal TP. Specifically, the clock signal TP is typically generated by a clock generator provided in the circuit. The clock generator is typically composed of a crystal oscillator or an oscillation circuit, which can generate a square wave signal with a fixed frequency. Using the clock signal TP as the first control signal can reduce the introduction of signals.

[0060] In some embodiments, clock signal TP plays a key role in liquid crystal display circuits, including synchronizing refresh, controlling scanning and driving, controlling cadence, and reducing power consumption. Liquid crystal displays typically consist of many pixels, each of which requires periodic refreshing to maintain the stability of the displayed image. Clock signal TP is used to synchronize the scanning and refreshing operations within the liquid crystal display circuit, ensuring that the pixel states are updated in the correct time sequence, thereby generating a stable image. Furthermore, the pixels of an liquid crystal display are typically arranged in a matrix structure of rows and columns. Clock signal TP controls the scanning and driving circuits, selecting and activating each row of pixels in a predetermined sequence and applying the correct voltages and signals to each pixel to achieve image display. Accordingly, clock signal TP also provides a unified clock rhythm across various components of the display system. Different signals and operations must be processed and executed within the correct time intervals to ensure accurate display results. Clock signal TP serves as a time reference to coordinate the operations of various components, ensuring the normal operation of the entire display system. Clock signal TP can also be used to control the activation time and duration of pixels, as well as the operating time of the driving circuits, to minimize power consumption.

[0061] like Figure 5 As shown, an embodiment of the present application also provides a display panel, which is driven based on a driving circuit 300 and includes: a substrate 100; a liquid crystal layer 200, which is connected to the substrate 100; a signal connection terminal 101, which is connected to the substrate 100 to input a display signal into the liquid crystal layer 200; wherein the driving circuit has a first output terminal and a first input terminal, the signal connection terminal 101 is connected to the first output terminal 301 in the driving circuit 300, and the first output terminal 301 is connected to the common voltage line 400 through the first input terminal 302, and the common voltage line 400 is configured to transmit a common voltage. After the first output terminal 301 is connected to the first input terminal 302, the potential output by the first output terminal 301 is equal to the potential of the common voltage. Specifically, the driving circuit sends a first driving signal to the first control module through the driving module to connect the first output end of the first control module to the common voltage line, thereby reducing the voltage difference between the voltage output by the first output end (that is, the voltage input into the display panel) and the common voltage, thereby improving the white flickering phenomenon of the display panel and further improving the display effect of the display panel.

[0062] like Figure 6As shown, an embodiment of the present application further provides a display device, comprising: a driving circuit and a power integrated circuit as provided in any of the above embodiments, the power integrated circuit being configured to generate a common voltage, which is transmitted to the driving circuit via a common voltage line; or a display panel and a power integrated circuit as provided in the above embodiments, the power integrated circuit being configured to generate a common voltage, which is transmitted to the driving circuit via a common voltage line, and the display panel being connected to the driving circuit to receive a display signal. Specifically, the driving circuit sends a first driving signal to the first control module through the driving module to connect the first output terminal of the first control module to the common voltage line, thereby reducing the voltage difference between the voltage output by the first output terminal (i.e., the voltage input to the display panel) and the common voltage, thereby improving the white flickering phenomenon of the display device and further improving the display effect of the display device.

[0063] The above is a detailed introduction to a driving circuit, a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving circuit, characterized in that: include: a driving module configured to receive a first control signal to output a first driving signal; a common voltage line configured to transmit a common voltage; a first control module, the first control module having a first control end, a first output end, and a first input end, the first control end being connected to the driving module, the first input end being connected to the common voltage line, the first output end being connected to the display panel, and the first output end being configured to input a display signal into the display panel; a second control module, the second control module being connected between the driving module and the first control module, the second control module being configured to receive the first driving signal and send a second control signal to the first control module; the second control signal being configured to turn on the first control module; The second control module has a second control end, a second input end and a second output end; Wherein, the first control end is connected to the second output end, the second control end is connected to the driving module, the second input end is connected to a third control signal line, and the third control signal line is configured to transmit an AVDD voltage; In response to the driving module outputting the first driving signal, the first output terminal is connected to the first input terminal, so that the potential output by the first output terminal is equal to the potential of the common voltage.

2. The driving circuit according to claim 1, wherein: There are multiple first control modules, and the first input terminals and the first output terminals of the multiple first control modules are cascade-connected to each other to form a cascade logic circuit. The first control terminals of the multiple first control modules are commonly connected to the second output terminal.

3. The driving circuit according to claim 1, wherein: The driving module includes a first driver, the first driver having a first driving input terminal, a second driving input terminal and a first driving output terminal, the first driving output terminal is connected to the second control module, the second driving input terminal is grounded, and the first driving input terminal is configured to receive a second driving signal to output the first driving signal.

4. The driving circuit according to claim 3, wherein: The driving module also includes a second driver, which has a third driving input terminal, a fourth driving input terminal and a second driving output terminal. The third driving input terminal is connected to the working voltage line, the second driving output terminal is connected to the first driving input terminal, and the fourth driving input terminal is configured to receive a third driving signal to output the second driving signal.

5. The driving circuit according to claim 4, wherein: The driving module also includes a third driver, which has a fifth driving input terminal, a sixth driving input terminal and a third driving output terminal. The fifth driving input terminal is connected to the working voltage line, the third driving output terminal is connected to the fourth driving input terminal, and the sixth driving input terminal is configured to receive the first control signal to output the third driving signal.

6. The driving circuit according to claim 1, wherein: The first control signal includes a clock signal.

7. A display panel driven by a driving circuit, characterized in that: include: substrate; a liquid crystal layer connected to the substrate; a signal connection terminal connected to the substrate to input a display signal into the liquid crystal layer; Wherein, the driving circuit includes: a first control module, the first control module having a first control end, a first output end, and a first input end, the first control end being connected to the driving module, the first input end being connected to the common voltage line, the first output end being connected to the display panel, and the first output end being configured to input a display signal into the display panel; a second control module, the second control module being connected between the driving module and the first control module, the second control module being configured to receive the first driving signal and send a second control signal to the first control module; the second control signal being configured to turn on the first control module; The second control module has a second control end, a second input end and a second output end; Wherein, the first control end is connected to the second output end, the second control end is connected to the driving module, the second input end is connected to a third control signal line, and the third control signal line is configured to transmit an AVDD voltage; The signal connection end is connected to the first output end, the first output end is connected to the common voltage line through the first input end, the common voltage line is configured to transmit a common voltage, and after the first output end is connected to the first input end, the potential output by the first output end is equal to the potential of the common voltage.

8. A display device, characterized in that: include: The driving circuit according to any one of claims 1 to 6; and a power integrated circuit, wherein the power integrated circuit is configured to generate a common voltage, and the common voltage is transmitted to the driving circuit via a common voltage line; or A display panel as claimed in claim 7; and a power integrated circuit, wherein the power integrated circuit is configured to generate a common voltage, the common voltage is transmitted to a driving circuit through a common voltage line, and the display panel is connected to the driving circuit to receive a display signal.

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