Asymmetric pass voltage scheme for non-volatile memory device size reduction

Abstract

The invention provides a memory device and an operating method. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in a memory hole, and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The control device is coupled to the plurality of word lines and the memory holes. The control device is configured to, during a plurality of program cycles of a program operation, apply a plurality of pulses of a program voltage, the magnitude of which increases by a program step amount, to a selected word line of the plurality of word lines while applying at least one pass voltage to an unselected word line of the plurality of word lines. The control device is further configured to adjust the at least one pass voltage based on the programming voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 523,810, filed on June 28, 2023. The entire disclosure of the above application is incorporated herein by reference. Technical Field

[0003] The present application relates to nonvolatile memory devices and the operation of nonvolatile memory devices. Background Art

[0004] This section provides background information related to technology related to the present disclosure and thus is not necessarily prior art.

[0005] Semiconductor memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0006] It is desirable to reduce the size of such memory devices, however, there are various limitations in reducing the size of certain components of the memory devices. Therefore, there is a need for an improved memory device and operating method that provides a reduction in size while maintaining suitable operation and speed. Summary of the invention

[0007] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features and advantages.

[0008] An object of the present disclosure is to provide a memory device and a method of operating the memory device that solves and overcomes the above-mentioned disadvantages.

[0009] Therefore, one aspect of the present disclosure is to provide a memory device including memory cells, each of which is connected to one of a plurality of word lines. A control device is coupled to the plurality of word lines and is configured to apply a plurality of pulses of a program voltage whose magnitude increases by a program step amount to a selected word line among the plurality of word lines during a plurality of programming loops of a programming operation, while applying at least one pass voltage to unselected word lines among the plurality of word lines. The control device is also configured to adjust the at least one pass voltage based on the program voltage.

[0010] According to another aspect of the present disclosure, there is also provided a controller in communication with a memory device including memory cells, each of which is connected to one of a plurality of word lines. The controller is configured to instruct the memory device to apply a plurality of pulses of a programming voltage whose magnitude increases by a programming step amount to a selected word line of the plurality of word lines during a plurality of programming cycles of a programming operation, while applying at least one pass voltage to an unselected word line of the plurality of word lines. The controller is further configured to adjust the at least one pass voltage based on the programming voltage.

[0011] According to an additional aspect of the present disclosure, a method of operating a memory device is provided. The memory device includes memory cells each connected to one of a plurality of word lines. The method includes the steps of applying a plurality of pulses of a programming voltage whose magnitude increases by a programming step amount to a selected word line of the plurality of word lines during a plurality of programming cycles of a programming operation, while applying at least one pass voltage to an unselected word line of the plurality of word lines. The method also includes the step of adjusting the at least one pass voltage based on the programming voltage.

[0012] Further areas of applicability will become apparent from the description provided herein.The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0014] Figure 1 is a schematic block diagram illustrating a system according to aspects of the present disclosure;

[0015] Figure 2 is a schematic block diagram illustrating another system according to aspects of the present disclosure;

[0016] Figure 3 is a schematic block diagram illustrating a NAND string according to aspects of the present disclosure;

[0017] Figure 4 is a schematic block diagram illustrating a memory array according to aspects of the present disclosure;

[0018] Figure 5 illustrates one embodiment of a top view of a portion of a memory array according to aspects of the present disclosure;

[0019] Figure 6 illustrates one embodiment of a cross-sectional view of a portion of a memory array according to aspects of the present disclosure;

[0020] Figure 7shows a cross-sectional view of a memory array according to aspects of the present disclosure;

[0021] Figure 8 shows a word line driven from one side according to aspects of the present disclosure;

[0022] Fig. 9 Memory arrays according to aspects of the present disclosure are shown;

[0023] Fig.10 shows a side cross-sectional view of an exemplary memory die according to aspects of the present disclosure and showing a portion of the die where a word line switch resides;

[0024] Fig.11 illustrates a top cross-sectional view of a portion of an exemplary memory die showing dimensions of word line switches including shallow trench isolation (STI) spacing between word line switches according to aspects of the present disclosure;

[0025] Fig.12 is a table showing possible shallow trench isolation width reductions for different minimum pass voltages according to aspects of the present disclosure;

[0026] Fig.13 shows a cross-sectional view of a portion of a memory hole with exemplary pass voltages applied during a programming operation and illustrating adjacent word line interference in accordance with aspects of the present disclosure;

[0027] Fig.14A and Fig. 14B Graphs showing a program voltage applied to a selected word line of a plurality of word lines, a first pass voltage applied to a first adjacent word line, a second pass voltage applied to a second adjacent word line, a pass voltage applied to a word line of a plurality of word lines that is vertically above the first adjacent word line, and a pass voltage applied to a word line of a plurality of word lines that is vertically below the second adjacent word line for current asymmetric pass voltage schemes and one proposed asymmetric pass voltage scheme described herein in accordance with aspects of the present disclosure;

[0028] Fig.15 is a graph of programming voltage minus pass voltage versus programming voltage for current asymmetric pass voltage schemes and the proposed asymmetric pass voltage scheme described herein in accordance with aspects of the present disclosure; and

[0029] Fig.16 Steps of a method of operating a memory device according to aspects of the present disclosure are shown.

[0030] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0031] In the following description, details are set forth to provide an understanding of the present disclosure. In some cases, certain circuits, structures, and techniques have not been described or shown in detail to avoid obscuring the present disclosure.

[0032] Generally speaking, the present disclosure relates to non-volatile memory devices of a type that is very suitable for many applications. The non-volatile memory devices and associated operating methods of the present disclosure will be described in conjunction with one or more example embodiments. However, the specific example embodiments disclosed are only for the purpose of clearly describing the concepts, features, advantages and purposes of the present invention to allow those skilled in the art to understand and practice the present disclosure. Specifically, example embodiments are provided so that the present disclosure will be comprehensive and the scope will be fully conveyed to those skilled in the art. Many specific details, such as examples of specific components, devices and methods, are set forth to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details do not need to be adopted, and the example embodiments can be embodied in a variety of different forms, and none of them should be construed as limiting the scope of the present disclosure. In some example embodiments, well-known processes, well-known device structures and well-known technologies are not described in detail.

[0033] In some memory devices or apparatuses, memory cells are joined to each other, such as in NAND strings in blocks or sub-blocks. Each NAND string includes a plurality of memory cells connected in series between one or more drain-side select gate SG transistors (SGD transistors) located on the drain side of the NAND string connected to the bit line and one or more source-side select gate SG transistors (SGS transistors) located on the source side of the NAND string connected to the source line. In addition, the memory cells may be arranged with a common control gate line (e.g., word line) used as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. The memory cells may be connected in other types of strings and may also be connected in other ways.

[0034] In a 3D memory structure, memory cells may be arranged in stacked vertical strings, wherein the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connected to the memory cells. The memory cells may include data memory cells that are eligible to store user data, and dummy memory cells or non-data memory cells that are not eligible to store user data.

[0035] Before programming certain non-volatile memory devices, memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gate of the erased memory cell. Alternatively, the erase operation removes electrons from the charge trapping layer.

[0036] Each memory cell can be associated with a data state according to the write data in the program command. Based on the data state of the memory cell, the memory cell will remain in the erased state or be programmed to the programmed data state. For example, in a three-bit per cell memory device, there are eight data states, including the erased state and the programmed state.

[0037] During a programming operation, memory cells are programmed according to a word line programming order. For example, programming may start with a word line on the source side of a block and proceed to a word line on the drain side of the block. In one approach, programming of each word line is completed before programming the next word line. For example, a first word line WL0 is programmed using one or more programming pulses until programming is complete. Next, a second word line WL1 is programmed using one or more programming pulses until programming is complete, and so on. The programming pulses may include a set of increasing programming voltages that are applied to the word lines in a corresponding programming loop or program-verify iteration. A verification operation or stage may be performed after each programming voltage to determine whether the memory cell has completed programming. When programming of a memory cell is completed, the memory cell may be inhibited from further programming while continuing to program other memory cells in subsequent programming loops.

[0038] A memory device may have a word line switch (WLSW) coupled to one or more word lines (WL) from a block of memory cells. As the number of word lines increases, the number of word line switches per block also increases. As a result, the width of the switch increases, and thus the area of ​​the memory die required for the word line switches also increases.

[0039] Figure 1is a block diagram of one embodiment of a system 100 including a non-volatile memory device 118 configured according to an embodiment of the claimed solution. The computing device 104 may include a non-volatile memory system 102, a processor 106, a volatile memory 108, and a communication interface 110. The processor 106 may include one or more central processing units, one or more general purpose processors, one or more special purpose processors, one or more virtual processors (e.g., the computing device 104 may be a virtual machine operating within a host computer), one or more processor cores, etc. The communication interface 110 may include one or more network interfaces configured to communicatively couple the computing device 104 and / or the non-volatile memory controller 126 to a communication network 114, such as an Internet Protocol (IP) network, a storage area network (SAN), a wireless network, a wired network, etc.

[0040] In various embodiments, the non-volatile memory device 118 may be disposed at one or more different locations relative to the computing device 104. In one embodiment, the non-volatile memory device 118 includes one or more non-volatile memory elements 122, such as semiconductor chips, memory dies, or packages or other integrated circuit devices disposed on one or more printed circuit boards, storage enclosures, and / or other mechanical support structures and / or electrical support structures. For example, the non-volatile memory device 118 may include one or more direct-insertion memory modules (DIMM) cards, one or more expansion cards and / or daughter cards, solid-state drives (SSDs) or other hard drive devices, and / or may have another memory and / or storage form factor known to those skilled in the art. The non-volatile memory device 118 may be integrated with and / or mounted on a motherboard of the computing device 104, mounted in a port and / or slot of the computing device 104, mounted on a different computing device 104 and / or mounted on a dedicated storage device on the network 114, communicate with the computing device 104 via an external bus (e.g., an external hard drive), etc.

[0041] In one embodiment, the non-volatile memory device 118 may be disposed on a memory bus of the processor 106 (e.g., on the same memory bus as the volatile memory 108, on a different memory bus than the volatile memory 108, in place of the volatile memory 108, etc.). In another embodiment, the non-volatile memory device 118 may be disposed on a peripheral bus of the computing device 104, such as a Peripheral Component Interconnect Express (PCI Express or PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switch (PCIe-AS) bus, etc. In another embodiment, the non-volatile memory device 118 may be disposed on a data network 114, such as an Ethernet network, an Infiniband network, SCSI RDMA over the network 114, a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and / or wireless network 114, etc.

[0042] The computing device 104 may also include a non-transitory computer-readable storage medium 112. The computer-readable storage medium 112 may include executable instructions configured to cause the computing device 104 (eg, the processor 111) to perform steps of one or more methods disclosed herein.

[0043] According to various embodiments, the non-volatile memory controller 126 may manage one or more non-volatile memory devices 118 and / or non-volatile memory elements 122. The non-volatile memory device 118 may include a record, memory, and / or storage device, such as a solid-state storage device and / or a semiconductor storage device that is arranged and / or divided into a plurality of addressable storage locations. As used herein, a storage location refers to any physical unit of memory (e.g., any number of physical storage media on the non-volatile memory device 118). Memory units may include, but are not limited to, pages, memory partitions, blocks, data blocks, erase blocks, sectors, collections or sets of physical storage locations (e.g., logical pages, logical blocks, logical erase blocks), etc.

[0044] In certain embodiments, the device driver and / or non-volatile memory controller 126 may present a logical address space 136 to the storage client 116. As used herein, a logical address space 136 refers to a logical representation of a memory resource. The logical address space 136 may include multiple (e.g., a series of) logical addresses. As used herein, a logical address refers to any identifier used to reference a memory resource (e.g., data), including but not limited to: a logical block address (LBA), a cylinder / head / sector (CHS) address, a file name, an object identifier, an index node, a universally unique identifier (UUID), a globally unique identifier (GUID), a hash code, a signature, an index entry, a range, an extent, etc.

[0045] The device driver for the non-volatile memory device 118 may maintain metadata 138, such as a logical to physical address mapping structure, to map logical addresses of the logical address space 136 to storage locations on the non-volatile memory device 118. The device driver may be configured to provide storage services to one or more storage clients 116. The storage clients 116 may include local storage clients 116 operating on the computing device 104 and / or remote storage clients 116 accessible via the network 114 and / or the communication interface 110. The storage clients 116 may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

[0046] The device driver may be communicatively coupled to one or more non-volatile memory devices 118. The one or more non-volatile memory devices 118 may include different types of non-volatile memory devices, including but not limited to: solid-state storage devices, semiconductor storage devices, SAN storage resources, etc. The one or more non-volatile memory devices 118 may include one or more of a corresponding non-volatile memory controller 126 and / or a non-volatile memory medium 120. The device driver may provide access to the one or more non-volatile memory devices 118 via a traditional block I / O interface 132. In addition, the device driver may provide access to other functions through a storage class memory interface (SCM interface 134). Metadata 138 may be used to manage and / or track data operations performed through any of the block I / O interface 132, the SCM interface 134, or other related interfaces.

[0047] In one embodiment, user applications such as software applications operating on or in conjunction with storage clients 116 use the non-volatile memory system 102. The storage clients 116 manage files and data and utilize the functions and features of the non-volatile memory controller 126 and associated non-volatile memory media 120. Representative examples of storage clients include, but are not limited to, servers, file systems, operating systems, database management systems ("DBMS"), volume managers, etc. In one embodiment, the storage clients 116 access one or more non-volatile memory devices 118 via a traditional block I / O interface 132.

[0048] Some conventional block storage devices divide the storage medium into volumes or partitions. Each volume or partition may include multiple sectors. One or more sectors are organized into blocks (also called data blocks). In some storage systems (such as In a storage system that interfaces with a nonvolatile memory controller 126, a block of data is referred to as a cluster. In other storage systems, such as storage systems that interface with UNIX, Linux, or similar operating systems, a block of data is referred to simply as a block. A block or cluster represents the smallest physical amount of storage space on a storage medium managed by the nonvolatile memory controller 126. A block storage device may associate n blocks of user data that may be used for storage across the nonvolatile memory medium 120 with logical block addresses numbered from 0 to n. In some block storage devices, the logical block address range for each volume or partition may be from 0 to n. In conventional block storage devices, a logical block address is directly mapped to a specific logical block.

[0049] The device driver may present the logical address space 136 to the storage client 116 through one or more interfaces. As described above, the logical address space 136 may include a plurality of logical addresses, each corresponding to a respective storage location within the one or more non-volatile memory devices 118. The device driver may maintain metadata 138 including, among other things, any-to-any mappings between logical addresses and storage locations.

[0050] The device driver may also include and / or communicate with a non-volatile memory device interface 140 configured to transmit data, commands, and / or queries to one or more non-volatile memory devices 118 via a bus 124, which may include, but is not limited to, a memory bus of the processor 106, a peripheral component interconnect express (PCI Express or PCIe) bus, a serial advanced technology attachment (ATA) bus, a parallel ATA bus, a small computer system interface (SCSI), FireWire, Fibre Channel, a universal serial bus (USB), a PCIe advanced switch (PCIe-AS) bus, a network 114, Infiniband, SCSI RDMA, non-volatile memory express (NVMe), etc. The non-volatile memory device interface 140 may communicate with the one or more non-volatile memory devices 118 using input-output control (IO-CTL) commands, IO-CTL command extensions, remote direct memory access, etc.

[0051] The communication interface 110 may include one or more network interfaces configured to communicatively couple the computing device 104 and / or the non-volatile memory controller 126 to the network 114 and / or to one or more remote storage clients 116 accessible to the network. The storage clients 116 may include local storage clients 116 operating on the computing device 104 and / or remote storage clients 116 accessible via the network 114 and / or the communication interface 110. The non-volatile memory controller 126 is part of and / or in communication with one or more non-volatile memory devices 118. Although Figure 1 A single non-volatile memory device 118 is depicted, but the present disclosure is not limited in this regard and may be adapted to include any number of non-volatile memory devices 118 .

[0052] The non-volatile memory device 118 may include one or more non-volatile memory elements 122 of a non-volatile memory medium 120, which may include, but are not limited to: ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, bidirectional unified memory, chalcogenide RAM or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon oxide-based sub-10 nm process memory, graphene memory, silicon oxide nitride oxide (SONOS), programmable metallization cell (PMC), conductive bridge RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, tape), optical storage media, etc. In some embodiments, the one or more non-volatile memory elements 122 of the non-volatile memory medium 120 include storage class memory (SCM).

[0053] While conventional technologies such as NAND flash memory may be block and / or page addressable, in one embodiment, storage class memory is byte addressable. In other embodiments, storage class memory may be faster and / or have a longer life (e.g., durability) than NAND flash memory; may have a lower cost, use less power, and / or have a higher storage density than DRAM; or provide one or more other benefits or improvements over other technologies. For example, storage class memory may include one or more non-volatile memory elements 122 of ReRAM, memristor memory, programmable metallization cell memory, phase change memory, nano RAM, nanocrystal wire-based memory, silicon oxide-based sub-10 nm process memory, graphene memory, SONOS memory, PMC memory, CBRAM, MRAM, and / or variants thereof.

[0054] Although the nonvolatile memory medium 120 is referred to herein as a "memory medium," in various embodiments, the nonvolatile memory medium 120 may more generally include one or more nonvolatile recording media capable of recording data, which may be referred to as nonvolatile memory media, nonvolatile storage media, etc. In addition, in various embodiments, the nonvolatile memory device 118 may include a nonvolatile recording device, a nonvolatile memory device, a nonvolatile storage device, etc.

[0055] The non-volatile memory medium 120 may include one or more non-volatile memory elements 122, which may include, but are not limited to, chips, packages, planes, dies, etc. The non-volatile memory controller 126 may be configured to manage data operations on the non-volatile memory medium 120, and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, the non-volatile memory controller 126 is configured to store data on the non-volatile memory medium 120 and / or read data from the non-volatile memory medium, to transfer data to / from the non-volatile memory device 118, etc.

[0056] The non-volatile memory controller 126 may be communicatively coupled to the non-volatile memory medium 120 via a bus 128. The bus 128 may include a bus for transferring data to / from the non-volatile memory elements 122. In one embodiment, the bus 128 may also include a control bus for transferring addressing and other command and control information to the non-volatile memory elements 122. In some embodiments, the bus 128 may communicatively couple the non-volatile memory elements 122 to the non-volatile memory controller 126 in parallel. This parallel access may allow the non-volatile memory elements 122 to be managed as a group, thereby forming a logical memory element 130. The logical memory element 130 may be divided into corresponding logical memory units (e.g., logical pages) and / or logical memory partitions (e.g., logical data blocks, logical blocks, logical erase blocks). The logical memory units may be formed by logically combining the physical memory units of each of the non-volatile memory elements 122.

[0057] In some embodiments, the non-volatile memory controller 126 can be configured to store data on one or more asymmetric write-once media such as the non-volatile memory medium 120. As used herein, a "write-once" storage medium refers to a storage medium that is reinitialized (e.g., erased) each time new data is written or programmed thereon. As used herein, an "asymmetric" storage medium refers to a storage medium that has different latencies for different storage operations. Many types of non-volatile memory media 120 are asymmetric; for example, read operations can be much faster than write / program operations, and write / program operations can be much faster than erase operations (e.g., reading the medium can be hundreds of times faster than erasing, and tens of times faster than programming the medium).

[0058] The non-volatile memory medium 120 may be divided into memory partitions that may be erased as groups (e.g., erase blocks) to specifically account for media asymmetric properties. Thus, modifying a single data sector or block in-place may require erasing the entire erase block containing the data, and rewriting the modified data to the erase block along with the original unchanged data. This may result in inefficient "write amplification" that may excessively wear out the non-volatile memory medium 120.

[0059] Therefore, in some embodiments, the non-volatile memory controller 126 can be configured to write data off-site. As used herein, writing data "off-site" refers to writing data to one or more different physical storage locations, rather than overwriting the data "in place" (e.g., overwriting the data in the original physical location). Modifying data off-site can avoid write amplification because existing valid data on the erase block with the data to be modified does not need to be erased and rewritten. In addition, writing data off-site can remove the delay effect of erasure from certain storage operations.

[0060] In certain embodiments, the nonvolatile memory controller 126 can be organized according to multiple erase blocks of word lines within the nonvolatile memory elements 122 using the addresses of the word lines so that the word lines are logically organized into a monotonically increasing sequence (e.g., the addresses of the word lines are decoded and / or converted into a monotonically increasing sequence, etc.). In another embodiment, the word lines of the erase blocks within the nonvolatile memory elements 122 can be physically arranged in a monotonically increasing sequence of word line addresses, where consecutively addressed word lines are also physically adjacent (e.g., WL0, WL1, WL2, . . . , WLN).

[0061] The non-volatile memory controller 126 may include a device driver executing on the computing device 104 and / or communicating with it. The device driver may provide storage services to the storage client 116 via one or more interfaces (block I / O interface 132, SCM interface 134, and / or other interfaces). In some embodiments, the device driver provides a block I / O interface 132 to the computing device 104, and the storage client 116 performs block-level I / O operations through the block I / O interface. Alternatively or in addition, the device driver may provide an SCM interface 134, which may provide other storage services to the storage client 116. In some embodiments, the SCM interface 134 may include an extension to the block I / O interface 132 (e.g., the storage client 116 may access the SCM interface 134 through an extension or addition to the block I / O interface 132). Alternatively or in addition, the SCM interface 134 may be provided as a separate API, service, and / or library.

[0062] The device driver may also include a non-volatile memory device interface 140 configured to transmit data, commands, and / or queries to the non-volatile memory controller 126 via the bus 124, as described above.

[0063] Figure 2 An embodiment of a non-volatile storage system 200 that may include one or more memory dies 202 or chips is shown. In some embodiments, the memory die 202 includes a memory array 204 (two-dimensional or three-dimensional) of memory cells, a die controller 206, a read / write circuit A 222, and a read / write circuit B 224. In one embodiment, access to the memory array 204 by various peripheral circuits is implemented in a symmetrical manner on opposite sides of the array, so that the density of access lines and circuits on each side is reduced by half. In another embodiment, the read / write circuit A 222 and the read / write circuit B 224 include multiple sense amplifiers 230 that allow pages of memory cells to be read or programmed in parallel.

[0064] In various embodiments, the memory array 204 is addressable by word lines via row decoder A 218 and row decoder B 220, and by bit lines via column decoder A 226 and column decoder B 228. In some embodiments, the controller 216 is included in the same memory system 200 (e.g., a removable memory card or package) as the one or more memory dies 202. Commands and data are transmitted between the host device 232 and the controller 216 via lines 214, and between the controller and the one or more memory dies 202 via lines 212. A specific implementation may include multiple memory dies 202.

[0065] In one embodiment, die controller 206 cooperates with read / write circuit A 222 and read / write circuit B 224 to perform storage operations / memory operations on memory array 204. In certain embodiments, die controller 206 includes voltage driver 234, state machine 208, and on-chip address decoder 210. In one embodiment, state machine 208 includes at least a portion of voltage driver 234. In another embodiment, controller 216 includes at least a portion of voltage driver 234.

[0066] In one embodiment, the voltage driver 234 is configured to supply a voltage to one or more components of the memory array. The magnitude of the voltage and whether the supplied voltage level is increasing or decreasing depends on the operation being implemented by the die controller 206. At some point during operation, the voltage level provided by the voltage driver 234 may include an analog signal that increases from ground or zero voltage or a level substantially close to zero to a desired voltage level required by the component coupled to the voltage driver 234 to implement the desired operation. As the voltage applied to the component coupled to the voltage driver 234 increases, the period of time during which the voltage level changes is referred to herein as charging, precharging, or ramping.

[0067] At another point during operation, the voltage level provided by the voltage driver 234 may include an analog signal configured to maintain the voltage level required by the components coupled to the voltage driver 234 during a particular phase of achieving the desired operation. Because the voltage applied to the components coupled to the voltage driver 234 is substantially maintained at the desired voltage level, this period of time is referred to herein as a steady state or stable.

[0068] At another point during operation, the voltage level provided by the voltage driver 234 may include an analog signal that decreases from a desired voltage level to a lower voltage level, a ground level, or a zero voltage, or a level substantially close to zero for the desired operation. As the voltage applied to the components coupled to the voltage driver 234 decreases, the period of time during which the voltage level changes is referred to herein as a discharge, post-charge, or ramp-down.

[0069] In one embodiment, the state machine 208 provides chip-level control of storage and / or memory operations. The on-chip address decoder 210 provides an address interface for converting between addresses used by a host or memory controller and hardware addresses used by row decoder A 218, row decoder B 220, column decoder A 226, and column decoder B 228. The state machine 208 includes logic for activating and controlling the voltage driver 234 and other logic coupled to circuits in electrical communication with the voltage driver 234.

[0070] In one embodiment, one or any combination of the die controller 206, the voltage driver 234, the on-chip address decoder 210, the state machine 208, the row decoder A 218, the row decoder B 220, the column decoder A 226, the column decoder B 228, the read / write circuit A 222, the read / write circuit B 224 and / or the controller 216 may be referred to as one or more management circuits.

[0071] Figure 3 One embodiment of a NAND string 300 including a plurality of memory cells is shown. In some embodiments, Figure 3 The NAND string 300 depicted in FIG. 1 includes four transistors (transistor 302, transistor 304, transistor 306, and transistor 308) connected in series and located between a first select transistor 310 and a second select transistor 312. In some embodiments, transistor 302, transistor 304, transistor 306, and transistor 308 each include a control gate having a charge trapping layer 330. In one embodiment, control gate 322, control gate 324, control gate 326, and control gate 328 are connected to a word line or form part of a word line. In another embodiment, transistor 302, transistor 304, transistor 306, and transistor 308 are storage cells, storage elements, etc., also referred to as memory cells. In some embodiments, a single memory cell may include multiple transistors.

[0072] In some embodiments, the first select transistor 310 gates / connects the NAND string 300 to the bit line 314 via a drain select gate / select gate drain (SGD). In certain embodiments, the second select transistor 312 gates / connects the NAND string 300 to the source line 316 via a source select gate / select gate source (SGS). In another embodiment, the first select transistor 310 is controlled by applying a voltage to a corresponding select gate 318. In some embodiments, the second select transistor 312 is controlled by applying a voltage to a corresponding select gate 320.

[0073] like Figure 3 As shown, in one embodiment, source line 316 is connected to the source of each transistor / memory cell in NAND string 300. In some embodiments, NAND string 300 may include some memory cells that have been programmed and some memory cells that have not been programmed.

[0074] Figure 4 4 is a circuit diagram depicting a memory array 400 including a plurality of NAND strings. The architecture of a memory array using a NAND structure may include a large number of NAND strings. For example, Figure 4Memory array 400 is shown including NAND string 404, NAND string 420, NAND string 436, and NAND string 452. In the depicted embodiment, each NAND string includes drain select transistors (select transistor 408, select transistor 424, select transistor 440, and select transistor 456), source select transistors (select transistor 418, select transistor 434, select transistor 450, select transistor 466), and storage elements (memory cell 410, memory cell 412, memory cell 414, memory cell 416, memory cell 426, memory cell 428, memory cell 430, memory cell 432, memory cell 442, memory cell 444, memory cell 446, memory cell 448, memory cell 458, memory cell 460, memory cell 462, and memory cell 464). The memory cells may be transistors that include a charge trapping layer 468. Although four storage elements are shown for each NAND string for simplicity, some NAND strings may include any number of storage elements, eg, thirty-two, sixty-four, etc. storage elements.

[0075] In one embodiment, NAND string 404, NAND string 420, NAND string 436, and NAND string 452 are connected to source line 402 through source select transistor 418, select transistor 434, select transistor 450, and select transistor 466, respectively. Source select line SGS can be used to control source side select transistors 418, 434, 450, 466. In one embodiment, various NAND strings are connected to bit line 406, bit line 422, bit line 438, and bit line 454 through drain select transistor 408, select transistor 424, select transistor 440, and select transistor 456, respectively, as shown. The drain select transistors can be controlled by drain select line SGD. In some embodiments, the select lines do not necessarily need to be shared between NAND strings; that is, different select lines can be provided for different NAND strings.

[0076] As described above, each word line WL0-WLn connects one or more memory cells. In the depicted embodiment, bit line 406, bit line 422, bit line 438 and bit line 454, and corresponding NAND string 404, NAND string 420, NAND string 436 and NAND string 452 constitute the corresponding columns of memory array 400, storage block, erase block, etc. These columns may also be referred to as channels. In some embodiments, word lines WL0 to WLn constitute rows of memory array 400, storage block, erase block, etc. In some embodiments, each word line WL0 to WLn connects the control gate of each memory cell into a row. Alternatively, the control gate may be provided by word lines WL0 to WLn themselves. In some embodiments, word lines WL0 to WLn may include tens, hundreds, thousands, millions, etc. of memory cells.

[0077] In one embodiment, each memory cell is configured to store data. For example, when storing one bit of digital data, the range of possible threshold voltages ("VTH") of each memory cell can be divided into two ranges, which are assigned logical data "1" and "0". As used herein, the threshold voltage refers to the magnitude of the voltage applied to the gate of the memory cell sufficient to cause the memory cell to activate. In an embodiment in which the memory cell is a NAND transistor, the threshold voltage is a sufficient voltage applied to the gate terminal of the transistor to cause the transistor to conduct current between its source terminal and drain terminal. In an example of a NAND type flash memory, VTH may be negative after the memory cell is erased and may be defined as a logical "1". In one embodiment, the VTH after a programming operation is positive and defined as a logical "0".

[0078] In some embodiments, when VTH is negative and a read is attempted, the memory cell will turn on to indicate that a logical "1" is being stored. In another embodiment, when VTH is positive and a read operation is attempted, the memory cell will not turn on, indicating that a logical "0" is being stored. Each memory cell may also store multiple levels of information, e.g., multiple bits of digital data. In such embodiments, the range of VTH values ​​is divided into the number of levels of data. For example, if four levels of information can be stored in each memory cell, there will be four VTH ranges assigned to the data values ​​"11", "10", "01", and "00".

[0079] In one example of a NAND type memory, the VTH after an erase operation may be negative and defined as "11". Positive VTH values ​​may be used for the "10", "01", and "00" states. In one embodiment, the specific relationship between the data programmed into the memory cell and the threshold voltage range of the memory cell depends on the data encoding scheme employed by the memory cell.

[0080] Figures 5 to 7 Various views of an exemplary three dimensional memory array are depicted. Figure 5 is a block diagram depicting a top view of a portion of a three-dimensional memory array. Figure 5 It can be seen that the memory array extends in the direction of the arrow 530 shown. In one embodiment, the memory array may have 60 to 128 layers. Other embodiments may have fewer or more than 60 to 128 layers. However, Figure 5 The top layer is shown.

[0081] Figure 5 A top view of a portion of a memory array 500 is depicted. A plurality of circles represent vertical columns (e.g., vertical column 522 and vertical column 524, also referred to as channels). Each of the vertical columns includes a plurality of select transistors and a plurality of memory cells. In one embodiment, each of the vertical columns implements a NAND string. More details of these vertical columns are provided below. Since the memory array extends in the direction of the two arrows 530 shown, an erase block includes more than one row of cells. Figure 5 The vertical columns depicted in FIG. 5 are further vertical columns 522 .

[0082] Figure 5 A set of bit lines 514 are also depicted. Figure 5 Twenty-four bit lines are shown because only a portion of an erase block is depicted. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of erase blocks. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line 516.

[0083] Figure 5 The portion of the erase block depicted in FIG. 5 includes a set of openings (grooves 504, 506, 508, 510, and 512). The grooves separate the layers of the three-dimensional array so that smaller partitions can be used in certain storage operations. For example, in Figure 5 , the trenches, along with the individual source line connections, break up the monolithic memory array into portions 518, 520, 526, 528 of the four erase blocks shown. These trenches facilitate performing erase operations on one erase block without adversely affecting the other erase blocks. The trenches may also be used for other routing signals and may be referred to as interconnects or local interconnects in such embodiments. For example, in one embodiment, the connection to the source gate select line may be connected to the source line through a line in one or more trenches.

[0084] although Figure 5 Each region is shown to have four vertical columns, four sections, and sixteen vertical columns, but these exact numbers are exemplary implementations. Other embodiments may include more or fewer regions, more or fewer vertical columns per region, and more or fewer vertical columns per block.

[0085] Figure 5 It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0086] Figure 6 1 depicts a portion of an embodiment of a non-volatile memory medium 120, which shows a cross-sectional view of a portion of a memory array 600. Figure 5 As indicated in FIG. 1 , the cross-sectional view cuts through vertical column 522 and vertical columns 524 and 520 (see Figure 5 ). Figure 6 The structure includes four drain side selection layers SGD0, SGD1, SGD2, and SGD3; four source side selection layers SGS0, SGS1, SGS2, and SGS3; four dummy word line layers DWLL1 a, DWLL1 b, DWLL2 a, and DWLL2 b; and forty-eight data word line layers WLL0-WLL47, which are used to connect to data memory cells. Other embodiments may implement more or less than four drain side selection layers, more or less than four source side selection layers, more or less than four dummy word line layers, and more or less than forty-eight word line layers. Vertical columns 522 and vertical columns 524 are depicted as protruding through the drain side selection layers, source side selection layers, dummy word line layers, and word line layers. In one embodiment, each vertical column includes a NAND string. Below the vertical columns and the layers listed below are substrate 602, insulating film 604 on substrate 602, and source line 316 (SL). The NAND strings of vertical column 522 have source terminals at the bottom of the stack and drain terminals at the top of the stack. Figure 5 Consistent, Figure 6 Vertical columns 522 are shown connected to bit lines 516 via connectors 606. Also depicted are trenches 506 and trenches 508. Portions of erase blocks 518 and 526 extend to either side of the portion shown.

[0087] For ease of reference, drain side selection layers SGD0, SGD1, SGD2, and SGD3; source side selection layers SGS0, SGS1, SGS2, and SGS3; dummy word line layers DWLL1 a, DWLL1 b, DWLL2 a, and DWLL2 b; and word line layers WLL0-WLL47 are collectively referred to as conductive layers. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten), or metal silicides. In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers are dielectric layers DL0-DL59. For example, dielectric layer DL49 is above word line layer WLL43 and below word line layer WLL44. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0088] The non-volatile memory cells are formed along vertical columns (also called channels) that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0-WLL47 are connected to storage cells (also called storage cells, memory cells, or data storage cells). Dummy word line layers DWLL1 a, DWLL1 b, DWLL2 a, and DWLL2 b are connected to dummy memory cells. The dummy memory cells do not store user data, while the data storage cells are eligible to store user data. The drain side selection layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND string to the bit lines. The source side selection layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND string to the source line 316SL. In Figure 7 The illustrated memory array 700 is shown in greater detail in FIG.

[0089] Figure 7 A cross-sectional view of a memory array 700 is shown. In one embodiment, the vertical columns 522 are circular and include four layers; however, in other embodiments, more or less than four layers may be included, and other shapes may be used (e.g., a "U" shape instead of an "I" shape, etc.). In one embodiment, the vertical columns 522 include an inner core layer 702 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core layer 702 is a polysilicon channel 704. Materials other than polysilicon may also be used. Note that the channel 704 is connected to the bit line. Surrounding the channel 704 is a tunneling dielectric 706. In one embodiment, the tunneling dielectric 706 has an ONO structure. Surrounding the tunneling dielectric 706 is a shared charge trapping layer 708, such as (for example) silicon nitride. Other materials and structures may also be used. The technology described herein is not limited to any particular material or structure.

[0090] Figure 7 Dielectric layers DL49, DL50, DL51, DL52, and DL53 are depicted, as well as word line layers WLL43, WLL44, WLL45, WLL46, and WLL47. Each word line layer includes a word line region 710 surrounded by an aluminum oxide layer 712, which is surrounded by a blocking oxide layer 714 that may have SiO2. The physical interaction of the word line layers with the vertical columns forms a memory cell (also referred to as a memory cell). Therefore, in one embodiment, the memory cell includes a channel 704, a tunneling dielectric 706, a charge trapping layer 708 (e.g., shared with other memory cells), a blocking oxide layer 714, an aluminum oxide layer 712, and a word line region 710. In some embodiments, the blocking oxide layer 714 and the aluminum oxide layer 712 may be replaced by a single layer of material having insulating properties or by more than 2 layers of different materials having insulating properties. In addition, the materials used are not limited to silicon dioxide (SiO2) or aluminum oxide.

[0091] For example, word line layer WLL47 and a portion of vertical column 522 constitute memory cell MC1. Word line layer WLL46 and a portion of vertical column 522 constitute memory cell MC2. Word line layer WLL45 and a portion of vertical column 522 constitute memory cell MC3. Word line layer WLL44 and a portion of vertical column 522 constitute memory cell MC4. Word line layer WLL43 and a portion of vertical column 522 constitute memory cell MC5. In other architectures, the memory cells may have different structures; however, the memory cells will still remain data storage cells.

[0092] When programming a memory cell, electrons are stored in a portion of the charge trapping layer 708 associated with the memory cell. In response to an appropriate voltage on the word line region 710, these electrons are attracted from the channel 704 into the charge trapping layer 708 through the tunnel dielectric 706. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer via a physical mechanism such as gate induced drain leakage (GIDL).

[0093] In certain embodiments, memory cells in the same position or location in different memory structures (e.g., different NAND strings) on different bit lines can be on the same word line. Each word line can store: one page of data, such as when each single-level cell (SLC) stores 1 bit of data; two pages of data, such as when each multi-level cell (MLC) stores 2 bits of data; three pages of data, such as when each triple-level cell (TLC) stores 3 bits of data; four pages of data, such as when each quad-level cell (QLC) stores 4 bits of data; or other number of pages of data.

[0094] In the depicted embodiment, the vertical 3D NAND flash memory structure includes an "I" shaped memory structure. In other embodiments, the vertical 3D NAND flash memory structure may include a "U" shaped structure, or may have another vertical and / or stacked architecture. In some embodiments, four groups of strings (e.g., four groups of 48 word lines, or another predefined number of word lines) may form an erase block, while in other embodiments, less than or more than four groups of strings may form an erase block. As can be appreciated, any suitable number of memory cells may be part of a single NAND string. In one embodiment, the NAND string includes 48 memory cells.

[0095] Figure 8 The word lines driven from one side 800 are shown. Eight erase blocks of the memory are shown: BLK0 802, BLK1 806, BLK2 810, BLK3 814, BLK4 818, BLK5 822, BLK6 826, and BLK7 830. Note that these numbers are for labeling purposes only and are not intended to represent exact physical locations within the memory array. These erase blocks may be as shown. Figures 5 to 7 Configure as shown.

[0096] As used herein, an "erase block" or "memory block" includes a group of memory cells organized within a memory array so that an erase storage operation affects each memory cell within the erase block. Ideally, each memory cell of the erase block transitions to an erased state as a result of the erase storage operation. In practice, some memory cells may not transition to an erased state and are therefore in an error state due to being improperly erased.

[0097] A single conductive layer may be located under all erase blocks and provide a common source line 834. This is similar to Figure 4836. In the example of FIG. 836, a word line layer may be connected to a high voltage word line switch, which connects one or more voltage sources referred to herein as drivers. The gates used to drive the memory command signals and switch these signals to specific locations in the memory may reside at least partially in the step region 836 and be connected through the step region.

[0098] because Figure 2 The area required for row decoder logic is shown, where word lines are typically driven from only one side. (e.g., row decoder A 218 and row decoder B 220) In conventional architectures of memory arrays, the silicon area required for row decoders to drive each word line from both sides would require twice the conventional area used for row decoders that drive each word line from only one side.

[0099] In a conventional memory array, the row decoders on either side of the memory array are configured to drive word lines and / or half of an erase block. To accommodate the logic and connections required for each block, the conventional die layout alternates the high voltage word line switch groups adjacent to the erase blocks in the staircase region 836 that will connect to and drive the word lines within the erase block.

[0100] exist Figure 8 This alternating connection pattern is illustrated using solid and dashed lines in order to show which staircase region includes the word line switch (WLSW) that controls each erase block. Starting from the bottom, BLK0 802 is controlled and / or driven by BLK0 WLSW 804 located on the right, while BLK1 806 is controlled and / or driven by BLK1 WLSW 808 located on the left. BLK2 810 is controlled and / or driven by BLK2 WLSW 812 on the right, and BLK3 814 is controlled and / or driven by BLK3 WLSW 816 on the left. BLK4 818 is controlled and / or driven by BLK4 WLSW 820, BLK5 822 is controlled and / or driven by BLK5 WLSW 824, BLK6 826 is controlled and / or driven by BLK6 WLSW 828, and BLK7 830 is controlled and / or driven by BLK7 WLSW 832.

[0101] Note that in this configuration, the signal (e.g., voltage and / or current) delivered by the WLSW to the coupled word line propagates over the entire length of the word line layer to reach all memory cells constructed around the vertical column along the word line, including the memory cells at the end opposite to the WLSW. This worst-case delay may result in reduced performance that cannot meet current demands on the non-volatile memory medium 120.

[0102] Fig. 9 A top view of a memory array 900 is shown according to one embodiment. Certain details (eg, bit lines and vertical columns) are not shown in order to clearly illustrate other elements.

[0103] Memory array 900 includes a three-dimensional array of memory cells organized into rows and columns. The rows include a plurality of word lines, and the columns are connected to bit lines. The word lines are organized into erase blocks BLK0 802, BLK1 806, BLK2 810, BLK3 814, BLK4 818, BLK5 822, BLK6 826, and BLK7 830.

[0104] The memory cells within the memory array are connected to the die controller 206 through row decoder A 218, row decoder B 220, column decoder A 226, and column decoder B 228. The die controller 206 supplies voltages and / or currents to the circuits and logic of the decoders to implement memory operations, such as reading a memory cell, writing to a memory cell, and / or erasing a memory cell.

[0105] Specifically, the row decoder and / or the column decoder include a circuit for selectively connecting the memory cell to a voltage driver (such as voltage driver 234 (see Figure 2 )) logic (such as switches). In one embodiment, the memory array includes a connection circuit. The connection circuit is any circuit configured to electrically couple one or more circuit drivers (voltage and / or current) to both ends of the word line. In some embodiments, the connection circuit includes one or more gates or switches to enable certain components to be selectively coupled or substantially simultaneously coupled to one or more drivers. The connection circuit provides a conductive path that includes one or more word lines in the first group of word lines, one or more word lines in the second group of word lines, and a common driver such as voltage driver 234.

[0106] In certain embodiments, the connection circuit includes a plurality of switches (e.g., 902, 904, 906, 908, 910, 912, 914, 916) positioned in the step region 836. The switches selectively connect each word line of the erase block to the voltage driver 234. In one embodiment, the switches are transistors having one terminal in electrical communication with the word line and another terminal in electrical communication with the voltage driver 234, and a gate in electrical communication with the die controller 206 (e.g., the state machine 208).

[0107] exist Fig. 9In the illustrated embodiment, the connection circuit 926 electrically connects a first word line in one erase block (e.g., BLK0 802) and a second word line in an adjacent erase block (e.g., BLK1 806) to the same voltage driver 234. In certain embodiments, the connection circuit 926 includes circuits, logic, etc. to enable the state machine 208 to activate a switch located on one side of the erase block (e.g., BLK0 802) and substantially simultaneously activate a switch located on the opposite end of the erase block (e.g., BLK1 806). In this way, the state machine 208, the voltage driver 234, and the connection circuit 926 work together to supply a voltage signal (e.g., bias voltage) to both the second word line and the first word line substantially simultaneously from both ends.

[0108] As used herein, an adjacent erase block includes an erase block that is located close to or adjacent to an existing erase block, with no other erase blocks between the two erase blocks. Fig. 9 In the illustrated embodiment, BLK0 802 and BLK1 806 are representative examples of adjacent erase blocks. In contrast, BLK0 802 and BLK2 810 are not adjacent erase blocks because BLK1 806 is located between the two erase blocks.

[0109] As mentioned above, analog circuits (such as those of the word lines) experience a resistance-capacitance (RC) load when a voltage is applied. Figure 3 As explained, the voltage applied to the word line is applied to the gate of the memory cell along the word line to bias the memory cell for a memory operation.

[0110] is configured with a state machine 208, a voltage driver 234 (see Figure 2 ) and the memory array 900 of the connection circuit 926 adjust the voltage signals (eg, bias voltages) on the second word line and the first word line from both ends substantially simultaneously, which mitigates the delay caused by the RC load. Figure 8 The embodiment is shown in a top view, so the details of the connection between one word line in a selected erase block (such as BLK0 802) and another word line in an unselected erase block (such as the word line layer and / or connecting circuit of the memory array below the top view) are not shown here for clarity. However, these details are included in subsequent figures of other embodiments. It should be noted that in the embodiments described herein, each word line within a selected erase block of the three-dimensional array is coupled to a corresponding word line in an adjacent erase block of the three-dimensional array.

[0111] In order to reduce the delay caused by propagating the signal over the entire length of the word line, the device disclosed herein uses WLSW (connecting circuits) on both sides of a pair of adjacent erase blocks to drive the signal onto the word line layer from both ends. Therefore, the worst-case delay is caused in the middle of the word line layer and is much smaller than the delay caused by propagating the signal from one end to the other.

[0112] As shown, in the depicted embodiment, WLSWs located in two staircase regions are used to drive even and odd adjacent erase blocks. BLK0+BLK1 WLSW 902 and BLK0+BLK1 WLSW 904 both drive BLK0 802 and BLK1 806. BLK2+BLK3 WLSW 906 and BLK2+BLK3 WLSW 908 drive BLK2 810 and BLK3 814. BLK4+BLK5 WLSW 910 and BLK4+BLK5 WLSW 912 drive BLK4 818 and BLK5 822. BLK6+BLK7 WLSW 914 and BLK6+BLK7 WLSW 916 drive BLK6 826 and BLK7 830.

[0113] Additionally, using switches on both sides to drive two erase blocks instead of driving the gate of a single erase block alternately from one side to the other reduces RC delay and propagation delay without increasing the row decoder (e.g., row decoder A 218, row decoder B 220) layout area.

[0114] Typically, the word lines of memory array 900 are subjected to voltages ranging from about 0 volts to about 20 volts. In embodiments where connection circuit 926 includes switches for connecting both sides of one or more word lines to common driver 1016, and the switches include transistors, the transistors are relatively large compared to other CMOS components of memory array 900. Thus, a word line switch for one erase block may occupy space vertically aligned with a word line of an adjacent erase block as well as space vertically aligned with a word line of a particular erase block. (For example, in Fig. 9 802 and BLK1 806 using the same area previously designed to connect to a single erase block.)

[0115] In one embodiment, the connection circuit 926 includes both one or more external conductive links 920 and one or more internal conductive links 924. The external conductive links 920 are electrical components external to the memory array (outside its perimeter) that are configured to conduct or pass a voltage or current between two word lines of the memory array and the voltage driver 234. Examples of external conductive links 920 and / or components that may include one or more external conductive links 920 include, but are not limited to, wires, leads, traces, metal lines, resistors, conductors, capacitors, inductors, switches, and the like.

[0116] The internal conductive link 924 is an electrical component inside (within the perimeter of) the memory array that is configured to conduct or pass a voltage or current between two word lines of the memory array and the voltage driver 234. Examples of the internal conductive link 924 and / or components that may include one or more internal conductive links 924 include, but are not limited to, wires, leads, traces, metal lines, resistors, conductors, capacitors, inductors, switches, etc. In one embodiment, the connection circuit includes only the external conductive link 920 and does not include the internal conductive link 924.

[0117] Please note that Figure 8 In the disclosed apparatus, the word line layers within the die are separated by trenches to separate adjacent erase blocks. In the disclosed apparatus, one word line in any erase block is driven by a common driver that also drives the word line at the same layer of the memory array in the other erase block, so such separation is unnecessary. Thus, adjacent erase blocks can be operated as a single erase block of double size compared to an embodiment including trenches. Embodiments with larger erase block sizes can be used for products that have larger limited capacities but are optimized to store large contiguous data sets for fast read access.

[0118] As used herein, a "selected" component refers to a component that is targeted / addressed / selected by a command, instruction, or controller (such as die controller 206 or storage controller 216) for a particular operation. Examples of such references include a selected memory cell, a selected page of memory cells, a selected word line, a selected erase block, a selected plane, a selected memory die, etc. As used herein, an "unselected" component refers to a component that is not targeted / addressed / selected by a command, instruction, or controller (such as die controller 206 or storage controller 216) for a particular operation. Examples of such references include an unselected memory cell, an unselected page of memory cells, an unselected word line, an unselected erase block, an unselected plane, an unselected memory die, etc. An operation may include an internal test or maintenance operation (e.g., garbage collection, test mode operation), a user command / request, or a specific storage operation (such as a read operation, a write operation, or an erase operation). Due to various semiconductor architectures and configurations, similar components may be connected, coupled, or otherwise associated with each other in a manner such that an operation on a selected component may adversely affect an unselected component. For example, in a read operation of a memory cell of a NAND string, unselected memory cells along the NAND string are turned on, activated, so that the programmed state of the selected memory cell can be sensed. During the read operation, activating the unselected memory cells along the NAND string may unintentionally change the threshold voltage of some of the unselected memory cells along the NAND string. Such unintended changes are referred to as "disturbance" or "interference." In order to perform a desired operation, a voltage signal or bias at one level may be sent to a selected component, while a voltage signal of a different magnitude may be sent to an unselected component.

[0119] As described above, the number of wordline switches per block increases as the number of wordlines used by the memory device increases. As a result, the width of the switches increases, and thus the area of ​​the memory die required for the wordline switches also increases. Fig.10 A side cross-sectional view of an exemplary memory die is shown, and a portion of the die where wordline switches reside is shown. The width of the area where the wordline switches are located (indicated as WLSW) depends on the number of wordline switches, the width of each wordline switch, and the shallow trench isolation (STI) spacing between each wordline switch to provide electrical isolation. In the case of structures such as CMOS bonded array (CbA), the width of the area used for wordline switches is even more problematic because the memory cell array can shrink dramatically, whereby the CMOS (complementary metal oxide semiconductor) footprint is larger than the array footprint, resulting in reduced chip area / cost efficiency.

[0120] The purpose of the word line switch is to avoid transferring bias from the control gate (CG) line to the unselected blocks. Fig.11A top cross-sectional view of a portion of an exemplary memory die is shown, showing shallow trench isolation (STI) spacing between wordline switches. As more wordline switches are used, the number of isolation trenches increases, which requires more area. Specifically, the horizontal dimension of the memory die, i.e., the X dimension ( Fig.10 The width of the shallow trench isolation is indicated by the number of word line switches per row (memory hole) multiplied by an amount equal to the width of each word line switch plus the width of the shallow trench isolation. For proper electrical isolation, a sufficient width of the isolation trench should be maintained. More specifically, the width of the shallow trench isolation is determined by the maximum programming voltage VPGMmax minus the minimum pass voltage VPASSmin (i.e., the lowest pass voltage among the pass voltages VPASS applied to unselected ones of the word lines during a programming operation).

[0121] In an exemplary memory device, the minimum pass voltage VPASSmin increases by 1 a.u. and the shallow trench isolation pitch or width can be reduced by about 0.1 au. Fig.12 is a table showing possible shallow trench isolation width reductions for different minimum pass voltages VPASSmin (Δ in the table equals 0.1 au). The 1 micron shown should be considered an arbitrary value for illustration purposes only. Depending on the number of word lines, such a reduction can amount to a significant reduction in chip size. Therefore, it is desirable to reduce the width of the isolation trenches between word line switches as much as possible.

[0122] Fig.13A cross-sectional view of a portion of a memory hole with an exemplary pass voltage applied during a programming operation is shown, and neighboring word line interference (NWI, indicated as X) is shown. In order to eliminate NWI, the application of an asymmetric pass voltage VPASS can be utilized. In more detail, a relatively low pass voltage VPASS can be applied on the first neighboring word line WLn+1 to prevent undesired programming, and a relatively high pass voltage VPASS can be applied on the second neighboring word line WLn-1 for boosting. The relatively low pass voltage VPASS on the first neighboring word line WLn+1 makes the difference between the maximum programming voltage VPGMmax and the pass voltage VPASS relatively large, which requires a larger STI spacing. However, when the maximum programming voltage VPGMmax is applied, the number of memory cells being programmed is very small. Therefore, the number of memory cells with NWI is very small (a combination of programmed memory cells plus the first neighboring word line WLn+1 that is erased / in the A state). When the programming voltage VPGM is equal to the maximum programming voltage VPGMmax, since the number of memory cells with NWI problems is very small, the low pass voltage VPASS on the first adjacent word line WLn+1 is not required. Therefore, when the programming voltage is at the maximum programming voltage VPGMmax, the pass voltage VPASS on the first adjacent word line WLn+1 can be increased without significantly affecting the threshold voltage Vth distribution of the programmed memory cells.

[0123] Thus, described herein are memory cells (e.g., Figure 7 MC1-MC5) of the memory device (eg, Figure 2 Memory device 200), each memory cell is connected to a plurality of word lines (eg, Figure 7 One of the word line layers WLL43-WLL47) and disposed in the memory hole (eg, Figure 7 The memory device also includes a control circuit or device (e.g., a control circuit or device coupled to the plurality of word lines and the memory holes) and is configured to maintain a threshold voltage corresponding to one of the plurality of data states. Figure 1 Controller 126, Figure 2 The control device is configured to increase the programming voltage VPGM (VGM) by a programming step size ΔVPGM during a plurality of programming cycles of the programming operation. Fig.14A and Fig. 14BEach of the data points of the programming voltage VPGM in the data points represents one cycle of the programming operation, so ΔVPGM is the amount by which the programming voltage VPGM is increased in the next cycle) is applied to a selected word line of the plurality of word lines, while at least one pass voltage VPASS (i.e., a voltage having a magnitude sufficient to turn on the memory cells connected thereto) is applied to unselected word lines of the plurality of word lines. The control device is also configured to adjust at least one pass voltage VPASS based on the programming voltage VPGM (i.e., a new asymmetric pass voltage VPASS scheme), which is described in more detail below.

[0124] Return to reference Figure 6 and Figure 7 , for example, a plurality of word lines (eg, Figure 6 word line layers WLL0-WLL47), multiple dielectric layers (eg, Figure 6 The dielectric layers DL0-DL52) extend horizontally and overlap each other in an alternating manner in the stack. The memory holes (e.g., Figure 6 A vertical column 522 of memory cells (e.g., Figure 7 The memory cells MC1-MC5 of FIG. 1 are connected in series to a drain side select gate SGD transistor (eg, Figure 6 SGD0-SGD3) with a source side select gate SGS transistor on the source side of each memory well (e.g., Figure 6 The drain side select gate SGD transistor of each memory hole is connected to one of a plurality of bit lines (e.g., Figure 6 The bit line 516 of the memory cell is connected to the source line (eg, Figure 6 SL of the source line SL). Therefore, according to one aspect, the first adjacent word line WLn+1 is adjacent to each selected word line of the plurality of word lines in the stack and is vertically disposed above each selected word line, and the second adjacent word line WLn-1 is adjacent to each selected word line of the plurality of word lines in the stack (i.e., the word line selected for programming and to which a programming voltage is applied) and is vertically disposed below each selected word line. The at least one pass voltage VPASS includes a first pass voltage VPASS1 and a second pass voltage VPASS2. The control device is also configured to apply the first pass voltage VPASS1 to the first adjacent word line WLn+1 and the second pass voltage VPASS2 to the second adjacent word line WLn-1 during a programming operation. Fig.14A and Fig. 14BA graph is shown of a programming voltage VPGM applied to a selected word line among a plurality of word lines, a first pass voltage VPASS1 applied to a first adjacent word line WLn+1, a second pass voltage VPASS2 applied to a second adjacent word line WLn+1, a pass voltage VPASS applied to a word line among a plurality of word lines vertically above the first adjacent word line WLn+1 (indicated as >WLn+1), and a pass voltage VPASS applied to a word line among a plurality of word lines vertically below the second adjacent word line WLn+1 (indicated as <WLn-1) for a current asymmetric pass voltage VPASS scheme and a proposed asymmetric pass voltage VPASS scheme described herein.

[0125] According to one aspect, the control device is further configured to respond to the program voltage VPGM reaching a predetermined maximum program voltage VPGMmax (eg, Fig.14A and Fig. 14B The first pass voltage VPASS applied to the first adjacent word line WLn+1 is ramped up by an incremental pass voltage ΔVPASS based on the last VPGM data point in the program voltage VPGM data points ...

[0126] According to another aspect, the control device is further configured to ramp the first pass voltage VPASS1 applied to the first adjacent word line WLn+1 by an incremental pass voltage ΔVPASS in response to the programming voltage VPGM being equal to the predetermined maximum programming voltage VPGMmax minus twice the programming step amount ΔVPGM or being equal to the predetermined maximum programming voltage VPGMmax minus the programming step amount ΔVPGM. Further, according to another aspect, the incremental pass voltage ΔVPASS is equal to the programming step amount ΔVPGM.

[0127] As mentioned above and return reference Figure 8 and Fig. 9 , for example, a memory device includes a word line switch coupled to a plurality of word lines (eg, Figure 8 BLK0 WLSW 804, BLK1 WLSW 808, BLK2 WLSW 812, BLK3 WLSW 816, BLK4WLSW 820, BLK5 WLSW 824, BLK6 WLSW 828, BLK7 WLSW 832 or Fig. 9902, BLK0+BLK1 WLSW 904, BLK2+BLK3 WLSW 906, BLK2+BLK3 WLSW 908, BLK4+BLK5 WLSW 910, BLK4+BLK5 WLSW 912, BLK6+BLK7 WLSW 914, BLK6+BLK7 WLSW 916). The word line switches are each configured to maintain a switch threshold voltage and selectively connect one or more of the plurality of word lines to a common driver (e.g., Figure 2 The word line switches are connected by shallow trench isolation spacing (at Fig.11 At least one pass voltage VPASS is selected to reduce the electric field across the shallow trench isolation spacing.

[0128] Fig.15 is a graph of programming voltage VPGM minus pass voltage VPASS (i.e., the difference between programming voltage VPGM and pass voltage VPASS) versus programming voltage for a current asymmetric pass voltage VPASS scheme (indicated as "current") and a proposed asymmetric pass voltage VPASS scheme described herein (indicated as "new"). As shown, reducing the maximum electric field across the shallow trench isolation spacing STI can shrink or reduce the STI spacing (e.g., for every 1 a.u. reduction in pass voltage VPASS, the STI spacing is reduced by 0.1 au). Such a reduction in shallow trench isolation STI spacing helps reduce memory die or chip size.

[0129] Fig.16 The steps of the method for operating a memory device are shown. As described above, a memory device (e.g., Figure 2 The memory device 200 includes a memory unit (eg, Figure 7 MC1-MC5), each of which is connected to a plurality of word lines (e.g., Figure 7 One of the word line layers WLL43-WLL47) and disposed in the memory hole (eg, Figure 7 The memory device also includes a control circuit or device (e.g., a control circuit or device coupled to the plurality of word lines and the memory holes) and is configured to maintain a threshold voltage corresponding to one of the plurality of data states. Figure 1 Controller 126, Figure 2The method includes step 1600 of increasing a programming voltage VPGM (V) by a programming step size ΔVPGM during a plurality of programming cycles of a programming operation. Fig.14A and Fig. 14B Each data point in the program voltage VPGM data points represents one cycle of the programming operation, so ΔVPGM is the amount by which the program voltage VPGM is increased in the next cycle) is applied to a selected word line of the plurality of word lines, while at least one pass voltage VPASS (i.e., a voltage having a magnitude sufficient to turn on the memory cells connected thereto) is applied to unselected word lines of the plurality of word lines. The method also includes a step 1602 of adjusting at least one pass voltage VPASS based on the program voltage VPGM.

[0130] Go one step further and return to reference Figure 6 and Figure 7 , for example, a plurality of word lines (eg, Figure 6 word line layers WLL0-WLL47), multiple dielectric layers (eg, Figure 6 The dielectric layers DL0-DL52) extend horizontally and overlap each other in an alternating manner in the stack. The memory holes (e.g., Figure 6 A vertical column 522 of memory cells (e.g., Figure 7 The memory cells MC1-MC5 of FIG. 1 are connected in series to a drain side select gate SGD transistor (eg, Figure 6 SGD0-SGD3) with a source side select gate SGS transistor on the source side of each memory well (e.g., Figure 6 The drain side select gate SGD transistor of each memory hole is connected to one of a plurality of bit lines (e.g., Figure 6 The bit line 516 of the memory cell is connected to the source line (eg, Figure 6Source line SL). Therefore, according to one aspect, the first adjacent word line WLn+1 is adjacent to each selected word line of the plurality of word lines in the stack and is vertically disposed above each selected word line, and the second adjacent word line WLn-1 is adjacent to each selected word line of the plurality of word lines in the stack (i.e., the word line selected for programming and to which a programming voltage is applied) and is vertically disposed below each selected word line. The at least one pass voltage VPASS includes a first pass voltage VPASS1 and a second pass voltage VPASS2. Therefore, according to one aspect, the method further includes the step of applying a first pass voltage VPASS1 to the first adjacent word line WLn+1 and applying a second pass voltage VPASS2 to the second adjacent word line WLn-1 during a programming operation.

[0131] According to one aspect, the method further comprises the step of ramping up the first pass voltage VPASS1 applied to the first adjacent word line WLn+1 by an incremental pass voltage ΔVPASS in response to the program voltage VPGM reaching a predetermined maximum program voltage VPGMmax. As described above and according to another aspect, the incremental pass voltage ΔVPASS is equal to the program step size ΔVPGM.

[0132] According to another aspect, the method further includes the step of ramping the first pass voltage applied to the first adjacent word line Wln+1 by an incremental pass voltage ΔVPASS in response to the program voltage VPGM being equal to a predetermined maximum program voltage VPGMmax minus two times the program step amount ΔVPGM or being equal to a predetermined maximum program voltage VPGMmax minus the program step amount ΔVPGM. Still further, according to another aspect, the incremental pass voltage ΔVPASS is equal to the program step amount ΔVPGM.

[0133] Going one step further, as above and returning to reference Figure 8 and Fig. 9 , for example, a memory device includes a word line switch coupled to a plurality of word lines (eg, Figure 8 BLK0 WLSW 804, BLK1 WLSW 808, BLK2 WLSW 812, BLK3 WLSW816, BLK4 WLSW 820, BLK5 WLSW 824, BLK6 WLSW 828, BLK7 WLSW 832 or Fig. 9902, BLK0+BLK1 WLSW 904, BLK2+BLK3 WLSW 906, BLK2+BLK3 WLSW 908, BLK4+BLK5 WLSW 910, BLK4+BLK5 WLSW 912, BLK6+BLK7 WLSW 914, BLK6+BLK7 WLSW 916). The word line switches are each configured to maintain a switch threshold voltage and selectively connect one or more of the plurality of word lines to a common driver (e.g., Figure 2 The word line switches are connected by shallow trench isolation spacing (at Fig.11 At least one pass voltage VPASS is selected to reduce the electric field across the shallow trench isolation spacing.

[0134] Obviously, without departing from the scope defined in the appended claims, changes may be made to what is described and shown herein. The foregoing description of the embodiments has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present disclosure. The individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable where applicable and can be used in selected embodiments, even if not specifically shown or described. The same situation may also be different in many ways. Such variations should not be considered as departing from the present disclosure, and all such modifications are intended to be included within the scope of the present disclosure.

Claims

1. A memory device, comprising: memory cells, each of the memory cells being connected to one of a plurality of word lines; and a control device coupled to the plurality of word lines and configured to: During a plurality of programming loops of a programming operation, a plurality of pulses of a program voltage whose magnitude increases by a program step amount are applied to a selected word line among the plurality of word lines, while at least one pass voltage is applied to an unselected word line among the plurality of word lines, and The at least one pass voltage is adjusted based on the programming voltage.

2. The memory device of claim 1 , wherein the plurality of word lines and the plurality of dielectric layers extend horizontally and overlap each other in an alternating manner in a stack, the memory cells are disposed in memory holes extending vertically through the stack and are configured to hold a threshold voltage corresponding to one of a plurality of data states, the memory cells are connected in series between a drain-side select gate transistor on a drain side of each of the memory holes and a source-side select gate transistor on a source side of each of the memory holes, the drain-side select gate transistor of each of the memory holes being connected to one of a plurality of bit lines, and the source-side select gate transistor of each of the memory holes being connected to a source line, a first adjacent word line being adjacent to each selected word line of the plurality of word lines in the stack and being disposed vertically above each selected word line, and a second adjacent word line being adjacent to each selected word line of the plurality of word lines in the stack and being disposed vertically below each selected word line, the at least one pass voltage comprising a first pass voltage and a second pass voltage, and the control device is further configured to apply the first pass voltage to the first adjacent word line and the second pass voltage to the second adjacent word line during the programming operation.

3. The memory device of claim 2, wherein the control device is further configured to cause the first pass voltage applied to the first adjacent word line to ramp up in incremental pass voltages in response to the program voltage reaching a predetermined maximum program voltage.

4. The memory device of claim 3, wherein the incremental pass voltage is equal to the programming step amount.

5. The memory device of claim 2 , wherein the control device is further configured to cause the first pass voltage applied to the first adjacent word line to increase by an incremental pass voltage ramp in response to the programming voltage being equal to a predetermined maximum programming voltage minus twice the programming step amount or being equal to the predetermined maximum programming voltage minus the programming step amount.

6. The memory device of claim 5, wherein the incremental pass voltage is equal to the programming step amount.

7. The memory device of claim 1 , further comprising word line switches coupled to the plurality of word lines, wherein the word line switches are each configured to maintain a switching threshold voltage and selectively connect one or more of the plurality of word lines to a common driver for supplying a voltage to the one or more of the plurality of word lines during the programming operation, the word line switches being separated from each other by a shallow trench isolation spacing for providing electrical isolation, and the at least one pass voltage being selected to reduce an electric field across the shallow trench isolation spacing.

8. A controller in communication with a memory device, the memory device comprising memory cells, the memory cells each connected to one of a plurality of word lines, the controller being configured to: instructing the memory device to apply a plurality of pulses of a program voltage having a magnitude increasing by a program step amount to a selected word line among the plurality of word lines while applying at least one pass voltage to an unselected word line among the plurality of word lines during a plurality of program loops of a program operation; and The at least one pass voltage is adjusted based on the programming voltage.

9. The controller of claim 8, wherein the plurality of word lines and the plurality of dielectric layers extend horizontally and overlap each other in an alternating manner in the stack, the memory cells are disposed in memory holes extending vertically through the stack and are configured to hold a threshold voltage corresponding to one of a plurality of data states, the memory cells are connected in series between a drain-side select gate transistor on a drain side of each of the memory holes and a source-side select gate transistor on a source side of each of the memory holes, the drain-side select gate transistor of each of the memory holes being connected to one of a plurality of bit lines, and the source-side select gate transistor of each of the memory holes being connected to a source line, a first adjacent word line being adjacent to each selected word line of the plurality of word lines in the stack and being disposed vertically above each selected word line, and a second adjacent word line being adjacent to each selected word line of the plurality of word lines in the stack and being disposed vertically below each selected word line, the at least one pass voltage comprising a first pass voltage and a second pass voltage, and the controller is further configured to instruct the memory device to apply the first pass voltage to the first adjacent word line and the second pass voltage to the second adjacent word line during the programming operation.

10. The controller of claim 9, wherein the controller is further configured to ramp the first pass voltage applied to the first adjacent word line by an incremental pass voltage in response to the program voltage reaching a predetermined maximum program voltage.

11. The controller of claim 10, wherein the incremental pass voltage is equal to the programming step size.

12. The controller of claim 9 , wherein the controller is further configured to instruct the memory device to ramp up the first pass voltage applied to the first adjacent word line by an incremental pass voltage in response to the programming voltage being equal to a predetermined maximum programming voltage minus two times the programming step amount or being equal to the predetermined maximum programming voltage minus the programming step amount.

13. The controller of claim 8 , wherein the memory device further comprises word line switches coupled to the plurality of word lines, the word line switches each being configured to maintain a switching threshold voltage and to selectively connect one or more of the plurality of word lines to a common driver for supplying a voltage to the one or more of the plurality of word lines during the programming operation, the word line switches being separated from one another by a shallow trench isolation spacing for providing electrical isolation, and the at least one pass voltage being selected to reduce an electric field across the shallow trench isolation spacing.

14. A method of operating a memory device, the memory device comprising memory cells, each of the memory cells being connected to one of a plurality of word lines, the method comprising the steps of: applying a plurality of pulses of a program voltage having a magnitude increasing by a program step amount to a selected word line of the plurality of word lines, while applying at least one pass voltage to an unselected word line of the plurality of word lines, during a plurality of program loops of a program operation; as well as The at least one pass voltage is adjusted based on the programming voltage.

15. The method of claim 14, wherein the plurality of word lines and the plurality of dielectric layers extend horizontally and overlap each other in an alternating manner in a stack, the memory cells are disposed in memory holes extending vertically through the stack and are configured to hold a threshold voltage corresponding to one of a plurality of data states, the memory cells are connected in series between a drain-side select gate transistor on a drain side of each of the memory holes and a source-side select gate transistor on a source side of each of the memory holes, the drain-side select gate transistor of each of the memory holes being connected to one of a plurality of bit lines, and the source-side select gate transistor of each of the memory holes being connected to a source line, a first adjacent word line being immediately adjacent to each selected word line of the plurality of word lines in the stack and being vertically disposed above each selected word line, and a second adjacent word line being immediately adjacent to each selected word line of the plurality of word lines in the stack and being vertically disposed below each selected word line, the at least one pass voltage comprising a first pass voltage and a second pass voltage, and the method further comprising the step of applying the first pass voltage to the first adjacent word line and applying the second pass voltage to the second adjacent word line during the programming operation.

16. The method of claim 15, further comprising the step of ramping up the first pass voltage applied to the first adjacent word line in incremental pass voltages in response to the program voltage reaching a predetermined maximum program voltage.

17. The method of claim 16, wherein the incremental pass voltage is equal to the programming step size.

18. The method of claim 15, further comprising the step of ramping up the first pass voltage applied to the first adjacent word line by an incremental pass voltage in response to the programming voltage being equal to a predetermined maximum programming voltage minus twice the programming step amount or being equal to the predetermined maximum programming voltage minus the programming step amount.

19. The method of claim 18, wherein the incremental pass voltage is equal to the programming step size.

20. The method of claim 14, wherein the memory device further comprises word line switches coupled to the plurality of word lines, the word line switches each being configured to maintain a switching threshold voltage and to selectively connect one or more of the plurality of word lines to a common driver for supplying a voltage to the one or more of the plurality of word lines during the programming operation, the word line switches being separated from one another by a shallow trench isolation spacing for providing electrical isolation, and the method further comprising the step of selecting the at least one pass voltage to reduce an electric field across the shallow trench isolation spacing.

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