Semiconductor package and method of package

Abstract

The semiconductor package includes a first semiconductor die and a second semiconductor die bonded over the first semiconductor die. The second semiconductor die includes a first backside interconnect structure having a first power rail structure. An integrated voltage regulator die is bonded over the second semiconductor die such that the integrated voltage regulator die is electrically connected to the first power rail structure. A via is on and electrically coupled to the first semiconductor die. The via is disposed outside the second semiconductor die and adjacent to the second semiconductor die. A via also electrically couples the first semiconductor die to the second semiconductor die through the integrated voltage regulator die. The embodiment of the invention relates to a semiconductor package and a method of packaging.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor packages and packaging methods. Background Art

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, which allows more components, and therefore more functionality, to be integrated into a given area. When creating a semiconductor package with a top die and a bottom die, the top die may need to be electrically connected to the bottom die. Forming power through silicon vias (TSVs) may require more processing steps, may take up more area, and may increase the cost of manufacturing the CPU top die. It is highly desirable to reduce area and cost and improve form factor. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor package, comprising: a first semiconductor die; a second semiconductor die bonded above the first semiconductor die, wherein the second semiconductor die includes a first backside interconnect structure having a first power rail structure; an integrated voltage regulator die bonded above the second semiconductor die; and a first through-hole located on the first semiconductor die and electrically coupled to the first semiconductor die, wherein the first through-hole is disposed outside the second semiconductor die and adjacent to the second semiconductor die, and wherein the first through-hole electrically couples the first semiconductor die to the first power rail structure of the second semiconductor die through the integrated voltage regulator die.

[0004] Some other embodiments of the present application provide a semiconductor package, including: a first semiconductor die, the first semiconductor die including a first front-side interconnect structure; a second semiconductor die and a third semiconductor die, separated by a distance and bonded above the first semiconductor die, wherein the second semiconductor die includes a first back-side interconnect structure having a first power rail structure, and the third semiconductor die includes a second back-side interconnect structure having a second power rail structure; an integrated voltage regulator die, bonded above the second semiconductor die and the third semiconductor die, the integrated voltage regulator die being electrically connected to the first power rail structure and the second power rail structure; and one or more through-holes, arranged on the first front-side interconnect structure of the first semiconductor die, and wherein the one or more through-holes electrically couple the first power rail structure and the second power rail structure to the first front-side interconnect structure of the first semiconductor die.

[0005] Still other embodiments of the present application provide a packaging method, comprising: bonding a first semiconductor die to a second semiconductor die, wherein the first semiconductor die includes a first front-side interconnect structure, and wherein the second semiconductor die includes a first back-side interconnect structure having a first power rail structure; depositing an insulating layer above the first semiconductor die and adjacent to the second semiconductor die; forming a first through-hole in the insulating layer, wherein a first end of the first through-hole is electrically coupled to the first front-side interconnect structure of the first semiconductor die; and bonding an integrated voltage regulator die over the second semiconductor die and the insulating layer, wherein a second end of the first through-hole opposite to the first end is electrically connected to the first power rail structure in the first back-side interconnect structure of the second semiconductor die through the integrated voltage regulator die. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F A cross-sectional view of a semiconductor device at an intermediate stage in the formation of a package according to some embodiments of the present disclosure and a top view of the semiconductor device are shown.

[0008] Figure 2A , Figure 2B and Figure 2C A cross-sectional view of an intermediate stage in the production of a semiconductor die including a semiconductor device, metallization layers, and power rail structures is shown.

[0009] Figure 3 A cross-sectional view of a metallization layer is shown.

[0010] Figure 4 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0011] Figure 5 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0012] Figure 6 A flow chart of a process for producing a semiconductor package according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] According to various embodiments, two semiconductor dies (one attached on top of the other) may be electrically connected to each other. In some embodiments, a first semiconductor die including a central processing unit (CPU) or including a graphics processing unit (GPU) is attached (e.g., bonded) over a second semiconductor die including a random access memory (RAM) circuit and / or a static RAM (SRAM) circuit. In some embodiments, one or more TSVs or TSV towers (e.g., power TSVs) for delivering power are arranged outside the semiconductor die having the CPU.

[0016] The power supply can be regulated by an integrated voltage regulator (IVR) attached to a power rail structure inside the semiconductor die, such as a power rail or a super power rail (SPR). The IVR can receive power from a power supply unit (PSU) and provide regulated power, such as regulated voltage and current, to one or more semiconductor dies including a semiconductor die having a CPU / GPU. In some embodiments, the IVR is connected by one or more through-holes, which extend through a dielectric layer outside the semiconductor die including the CPU / GPU, such as an insulating layer or a sealant layer. Therefore, each through-hole of the one or more through-holes is a dielectric through-hole (TDV) connected between the IVR and another semiconductor die (e.g., a semiconductor die including an SRAM), and therefore, power is provided to the other semiconductor die by the TDV. Implementing one or more TDVs arranged outside the semiconductor die having a CPU / GPU can reduce the processing steps and cost of the package, and can also improve the form factor.

[0017] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F A cross-sectional view of a semiconductor device at an intermediate stage in the formation of a package 160 and a top view of the semiconductor device are shown in accordance with some embodiments of the present disclosure. Figure 1A Semiconductor device 100 is shown including semiconductor die 111 bonded (eg, connected) to semiconductor die 115 . Figure 1A Also shown is semiconductor die 113 bonded to semiconductor die 115. Semiconductor die 111 and 113 are bonded to semiconductor die 115 via surface-to-surface bonding (eg, metal-to-metal bonding and dielectric-to-dielectric bonding), as explained in more detail below.

[0018] As shown, each of the semiconductor dies 111 and 113 includes a backside interconnect structure 112 at the top and a frontside interconnect structure 107 at the bottom. The backside interconnect structure 112 may include a power rail structure for power transmission in the semiconductor dies 111 and 113. In some embodiments, each of the semiconductor dies 111 and 113 includes a semiconductor device layer 105, which may include active devices (e.g., transistors) interconnected together by the backside interconnect structure 112 to provide functional circuits. For example, each of the semiconductor dies 111 and 113 can provide a logic circuit (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.) in a completed semiconductor package. The semiconductor die 115 includes a frontside interconnect structure 103 at the top, so that a surface-to-surface bonding connection is made between the frontside interconnect structure 103 of the semiconductor die 115 and the frontside interconnect structure 107 of the semiconductor die 111 and 113. In some embodiments, the package 160 has one of the semiconductor die 111 or the semiconductor die 113. Optionally, package 160 may include additional semiconductor dies at the same level as semiconductor dies 111 and 113 .

[0019] In addition, each of the semiconductor dies 111 and 113 includes an insulating bonding layer 109 on the front side interconnect structure 107 and a bonding pad 117 formed in the insulating bonding layer 109. The bonding pad 117 may be a conductive column, a pad, etc. that makes an external connection. The bonding pad 117 may be formed of a metal such as copper, aluminum, etc., and may be formed by, for example, plating, etc. In some embodiments, the bonding pad 117 may be electrically connected to a conductive component of the front side interconnect structure 107 through a conductive via (sometimes referred to as a bonding pad via). The insulating bonding layer 109 may be made of a material suitable for subsequent dielectric-to-dielectric bonding, such as silicon oxide, silicon oxynitride, etc. The insulating bonding layer 109 may be deposited on the front side interconnect structure 107, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. A planarization process (e.g., chemical mechanical polishing (CMP), etc.) may be implemented so that the top surfaces of the bonding pad 117 and the insulating bonding layer 109 are coplanar (within process variations). As will be described in more detail below, planarized bottom surfaces 145 of semiconductor die 111 and 113 are bonded to underlying semiconductor die 115 .

[0020] The semiconductor die 115 includes a semiconductor device layer 101 and a front-side interconnect structure 103. The semiconductor device layer 101 may include active devices (e.g., transistors) disposed at the top surface of the semiconductor substrate, and the active devices of the semiconductor device layer 101 may be interconnected together through the front-side interconnect structure 103 to provide a functional circuit. For example, each of the semiconductor dies 111 and 113 may provide a memory circuit (e.g., a static random access memory (SRAM) circuit, a dynamic random access memory (DRAM) circuit, etc.) in a completed semiconductor package. The semiconductor die 115 also includes an insulating bonding layer 119 on the front-side interconnect structure 103 and a bonding pad 121 formed in the insulating bonding layer 119. The bonding pad 121 and the insulating bonding layer 119 may be formed of the same material using the same process as the bonding pad 117 and the insulating bonding layer 109, respectively, as described above. In some embodiments, a planarization process (eg, chemical mechanical polishing (CMP), etc.) may be performed to make the top surfaces of the bonding pad 121 and the insulating bonding layer 119 coplanar (within process variations).

[0021] like Figure 1AAs shown in , semiconductor die 111 and 113 are bonded side by side on the top surface of semiconductor die 115 with a gap therebetween. Semiconductor die 111 and 113 and semiconductor die 115 are directly bonded in a face-to-face manner (sometimes referred to as hybrid bonding) by dielectric-to-dielectric bonding and metal-to-metal bonding processes, so that the front sides of semiconductor die 111 and 113 are bonded side by side to the front side of semiconductor die 115 with a gap therebetween. Specifically, insulating bonding layer 109 of semiconductor die 111 and 113 is bonded to insulating bonding layer 119 on semiconductor die 115 by dielectric-to-dielectric bonding without using any adhesive material (e.g., die attach film), and bonding pads 117 of semiconductor die 111 and 113 are bonded to bonding pads 121 on semiconductor die 115 by metal-to-metal bonding without using any eutectic material (e.g., solder). Bonding may include surface activation, pre-bonding, and annealing. Surface activation may include activating the insulating bonding layer 109 and / or 119, and may be implemented using, for example, dry processing, wet processing, plasma processing, exposure to H2, exposure to N2, exposure to O2, combinations of these, and the like. In an embodiment using wet processing, for example, an RCA cleaning process may be used. Through the activation process, the number of OH groups at the surface of the insulating bonding layer 109 and / or 119 increases. After activating the surface of the insulating bonding layer 109 and / or 119, pre-bonding is implemented by applying a small pressure to press the semiconductor die 111 and 113 against the semiconductor die 115. The pre-bonding is implemented at a low temperature, such as room temperature, such as a temperature in the range of about 15°C to about 30°C. The bonding strength of the insulating bonding layers 109 and 119 is then improved in a subsequent annealing step, wherein the insulating bonding layers 109 and 119 are annealed at a high temperature, such as a temperature in the range of about 100°C to about 450°C. After annealing, a bond, such as a covalent bond, is formed to bond the insulating bonding layers 109 and 119. Bonding pads 117 and 121 may be in physical contact after pre-bonding, or may expand to make physical contact during annealing. In addition, during annealing, the materials (e.g., copper) of bonding pads 117 and 121 mix, thereby also forming a metal-to-metal bond. Therefore, the resulting bond is a mixed bond including a dielectric-to-dielectric bond and a metal-to-metal bond. Therefore, the circuits within semiconductor die 111 and 113 can be electrically connected to the circuits within semiconductor die 115 through bonding pads 117 and 121.

[0022] Due to the bonding, portion 149 of semiconductor die 115 (e.g., portion of frontside interconnect structure 103 of semiconductor die 115) is not covered by semiconductor die 111 and 113, and a subset of bonding pads 121 may be exposed. In some embodiments, semiconductor die 115 has width 106, and semiconductor die 111 has width 108 that is shorter than width 106. In some embodiments, the total width of semiconductor die 111 and 113 is less than width 106 of semiconductor die 115. Therefore, portion 149 not covered by semiconductor die 111 and 113 has width 104.

[0023] Figure 1B The semiconductor device 100 is shown to additionally include bottom surfaces 145 (e.g., first surfaces) of the semiconductor dies 111 and 113, and also shows top surfaces 147 (e.g., second surfaces) of the semiconductor dies 111 and 113. The semiconductor device 100 also shows the top surface 143 (e.g., first surface) of the semiconductor die 115. In addition, the surface-to-surface bonding is located between the top surface 143 of the front-side interconnect structure 103 and the bottom surface 145 of the front-side interconnect structure 107 of the semiconductor dies 111 and 113.

[0024] Figure 1B A portion 149 on the top of the semiconductor die 115 is shown covered with an insulating layer 114 so that the insulating layer 114 is also in contact with the semiconductor die 111 and 113. For example, in some embodiments, the insulating layer 114 includes a dielectric, gap filling material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, combinations thereof, etc., deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. In some embodiments, the insulating layer 114 is a molding material or compound formed by compression molding, transfer molding, etc. and a subsequent curing process. The molding material may or may not include a filling material (e.g., a silicon dioxide filler). A planarization process may be implemented to planarize the top surfaces of the insulating layer 114 and the semiconductor die 111 and 113. The planarization process may be CMP, etch back, combinations thereof, etc. Insulation layer 114 extends from top surface 143 of insulation bonding layer 119 to top surfaces 147 of semiconductor dies 111 and 113 , and thus, insulation layer 114 has a top surface at the level of top surface 147 .

[0025] In addition, the vias 120 extend through the height of the insulating layer 114. In embodiments where the insulating layer 114 is made of a dielectric material, the vias 120 may be referred to as TDVs. As an example of forming the vias 120, an opening may be etched through the insulating layer 114 using, for example, a combination of photolithography and etching. The opening may expose certain bonding pads 121. Then, a conductive material (e.g., a metal such as copper) may be filled in the opening to form the vias 120. Each via 120 is electrically coupled (e.g., electrically connected) from a first end 131 of the via 120 to a bonding pad 121 at a top surface 143 of the semiconductor die 115. In addition, the second end 132 of each via 120 extends to the height of the insulating layer 114, the height of the insulating layer 114 being the top surface 147. Figure 1E and Figure 1F The distribution of vias 120 over semiconductor die 115 is depicted.

[0026] Next, in Figure 1C In the embodiment, an insulating bonding layer 171 having a bonding pad 175 disposed therein is formed over the semiconductor dies 111 and 113 and the insulating layer 114 and the through hole 120. The bonding pad 175 may be a conductive column, a pad, etc. made into an external connection. The bonding pad 175 is similar to the bonding pads 117 and 121 described above. In some embodiments, the bonding pad 175 and / or the bonding pad 177 may be electrically connected to a conductive component of the backside interconnect structure 112 (e.g., a power rail structure) through a conductive via. The insulating bonding layer 171 may be made of a material suitable for subsequent dielectric-to-dielectric bonding and is similar to the insulating bonding layer 109 or 119. A planarization process (e.g., chemical mechanical polishing (CMP), etc.) may be implemented so that the top surfaces of the bonding pad 175 and the insulating bonding layer 171 are coplanar (within process variations). In some embodiments, the insulating layer 114 contacts the insulating bonding layer 171, and the insulating bonding layer 171 includes a bonding pad 175 formed in the insulating bonding layer 171. In some embodiments, the second end 132 of each via 120 is electrically connected to the bonding pad 175 .

[0027] like Figure 1CAs further shown, an integrated voltage regulator die 127 can be bonded to the semiconductor dies 111 and 113 and the vias 120. The integrated voltage regulator die 127 can include a semiconductor substrate 125 (e.g., a semiconductor device layer) on which active devices are disposed and a front-side interconnect structure 122 that electrically connects the active devices to form one or more functional circuits (such as an IVR circuit). The integrated voltage regulator die 127 also includes an insulating bonding layer 173 connected to the front-side interconnect structure 122 and a bonding pad 177 formed in the insulating bonding layer 173. The insulating bonding layer 173 and the bonding pad 177 can be made of the same material using the same process as the insulating bonding layer 109 and the bonding pad 117 discussed above, respectively. Insulating bonding layer 173 and bonding pad 177 can be directly bonded to insulating bonding layer 171 and bonding pad 175 using the dielectric-to-dielectric bonding and metal-to-metal bonding processes described above (e.g., the bonding processes used to bond semiconductor die 111 and 113 to semiconductor die 115). Planarized insulating bonding layer 173 is bonded to top surface 147 of semiconductor die 111 and 113. In some embodiments, integrated voltage regulator die 127 receives voltage from a power supply unit (PSU), regulates the voltage, and provides the regulated voltage, e.g., a stabilized voltage, to semiconductor die 111 and 113 via backside interconnect structure 112. In some embodiments, second end 132 of through-hole 120 is connected to front-side interconnect structure 122 of integrated voltage regulator die 127, and integrated voltage regulator die 127 receives voltage, e.g., an unregulated voltage, from a power supply unit through through-hole 120. For example, voltage and current of the integrated voltage regulator die 127 are received by the bond pads 175 and passed to the vias 120 .

[0028] In some embodiments, the integrated voltage regulator die 127 provides a constant power supply, for example, a constant voltage and current, for each device in the semiconductor die (such as the CPU, GPU, or SRAM of the semiconductor die 111, 113, and 115). The CPU, GPU, and SRAM may be sensitive to voltage fluctuations or insufficient current. Therefore, for reliable performance, the integrated voltage regulator die 127 is implemented in the semiconductor die where the CPU is located. In some embodiments, when implementing computationally intensive tasks, the CPU consumes considerable energy of about tens of watts or even more than one hundred watts. When implementing computationally intensive tasks, the lack of sufficient current or voltage drop may shorten the CPU clock cycle and impair performance or even shut down the CPU. Therefore, the integrated voltage regulator die 127 is used to provide reliable performance through the CPU. In some embodiments, when receiving current and voltage from the power supply unit, the integrated voltage regulator die 127 generates a reliable voltage and provides a reliable power supply to one or more CPUs / GPUs of the semiconductor die 111 and 113 through the backside interconnect structure 112 and to the SRAM of the semiconductor die 115 through one or more through-holes 120. In some embodiments, the backside interconnect structure 112 includes a power rail structure. When providing current for sensitive devices such as CPU or SRAM, the power rail can be made wider than the connection line of the tube die to reduce the ohmic drop. Figure 2C to describe.

[0029] In some embodiments, regulated power is provided from integrated voltage regulator die 127 to semiconductor die 111 and 113 through backside interconnect structure 112. In addition, regulated power is provided from integrated voltage regulator die 127 to semiconductor die 115 through via 120. In some embodiments, signal communication between semiconductor die 111 and 113 and semiconductor die 115 is accomplished through bonding between frontside interconnect structure 103 and frontside interconnect structure 107. Implementing via 120 outside the semiconductor die with a top semiconductor device (e.g., a CPU or GPU) can reduce processing steps and cost of packaging, and can also improve form factor.

[0030] Figure 1C Also included are vias 124 and 126 that extend the height of semiconductor die 115 and connect first ends 141 (the narrower ends) of vias 124 and 126 to front-side interconnect structure 103 of semiconductor die 115. Second ends 142 (the wider ends) of vias 124 and 126 are located at the bottom of semiconductor die 115.

[0031] Figure 1D In addition to Figure 1CThe semiconductor device 100 further includes two or more connector bumps 102. The connector bumps 102 are connected to the bottom of the semiconductor die 115 and can be connected to the second ends 142 of the vias 124 and 126. Figure 1D Also shown is a printed circuit board PCB 110 electrically connected to semiconductor die 115 via connector bumps 102. In some embodiments, PCB 110 provides a voltage from a power supply unit. The provided voltage can be connected to an integrated voltage regulator die 127 through connector bumps 102, one or both of vias 124 and 126, front-side interconnect structure 103, and via 120. The provided voltage is then regulated by integrated voltage regulator die 127 as described above. Connector bumps 102 can also provide communication between PCB 110 and semiconductor die 115, semiconductor die 111, and semiconductor die 113. Figure 1D Also shown is a package 160 , such as a semiconductor device package, coupled to the PCB 110 .

[0032] Figure 1E and Figure 1F Some embodiments of the present disclosure are shown Figure 1B Top view of a semiconductor package. Figure 1E and Figure 1F Semiconductor dies 111 and 113 are shown disposed over semiconductor die 115 and two or more vias 120 disposed on semiconductor die 115 and outside of the area covered by semiconductor die 111 and 113 . Figure 1E Similar to Figure 1B , Figure 1C and Figure 1D , because via 120 is arranged in portion 137 between semiconductor dies 111 and 113, for example, a segment. However, Figure 1F is different because vias 120 are arranged at end portions 136 and 138, which are located at sides of semiconductor dies 111 and 113 that do not face each other. In some embodiments, insulating layer 114 is deposited over portions 136, 137, and 138 on semiconductor die 115, and vias 120 extend in the insulating layer.

[0033] Figure 2A , Figure 2B and Figure 2C A cross-sectional view of an intermediate stage for producing a semiconductor die including a semiconductor device, a metallization layer, and a power rail structure is shown. In some embodiments, the metallization layer is a front-side metallization layer, and the power rail structure is a back-side power rail structure. Figure 2A , Figure 2B and Figure 2C The stage can be used to produce semiconductor die 111 and semiconductor die 113. Therefore, in Figure 2A , Figure 2B and Figure 2C In the following discussion, Figure 2A , Figure 2B and Figure 2C The device layer 204 and Figure 1A , Figure 1B , Figure 1C and Figure 1D The semiconductor device layer 105 is consistent with the semiconductor device layer 105. Figure 2C The backside interconnect structure 206B including the power rails is consistent with the backside interconnect structure 112, and Figure 2A , Figure 2B and Figure 2C The front-side interconnect structure 206F and Figure 1A , Figure 1B , Figure 1C and Figure 1D The front side interconnect structure 107 is consistent with the front side interconnect structure 107.

[0034] Figure 2A , Figure 2B and Figure 2C Exemplary details of intermediate processing steps for forming an integrated circuit die 200 (eg, a semiconductor die) including a backside power rail are shown. Initially, the integrated circuit die 200 may be formed as part of a wafer that is subsequently singulated. Referring first to Figure 2A , the integrated circuit die 200 includes a semiconductor substrate 202, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 202 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer or gradient substrates. The semiconductor substrate 202 has an active surface (e.g., Figure 2A the upward-facing surface) (sometimes referred to as the front side) and the inactive surface (e.g. Figure 2A The downward-facing surface in the middle (and sometimes called the dorsal side).

[0035] The device layer 204 is formed at the front side (i.e., active surface) of the semiconductor substrate 202. The device layer 204 may include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. In some embodiments, the active devices of the device layer 204 include nano FETs (e.g., nanowire field effect transistors (FETs), nanosheet FETs (nano FETs), etc.). The nano FETs include nano structures 210 (e.g., nanosheets, nanowires, etc.) above the fins 203 extending upward from the base substrate 202, and the nano structures 210 are used as channel regions for the nano FETs. The nano structures 210 may include p-type nano structures, n-type nano structures, or combinations thereof.

[0036] The gate stack 212 (including the gate dielectric layer 212D and the gate electrode 212E) is disposed above the top surface of the fin 203 and along the top surface, sidewalls and bottom surface of the nanostructure 210. The gate dielectric layer 212D can be disposed between the gate electrode 212E and the nanostructure 210. The epitaxial source / drain regions 208 are disposed on the fin 203 on the opposite side of the gate stack 212, and the nanostructure 210 can extend between adjacent epitaxial source / drain regions 208. The source / drain region 208 can refer to a source or a drain, individually or collectively depending on the context. The device layer 204 can also include other types of transistors (e.g., fin field effect transistors (FinFETs), etc.).

[0037] An interlayer dielectric, such as ILD 214, is formed over the front side of semiconductor substrate 202. ILD 214 surrounds and covers the devices of device layer 204. ILD 214 may include one or more dielectric layers formed of materials such as silicon oxide, silicon oxynitride, carbon silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. ILD 214 may be deposited by CVD, ALD, PVD, etc. In some embodiments, a contact etch stop layer (e.g., CESL 213) including silicon nitride, etc. may be disposed between ILD 214 and the devices of device layer 204.

[0038] The conductive plugs 216 extend through the ILD 214 and the CESL 213 to electrically and physically couple the devices of the device layer 204. For example, the conductive plugs 216 can couple the gate stack 212 and the source / drain regions 208. In some embodiments, a silicide region can be disposed at the interface between the conductive plugs 216 and the source / drain regions 208. The conductive plugs 216 can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof. Because the conductive plugs 216 are disposed on the front side of the substrate 202, they can also be referred to as conductive plugs 216, for example, front side contacts.

[0039] The front-side interconnect structure 206F is disposed above the ILD 214 and the conductive plug 216. The front-side interconnect structure 206F interconnects the devices of the device layer 204 to form an integrated circuit. The front-side interconnect structure 206F includes, for example, a metallization pattern in one or more dielectric layers. The metallization pattern includes, for example, metal lines and vias formed in one or more low-k dielectric layers using a damascene process. The metallization pattern of the front-side interconnect structure 206F is electrically coupled to the devices of the device layer 204 through the conductive plug 216.

[0040] exist Figure 2B In the embodiment of the present invention, the carrier substrate 220 is bonded to the top surface of the front-side interconnect structure 206F by the first bonding layer 218A and the second bonding layer 218B. The carrier substrate 220 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. The carrier substrate 220 can provide structural support for the integrated circuit die 200 during subsequent processing steps and in the completed device. The first bonding layer 218A and the second bonding layer 218B can be deposited on the front-side interconnect structure 206F and the carrier substrate 220 respectively by any suitable process (such as PVD, CVD, ALD, etc.). The first bonding layer 218A and the second bonding layer 218B can each include an insulating material suitable for a dielectric to dielectric bonding process. Exemplary materials for the first bonding layer 218A and the second bonding layer 218B include silicon oxide (e.g., SiO2), silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, etc.

[0041] After depositing the first bonding layer 218A and the second bonding layer 218B, the carrier substrate 220 can be bonded to the front side interconnect structure 206F using a suitable technique (such as dielectric to dielectric bonding, etc.). The dielectric to dielectric bonding process may include applying a surface treatment to one or more of the first bonding layer 218A and the second bonding layer 218B. The surface treatment may include a plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsed with deionized water, etc.) that may be applied to one or more of the first bonding layer 218A and the second bonding layer 218B. Then, the carrier substrate 220 is aligned with the front side interconnect structure 206F, and the two are pressed against each other to start the pre-bonding of the carrier substrate 220 to the front side interconnect structure 206F. The pre-bonding may be implemented at room temperature (e.g., between about 21°C and about 25°C). After the pre-bonding, an annealing process may be applied by, for example, heating the front side interconnect structure 206F and the carrier substrate 220 to a temperature in the range of 150°C to 500°C. The annealing process drives and triggers the formation of covalent bonds between the first bonding layer 218A and the second bonding layer 218B. After bonding, the first bonding layer 218A and the second bonding layer 218B may be collectively referred to as bonding layers 218. In other embodiments, other bonding processes may be used, such as ambient bonding, vacuum bonding, etc.

[0042] exist Figure 2C , the substrate 202 and the fins 203 are at least substantially replaced with the backside interconnect structure 206B. For example, the substrate 202 and the fins 203 may be substantially removed from the backside of the device layer 204 using one or more planarization processes (e.g., chemical mechanical polishing (CMP), etc.) and an etch-back process. The etch-back process may be a selective process that etches the material of the substrate 202 and the fins 203 at a faster rate than the material of the gate stack 212 or the epitaxial source / drain regions 208. In some embodiments, a sacrificial masking layer may be formed as part of forming the device layer 204 to assist in the selective removal of the substrate 202 and the fins 203. In the illustrated embodiment, the substrate 202 and the fins 203 are completely removed. In other embodiments, a small portion of the substrate 202 and / or the fins 203 may remain.

[0043] After the substrate 202 and the fins 203 are substantially removed, a backside ILD 226 is deposited on the backside of the device layer 204. The backside ILD 226 may include one or more dielectric layers formed of materials such as silicon oxide, silicon oxynitride, carbon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. A backside conductive plug 222 extends through the backside ILD 226 to electrically and physically couple the epitaxial source / drain regions 208. In some embodiments, a silicide region may be provided at the interface between the backside conductive plug 222 and the source / drain regions 208. The backside conductive plug 222 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof. The backside conductive plug 222 allows additional connections to be made to the backside of the device layer 204 for increased routing flexibility.

[0044] A backside interconnect structure 206B is formed over the backside ILD 226 and the backside conductive plug 222 on the backside of the device layer 204. The backside interconnect structure 206B may include, for example, a metallization pattern in one or more dielectric layers. The metallization pattern includes, for example, metal lines and vias formed in one or more low-k dielectric layers using a damascene process. Specifically, the backside interconnect structure 206B may provide a power delivery circuit to the devices of the device layer 204. For example, the backside interconnect structure 206B may include a power rail 224 (sometimes referred to as a backside power rail, a super power rail, a power rail structure, etc.) to provide power to the transistors of the device layer 204. Because the power rail 224 may be larger (e.g., wider and / or thicker) than the signal line of the frontside interconnect structure 206F, positioning the power rail 224 in the backside interconnect structure 206B improves routing flexibility and allows additional signal lines to be formed in the frontside interconnect structure 206F.

[0045] After forming the backside interconnect structure 206B, the substrate 220 may be removed (eg, using a planarization process) to expose the frontside interconnect structure so that an insulating bonding layer / bonding pad (eg, Figures 1A to 1D Insulating bonding layer 109 and bonding pad 117) for surface-to-surface bonding. In some embodiments, a second substrate (similar to substrate 202, not explicitly shown) can be temporarily attached to backside interconnect structure 206B when forming the insulating bonding layer / bonding pad.

[0046] Figure 3 A cross-sectional view of a metallization layer, such as a front-side interconnect structure 103 of a semiconductor die 115 is shown. Figure 3Front side interconnect structures 107 and 122 may also be shown. In some embodiments, front side interconnect structure 103 includes one or more connection layers, for example, connection layers 103A and 103B. Front side interconnect structure 103 including connection layers 103A and 103B includes conductive connection lines 301 produced in and on top of dielectric layer 306, which may include silicon dioxide.

[0047] Figure 4 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown. Figure 4 include Figure 1D The package 160 is disposed above the PCB 110, and the PCB 110 includes one or more holes 403 for heat exchange to remove heat generated by the package 160. The package 160 is disposed on the PCB 110 via a plurality of inductors 405 between the package 160 and the PCB 110. The PCB 110 is disposed on the carrier substrate 401 via a plurality of inductors 405 between the PCB 110 and the carrier substrate 401. Figure 4 Also shown is a filler 425 (e.g., a thermally conductive filler) or air around the package 160 and thermally conductive walls 415 and 420 around the filler 425. In some embodiments, the filler 425 is air or a vacuum, and in some other embodiments, the filler 425 is thermally conductive. In addition, the heat sink 410 is arranged above the thermally conductive walls 415. In some embodiments, the package 160 is infused with a thermally conductive filler 418 that also surrounds the package 160.

[0048] Figure 4 Also shown is a bonding pad 177 that is also used to receive the voltage and current generated by the integrated voltage regulator die 127. The integrated voltage regulator die 127 generates a regulated voltage, for example, a substantially constant voltage, and also generates a desired current so that the voltage does not fluctuate when the current varies. The generated regulated voltage and the generated current are transferred from the bonding pad 177 to the backside interconnect structure 112 of the semiconductor dies 111 and 113 via the bonding pad 175. The generated regulated voltage and the generated current are also transferred to the semiconductor die 115 through the through-hole 120.

[0049] Figure 5 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown. Figure 5 Similar to Figure 1D , wherein the same reference numerals represent the same elements formed by the same process. Figure 1D , Figure 5The semiconductor package includes a semiconductor die 111 disposed above a semiconductor die 115, and a through hole 120 is located outside the semiconductor die 111 and passes through an insulating layer 114, such as a dielectric layer or a sealant layer. The surface-to-surface bonding process couples the front side interconnect structure 107 of the semiconductor die 111 to the front side interconnect structure 103 of the semiconductor die 115. The surface-to-surface bonding includes an insulating bonding layer 109 having bonding pads 117, and the insulating bonding layer 109 having bonding pads 117 is respectively bonded to the insulating bonding layer 119 having bonding pads 121, as also shown in FIG. Figures 1A to 1D as shown in .

[0050] Figure 5 The semiconductor package includes another semiconductor die 116, the semiconductor die 116 includes through-holes 502 and 504 inside the semiconductor die 116, and does not include a back-side interconnect structure 112. In addition, the semiconductor die receives power from the PCB 110 through the connector bumps 102 and the through-holes 126. Specifically, the semiconductor die 116 includes: a semiconductor substrate 505, having active devices arranged at the top surface of the semiconductor substrate 505, and the active devices are electrically connected together through the front-side interconnect structure 507 to form a functional circuit (e.g., a CPU circuit, a GPU circuit, etc.). The through-holes 502 and 504 extend through the semiconductor substrate 505, and electrically connect the front-side interconnect structure 507 to the back side (bottom surface) of the semiconductor die 116. The semiconductor die 116 can be bonded to the semiconductor die 115 in a face-to-back manner through the bonding between the back side of the semiconductor die 116 and the front-side interconnect structure 103 of the semiconductor die 115. The bonding (eg, face-to-back bonding) includes an insulating bonding layer 509 having a bonding pad 517, which is bonded using a bonding pad similar to that described above with respect to bonding semiconductor die 111 to Figure 1A The semiconductor die 115 is directly bonded to the insulating bonding layer 519 having the bonding pad 521 by the dielectric-to-dielectric and metal-to-metal bonding processes described in the prior art. The bonding pad 517 can be electrically connected to the front-side interconnect structure 507 through the vias 502 and 504.

[0051] Figure 6 FIG. 6 is a flowchart of a process 600 for producing a packaged semiconductor device according to some embodiments of the present disclosure. The steps of the process are as follows: Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 4 In step 610, the first semiconductor die is bonded (eg, connected) to the second semiconductor die. Figure 1A and Figure 1BAs shown in , the top surface 143 of the semiconductor die 115 and the bottom surface 145 of the second semiconductor die 111 are bonded together. As shown, the semiconductor die 115 and the second semiconductor die 111 are bonded via surface-to-surface bonding, such as metal-to-metal bonding and dielectric-to-dielectric bonding. The surface-to-surface bonding is located between two metallization layers, which are the front side interconnect structure 103 of the semiconductor die 115 and the front side interconnect structure 107 of the second semiconductor die 111. In some embodiments, the width 106 of the semiconductor die 115 is longer than the width 108 of the second semiconductor die 111. The dielectric-to-dielectric bonding is located between the insulating bonding layer 109 and the insulating bonding layer 119. The metal-to-metal bonding is located between the bonding pad 117 of the insulating bonding layer 109 and the bonding pad 121 of the insulating bonding layer 119.

[0052] In step 620, an insulating layer is deposited over the first semiconductor die and adjacent to the second semiconductor die. Figure 1B As shown in , an insulating layer 114 is deposited over the first semiconductor die 115 and adjacent to the second semiconductor die 111 .

[0053] In step 630, one or more vias are formed in the insulating layer over the first semiconductor die. Figure 1B and Figure 1E As shown in , one or more vias 120 extend through insulating layer 114 and are formed in portion 137 above semiconductor die 115. Figure 1B As shown in FIG. 1 , the via 120 extends the height of the insulating layer 114. Figure 1B and Figure 1C 14) such that the first end 131 of the through-hole 120 is electrically coupled to the front-side interconnect structure 103 at the top surface 143 of the semiconductor die 115. Thus, the first end 131 is connected to the bonding pad 121 and is connected to the front-side interconnect structure 103 through the bonding pad 121. In addition, the second end 132 of the through-hole 120 is electrically coupled to the back-side interconnect structure 112 at the top surface 147 of the second semiconductor die 111. Thus, the second end 132 is connected to the bonding pad 175 and is therefore connected to the back-side interconnect structure 112 of the semiconductor die 111. In some embodiments, the portion 137 is immediately adjacent to the semiconductor die 111.

[0054] In step 640, an integrated voltage regulator die is bonded over the second semiconductor die and the insulating layer. Figure 1CAs shown in FIG. 1 , the integrated voltage regulator die 127 is bonded over the second semiconductor die 111 and the insulating layer 114. A second end 132 of the at least one through-via 120 opposite to the first end 131 is electrically connected to a power rail structure of the first backside interconnect structure 112 of the second semiconductor die 111. In some embodiments, the power rail structure has a connection line similar to the conductive connection line 301, but is about 2 to 3 times wider to reduce ohmic losses.

[0055] In the embodiments disclosed herein, the vias 120 are arranged outside the top semiconductor die including the top semiconductor device. Therefore, the processing steps, size and cost of the package can be reduced, and the form factor can also be improved.

[0056] Therefore, packaged semiconductors can be used for advanced network and server applications (e.g., AI (artificial intelligence)) that operate at high data rates, high bandwidth requirements, and low latency. In addition, packaged semiconductor devices can be provided with a high degree of chip packaging integration in a small form factor.

[0057] According to an embodiment, a semiconductor package includes a first semiconductor die and a second semiconductor die bonded over the first semiconductor die. The second semiconductor die includes a first backside interconnect structure having a first power rail structure. The semiconductor package also includes: an integrated voltage regulator die bonded over the second semiconductor die; and a first through-hole located on the first semiconductor die and electrically coupled to the first semiconductor die. The first through-hole is disposed outside the second semiconductor die and adjacent to the second semiconductor die, and the first through-hole electrically couples the first semiconductor die to the first power rail structure of the second semiconductor die through the integrated voltage regulator die.

[0058] In an embodiment, the semiconductor package further comprises: a second through-hole located on the first semiconductor die; and a third semiconductor die, the third semiconductor die comprising a second backside interconnect structure having a second power rail structure bonded above the first semiconductor die. The first through-hole and the second through-hole are disposed between the second semiconductor die and the third semiconductor die, and the second through-hole electrically couples the first semiconductor die to the second power rail structure of the third semiconductor die through the integrated voltage regulator die. In an embodiment, the semiconductor package further comprises: an insulating layer located on the first semiconductor die between the second semiconductor die and the third semiconductor die, such that the first through-hole and the second through-hole extend through the insulating layer. In an embodiment, the first semiconductor die further comprises: one or more connector bumps connected to the bottom side of the first semiconductor die; and one or more third through-holes, the one or more third through-holes extending to the first frontside interconnect structure of the first semiconductor die between the connector bumps and at the bottom of the first semiconductor die. In an embodiment, the semiconductor package further comprises: a fourth semiconductor die, the fourth semiconductor die comprising a second frontside interconnect structure and one or more second through-holes, such that the fourth semiconductor die is bonded above the first semiconductor die. The second front side interconnect structure is remote from the first semiconductor die, the first through-hole is arranged between the second semiconductor die and the fourth semiconductor die, and one or more second through-holes electrically connect the first front side interconnect structure of the first semiconductor die to the second front side interconnect structure of the fourth semiconductor die. In an embodiment, the integrated voltage regulator die is bonded over the second semiconductor die by dielectric-to-dielectric bonding and metal-to-metal bonding. In an embodiment, the integrated voltage regulator die provides electrical power to the second semiconductor die.

[0059] According to an embodiment, a semiconductor package includes: a first semiconductor die, the first semiconductor die including a first front-side interconnect structure. The semiconductor package includes: a second semiconductor die and a third semiconductor die, separated by a distance and bonded above the first semiconductor die. The second semiconductor die includes a first back-side interconnect structure having a first power rail structure, and the third semiconductor die includes a second back-side interconnect structure having a second power rail structure. The semiconductor package also includes: an integrated voltage regulator die bonded above the second semiconductor die and the third semiconductor die, so that the integrated voltage regulator die is electrically connected to the first power rail structure and the second power rail structure. The semiconductor package also includes: one or more through-vias, arranged on the first front-side interconnect structure of the first semiconductor die, and the one or more through-vias electrically couple the first power rail structure and the second power rail structure to the first front-side interconnect structure of the first semiconductor die.

[0060] In an embodiment, the semiconductor package further comprises: an insulating layer located on the first semiconductor die in the distance between the second semiconductor die and the third semiconductor die, so that one or more through holes extend through the insulating layer. In an embodiment, the semiconductor package further comprises: a first insulating bonding layer located above the second semiconductor die and the third semiconductor die; and a first bonding pad located in the first insulating bonding layer, so that one or more through holes extend from the first bonding pad to the first semiconductor die. In an embodiment, the integrated voltage regulator comprises a second front side interconnect structure and a second insulating bonding layer connected to the second front side interconnect structure. The second insulating bonding layer comprises a second bonding pad, the second insulating bonding layer is directly bonded to the first insulating bonding layer, and the second bonding pad is directly bonded to the first bonding pad. In an embodiment, one or more through holes are arranged in the distance between the second semiconductor die and the third semiconductor die. In an embodiment, one or more through holes are arranged on the opposite side of the second semiconductor die relative to the third semiconductor die. In an embodiment, the semiconductor package further includes: a plurality of connector bumps connected to a side of the first semiconductor die opposite the first front side interconnect structure; and a plurality of second vias extending between the first front side interconnect structure and the plurality of connector bumps.

[0061] According to an embodiment, a method of packaging includes: bonding a first semiconductor die to a second semiconductor die, such that the first semiconductor die includes a first front-side interconnect structure, and the second semiconductor die includes a first back-side interconnect structure having a first power rail structure. The method also includes: depositing an insulating layer over the first semiconductor die and adjacent to the second semiconductor die; forming a first through-hole in the insulating layer, such that a first end of the first through-hole is electrically coupled to the first front-side interconnect structure of the first semiconductor die. The method also includes: bonding an integrated voltage regulator die over the second semiconductor die and the insulating layer, such that a second end of the first through-hole opposite to the first end is electrically connected to the first power rail structure in the first back-side interconnect structure of the second semiconductor die through the integrated voltage regulator die.

[0062] In an embodiment, bonding the first semiconductor die to the second semiconductor die includes dielectric-to-dielectric bonding and metal-to-metal bonding. In an embodiment, the dielectric-to-dielectric bonding includes bonding a first insulating bonding layer between a second front-side interconnect structure of the second semiconductor die and a second insulating bonding layer on the first front-side interconnect structure of the first semiconductor die, and the metal-to-metal bonding includes electrically connecting a first bonding pad in the first insulating bonding layer to a second bonding pad in the second insulating bonding layer. In an embodiment, the method of packaging further includes: bonding the second front-side interconnect structure of the third semiconductor die to the first front-side interconnect structure of the first semiconductor die, so that the third semiconductor die includes a second back-side interconnect structure having a second power rail structure; bonding an integrated voltage regulator die above the third semiconductor die; and forming a second through-hole in the insulating layer. A first end of the second through-hole is electrically coupled to the first front-side interconnect structure of the first semiconductor die, and a second end of the second through-hole opposite to the first end is electrically connected to the second power rail structure in the second back-side interconnect structure of the third semiconductor die through the integrated voltage regulator die. In an embodiment, the method of packaging further comprises: bonding a back side of the third semiconductor die to a first front side interconnect structure of the first semiconductor die. The third semiconductor die comprises a second through hole electrically connecting the first front side interconnect structure of the first semiconductor die to a second front side interconnect structure of the third semiconductor die. In an embodiment, the method of packaging further comprises: forming a plurality of third through holes in the first semiconductor die; and coupling a plurality of connector bumps to a side of the first semiconductor die opposite to the first front side interconnect structure, such that the third through holes electrically connect the first front side interconnect structure to the plurality of connector bumps.

[0063] Some embodiments of the present application provide a semiconductor package, comprising: a first semiconductor die; a second semiconductor die bonded above the first semiconductor die, wherein the second semiconductor die includes a first backside interconnect structure having a first power rail structure; an integrated voltage regulator die bonded above the second semiconductor die; and a first through-hole located on the first semiconductor die and electrically coupled to the first semiconductor die, wherein the first through-hole is disposed outside the second semiconductor die and adjacent to the second semiconductor die, and wherein the first through-hole electrically couples the first semiconductor die to the first power rail structure of the second semiconductor die through the integrated voltage regulator die.

[0064] In some embodiments, the semiconductor package further comprises: a second through-hole located on the first semiconductor die; and a third semiconductor die, the third semiconductor die comprising a second backside interconnect structure having a second power rail structure bonded over the first semiconductor die, wherein the first through-hole and the second through-hole are disposed between the second semiconductor die and the third semiconductor die, and wherein the second through-hole electrically couples the first semiconductor die to the second power rail structure of the third semiconductor die through the integrated voltage regulator die. In some embodiments, the semiconductor package further comprises: an insulating layer located on the first semiconductor die between the second semiconductor die and the third semiconductor die, wherein the first through-hole and the second through-hole extend through the insulating layer. In some embodiments, the first semiconductor die further comprises: one or more connector bumps connected to the bottom side of the first semiconductor die; and one or more third through-holes extending to the first frontside interconnect structure of the first semiconductor die between the connector bumps and at the bottom of the first semiconductor die. In some embodiments, the semiconductor package further comprises: a fourth semiconductor die comprising a second front-side interconnect structure and one or more second vias, wherein the fourth semiconductor die is bonded over the first semiconductor die, wherein the second front-side interconnect structure is remote from the first semiconductor die, wherein the first via is arranged between the second semiconductor die and the fourth semiconductor die, and wherein the one or more second vias electrically connect the first front-side interconnect structure of the first semiconductor die to the second front-side interconnect structure of the fourth semiconductor die. In some embodiments, the integrated voltage regulator die is bonded over the second semiconductor die by dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, the integrated voltage regulator die is configured to provide electrical power to the second semiconductor die.

[0065] Some other embodiments of the present application provide a semiconductor package, including: a first semiconductor die, the first semiconductor die including a first front-side interconnect structure; a second semiconductor die and a third semiconductor die, separated by a distance and bonded above the first semiconductor die, wherein the second semiconductor die includes a first back-side interconnect structure having a first power rail structure, and the third semiconductor die includes a second back-side interconnect structure having a second power rail structure; an integrated voltage regulator die, bonded above the second semiconductor die and the third semiconductor die, the integrated voltage regulator die being electrically connected to the first power rail structure and the second power rail structure; and one or more through-holes, arranged on the first front-side interconnect structure of the first semiconductor die, and wherein the one or more through-holes electrically couple the first power rail structure and the second power rail structure to the first front-side interconnect structure of the first semiconductor die.

[0066] In some embodiments, the semiconductor package further comprises: an insulating layer located on the first semiconductor die in the distance between the second semiconductor die and the third semiconductor die, wherein the one or more through-holes extend through the insulating layer. In some embodiments, the semiconductor package further comprises: a first insulating bonding layer located above the second semiconductor die and the third semiconductor die; and a first bonding pad located in the first insulating bonding layer, wherein the one or more through-holes extend from the first bonding pad to the first semiconductor die. In some embodiments, the integrated voltage regulator comprises a second front-side interconnect structure and a second insulating bonding layer connected to the second front-side interconnect structure, wherein the second insulating bonding layer comprises a second bonding pad, wherein the second insulating bonding layer is directly bonded to the first insulating bonding layer, and wherein the second bonding pad is directly bonded to the first bonding pad. In some embodiments, the one or more through-holes are arranged in the distance between the second semiconductor die and the third semiconductor die. In some embodiments, the one or more through-holes are arranged on an opposite side of the second semiconductor die relative to the third semiconductor die. In some embodiments, the semiconductor package further includes: a plurality of connector bumps connected to a side of the first semiconductor die opposite the first front side interconnect structure; and a plurality of second vias extending between the first front side interconnect structure and the plurality of connector bumps.

[0067] Still other embodiments of the present application provide a packaging method, comprising: bonding a first semiconductor die to a second semiconductor die, wherein the first semiconductor die includes a first front-side interconnect structure, and wherein the second semiconductor die includes a first back-side interconnect structure having a first power rail structure; depositing an insulating layer above the first semiconductor die and adjacent to the second semiconductor die; forming a first through-hole in the insulating layer, wherein a first end of the first through-hole is electrically coupled to the first front-side interconnect structure of the first semiconductor die; and bonding an integrated voltage regulator die over the second semiconductor die and the insulating layer, wherein a second end of the first through-hole opposite to the first end is electrically connected to the first power rail structure in the first back-side interconnect structure of the second semiconductor die through the integrated voltage regulator die.

[0068] In some embodiments, bonding the first semiconductor die to the second semiconductor die includes a dielectric-to-dielectric bond and a metal-to-metal bond. In some embodiments, the dielectric-to-dielectric bond includes bonding a first insulating bond layer between a second front-side interconnect structure of the second semiconductor die and a second insulating bond layer on the first front-side interconnect structure of the first semiconductor die, and wherein the metal-to-metal bond includes electrically connecting a first bond pad in the first insulating bond layer to a second bond pad in the second insulating bond layer. In some embodiments, the method further includes: bonding a second front-side interconnect structure of a third semiconductor die to the first front-side interconnect structure of the first semiconductor die, wherein the third semiconductor die includes a second back-side interconnect structure having a second power rail structure; bonding the integrated voltage regulator die over the third semiconductor die; and forming a second via in the insulating layer, wherein a first end of the second via is electrically coupled to the first front-side interconnect structure of the first semiconductor die, and wherein a second end of the second via opposite to the first end is electrically connected to the second power rail structure in the second back-side interconnect structure of the third semiconductor die through the integrated voltage regulator die. In some embodiments, the method further comprises: bonding a back side of a third semiconductor die to the first front side interconnect structure of the first semiconductor die, wherein the third semiconductor die comprises a second through-hole electrically connecting the first front side interconnect structure of the first semiconductor die to a second front side interconnect structure of the third semiconductor die. In some embodiments, the method further comprises: forming a plurality of third through-holes in the first semiconductor die; and coupling a plurality of connector bumps to a side of the first semiconductor die opposite to the first front side interconnect structure, wherein the third through-holes electrically connect the first front side interconnect structure to the plurality of connector bumps.

[0069] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor package, comprising: a first semiconductor die; a second semiconductor die bonded over the first semiconductor die, wherein the second semiconductor die includes a first backside interconnect structure having a first power rail structure; an integrated voltage regulator die bonded over the second semiconductor die; and A first through-via is located on the first semiconductor die and electrically coupled to the first semiconductor die, wherein the first through-via is disposed outside of and adjacent to the second semiconductor die, and wherein the first through-via electrically couples the first semiconductor die to the first power rail structure of the second semiconductor die through the integrated voltage regulator die.

2. The semiconductor package according to claim 1, further comprising: a second through hole located on the first semiconductor die; as well as a third semiconductor die including a second backside interconnect structure having a second power rail structure bonded over the first semiconductor die, wherein the first through-via and the second through-via are disposed between the second semiconductor die and the third semiconductor die, and wherein the second through-via electrically couples the first semiconductor die to the second power rail structure of the third semiconductor die through the integrated voltage regulator die.

3. The semiconductor package according to claim 2, further comprising: An insulating layer is located on the first semiconductor die between the second semiconductor die and the third semiconductor die, wherein the first through-via and the second through-via extend through the insulating layer.

4. The semiconductor package according to claim 1, wherein: The first semiconductor die also includes: one or more connector bumps connected to a bottom side of the first semiconductor die; and One or more third vias extend between the connector bumps and at the bottom of the first semiconductor die to the first frontside interconnect structure of the first semiconductor die.

5. The semiconductor package according to claim 4, further comprising: A fourth semiconductor die comprises a second front side interconnect structure and one or more second through vias, wherein the fourth semiconductor die is bonded over the first semiconductor die, wherein the second front side interconnect structure is away from the first semiconductor die, wherein the first through via is arranged between the second semiconductor die and the fourth semiconductor die, and wherein the one or more second through vias electrically connect the first front side interconnect structure of the first semiconductor die to the second front side interconnect structure of the fourth semiconductor die.

6. The semiconductor package according to claim 1, wherein: The integrated voltage regulator die is bonded over the second semiconductor die via dielectric-to-dielectric bonding and metal-to-metal bonding.

7. The semiconductor package according to claim 6, wherein: The integrated voltage regulator die is configured to provide electrical power to the second semiconductor die.

8. A semiconductor package, comprising: a first semiconductor die comprising a first front-side interconnect structure; a second semiconductor die and a third semiconductor die, separated by a distance, bonded over the first semiconductor die, wherein the second semiconductor die includes a first backside interconnect structure having a first power rail structure, and the third semiconductor die includes a second backside interconnect structure having a second power rail structure; an integrated voltage regulator die bonded over the second semiconductor die and the third semiconductor die, the integrated voltage regulator die electrically connected to the first power rail structure and the second power rail structure; and One or more through vias are arranged on the first front-side interconnect structure of the first semiconductor die, and wherein the one or more through vias electrically couple the first power rail structure and the second power rail structure to the first front-side interconnect structure of the first semiconductor die.

9. The semiconductor package according to claim 8, further comprising: An insulating layer is located on the first semiconductor die in the distance between the second semiconductor die and the third semiconductor die, wherein the one or more vias extend through the insulating layer.

10. A packaging method, comprising: bonding a first semiconductor die to a second semiconductor die, wherein the first semiconductor die includes a first frontside interconnect structure, and wherein the second semiconductor die includes a first backside interconnect structure having a first power rail structure; depositing an insulating layer over the first semiconductor die and proximate to the second semiconductor die; forming a first via in the insulating layer, wherein a first end of the first via is electrically coupled to the first front-side interconnect structure of the first semiconductor die; and An integrated voltage regulator die is bonded over the second semiconductor die and the insulating layer, wherein a second end of the first via opposite the first end is electrically connected to the first power rail structure in the first backside interconnect structure of the second semiconductor die through the integrated voltage regulator die.

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