Semiconductor device and communication system

Abstract

The invention provides a semiconductor device and a communication system. A semiconductor device (10) includes: an interface (1) configured to receive write data (WDT) transmitted via serial communication from outside; a register (21) configured to store setting data (DIMSETn) corresponding to the plurality of channels; and an update controller (22) configured to update the setting data based on the write data, where the write data includes: first data (PAFLG), where each bit indicates whether there is a data update in a channel corresponding to the each bit among the plurality of channels; and second data (DutyDT) for a data update in each of the plurality of channels set by the first data to have a data update.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a communication system. Background Art

[0002] Semiconductor devices equipped with a serial communication function are used in various applications.

[0003] Patent Document 1 discloses an example of a circuit technique related to serial communication.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2017-224946 Summary of the invention

[0007] In this article, the semiconductor device may have a function of performing pulse width modulation (PWM) dimming, for example, as a device for driving light-emitting elements of multiple channels. When performing such PWM dimming, a duty cycle may be set for each channel via serial communication. In this case, it is desirable to reduce the amount of data sent to the semiconductor device via serial communication as much as possible.

[0008] The present disclosure is directed to providing a semiconductor device that can reduce the amount of communication data in serial communication when setting data of a plurality of channels.

[0009] For example, a semiconductor device according to an embodiment of the present disclosure includes: an interface, which is configured to receive write data sent from the outside via serial communication; a register, which is configured to store setting data corresponding to multiple channels; and an update controller, which is configured to update the setting data based on the write data, wherein the write data includes: first data, in which each bit indicates whether there is a data update in a channel corresponding to each bit in the multiple channels; and second data, which is used for data update in each channel of the multiple channels set by the first data to have data update. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure.

[0011] Figure 1 is a schematic diagram showing a configuration of a communication system according to an exemplary embodiment of the present disclosure.

[0012] Figure 2 is a schematic diagram illustrating a configuration of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0013] Figure 3: is a schematic diagram showing the data structure of the reception data RX.

[0014] Figure 4 is a schematic diagram showing a configuration example regarding update of dimming settings in a semiconductor device.

[0015] Figure 5 is a diagram showing a register map for storing dimming setting data in low resolution mode.

[0016] Figure 6 is a register map associated with the settings for updating dimming settings in low resolution mode.

[0017] Figure 7 is a configuration diagram showing an example of updating dimming setting data in the low-resolution mode and the absolute mode.

[0018] Figure 8 is a register map diagram showing the storage of dimming setting data in registers in high resolution mode.

[0019] Fig. 9 is a register map diagram related to the settings for updating the dimming settings in high-resolution mode.

[0020] Fig.10 is a configuration diagram showing an example of updating dimming setting data in the high-resolution mode and the relative mode.

[0021] Fig.11 is a diagram showing an example of a correspondence relationship between a duty ratio range and a step size for changing the duty ratio when gradual dimming is performed. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other cases, well-known methods, processes, systems, and components are not described in detail in order to avoid unnecessarily obscuring aspects of the various embodiments.

[0023] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0024] <1. Communication system>

[0025] Figure 1is a schematic diagram showing a configuration of a communication system 501 according to an exemplary embodiment of the present disclosure. The communication system 501 includes a microcontroller unit (MCU) 20, a controller area network (CAN) transceiver 30, a CAN transceiver 40, and a plurality of semiconductor devices 10. The communication system 501 is used in a vehicle, for example.

[0026] Communication using a Universal Asynchronous Receiver / Transmitter (UART) is performed between the MCU 20 and the CAN transceiver 30. UART is a protocol for exchanging serial data between two devices. In UART, bidirectional communication using two lines is performed between a transmitting side and a receiving side.

[0027] Communication is performed between the CAN transceiver 30 and the CAN transceiver 40 via the CAN bus 35. CAN is a serial communication protocol standardized by international standards such as ISO11898.

[0028] The CAN transceiver 30 has a TXD (transmit data input) terminal 30A and a RXD (receive data output) terminal 30B. The CAN transceiver 30 outputs data input to the TXD terminal 30A to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 30B.

[0029] The CAN transceiver 40 has a RXD terminal 40A and a TXD terminal 40B. The CAN transceiver 40 outputs data input to the TXD terminal 40B to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 40A.

[0030] Each semiconductor device 10 is an IC (Integrated Circuit) in which a circuit having a predetermined function is integrated, and is configured as, for example, an LED (Light Emitting Diode) driver IC. All of the plurality of semiconductor devices 10 may be LED driver ICs, or some of the semiconductor devices 10 may be LED driver ICs. Details of the semiconductor device 10 as an LED driver IC will be described later.

[0031] The semiconductor device 10 has an RX (receive data input) terminal 10A and a TX (transmit data output) terminal 10B. The RX terminals 10A of the plurality of semiconductor devices 10 are commonly connected to the RXD terminal 40A. The TX terminals 10B of the plurality of semiconductor devices 10 are commonly connected to the TXD terminal 40B.

[0032] The reception data RX output from the RXD terminal 40A is input to the RX terminal 10A of each of the plurality of semiconductor devices 10. The device address of one of the plurality of semiconductor devices 10 is specified in the reception data RX. In addition, the transmission data TX output from the TX terminal 10B of each of the plurality of semiconductor devices 10 is input to the TXD terminal 40B.

[0033] <2. Configuration of semiconductor device>

[0034] Figure 2 is a schematic diagram showing a configuration of a semiconductor device 10 according to an exemplary embodiment of the present disclosure. Figure 2 The semiconductor device 10 shown is configured as an LED driver IC configured to drive the LED 6. The LED is an example of a light emitting element. That is, the LED driver is an example of a light emitting element driving device.

[0035] The LED 6 is provided to include a plurality of channels. Hereinafter, as an example, it is assumed that the channels of the LED 6 are 24 channels. The channels of the LED 6 may be a plurality of channels other than 24 channels. The LED 6 of each channel is configured by connecting LED elements in series. However, the LED 6 of each channel may be configured by connecting LED elements in series and in parallel, or may be configured with a single LED element.

[0036] The semiconductor device 10 includes in an integrated manner a UART interface 1, a controller 2, a PWM generator 3, and a current driver 4. Furthermore, the semiconductor device 10 includes an RX terminal 10A, a TX terminal 10B, and a cathode terminal 10C as external terminals for establishing electrical connection with the outside.

[0037] As described above, reception data RX input from the outside to the RX terminal 10A is input to the UART interface 1. Also, as described above, transmission data TX output from the UART interface 1 is output from the TX terminal 10B to the outside.

[0038] The controller 2 includes a register 21. When the received data RX input to the UART interface 1 indicates writing, the controller 2 updates the data of the register 21 based on the write data included in the received data RX. On the other hand, when the received data RX input to the UART interface 1 indicates reading, the controller 2 reads the data from the register 21. The details of the RX data will be described later.

[0039] A PWM generator 3 is provided corresponding to each channel of the LED 6. Therefore, in the case where the LED 6 includes 24 channels, a PWM generator 3 is provided for each of the channels CH01 to CH 24. The channel CHn corresponds to the nth channel. The register 21 stores the dimming setting data of each channel. The PWM generator 3 of each channel generates a duty cycle PWM signal based on the dimming setting data of each channel. That is, the dimming setting data of each channel represents the duty cycle of the PWM dimming of each channel.

[0040] The PWM signal is a pulse signal with a high level and a low level. In one cycle (PWM cycle), the period when the PWM signal is at a first level (e.g., a high level) is the on period, and the period when the PWM signal is at a second level (e.g., a low level) is the off period.

[0041] The current driver 4 is provided corresponding to each channel of the LED 6. Therefore, in the case where the LED 6 includes 24 channels, the current driver 4 is provided for each of the channels CH01 to CH24. The current driver 4 of each channel is connected to the cathode of the LED 6 of each channel via each cathode terminal 10C. The anode of the LED 6 of each channel is commonly connected to the application terminal of the power supply voltage Vcc.

[0042] Each PWM signal generated by the PWM generator 3 of each channel is used for on / off control of the current driver 4 of each channel. Specifically, the current driver 4 is turned on during the on period of the PWM signal, and the current driver 4 is turned off during the off period of the PWM signal. When the current driver 4 is in the on state, a constant current flows through the LED 6, and the LED 6 emits light. When the current driver 4 is in the off state, no current flows through the LED 6, and the LED 6 is turned off. The on-duty ratio of PWM dimming is the ratio of the on period in one cycle. When the on-duty ratio becomes higher, the LED 6 becomes brighter.

[0043] With this configuration, the dimming setting data of each channel can be updated based on the data RX received through the UART communication, and the PWM dimming of the LED 6 of each channel can be performed based on each duty ratio set for each channel. As described below, in the present embodiment, the dimming setting data of only some channels (a single channel or a plurality of channels) among the 24 channels can also be updated with a single communication of the received data RX.

[0044] <3. Structure of received data>

[0045] Figure 3 : is a schematic diagram showing the data structure of received data RX. In UART, communication is performed in a data unit called a frame. A frame is composed of bit data from a start bit to a stop bit. The start bit is at a low level, and the stop bit is at a high level. A predetermined number of bit data is arranged between the start bit and the stop bit. In the following, as an example, the predetermined number of bits is 8 bits. A frame is composed of 10 bits of bit data.

[0046] like Figure 3As shown, the received data RX includes, from the beginning, a synchronization frame SYNC, a device frame Device, a data amount frame NumofData, an address frame Address, data frames Data1 to DataN (N is an integer of 1 or greater), a cyclic redundancy check (CRC) lower frame CRC 16L and a CRC upper frame CRC 16H.

[0047] The synchronization frame SYNC is bit data for setting a baud rate in the semiconductor device 10 .

[0048] The device frame Device includes a device address, a read / write bit, etc. The device address is bit data indicating the address of the target device (semiconductor device 10). The read / write bit is bit data indicating reading or writing.

[0049] The data amount frame NumofData is bit data indicating the number of frames (ie, N) of the data frames Data1 to DataN.

[0050] The address frame Address is bit data indicating an address for accessing the register 21 .

[0051] The data frames Data1 to DataN are bit data indicating the bit for updating the data in the register 21. When the read / write bit in the device frame Device indicates reading, the data frames Data1 to DataN are not included in the reception data RX.

[0052] The CRC lower frame CRC 16L and the CRC upper frame CRC 16H are bit data indicating an error detection code added to the data frames Data1 to DataN.

[0053] <4. Update of dimming settings>

[0054] Next, a method of updating the dimming setting data in the register 21 will be described. Figure 4 is a schematic diagram showing a configuration example regarding update of dimming settings in the semiconductor device 10 .

[0055] like Figure 4 As shown, the UART interface 1 includes a buffer 11. When the received data RX is input to the UART interface 1, the received data 11A is stored in the buffer 11. The received data 11A includes address data Address and write data WDT. The write data WDT is obtained by using the data frame Data1 to DataN ( Figure 3 ) to send data.

[0056] The controller 2 includes a register 21 and an update controller 22. The update controller 22 updates the dimming setting data DIMSET01 to DIMSET24 in the register 21 based on the received data 11A. The update controller 22 includes a relative calculator 221. The relative calculator 221 is used for relative update of the dimming setting data, which will be described below.

[0057] The dimming setting data DIMSET01 to DIMSET24 are stored in the register 21. The dimming setting data DIMSETn is the dimming setting of the channel CHn, and indicates the duty ratio of the channel CHn. The duty ratio is a value between 0 and 100%.

[0058] The resolution setting data HAMODE and the relative mode setting data RELMODE are stored in the register 21 .

[0059] The resolution setting data HAMODE is 1-bit data and indicates the setting of the high-resolution mode or the low-resolution mode. The low-resolution mode is a mode in which the dimming setting data DIMSETn is updated to a first predetermined number of bits (e.g., 8 bits) and the duty cycle can be adjusted with the resolution of the first predetermined number of bits. In the case where the first predetermined number of bits is, for example, 8 bits, the duty cycle can be adjusted in steps of about 0.4%. The high-resolution mode is a mode in which the dimming setting data DIMSETn is updated to a second predetermined number of bits (e.g., 12 bits) higher than the first predetermined number of bits and the duty cycle can be adjusted with the resolution of the second predetermined number of bits. In the case where the second predetermined number of bits is, for example, 12 bits, the duty cycle can be adjusted in steps of about 0.02%.

[0060] The relative mode setting data RELMODE is 1-bit data and indicates the setting of the relative mode or the absolute mode. The relative mode is a mode in which the dimming setting data DIMSETn is updated by a relative change from a current value. The absolute mode is a mode in which the dimming setting data DIMSETn is updated with an absolute value.

[0061] <<In the case of low resolution mode>>

[0062] Hereinafter, a method of updating dimming setting data when the resolution mode is set to the low resolution mode (HAMODE=0) will be described. Herein, as an example, it is assumed that the first predetermined bit number is 8 bits.

[0063] Figure 5 2 is a schematic diagram (register map) showing the storage of dimming setting data DIMSETn in the register 21 in the low-resolution mode. Figure 5 2 shows the correspondence between the addresses in the register 21 and the dimming setting data DIMSETn stored at these addresses. Figure 5As shown, in the register 21, the number of bits of data that can be stored for one address is a first predetermined number of bits (herein, 8 bits). Figure 5 The specific addresses shown in the following figures are examples only.

[0064] DIMSET01 to DIMSET24 each having 8 bits are stored in consecutive addresses from address 0x4B to address 0x62, respectively.

[0065] Figure 6 2 is a register map for updating the dimming settings in register 21. Figure 6 As shown, the channel setting flag PAFLG is stored for consecutive addresses from address 0x7B to address 0x7D. The channel setting flag PAFLG is 24-bit data, and each bit of the channel setting flag PAFLG indicates whether the dimming setting data is updated for each of the 24 channels.

[0066] The lower 8 bits of the channel setting flag PAFLG are stored in address 0x7B, the middle 8 bits of the channel setting flag PAFLG are stored in address 0x7C, and the upper 8 bits of the channel setting flag PAFLG are stored in address 0x7D. The lower 8 bits of the channel setting flag PAFLG correspond to channels CH01 to CH08 in order from low to high. The middle 8 bits of the channel setting flag PAFLG correspond to channels CH09 to CH16 in order from low to high. The upper 8 bits of the channel setting flag PAFLG correspond to channels CH17 to CH24 in order from low to high.

[0067] In addition, if Figure 6 As shown, the duty cycle setting data DutyDT01 to DutyDTm are stored in a continuous order starting from address 0x7E. In this article, m can take a value from 01 to 24. The duty cycle setting data DutyDT indicates the duty cycle setting value of the channel set to have an update by the channel setting flag PAFLG, and has 8 bits for one channel. In this article, m is the number of channels set to have an update by the channel setting flag PAFLG. The duty cycle setting data DutyDT is data for updating the dimming setting data DIMSETn using an absolute value.

[0068] When the dimming setting data DIMSETn is updated, by using the received data RX( Figure 3 ) performs the following transmission. Address 0x7B is specified in the address frame Address. In addition, the lower 8 bits, middle 8 bits, and upper 8 bits of the channel setting flag PAFLG and the duty setting data DutyDT of the channel set to have an update by the channel setting flag PAFLG are sequentially transmitted by using data frames Data1 to DataN.

[0069] Figure 7 is a configuration diagram showing an example of updating the dimming setting data DIMSETn in the case of the low-resolution mode and the absolute mode (HAMODE=0 and RELMODE=0) (corresponding to Figure 4 ).

[0070] exist Figure 7 In the example of , the received data RX is input to the UART interface 1, and the received data 11A is stored in the buffer 11. The received data 11A includes the address 0x7B and the write data WDT. The write data WDT includes the lower 8 bits (PAFLG[7:0]), the middle 8 bits (PAFLG[15:8]) and the upper 8 bits (PAFLG[23:16]) of the channel setting flag PAFLG, and the duty cycle setting data DutyDT01 to 05. In this article, as an example, PAFLG[7:0]=0x03(00000011), PAFLG[15:8]=0x00, and PAFLG[23:16]=0xE0(11100000). Since PAFLG=1 indicates that there is an update, and PAFLG=0 indicates that there is no update, the channels set to have updates are channels CH 01, CH 02, CH 22, CH 23, and CH 24. Therefore, the duty ratio setting data DutyDT is set to DutyDT01 to DutyDT05.

[0071] Based on the channel setting flag PAFLG and the duty cycle setting data DutyDT in the write data WDT stored in the buffer 11, the update controller 22 updates the channel setting flag PAFLG and the duty cycle setting data DutyDT at consecutive addresses starting from the address 0x7B in the register 21 ( Figure 6 ). Then, based on the data updated in this manner, the update controller 22 updates the dimming setting data DIMSETn corresponding to the channel set to have an update in the register 21. Figure 7 In the example of , each of DIMSET01 , DIMSET02 , DIMSET22 , DIMSET23 , and DIMSET24 corresponding to the channels CH01 , CH02 , CH22 , CH23 , and CH24 set to have update is updated with an absolute value by each of the duty setting data DutyDT01 to DutyDT05 .

[0072] In this way, in the present embodiment, the dimming setting data of only some of the 24 channels can be updated. In the case of a method of transmitting the dimming setting data of all 24 channels by receiving data RX so as to update the dimming setting data of only some of the channels (the method according to the first comparative example), the required transmission data is 24ch×1 byte+6 bytes (SYNC, Device, NumofData, Address, CRC16L, CRC16H)=30 bytes.

[0073] In addition, in order to update the dimming setting data of only some channels, it is assumed that a method of transmitting the reception data RX in the form of a group of consecutive channels starting from the channel CH01 set to have an update and a group of consecutive channels starting from the channel CH24 set to have an update is adopted (the method according to the second comparative example). In this case, Figure 7 In the example of , since the group of consecutive channels set to have an update is divided into a group of channels CH 01 and CH 02 and a group of channels CH 22, CH 23, and CH 24, the receive data RX must be sent twice. The required transmit data is 17 bytes, which is the sum of 2ch×1 byte+6 bytes and 3ch×1 byte+6 bytes.

[0074] In contrast, in this embodiment, Figure 7 In the example of , the transmission of the reception data RX is completed at one time, and the required transmission data is 3 bytes (PAFLG)+1 byte×5 (DutyDT01 to DutyDT05)=8 bytes, so that the communication data amount can be reduced.

[0075] In the present embodiment, dimming setting data can be set for any part of the 24 channels, and the degree of freedom of setting is higher than that in the method according to the second comparative example.

[0076] <<In the case of high resolution mode>>

[0077] Hereinafter, a method of updating dimming setting data when the resolution mode is set to the high resolution mode (HAMODE=1) will be described. Herein, as an example, it is assumed that the second predetermined bit number is 12 bits.

[0078] Figure 8 is a register map diagram showing the storage of dimming setting data DIMSETn in the register 21 in the high resolution mode.

[0079] The upper 8 bits of DIMSET01 are stored in address 0x4B. The lower 4 bits of DIMSET01 are stored in the upper portion of address 0x4C, and the lower 4 bits of DIMSET02 are stored in the lower portion of address 0x4C. The upper 8 bits of DIMSET02 are stored in address 0x4D. Similar to this storage mode of dimming setting data in addresses 0x4B to 0x4D, DIMSET03 to DIMSET24 are also stored in address 0x4E and subsequent addresses. In this way, 12 bits of DIMSET01 to DIMSET24 can be stored in each of consecutive addresses from 0x4B to 0x6E.

[0080] Fig. 9 2 is a register map related to the settings for updating the dimming settings in register 21 in the case of high resolution mode. Fig. 9 As shown, the channel setting flag PAFLG is stored for consecutive addresses 0x7B to 0x7D. The channel setting flag PAFLG is as described above.

[0081] In addition, polarity data SG01 to SGm, gain data GAIN01 to GAINm, and relative value data DUTY01 to DUTYm are stored in a continuous order starting from address 0x7E. Herein, m can take a value from 01 to 24. Polarity data SG, gain data GAIN, and relative value data DUTY of one address correspond to one channel.

[0082] The polarity data SG is 1-bit data and indicates a decrease or increase from the value of the current dimming setting data DIMSETn. For example, SG=0 indicates a decrease, and SG=1 indicates an increase.

[0083] The gain data GAIN is 2-bit data and indicates a gain value. For example, GAIN=0 indicates a 1-time gain, GAIN=1 indicates a 2-time gain, GAIN=2 indicates an 8-time gain, and GAIN=3 indicates a 16-time gain.

[0084] The relative value data DUTY is 5-bit data and indicates a relative change value. The relative value data DUTY can take a value from 0 to 31.

[0085] By using the polarity data SG, the gain data GAIN, and the relative value data DUTY, the dimming setting data DIMSETn of the channel CHn is updated according to the following equation (1).

[0086] DIMSETn = DIMSETn ± DUTY × GAIN (1)

[0087] DIMSETn on the right side indicates a current value, and DIMSETn on the left side indicates an updated value. In addition, ± indicates + (increase) or - (decrease) according to the polarity data SG.

[0088] For example, when SG=0, GAIN=1, and DUTY=5, DIMSETn=DIMSETn-5×2.

[0089] When the mode is set to high resolution mode and relative mode (RELMODE=1), when updating the dimming setting data DIMSETn, by using the received data RX ( Figure 3 ) performs the following transmission. Address 0x7B is specified in the address frame Address. In addition, the lower 8 bits, middle 8 bits and upper 8 bits of the channel setting flag PAFLG are sequentially transmitted by using data frames Data1 to DataN, and the polarity data SG, gain data GAIN and relative value data DUTY of the channel set by the channel setting flag PAFLG are set to have an updated channel.

[0090] Fig.10 is a configuration diagram showing an example of updating the dimming setting data DIMSETn in the case of the high resolution mode and the relative mode (HAMODE=1 and RELMODE=1) (corresponding to Figure 4 ).

[0091] exist Fig.10 In the example of , the received data RX is input to the UART interface 1, and the received data 11A is stored in the buffer 11. The received data 11A includes the address 0x7B and the write data WDT. The write data WDT includes the lower 8 bits (PAFLG[7:0]), the middle 8 bits (PAFLG[15:8]) and the upper 8 bits (PAFLG[23:16]) of the channel setting flag PAFLG, the polarity data SG, the gain data GAIN and the relative value data DUTY. In this article, as an example, PAFLG[7:0]=0x03(00000011), PAFLG[15:8]=0x00 and PAFLG[23:16]=0xE0(11100000). Therefore, the channels set to have updates are channels CH 01, CH 02, CH 22, CH 23 and CH 24. Therefore, the polarity data SG, the gain data GAIN, and the relative value data DUTY are set to SG01 to SG05, GAIN01 to GAIN05, and DUTY01 to DUTY05, respectively.

[0092] Based on the channel setting flag PAFLG, polarity data SG, gain data GAIN, and relative value data DUTY in the write data WDT stored in the buffer 11, the update controller 22 updates the channel setting flag PAFLG, polarity data SG, gain data GAIN, and relative value data DUTY at consecutive addresses starting from the address 0x7B in the register 21 ( Fig. 9 ). Then, based on the data updated in this manner, the update controller 22 updates the dimming setting data DIMSETn corresponding to the channel set to have an update in the register 21. Fig.10 In the example of , each of DIMSET01 , DIMSET02 , DIMSET 22 , DIMSET 23 , and DIMSET 24 corresponding to the channels CH01 , CH02 , CH 22 , CH 23 , and CH 24 set to have update is updated by the following calculation of the relative calculator 221 .

[0093] The relative calculator 221 performs calculation using the above equation (1). Fig.10 In the example, for channel CH01, the dimming setting data DIMSET01 is updated in the following way:

[0094] DIMSET01=DIMSET01±DUTY01×GAIN01

[0095] Herein, ± indicates + (increase) or - (decrease) according to the polarity data SG01. Fig.10 , the update of the dimming setting data of channels other than the channel CH01 is not shown.

[0096] As described above, in this embodiment, the high-resolution (eg, 12-bit) dimming setting data DIMSETn of some of the 24 channels may be relatively updated. Fig.11 is a schematic diagram showing an example of the correspondence between the duty cycle range and the step size of changing the duty cycle when performing gradual dimming. In this way, as the duty cycle becomes higher, the step size becomes larger. In gradual dimming, the duty cycle increases from the current value to the target value in a specified step size. By expressing the duty cycle with high resolution, the minimum step size can be made smaller. In such gradual dimming, since the required step size is small, dimming can be performed by updating the dimming setting data in relative mode.

[0097] When Fig.10When updating the dimming setting data for 5 channels as in the example, in the absolute mode, at least 3 bytes (PAFLG) + 5 ch × 12 bits = 10.5 bytes of data need to be sent. However, in the relative mode, 3 bytes + 5 ch × 8 bits = 8 bytes of data are sent, enabling a reduction in the communication data volume.

[0098] In addition, as Figure 1 shown, when the RX terminals 10A of multiple semiconductor devices 10 are commonly connected to the same RXD terminal 40A of the CAN transceiver 40, assume that the multiple semiconductor devices 10 are LED driver ICs. In this case, when updating the dimming setting data in each of the multiple semiconductor devices 10, it is necessary to sequentially send the received data RX to each of the multiple semiconductor devices 10 via serial communication, and it is effective to reduce the communication data volume in a single transmission in both the low-resolution mode and the high-resolution mode.

[0099] <<Check of NumofData>>

[0100] When sending the received data RX, the update controller 22 checks the data volume frame NumofData as follows. Specifically, for the channel setting flag PAFLG included in the write data WDT stored in the buffer 11, it is checked whether the following equation holds.

[0101] The number of bytes of PAFLG + the number of channels whose PAFLG is set to have an update = the number of frames indicated by the data volume frame NumofData (2)

[0102] If the equation (2) holds, the process continues with the control to update the dimming setting data DIMSETn.

[0103] For example, in the Figure 7 and Fig.10 example, since the number of bytes in PAFLG = 3 and the number of channels in PAFLG that are set to have an update = 5, it is checked whether the number of frames indicated by the data volume frame NumofData = 8.

[0104] <5. Others>

[0105] In addition to the above embodiments, various technical features disclosed in the present disclosure can be modified in various ways without departing from the gist of the technical features of the present disclosure. That is to say, the above embodiments should be considered illustrative in all aspects rather than restrictive, and the technical scope of the present disclosure should not be limited to the above embodiments, and it should be understood that the technical scope of the present disclosure includes all changes that fall within the meaning and scope equivalent to the claims.

[0106] For example, serial communication is not limited to UART communication, but may also be I 2 C communication, etc.

[0107] <6. Notes>

[0108] As described above, a semiconductor device (10) according to one aspect of the present disclosure has a configuration (first configuration) including:

[0109] An interface (1) configured to receive write data (WDT) sent from the outside via serial communication;

[0110] a register (21) configured to store setting data (DIMSETn) corresponding to a plurality of channels; and

[0111] An update controller (22) is configured to update the setting data based on the write data, wherein the write data includes:

[0112] first data (PAFLG), wherein each bit indicates whether data is updated in a channel corresponding to each bit among the plurality of channels; and

[0113] Second data (DutyDT), the second data being used for data update in each of the plurality of channels set as having data update by the first data.

[0114] According to the above configuration, the amount of transmission data including write data required to update the setting data of multiple channels can be reduced. Therefore, the problem of reducing the communication data amount of serial communication when setting the data of multiple channels can be solved.

[0115] In addition, the semiconductor device of the first configuration may have a configuration (second configuration) in which the number of bits of data that can be stored for an address in the register is a first predetermined number of bits (e.g., 8 bits), and the first data and the second data are sent with the first predetermined number of bits used as each of the data units.

[0116] Furthermore, the semiconductor device of the second configuration may have a configuration (third configuration) in which the setting data (DIMSETn) of one channel is the first predetermined bit number, and the setting data of one channel is updated with an absolute value by the second data in each of the data units.

[0117] In addition, the semiconductor device of the second or third configuration may have a configuration (fourth configuration) in which, in a high-resolution mode, the setting data of one channel is a second predetermined number of bits (for example, 12 bits) larger than the first predetermined number of bits, the second data in each of the data units includes polarity data (SG) indicating a decrease or increase corresponding to one channel, gain data (GAIN) indicating a gain value, and relative value data (DUTY) indicating a relative change value, the update controller includes a relative calculator (221), the relative calculator is configured to calculate a calculation result by subtracting or adding a value obtained by multiplying the relative change value by the gain value from a current value of the setting data according to the polarity data, and the update controller updates the setting data based on the calculation result.

[0118] Furthermore, the semiconductor device of the fourth configuration may have a configuration (fifth configuration) in which the gain value can be set to 1 based on the gain data.

[0119] In addition, the semiconductor device of the fourth or fifth configuration may have a configuration (sixth configuration) in which, in the high-resolution mode, in the register, the upper bits of the setting data of the first channel are stored in the first address, the lower bits of the setting data of the first channel and the lower bits of the setting data of the second channel are stored in the second address obtained by incrementing the first address, and the upper bits of the setting data of the second channel are stored in the third address obtained by incrementing the second address.

[0120] Furthermore, the semiconductor device of any one of the first to sixth configurations may have a configuration (seventh configuration) in which the setting data indicates a duty ratio of PWM dimming.

[0121] In addition, the semiconductor device of the fourth configuration can have a configuration (eighth configuration) in which the setting data indicates the duty cycle of PWM dimming, and as the duty cycle of the PWM dimming becomes higher, the step size of changing the duty cycle becomes larger, and gradual dimming can be performed by increasing the duty cycle according to the step size.

[0122] The semiconductor device of the second configuration may have a configuration (ninth configuration) in which data frames each including the first predetermined number of bits of data and a data amount indicating the number of the data frames are sent through the serial communication, and the update controller checks whether the sum of the number of the data units of the first data and the number of channels set by the first data to have the data update matches the data amount.

[0123] Furthermore, the semiconductor device of the ninth configuration may have a configuration (tenth configuration) in which the serial communication is UART communication.

[0124] Furthermore, a communication system (501) according to another aspect of the present disclosure has a configuration (eleventh configuration) including:

[0125] At least one semiconductor device (10) of any one of the first to tenth configurations; and

[0126] A transmitter (40) is configured to transmit the write data.

[0127] In addition, the communication system of the eleventh configuration may have a configuration (twelfth configuration) in which the at least one semiconductor device (10) includes a plurality of semiconductor devices (10), and input terminals (10A) respectively provided at the plurality of semiconductor devices (10) and configured to receive the write data are commonly connected to the same output terminal (40A) provided at the transmitter (40).

[0128] Industrial Applicability

[0129] The present disclosure may be used in, for example, a vehicle communication system.

[0130] Although certain embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present disclosure. In fact, the embodiments described herein may be implemented in various other forms. In addition, various omissions, substitutions, and changes may be made to the forms of the embodiments described herein without departing from the spirit of the present disclosure. The attached claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the present disclosure.

[0131] Description of Reference Numerals

[0132] 1: UART interface

[0133] 2: Controller

[0134] 3: PWM Generator

[0135] 4: Current driver

[0136] 6: LED

[0137] 10: Semiconductor devices

[0138] 10A: RX terminal

[0139] 10B: TX terminal

[0140] 10C: Cathode terminal

[0141] 11: Buffer

[0142] 11A: Receive data

[0143] 21: Register

[0144] 22: Update Controller

[0145] 30, 40: CAN transceiver

[0146] 30A: TXD terminal

[0147] 30B: RXD terminal

[0148] 35: CAN bus

[0149] 40A: RXD terminal

[0150] 40B: TXD terminal

[0151] 221: Relative Calculator

[0152] 501: Communication system.

Claims

1. A semiconductor device comprising: an interface configured to receive write data sent from the outside via serial communication; a register configured to store setting data corresponding to a plurality of channels; as well as an update controller configured to update the setting data based on the write data, The written data includes: first data, wherein each bit indicates whether there is a data update in a channel corresponding to each bit among the plurality of channels; as well as second data, the second data being used for data update in each of the plurality of channels set by the first data to have data update.

2. The semiconductor device according to claim 1, wherein the number of bits of data that can be stored for one address in the register is a first predetermined number of bits, and wherein the first data and the second data are transmitted with the first predetermined bit number used as each of the data units.

3. The semiconductor device according to claim 2, wherein the setting data of one channel is the first predetermined number of bits, and The setting data of one channel is updated with an absolute value by the second data in each of the data units.

4. The semiconductor device according to claim 2 , wherein in a high resolution mode, the setting data for one channel is a second predetermined number of bits larger than the first predetermined number of bits, wherein the second data in each of the data units includes polarity data indicating a decrease or increase corresponding to one channel, gain data indicating a gain value, and relative value data indicating a relative change value, wherein the update controller includes a relative calculator configured to calculate a calculation result by subtracting or adding a value obtained by multiplying the relative change value by the gain value from a current value of the setting data according to the polarity data, and wherein the update controller updates the setting data based on the calculation result. 5 . The semiconductor device according to claim 4 , wherein the gain value can be set to 1 based on the gain data.

6. The semiconductor device according to claim 4, wherein in the high-resolution mode, in the register, an upper bit of the setting data of the first channel is stored in a first address, a lower bit of the setting data of the first channel and a lower bit of the setting data of the second channel are stored in a second address obtained by incrementing the first address, and an upper bit of the setting data of the second channel is stored in a third address obtained by incrementing the second address. 7 . The semiconductor device according to claim 1 , wherein the setting data indicates a duty ratio of PWM dimming.

8. The semiconductor device according to claim 4, wherein the setting data indicates a duty ratio of PWM dimming, and As the duty cycle of the PWM dimming becomes higher, the step size of changing the duty cycle becomes larger, and gradual dimming that increases the duty cycle according to the step size can be performed.

9. The semiconductor device according to claim 2, wherein data frames each including the first predetermined number of bits of data and a data amount indicating the number of the data frames can be transmitted through the serial communication, and The update controller checks whether the sum of the number of the data units of the first data and the number of channels set by the first data to have the data update matches the data amount. 10 . The semiconductor device according to claim 9 , wherein the serial communication is UART communication.

11. A communication system comprising: The semiconductor device according to any one of claims 1 to 10; as well as A transmitter is configured to transmit the write data. 12 . The communication system according to claim 11 , wherein input terminals respectively provided at the plurality of semiconductor devices and configured to receive the write data are commonly connected to a same output terminal provided at the transmitter.

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