Display panel and manufacturing method thereof

Abstract

A display panel and a method for manufacturing the same are disclosed. The display panel includes: a base layer including a plurality of light emitting regions and sensing regions spaced apart from each other in a plan view; a plurality of light emitting elements disposed on the base layer, respectively, and overlapping the plurality of light emitting regions; and a light sensing element disposed on the base layer and overlapping the sensing region. The plurality of light emitting regions includes a first light emitting region emitting light having a first wavelength, and at least a portion of the sensing region is surrounded by the first light emitting region in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0087161 filed in the Korean Intellectual Property Office on July 5, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a display panel and a method of manufacturing the same, and more particularly, to a display panel for sensing a fingerprint and a method of manufacturing the display panel. Background Art

[0004] The display device provides various functions that enable the user to interact with the display device. For example, the display device displays an image to provide information to the user, or can sense the user's input. Recent display devices include a function for sensing information provided by the user (e.g., biometric information). User information can be recognized by a capacitive sensing technology for sensing a change in capacitance between electrodes, a light sensing technology for sensing incident light using an optical sensor, or an ultrasonic sensing technology for sensing vibration using a piezoelectric element. Summary of the invention

[0005] Embodiments provide a display panel including a sensor for sensing a fingerprint and a method for manufacturing the display panel.

[0006] However, the embodiments are not limited to those set forth herein. The above and other embodiments will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to an embodiment, a display panel may include: a base layer including a plurality of light emitting regions and a sensing region spaced apart from each other in a plan view; a plurality of light emitting elements respectively disposed on the base layer and overlapping the plurality of light emitting regions; and a light sensing element disposed on the base layer and overlapping the sensing region. The plurality of light emitting regions include a first light emitting region emitting light having a first wavelength, and at least a portion of the sensing region may be surrounded by the first light emitting region in a plan view.

[0008] In a first direction, the sensing region may be disposed between portions of the first light emitting region, and in a second direction crossing the first direction, the sensing region may be adjacent to at least one side of the first light emitting region.

[0009] The sensing region may have a rectangular shape including sides extending in a first direction and sides extending in a second direction crossing the first direction. The first light emitting region may surround at least three sides of the sensing region.

[0010] The plurality of light emitting regions may further include: a second light emitting region emitting light having a second wavelength different from the first wavelength; and a third light emitting region emitting light having a third wavelength different from the first wavelength and the second wavelength.

[0011] A sum of an area of ​​the first light emitting region and an area of ​​the sensing region may be substantially the same as an area of ​​the second light emitting region.

[0012] A length of the first light emitting region in one direction may be greater than a length of the second light emitting region in one direction.

[0013] The first light emitting area may include a plurality of first light emitting areas, the second light emitting area may include a plurality of second light emitting areas, and the third light emitting area may include a plurality of third light emitting areas. The plurality of first light emitting areas may be arranged side by side in one direction, the plurality of second light emitting areas may be arranged side by side in one direction, and the plurality of third light emitting areas may be arranged side by side in one direction.

[0014] An area of ​​the sensing region may be smaller than an area of ​​the first light emitting region.

[0015] The sensing area may include a first side and a second side extending in a first direction, and a third side and a fourth side extending in a second direction crossing the first direction. The first light emitting area may surround the first side, the third side, and the fourth side, and may not surround at least a portion of the second side.

[0016] The light having the first wavelength may be light having a green wavelength range.

[0017] The light having the first wavelength may be light having a red wavelength range.

[0018] The display panel may further include a pixel defining layer disposed on the base layer and having a plurality of openings, wherein the plurality of openings may define a plurality of light emitting regions and a plurality of sensing regions, respectively.

[0019] The pixel defining layer may include: a barrier wall portion disposed on the base layer; and a liquid repellent portion disposed on the barrier wall portion and including a liquid repellent organic material.

[0020] The pixel defining layer may include: a first pixel defining portion disposed between the plurality of light emitting regions; and a second pixel defining portion disposed between the first light emitting region and the sensing region. A height of the second pixel defining portion may be smaller than a height of the first pixel defining portion.

[0021] The plurality of light-emitting elements may include a first light-emitting element overlapping the first light-emitting region. The first light-emitting element may include: a first light-emitting electrode disposed on the base layer; a second light-emitting electrode disposed above the first light-emitting electrode; and a first functional layer disposed between the first light-emitting electrode and the second light-emitting electrode. The light-sensing element may include: a first light-sensing electrode disposed on the base layer; a second light-sensing electrode disposed above the first light-sensing electrode; and a second functional layer disposed between the first light-sensing electrode and the second light-sensing electrode. The first functional layer and the second functional layer may include the same material.

[0022] According to an embodiment, a display panel may include: a base layer including a first light emitting area and a sensing area spaced apart from each other in a plan view; a pixel defining layer disposed on the base layer and having a first opening defining the first light emitting area and a second opening defining the sensing area; a first light emitting element disposed on the base layer and disposed in the first opening; and a light sensing element disposed on the base layer and disposed in the second opening. At least a portion of the second opening may be surrounded by the first opening in a plan view.

[0023] According to an embodiment, a method for manufacturing a display panel may include: preparing a preliminary display panel including a base layer and a pixel defining layer disposed on the base layer; and forming a first light emitting element and a light sensing element by providing an organic material on the preliminary display panel. The pixel defining layer has a first opening and a second opening. The first opening may define a first light emitting area in which the first light emitting element is disposed, and the second opening may define a sensing area in which the light sensing element is disposed. At least a portion of the second opening may be surrounded by the first opening in a plan view.

[0024] The first light emitting element may include a first functional layer, and the light sensing element may include a second functional layer. The first functional layer and the second functional layer may be formed by the same process.

[0025] Forming each of the first functional layer and the second functional layer may include providing an organic material in the second opening.

[0026] The pixel defining layer may include: a first pixel defining portion adjacent to the first opening and spaced apart from the second opening; and a second pixel defining portion disposed between the first opening and the second opening. A height of the second pixel defining portion may be smaller than a height of the first pixel defining portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0028] Figure 1 is a schematic perspective view of a display device according to an embodiment.

[0029] Figure 2 is a schematic block diagram of a display device according to an embodiment.

[0030] Figure 3 is a schematic block diagram of a display layer and a display driver according to an embodiment.

[0031] Figure 4 A schematic diagram showing an equivalent circuit of a pixel and a schematic diagram showing an equivalent circuit of a sensor according to an embodiment are shown.

[0032] Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment.

[0033] Figure 6 is a schematic plan view showing a part of a display area of ​​a display panel according to an embodiment.

[0034] Fig. 7A and Figure 7B is an enlarged schematic plan view showing a portion of a display area of ​​a display panel according to an embodiment.

[0035] Figure 8 and Fig. 9 is a schematic cross-sectional view of a portion of a display area of ​​a display panel.

[0036] Fig.10 is a schematic cross-sectional view of a portion of a display area of ​​a display panel.

[0037] Fig.11 and Fig.12 is an enlarged schematic plan view showing a portion of a display area of ​​a display panel according to an embodiment.

[0038] Fig.13 is a flowchart illustrating a method for manufacturing a display panel according to an embodiment.

[0039] Fig.14A , Fig. 14B , Fig. 14C , Fig.14D , Fig.14E and Fig.14F 2 is a schematic cross-sectional view showing steps of a method for manufacturing a display panel according to an embodiment.

[0040] Fig.15A , Fig. 15B and Fig. 15C 2 is a schematic cross-sectional view showing steps of a method for manufacturing a display panel according to an embodiment. DETAILED DESCRIPTION

[0041] In the following description, for the purpose of illustration, many specific details are elaborated to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is obvious that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments are not necessarily exclusive and do not limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0042] Unless otherwise specified, the embodiments shown will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments, etc. (hereinafter, individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged without departing from the scope of the present invention.

[0043] The use of cross hatching and / or shading in the drawings is generally to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiment can be implemented differently, the specific processing sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0044] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or coupled to another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may represent a physical connection, an electrical connection and / or a fluid connection in the presence or absence of an intervening element. In addition, the axis of the first direction DR1, the axis of the second direction DR2 and the axis of the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as, X-axis, Y-axis and Z-axis), and may be interpreted in a broader sense. For example, the axis of the first direction DR1, the axis of the second direction DR2 and the axis of the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms "first", "second", etc. can be used in this article to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element.

[0046] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like may be used herein for descriptive purposes, and thereby to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would then be oriented to be "above" the other elements or features. Thus, the term "below" may encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus the spatially relative descriptors used herein should be interpreted accordingly.

[0047] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Terms, as defined in commonly used dictionaries, will be interpreted as having the same meaning as the contextual meaning in the relevant technical field, and will not be interpreted as having an ideal or overly formal meaning unless explicitly defined as having such a meaning in this application.

[0048] Figure 1 is a schematic perspective view of a display device according to an embodiment.

[0049] refer to Figure 1 , the display device 1000 may be activated based on the electrical signal. For example, the display device 1000 may be a mobile phone, a foldable mobile phone, a notebook computer, a television, a tablet computer, a car navigation unit, a game console, or a wearable device, but the embodiment is not limited thereto. Figure 1 , the display device 1000 is shown as a mobile phone.

[0050] The display device 1000 may include an active area 1000A and a peripheral area 1000NA. The display device 1000 may display an image through the active area 1000A. The active area 1000A may include a plane defined by a first direction DR1 and a second direction DR2. The peripheral area 1000NA may surround the periphery of the active area 1000A.

[0051] The thickness direction of the display device 1000 may be parallel to a third direction DR3 crossing the first direction DR1 and the second direction DR2. Therefore, the front surface (or upper surface) and the rear surface (or lower surface) of the member (or element) constituting the display device 1000 may be defined based on the third direction DR3.

[0052] Figure 2 is a schematic block diagram of a display device according to an embodiment.

[0053] refer to Figure 2 , the display device 1000 may include a display panel DP, a display driver 100C, a sensor driver 200C, and a main driver 1000C. The display panel DP may include a display layer 100 and a sensor layer 200 disposed on the display layer 100. In another example, the sensor layer 200 may be omitted.

[0054] The display layer 100 may be a component that basically displays an image. The display layer 100 may be an emissive display layer. For example, the display layer 100 may be an organic light-emitting display layer, an inorganic light-emitting display layer, an organic-inorganic light-emitting display layer, a quantum dot display layer, a micron light-emitting diode (LED) display layer, or a nano-LED display layer. For example, the display layer 100 may include a sensor that senses light reflected by (or reacts to) the user's fingerprint 2000fp.

[0055] The sensor layer 200 may be provided on the display layer 100. The sensor layer 200 may sense an external input 2000 applied from the outside. The external input 2000 may include all input methods that can provide (or cause) a change in capacitance. For example, the sensor layer 200 may sense not only an input by a passive type input method (e.g., a user's body), but also an input by an active type input method that provides a driving signal.

[0056] The main driver 1000C may control the overall operation of the display device 1000. For example, the main driver 1000C may control the operation of the display driver 100C and the sensor driver 200C. The main driver 1000C may include at least one microprocessor and may also include a graphics controller. The main driver 1000C may be referred to as an application processor, a central processing unit, or a main processor.

[0057] The display driver 100C may drive the display layer 100. The display driver 100C may receive image data RGB and a control signal D-CS from the main driver 1000C. The control signal D-CS may include various signals. For example, the control signal D-CS may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, a data enable signal, etc. Based on the control signal D-CS, the display driver 100C may generate a vertical synchronization signal and a horizontal synchronization signal for controlling the timing of providing a signal to the display layer 100.

[0058] The sensor driver 200C may drive the sensor layer 200. The sensor driver 200C may receive a control signal I-CS from the main driver 1000C. The control signal I-CS may include a mode determination signal for determining a driving mode of the sensor driver 200C, and a clock signal.

[0059] The sensor driver 200C may calculate the input coordinate information based on the signal received from the sensor layer 200, and may provide the coordinate signal I-SS having the coordinate information to the main driver 1000C. The main driver 1000C may perform an operation corresponding to the user input based on the coordinate signal I-SS. For example, the main driver 1000C may operate the display driver 100C so that a new application image may be displayed on the display layer 100.

[0060] Figure 3 is a schematic block diagram of a display layer and a display driver according to an embodiment.

[0061] refer to Figure 2 and Figure 3 , the display driver 100C may include a driving controller 100C1 , a data driver 100C2 , a scan driver 100C3 , an emission driver 100C4 , a voltage generator 100C5 , and a sensor controller 100C6 .

[0062] The display layer 100 may include an active area 1000A (refer to Figure 1 ) corresponding to the active area DA (or display area) and the peripheral area 1000NA (reference Figure 1 ) corresponds to a peripheral area NDA (or non-display area).

[0063] The display layer 100 may include pixels PX disposed in the active area DA and sensors FX disposed in the active area DA. The display layer 100 may also include initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 to RLh.

[0064] Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and emission control lines EML1 to EMLn may extend in the second direction DR2. Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and emission control lines EML1 to EMLn may be arranged in the first direction DR1 so as to be spaced apart from each other. Data lines DL1 to DLm and readout lines RL1 to RLh may extend in the first direction DR1, and may be arranged in the second direction DR2 so as to be spaced apart from each other.

[0065] The pixels PX may be electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. For example, each of the pixels PX may be electrically connected to four scan lines. However, the embodiment is not limited thereto, and the number of scan lines connected to each pixel PX may vary.

[0066] The sensor FX may be electrically connected to the readout lines RL1 to RLh. One sensor (e.g., a single sensor) FX may be electrically connected to one scan line (e.g., a single scan line) (e.g., one write scan line (e.g., a single write scan line) among the write scan lines SWL1 to SWLn). However, the embodiment is not limited thereto. The number of scan lines connected to each sensor FX may vary.

[0067] In an embodiment, the number of readout lines RL1 to RLh may correspond to half the number of data lines DL1 to DLm. However, the embodiment is not limited thereto. In another example, the number of readout lines RL1 to RLh may correspond to 1 / 4 or 1 / 8 of the number of data lines DL1 to DLm, or may be equal to the number of data lines DL1 to DLm.

[0068] The driving controller 100C1 may receive the image data RGB and the control signal D-CS. The driving controller 100C1 may generate the image data signal DATA by converting the data format of the image data RGB according to the specification of the interface with the data driver 100C2. The driving controller 100C1 may output the first control signal SCS, the second control signal ECS, the third control signal DCS, and the fourth control signal RCS.

[0069] The data driver 100C2 may receive the third control signal DCS and the image data signal DATA from the driving controller 100C1. The data driver 100C2 may convert the image data signal DATA into a data signal and may output the data signal to the data lines DL1 to DLm to be described below. The data signal may be an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0070] The scan driver 100C3 may receive a first control signal SCS from the drive controller 100C1. The scan driver 100C3 may output scan signals to the scan lines in response to the first control signal SCS. For example, in response to the first control signal SCS, the scan driver 100C3 may output initialization scan signals to the initialization scan lines SIL1 to SILn, and may output compensation scan signals to the compensation scan lines SCL1 to SCLn. For example, in response to the first control signal SCS, the scan driver 100C3 may output write scan signals to the write scan lines SWL1 to SWLn, and may output black scan signals to the black scan lines SBL1 to SBLn.

[0071] The emission driver 100C4 may receive the second control signal ECS from the drive controller 100C1. The emission driver 100C4 may output the emission control signal to the emission control lines EML1 to EMLn in response to the second control signal ECS. In another example, the scan driver 100C3 may be connected to the emission control lines EML1 to EMLn. Therefore, the emission driver 100C4 may be omitted, and the scan driver 100C3 may output the emission control signal to the emission control lines EML1 to EMLn.

[0072] The scan driver 100C3 and the emission driver 100C4 may be disposed in the peripheral area NDA of the display layer 100. However, the embodiment is not limited thereto. For example, at least a portion of the scan driver 100C3 and at least a portion of the emission driver 100C4 may be disposed in the active area DA.

[0073] The voltage generator 100C5 may generate voltages required for the operation of the display layer 100. In an embodiment, the voltage generator 100C5 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, and a reset voltage Vrst.

[0074] The sensor controller 100C6 may receive the fourth control signal RCS from the driving controller 100C1 .

[0075] The sensor controller 100C6 may receive detection signals from the sensing lines RL1 to RLh in response to the fourth control signal RCS. The sensor controller 100C6 may process the detection signals received from the sensing lines RL1 to RLh and may provide the processed detection signals S_FS to the driving controller 100C1.

[0076] Figure 4 A schematic diagram showing an equivalent circuit of a pixel and a schematic diagram showing an equivalent circuit of a sensor according to an embodiment are shown.

[0077] exist Figure 4 , a pixel PX (reference Figure 3 ) is an equivalent circuit of a pixel PXij among the pixels PX. The pixels PX may have the same circuit structure. Therefore, the description of the circuit structure of the pixel PXij may be applied to the remaining pixels PX, and for ease of description, the detailed description of the remaining pixels PX will be omitted. For example, in Figure 4 In the Figure 3An equivalent circuit of one sensor (e.g., a single sensor) FXdj among the sensors FX is shown. The sensors FX have the same circuit structure. Therefore, the description of the circuit structure of the sensor FXdj can be applied to the remaining sensors FX, and for the sake of convenience of description, the detailed description of the remaining sensors FX will be omitted.

[0078] refer to Figure 3 and Figure 4 , the pixel PXij can be connected to the i-th data line DLi among the data lines DL1 to DLm, the j-th initialization scan line SILj among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj among the compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj among the write scan lines SWL1 to SWLn, the j-th black scan line SBLj among the black scan lines SBL1 to SBLn, and the j-th emission control line EMLj among the emission control lines EML1 to EMLn.

[0079] The pixel PXij may include a light emitting element ED and a pixel driving circuit PDC. The light emitting element ED may be a light emitting diode. In an embodiment, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but the embodiment is not limited thereto.

[0080] The pixel driving circuit PDC may include first, second, third, fourth and fifth transistors T1, T2, T3, T4 and T5, first and second emission control transistors ET1 and ET2, and a capacitor Cst.

[0081] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be low temperature polycrystalline silicon (LTPS) transistors.

[0082] For example, the display device 1000 (reference Figure 1) may include a semiconductor layer formed of polysilicon having high reliability, and thus a display device having high resolution may be implemented. For example, an oxide semiconductor may have high carrier mobility and low leakage current, and thus the voltage drop may not be large even if the operation time is long. For example, even during low-frequency operation, the color of the image does not change greatly according to the voltage drop, and thus low-frequency operation is possible. Since oxide semiconductors have the advantage of low leakage current as described above, at least one of the third transistor T3 and the fourth transistor T4 connected to the third electrode (or gate electrode) of the first transistor T1 may be formed as an oxide semiconductor to reduce power consumption while preventing leakage current that may flow to the gate electrode.

[0083] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be P-type transistors, and the others may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0084] The configuration of the pixel driving circuit PDC according to the embodiment is not limited to Figure 4 The embodiment shown. Figure 4 The pixel driving circuit PDC shown is an example, and various changes and modifications may be made to the configuration of the pixel driving circuit PDC. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 and the first emission control transistor ET1 and the second emission control transistor ET2 may all be P-type transistors or N-type transistors.

[0085] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can transmit the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal SBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi can transmit the i-th data signal Di to the pixel PXij. The i-th data signal Di can have the same value as that input to the display device 1000 (reference Figure 2 ) image data RGB (reference Figure 2 ) corresponds to the voltage level.

[0086] The first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. For example, the first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT1 and VINT2 to the pixels PXij, respectively.

[0087] The first transistor T1 may be connected between a first driving voltage line VL1 receiving a first driving voltage ELVDD and the light emitting element ED. The first transistor T1 may include a first electrode connected to the first driving voltage line VL1 via a first emission control transistor ET1, a second electrode connected to the light emitting element ED via a second emission control transistor ET2, and a third electrode (e.g., a gate electrode) connected to an end portion (e.g., a first node N1) of the capacitor Cst. The first transistor T1 may receive an i-th data signal Di transmitted through an i-th data line DLi according to a switching operation of the second transistor T2, and may provide a driving current Id to the light emitting element ED.

[0088] The second transistor T2 may be connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 may be turned on based on the j-th write scan signal SWj transmitted through the j-th write scan line SWLj, and may transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0089] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 may be turned on based on the j-th compensation scan signal SCj transmitted through the j-th compensation scan line SCLj, and may diode-connect the first transistor T1 by connecting the third electrode and the second electrode of the first transistor T1.

[0090] The fourth transistor T4 may be connected between the first initialization voltage line VL3 through which the first initialization voltage VINT1 is applied and the first node N1. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line VL3 (through which the first initialization voltage VINT1 is transmitted), a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line SILj. The fourth transistor T4 may be turned on based on the jth initialization scan signal SIj transmitted through the jth initialization scan line SILj. The turned-on fourth transistor T4 may initialize the potential of the third electrode of the first transistor T1 (e.g., the potential of the first node N1) by transmitting the first initialization voltage VINT1 to the first node N1.

[0091] The first emission control transistor ET1 may include a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0092] The second emission control transistor ET2 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the light emitting element ED, and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0093] The first emission control transistor ET1 and the second emission control transistor ET2 may be turned on simultaneously based on the jth emission control signal EMj transmitted through the jth emission control line EMLj. The first driving voltage ELVDD may be applied to the diode-connected first transistor T1 through the turned-on first emission control transistor ET1, and may be compensated (or adjusted) by passing through the diode-connected first transistor T1, and the compensated (or adjusted) voltage may be transmitted to the light emitting element ED.

[0094] The fifth transistor T5 may include a first electrode connected to the second initialization voltage line VL4 (through which the second initialization voltage VINT2 is transmitted), a second electrode connected to the second electrode of the second emission control transistor ET2 (e.g., the second node N2), and a third electrode (e.g., a gate electrode) connected to the j-th black scan line SBLj. The voltage level of the second initialization voltage VINT2 may be lower than or equal to the voltage level of the first initialization voltage VINT1.

[0095] An end portion of the capacitor Cst may be connected to the third electrode of the first transistor T1 as described above, and an opposite end portion of the capacitor Cst may be connected to the first driving voltage line VL1. A cathode of the light emitting element ED may be connected to a second driving voltage line VL2 transmitting a second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD.

[0096] The sensor FXdj may be connected to a d-th readout line RLd among the readout lines RL1 to RLh, a j-th write scan line SWLj (referred to as an output control line), and a reset control line RCL.

[0097] The sensor FXdj may include a light sensing element OPD (referred to as a sensing element) and a sensor driving circuit O_SD.

[0098] The light sensing element OPD may be a photodiode. In an embodiment, the light sensing element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. The first electrode AE-S (reference Figure 5 ) can be connected to the first sensing node SN1, and the second electrode CE-S (reference Figure 5 ) can be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS. Figure 4 An example is shown in which the sensor FXdj may include a light sensing element (eg, a single light sensing element) OPD, but the embodiment is not limited thereto. For example, the sensor FXdj may include z light sensing elements connected in parallel. "z" may be an integer of 2 or greater.

[0099] The sensor driving circuit O_SD may include three transistors ST1, ST2, and ST3. The three transistors ST1, ST2, and ST3 may include a reset transistor ST1, an amplifier transistor ST2, and an output transistor ST3. At least one of the reset transistor ST1, the amplifier transistor ST2, and the output transistor ST3 may be an oxide semiconductor transistor. In an embodiment, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifier transistor ST2 and the output transistor ST3 may be low temperature polysilicon (LTPS) transistors. However, the embodiment is not limited thereto, and at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifier transistor ST2 may be a low temperature polysilicon (LTPS) transistor.

[0100] In addition, some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and the rest may be N-type transistors. In an embodiment, the amplifying transistor ST2 and the output transistor ST3 may be P-type transistors, and the reset transistor ST1 may be an N-type transistor. However, the embodiment is not limited thereto, and the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may all be N-type transistors, or may all be P-type transistors.

[0101] The circuit configuration of the sensor driving circuit O_SD according to the embodiment is not limited to Figure 4 The circuit configuration shown. Figure 4 The illustrated sensor driving circuit O_SD is an example, and various changes and modifications may be made to the configuration of the sensor driving circuit O_SD.

[0102] The reset transistor ST1 may include a first electrode connected to the third initialization voltage line VL5 and receiving a reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode receiving a reset control signal RST. The reset transistor ST1 may reset the potential of the first sensing node SN1 to the reset voltage Vrst in response to the reset control signal RST. The reset control signal RST may be a signal provided by a reset control line RCL.

[0103] The amplifier transistor ST2 may include a first electrode receiving a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplifier transistor ST2 may be turned on based on the potential of the first sensing node SN1, and the sensing drive voltage SLVD may be applied to the second sensing node SN2. In an embodiment, the sensing drive voltage SLVD may be one of the first drive voltage ELVDD and the first initialization voltage VINT1 and the second initialization voltage VINT2. In the case where the sensing drive voltage SLVD is the first drive voltage ELVDD, the first electrode of the amplifier transistor ST2 may be electrically connected to the first drive voltage line VL1. In the case where the sensing drive voltage SLVD is the first initialization voltage VINT1, the first electrode of the amplifier transistor ST2 may be electrically connected to the first initialization voltage line VL3, and in the case where the sensing drive voltage SLVD is the second initialization voltage VINT2, the first electrode of the amplifier transistor ST2 may be electrically connected to the second initialization voltage line VL4.

[0104] The output transistor ST3 may include a first electrode connected to the second sensing node SN2, a second electrode connected to the dth readout line RLd, and a third electrode receiving an output control signal. In response to the output control signal, the output transistor ST3 may transmit the detection signal FSd to the dth readout line RLd. The output control signal may be a jth write scan signal SWj (referred to as a jth output control signal) provided through the jth write scan line SWLj. For example, the output transistor ST3 may receive the jth write scan signal SWj provided from the jth write scan line SWLj as the output control signal.

[0105] The reset period may be defined as an activation period (e.g., a high level period) of the reset control line RCL. In the case where a reset control signal RST having a high level is provided through the reset control line RCL, the reset transistor ST1 may be turned on. In another example, in the case where the reset transistor ST1 is implemented as a PMOS transistor, a reset control signal RST having a low level may be provided to the reset control line RCL during the reset period. The first sensing node SN1 may be reset to a potential corresponding to the reset voltage Vrst during the reset period. In an embodiment, the reset voltage Vrst may have a voltage level lower than the second drive voltage ELVSS.

[0106] The light sensing element OPD of the sensor FXdj may be exposed to light during the light emitting period of the light emitting element ED. The voltage of the first sensing node SN1 may be maintained at the reset voltage Vrst during the reset period, and as the light sensing element OPD is exposed to light, the voltage of the first sensing node SN1 may gradually change to the second driving voltage ELVSS. The amplifying transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the amount of charge of the first sensing node SN1 (which is input to the third electrode).

[0107] The j-th write scan signal SWj having a low level may be provided to the output transistor ST3 through the j-th write scan line SWLj in the output period. When the output transistor ST3 is turned on in response to the j-th write scan signal SWj having a low level, the detection signal FSd corresponding to the current flowing through the amplifying transistor ST2 may be output to the d-th readout line RLd.

[0108] Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment.

[0109] refer to Figure 5 , the display panel DP may include a display layer 100 , a sensor layer 200 , and an anti-reflection layer 300 .

[0110] The display layer 100 may include a base layer BL, and a circuit layer DP-CL, a device layer DP-ED, and an encapsulation layer TFE sequentially disposed on the base layer BL.

[0111] At least one inorganic layer may be formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed as a multilayer. The plurality of inorganic layers may constitute barrier layers BR1 and BR2 and / or a buffer layer BFL to be described below. The barrier layers BR1 and BR2 and the buffer layer BFL may be selectively provided.

[0112] The barrier layers BR1 and BR2 can prevent foreign matter from penetrating (or permeating) from the outside. The barrier layers BR1 and BR2 may include a silicon oxide layer and a silicon nitride layer. A plurality of silicon oxide layers and a plurality of silicon nitride layers may be provided. The silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

[0113] The barrier layers BR1 and BR2 may include a first barrier layer BR1 and a second barrier layer BR2. The first back metal layer BMC1 may be disposed between the first barrier layer BR1 and the second barrier layer BR2. In another example, the first back metal layer BMC1 may be omitted.

[0114] The buffer layer BFL may be disposed on the barrier layers BR1 and BR2. The buffer layer BFL may improve the coupling force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

[0115] The first semiconductor pattern may be disposed on the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern may include low temperature polycrystalline silicon.

[0116] Figure 5 Only a portion of the first semiconductor pattern disposed on the buffer layer BFL is shown, and another portion of the first semiconductor pattern may be additionally disposed in other regions. The first semiconductor pattern may be arranged throughout a plurality of pixels according to a specific rule (or a specific pattern). Depending on whether the first semiconductor pattern is doped, the first semiconductor pattern may have different electrical characteristics. The first semiconductor pattern may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a doped region doped with a P-type dopant, and the N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region, or may be a region that is doped more lightly than the first region.

[0117] The conductivity of the first region may be higher than that of the second region, and the first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to an active region (or channel) of a transistor. For example, a portion of the first semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and another portion may be a connecting electrode or a connecting signal line.

[0118] The first electrode S1, the active region A1, and the second electrode D1 of the first transistor T1 may be formed of a first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 may extend in opposite directions from the active region A1.

[0119] exist Figure 5 , a portion of the connection signal line CSL formed by the first semiconductor pattern is shown. For example, the connection signal line CSL may be connected to the fifth transistor T5 (refer to Figure 4 )'s second electrode and the second emission control transistor ET2.

[0120] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with a plurality of pixels in common and may cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may be a single silicon oxide layer. Not only the first insulating layer 10 but also the insulating layers of the circuit layer DP-CL to be described below may be inorganic layers and / or organic layers and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but the embodiment is not limited thereto.

[0121] The third electrode G1 of the first transistor T1 may be disposed on the first insulating layer 10. The third electrode G1 may be a part of the metal pattern. The third electrode G1 of the first transistor T1 may overlap with the active region A1 of the first transistor T1. In the process of doping the first semiconductor pattern, the third electrode G1 of the first transistor T1 may be used as a mask. The third electrode G1 may include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO) or indium zinc oxide (IZO), but the embodiment is not limited thereto.

[0122] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the third electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0123] The upper electrode UE and the second back metal layer BMC2 may be disposed on the second insulating layer 20. The upper electrode UE may overlap the third electrode G1. The upper electrode UE may be a portion of the metal pattern. A portion of the third electrode G1 and the upper electrode UE overlapping the portion of the third electrode G1 may form a capacitor Cst (reference Figure 4 ). In an embodiment, the second insulating layer 20 may be replaced with an insulating pattern. For example, the upper electrode UE may be disposed on the insulating pattern. The upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0124] The second back metal layer BMC2 may be disposed under the oxide thin film transistor (eg, the third transistor T3 ) to overlap the third transistor T3 . A constant voltage or signal may be applied to the second back metal layer BMC2 .

[0125] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE and the second back metal layer BMC2. The third insulating layer 30 may have a single layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0126] The second semiconductor pattern may be disposed on the third insulating layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions that are distinguished according to whether the metal oxide is reduced (or deoxidized). The region where the metal oxide is reduced (hereinafter referred to as the reduction region) may have a higher conductivity than the region where the metal oxide is not reduced (hereinafter referred to as the non-reduction region). The reduction region may be substantially used as the source / drain of a transistor or a signal line. The non-reduction region may be substantially used as the active region (or semiconductor region or channel) of a transistor. For example, a portion of the second semiconductor pattern may be the active region of a transistor, another portion may be the source / drain region of a transistor, and another portion may be a signal transmission region.

[0127] The first electrode S3, the active region A3 and the second electrode D3 of the third transistor T3 may be formed by a second semiconductor pattern. The first electrode S3 and the second electrode D3 may include a metal reduced (or deoxidized) from a metal oxide semiconductor. The first electrode S3 and the second electrode D3 may extend from the active region A3 in opposite directions in a cross section.

[0128] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may overlap the plurality of pixels in common and may cover the second semiconductor pattern. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0129] The third electrode G3 of the third transistor T3 may be disposed on the fourth insulating layer 40. The third electrode G3 may be a portion of a metal pattern. The third electrode G3 of the third transistor T3 may overlap with the active region A3 of the third transistor T3. The third electrode G3 may be used as a mask in the process of restoring the second semiconductor pattern. In an embodiment, the fourth insulating layer 40 may be replaced with an insulating pattern.

[0130] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the third electrode G3. The fifth insulating layer 50 may be an inorganic layer.

[0131] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 penetrating (or passing through) the first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50.

[0132] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The organic layer may include, but is not limited to, a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a pentanol-based polymer or a blend thereof.

[0133] The second connection electrode CNE20 may be disposed on the sixth insulating layer 60. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a second contact hole CH2 penetrating (or passing through) the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and may cover the second connection electrode CNE20. The seventh insulating layer 70 may be an organic layer.

[0134] The third connection electrode CNE30 may be disposed on the seventh insulating layer 70. The third connection electrode CNE30 may be connected to the second connection electrode CNE20 through a third contact hole CH3 penetrating (or passing through) the seventh insulating layer 70. The eighth insulating layer 80 may be disposed on the seventh insulating layer 70 and may cover the third connection electrode CNE30. The eighth insulating layer 80 may be an organic layer.

[0135] The circuit layer DP-CL may further include a sensor driving circuit O_SD (refer to Figure 4 ). For ease of description, the reset transistor ST1 of the sensor driving circuit O_SD is shown. The first electrode STS1, the active area STA1, and the second electrode STD1 of the reset transistor ST1 may be formed by a second semiconductor pattern. The first electrode STS1 and the second electrode STD1 may include a metal reduced (or deoxidized) from a metal oxide semiconductor. The fourth insulating layer 40 may cover the first electrode STS1, the active area STA1, and the second electrode STD1 of the reset transistor ST1. The third electrode STG1 of the reset transistor ST1 may be disposed on the fourth insulating layer 40. In an embodiment, the third electrode STG1 may be a part of the metal pattern. The third electrode STG1 of the reset transistor ST1 may overlap with the active area STA1 of the reset transistor ST1.

[0136] In an embodiment, the reset transistor ST1 and the third transistor T3 may be arranged on the same layer. For example, the first electrode STS1, the active area STA1 and the second electrode STD1 of the reset transistor ST1 and the first electrode S3, the active area A3 and the second electrode D3 of the third transistor T3 may be formed by the same process. The third electrode STG1 of the reset transistor ST1 may be formed simultaneously with the third electrode G3 of the third transistor T3 by the same process. For example, the first electrode and the second electrode of the amplifying transistor ST2 and the output transistor ST3 of the sensor driving circuit O_SD may be formed by the same process as the first electrode S1 and the second electrode D1 of the first transistor T1. The reset transistor ST1 and the third transistor T3 may be formed on the same layer by the same process, and therefore no additional process for forming the reset transistor ST1 is required. Therefore, the process efficiency may be improved, and the manufacturing cost may be reduced.

[0137] The element layer DP-ED may be disposed on the circuit layer DP-CL. The element layer DP-ED may include a light emitting element ED and a light sensing element OPD. Figure 5 In the figure, a light emitting element (eg, a single light emitting element) ED and a light sensing element (eg, a single light sensing element) OPD are representatively shown.

[0138] The light emitting area PXA may be defined to correspond to the light emitting element ED, and the sensing area SA may be defined to correspond to the light sensing element OPD. The light emitting area PXA and the sensing area SA may be defined by a pixel defining layer PDL to be described below.

[0139] The light emitting element ED may include a first electrode AE, a first hole control layer HFL1, a light emitting layer EL, a first electron control layer EFL1, and a second electrode CE. The light sensing element OPD may include a first electrode AE-S, a second hole control layer HFL2, a photoelectric conversion layer LRL, a second electron control layer EFL2, and a second electrode CE-S. For example, the first electrode AE ​​of the light emitting element ED may be referred to as a first light emitting electrode, and the second electrode CE of the light emitting element ED may be referred to as a second light emitting electrode. The first electrode AE-S of the light sensing element OPD may be referred to as a first light sensing electrode, and the second electrode CE-S of the light sensing element OPD may be referred to as a second light sensing electrode.

[0140] The second electrodes CE and CE-S may be directed to a plurality of pixels PX (refer to Figure 3 ) and multiple sensor FX (reference Figure 3 ) are commonly provided. For example, the second electrode CE of the light emitting element ED and the second electrode CE-S of the light sensing element OPD may be connected to be integrated with each other. The second electrodes CE and CE-S may be connected to each other on the pixel defining layer PDL.

[0141] refer to Figure 5 The first electrode AE ​​of the light emitting element ED and the first electrode AE-S of the light sensing element OPD may be disposed on the eighth insulating layer 80. The first electrode AE ​​of the light emitting element ED may be connected to the third connection electrode CNE30 through a fourth contact hole CH4 penetrating (or passing through) the eighth insulating layer 80.

[0142] For example, each of the light emitting element ED and the light sensing element OPD may further include an auxiliary layer. The auxiliary layer may be disposed between the first hole control layer HFL1 and the light emitting layer EL and between the second hole control layer HFL2 and the photoelectric conversion layer LRL.

[0143] The pixel defining layer PDL may be disposed on the eighth insulating layer 80 and may cover portions of the first electrodes AE and AE-S. Openings PDLop1 and PDLop2 may be disposed in the pixel defining layer PDL. The emission area PXA and the sensing area SA may be defined by the openings PDLop1 and PDLop2.

[0144] The light emitting area PXA may be defined by the first opening PDLop1, and the sensing area SA may be defined by the second opening PDLop2. The first opening PDLop1 may expose at least a portion of the first electrode AE ​​of the light emitting element ED, and the second opening PDLop2 may expose at least a portion of the first electrode AE-S of the light sensing element OPD.

[0145] In an embodiment, the pixel defining layer PDL may further include a black material. The pixel defining layer PDL may further include carbon black, a black organic dye / pigment such as aniline black, and the like. The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may further include a liquid-repellent organic material. The pixel defining layer PDL may include a portion including a liquid-repellent organic material. A detailed description of this will be given below.

[0146] The light-emitting layer EL of the light-emitting element ED may be disposed in a region corresponding to the first opening PDLop1. The light-emitting layer EL may generate light of a specific color. Although a patterned light-emitting layer EL has been described as an example in the embodiment, a light-emitting layer (e.g., a single light-emitting layer) may be commonly disposed in a plurality of light-emitting regions. For example, the light-emitting layer may generate white light or blue light. For example, the light-emitting layer may have a multilayer structure called a cascade.

[0147] The light emitting layer EL may include a low molecular weight organic material or a high molecular weight organic material as a light emitting material. In another example, the light emitting layer EL may include a quantum dot material as a light emitting material. The core of the quantum dot may be selected from II-VI group compounds, III-V group compounds, III-VI group compounds, I-III-VI group compounds, IV-VI group compounds, IV group elements, IV group compounds, and combinations thereof.

[0148] The photoelectric conversion layer LRL may be disposed in a region corresponding to the second opening PDLop2. The photoelectric conversion layer LRL may include an organic photosensitive material. The second electrode CE-S may be disposed on the photoelectric conversion layer LRL. The first electrode AE-S and the second electrode CE-S may each receive an electrical signal. The first electrode AE-S and the second electrode CE-S may receive different signals. Therefore, an electric field may be formed between the first electrode AE-S and the second electrode CE-S. The photoelectric conversion layer LRL may generate an electrical signal corresponding to light incident on the sensor.

[0149] The charges generated in the photoelectric conversion layer LRL may change the electric field between the first electrode AE-S and the second electrode CE-S. The amount of charges generated in the photoelectric conversion layer LRL may vary depending on whether light is incident on the light sensing element OPD and the amount and intensity of light incident on the light sensing element OPD. Therefore, the electric field formed between the first electrode AE-S and the second electrode CE-S may vary. The light sensing element OPD according to an embodiment may obtain fingerprint information of the user through the change of the electric field between the first electrode AE-S and the second electrode CE-S.

[0150] For example, the element layer DP-ED may further include a capping layer disposed on the second electrode CE and CE-S. The capping layer may be used to improve the luminous efficiency by the principle of constructive interference. The capping layer may include, for example, a material having a refractive index of about 1.6 or greater for light having a wavelength of about 589 nm. The capping layer may be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material. For example, the capping layer may include a carbocyclic compound, a heterocyclic compound, a compound containing an amine group, a porphine derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or a combination thereof. For carbocyclic compounds, heterocyclic compounds, and compounds containing amine groups, substituents containing O, N, S, Se, Si, F, Cl, Br, I, or a combination thereof may be selectively substituted.

[0151] The encapsulation layer TFE may be disposed on the element layer DP-ED. The encapsulation layer TFE may include at least an inorganic layer or an organic layer. In an embodiment, the encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. In an embodiment, the encapsulation layer TFE may include inorganic layers and organic layers alternately stacked on each other.

[0152] The inorganic encapsulation layer can protect the light emitting element ED and the light sensing element OPD from moisture / oxygen, and the organic encapsulation layer can protect the light emitting element ED and the light sensing element OPD from foreign matter (such as dust particles). The inorganic encapsulation layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but the embodiment is not limited thereto. The organic encapsulation layer may include an acrylic organic layer, but the embodiment is not limited thereto.

[0153] The sensor layer 200 may be disposed on the display layer 100. The sensor layer 200 may sense an external input applied from the outside. The external input may be an input of a user. The input of the user may include various types of external inputs, such as a part of the user's body, light, heat, a pen, or pressure. The sensor layer 200 may be referred to as a sensor, an input sensing layer, or an input sensing panel. The sensor layer 200 may include a sensor base layer 201, a first sensor conductive layer, a sensor insulating layer 203, a second sensor conductive layer 204, and a sensor cover layer 205.

[0154] The sensor base layer 201 may be disposed (e.g., directly disposed) on the display layer 100. The sensor base layer 201 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. In another example, the sensor base layer 201 may be an organic layer including epoxy resin, acrylic resin, or imide-based resin. The sensor base layer 201 may have a single-layer structure, or may have a multi-layer structure stacked in the third direction DR3.

[0155] Each of the first sensor conductive layer and the second sensor conductive layer 204 may have a single-layer structure, or may have a multi-layer structure stacked in the third direction DR3.

[0156] The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide, indium zinc oxide, zinc oxide or indium zinc tin oxide. For example, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire or graphene.

[0157] The conductive layer having a multi-layer structure may include a plurality of metal layers. The metal layer may have a three-layer structure of, for example, titanium / aluminum / titanium. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0158] The sensor insulating layer 203 may be disposed between the first sensor conductive layer and the second sensor conductive layer 204. The sensor insulating layer 203 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0159] In another example, the sensor insulating layer 203 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane-based resin, cellulose resin, siloxane-based resin, polyimide resin, polyamide resin, and stilbene-based resin.

[0160] The sensor cover layer 205 may be disposed on the sensor insulating layer 203 and may cover the second sensor conductive layer 204. The second sensor conductive layer 204 may include a conductive pattern. The sensor cover layer 205 may cover the conductive pattern and may reduce or eliminate the probability of damage to the conductive pattern in a subsequent process. The sensor cover layer 205 may include an inorganic material. For example, the sensor cover layer 205 may include silicon nitride, but the embodiment is not limited thereto. In another example, the sensor cover layer 205 may be omitted.

[0161] The anti-reflection layer 300 may be disposed on the sensor layer 200. The anti-reflection layer 300 may include a spacer layer 310, a color filter 320, and a planarization layer 330.

[0162] The spacer layer 310 may overlap the conductive pattern of the second sensor conductive layer 204. The sensor cover layer 205 may be disposed between the spacer layer 310 and the second sensor conductive layer 204. The spacer layer 310 may prevent external light from being reflected by the second sensor conductive layer 204. The material constituting the spacer layer 310 is not limited as long as it is a material capable of absorbing light. The spacer layer 310 may be a black layer. In an embodiment, the spacer layer 310 may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof.

[0163] The partition layer 310 may have a partition opening defined (or formed) therein. The partition opening may overlap the light emitting layer EL and the photoelectric conversion layer LRL, respectively. The color filter 320 may be provided to correspond to the partition opening. The color filter 320 may transmit light provided from the light emitting layer EL overlapping with the color filter 320. In another example, the light may be transmitted through the color filter 320 and may be provided to the photoelectric conversion layer LRL.

[0164] The light-emitting layer EL may be a green light-emitting layer. Therefore, a color filter (e.g., a single color filter) 320 may be commonly provided for a plurality of light-emitting layers EL and a plurality of photoelectric conversion layers LRL. However, the embodiment is not limited thereto. For example, another color filter other than the green color filter may be provided on the photoelectric conversion layer LRL. In another example, the color filter 320 may not be provided on the photoelectric conversion layer LRL.

[0165] The planarization layer 330 may cover the partition layer 310 and the color filter 320. The planarization layer 330 may include an organic material, and may provide a flat surface on an upper surface of the planarization layer 330. In another example, the planarization layer 330 may be omitted.

[0166] In an embodiment, the anti-reflection layer 300 may include a reflection control layer instead of the color filter 320. For example, in Figure 5 The color filter 320 may be omitted, and a reflection control layer may be added at a position where the color filter 320 is omitted. The reflection control layer may selectively absorb light having a partial wavelength band of light reflected inside the display panel and / or the display device or light having a partial wavelength band of light incident from outside the display panel and / or the display device.

[0167] For example, the reflection control layer may absorb light having a first wavelength range of about 490 nm to about 505 nm and light having a second wavelength range of about 585 nm to about 600 nm, and thus the light transmittance in the first wavelength range and the second wavelength range may be about 40% or less. The reflection control layer may absorb light outside the wavelength range of red light, green light, and blue light emitted from the light emitting layer EL. As described above, since the reflection control layer absorbs light outside the wavelength range of red light, green light, or blue light emitted from the light emitting layer EL as described above, the brightness of the display panel and / or the display device may be prevented or minimized from being reduced. For example, the degradation of the luminous efficiency of the display panel and / or the display device may be prevented or minimized, and visibility may be improved.

[0168] The reflection control layer may be implemented as an organic layer including a dye, a pigment or a combination thereof. The reflection control layer may include a tetraazaporphyrin (TAP)-based compound, a porphyrin-based compound, a metal porphyrin-based compound, an oxazine-based compound, a cristobalite-based compound, a triarylmethane-based compound, a polymethyl-based compound, an anthraquinone-based compound, a phthalocyanine-based compound, an azo-based compound, a xylene-based compound, a yellow anthracene-based compound, a diimine-based compound, a dipyrromethene-based compound, a cyanine-based compound and a combination thereof.

[0169] In an embodiment, the reflection control layer may have a transmittance of about 64% to about 72%.The transmittance of the reflection control layer may be adjusted according to the content of the pigment and / or dye included in the reflection control layer.

[0170] Figure 6 is a schematic plan view showing a part of a display area of ​​a display panel according to an embodiment. Fig. 7A and Figure 7B is an enlarged schematic plan view showing a portion of a display area of ​​a display panel according to an embodiment. Fig. 7A is an enlarged schematic diagram showing a pixel unit PXU of a display area of ​​a display panel, and Figure 7B is an enlarged schematic diagram showing the arrangement of one light emitting region and one sensing region included in a pixel unit.

[0171] refer to Figure 3 , Figure 6 , Fig. 7A and Figure 7B , the active area DA may include a non-light emitting area NPXA, light emitting areas PXA-R, PXA-G, and PXA-B, and a sensing area SA. The light emitting areas PXA-R, PXA-G, and PXA-B may be areas from which light generated from the light emitting element is emitted. The light emitting areas PXA-R, PXA-G, and PXA-B may be spaced apart from each other in a plan view. The sensing area SA may be an area in which the light sensing element obtains the fingerprint information of the user. The sensing area SA may be spaced apart from the light emitting areas PXA-R, PXA-G, and PXA-B in a plan view.

[0172] The light emitting regions PXA-R, PXA-G, and PXA-B and the sensing region SA may be formed by a pixel defining layer PDL (refer to Figure 5 ) are separated from each other. The non-light emitting area NPXA may be located between the light emitting areas PXA-R, PXA-G, and PXA-B and the sensing area SA, and may be an area corresponding to the pixel defining layer PDL. For example, in the present disclosure, each of the light emitting areas PXA-R, PXA-G, and PXA-B and the sensing area SA may correspond to a pixel.

[0173] In the display panel DP of the embodiment, the light emitting regions PXA-R, PXA-G, and PXA-B may be divided into a plurality of groups according to the color of light generated from the light emitting elements. Figure 6 , Fig. 7A and Figure 7B In the effective area DA of the embodiment shown, three light-emitting areas PXA-R, PXA-G and PXA-B that emit red light, green light and blue light, respectively, are shown as examples. The display panel DP of the embodiment may include a red light-emitting area PXA-R, a green light-emitting area PXA-G and a blue light-emitting area PXA-B separated from each other. The red light-emitting area (e.g., a single red light-emitting area) PXA-R, the green light-emitting area (e.g., a single green light-emitting area) PXA-G, the blue light-emitting area (e.g., a single blue light-emitting area) PXA-B and the sensing area (e.g., a single sensing area) SA that are arranged adjacent to each other may be grouped into a pixel unit (e.g., a single pixel unit) PXU.

[0174] The light emitting elements corresponding to the light emitting regions PXA-R, PXA-G, and PXA-B, respectively, may emit light having different wavelength ranges. The display panel DP of the embodiment may include a red light emitting element emitting red light and corresponding to the red light emitting region PXA-R, a green light emitting element emitting green light and corresponding to the green light emitting region PXA-G, and a blue light emitting element emitting blue light and corresponding to the blue light emitting region PXA-B. The red light emitting region PXA-R may emit light having a wavelength range of about 620 nm to about 700 nm, the green light emitting region PXA-G may emit light having a wavelength range of about 500 nm to about 600 nm, and the blue light emitting region PXA-B may emit light having a wavelength range of about 410 nm to about 480 nm.

[0175] The light emitting elements corresponding to the light emitting regions PXA-R, PXA-G, and PXA-B, respectively, may emit light having the same wavelength range, or at least one of the light emitting elements may emit light having a wavelength range different from the wavelength range of light emitted by the remaining light emitting elements. For example, the light emitting elements corresponding to the light emitting regions PXA-R, PXA-G, and PXA-B, respectively, may all emit blue light.

[0176] In the display panel DP according to the embodiment, the light emitting areas PXA-R, PXA-G, and PXA-B and the sensing area SA may be arranged in a stripe form. Figure 6 , the red light emitting regions PXA-R may be arranged in the second direction DR2, the green light emitting regions PXA-G may be arranged in the second direction DR2, and the blue light emitting regions PXA-B may be arranged in the second direction DR2. For example, the light emitting regions PXA-R, PXA-G, and PXA-B may be alternately arranged in the first direction DR1 in the order of the red light emitting regions PXA-R, the green light emitting regions PXA-G, and the blue light emitting regions PXA-B. For example, the sensing regions SA may be arranged in the second direction DR2 in a form in which each of the sensing regions SA is surrounded by the green light emitting regions PXA-G. The display panel DP according to the embodiment may include a first pixel column PXL1 in which the red light emitting regions PXA-R are arranged in the second direction DR2, a second pixel column PXL2 in which the green light emitting regions PXA-G and the sensing regions SA are arranged in the second direction DR2, and a third pixel column PXL3 in which the blue light emitting regions PXA-B are arranged in the second direction DR2.

[0177] In the display panel DP according to the embodiment, the light emitting regions PXA-R, PXA-G, and PXA-B and the sensing region SA may have a rectangular shape in a plan view. However, the embodiment is not limited thereto, and the light emitting regions PXA-R, PXA-G, and PXA-B and the sensing region SA may have a rounded rectangular shape.

[0178] In the display panel DP according to the embodiment, the sensing area SA may be at least partially surrounded by one of the light emitting areas PXA-R, PXA-G, and PXA-B in a plan view. Figure 6 , Fig. 7A and Figure 7B As shown, the sensing area SA may be at least partially surrounded by the green light-emitting areas PXA-G in a plan view. For example, the expression "area A is surrounded by area B on a plane (in a plan view)" used herein means that area B is disposed adjacent to more than half of the periphery of area A, and area A is disposed within area B. The sensing area SA may be disposed in a plan view within the area in which the green light-emitting areas PXA-G are disposed. In the present disclosure, the light-emitting area surrounding at least a portion of the sensing area SA may be referred to as a "first light-emitting area." Figure 6 , Fig. 7A and Figure 7B In the illustrated embodiment, the green light emitting region PXA-G may correspond to the first light emitting region.

[0179] refer to Fig. 7A and Figure 7B , the sensing area SA may have a rectangular shape having a first side SS1 and a second side SS2 extending in the first direction DR1 in a plan view, and a third side SS3 and a fourth side SS4 extending in the second direction DR2 in a plan view. The green light emitting area PXA-G surrounding at least a portion of the sensing area SA may surround at least three sides of the sensing area SA having a rectangular shape. Figure 7B As shown, the green light emitting region PXA-G may surround the entire first side SS1, the third side SS3, and the fourth side SS4 of the sensing region SA. However, the embodiment is not limited thereto, and the green light emitting region PXA-G may have a shape that does not surround at least a portion of the third side SS3 and at least a portion of the fourth side SS4 of the sensing region SA.

[0180] like Fig. 7A and Figure 7B As shown, the green light emitting area PXA-G may not surround a portion of the sensing area SA having a rectangular shape. The green light emitting area PXA-G may surround three sides of the sensing area SA, and may not surround at least a portion of the remaining one side of the sensing area SA. The green light emitting area PXA-G may not surround at least a portion of the second side SS2 of the sensing area SA. For example, among the areas adjacent to the sensing area SA, a portion of the non-light emitting area NPXA that is not surrounded by the green light emitting area PXA-G may correspond to the wiring area SLA. Included in the area for driving the light sensing element OPD (reference Figure 5) sensor drive circuit O_SD (reference Figure 4 ) can be set in the wiring area SLA adjacent to the sensing area SA.

[0181] The sensing area SA may have a smaller area (or a smaller size) than the light emitting areas PXA-R, PXA-G, and PXA-B in a plan view. The sensing area SA may have a smaller area (or a smaller size) than the red light emitting area PXA-R and the blue light emitting area PXA-B. The sensing area SA may have a smaller area (or a smaller size) than the green light emitting area PXA-G surrounding at least a portion of the sensing area SA.

[0182] The area (or size) of the green light emitting region PXA-G surrounding the sensing region SA may be smaller than the area (or size) of other light emitting regions. For example, the area (or size) of the green light emitting region PXA-G may be smaller than the area (or size) of the red light emitting region PXA-R and the blue light emitting region PXA-B.

[0183] The sum of the area (or size) of the sensing area SA and the area (or size) of the green light-emitting area PXA-G surrounding at least a portion of the sensing area SA may be designed to correspond to the area (or size) of the other light-emitting areas. For example, the sum of the area (or size) of the sensing area SA and the area (or size) of the green light-emitting area PXA-G may be substantially the same as the area (or size) of each of the red light-emitting area PXA-R and the blue light-emitting area PXA-B. The expression "the areas (or sizes) of the two areas are 'substantially the same' as each other" used herein includes not only the case where these areas are physically equal, but also the case where there is a difference between the areas (or sizes) at the level of errors that occur in the process even if the same design is used. Since the sum of the area (or size) of the sensing area SA and the area (or size) of the green light-emitting area PXA-G is substantially the same as the area (or size) of each of the red light-emitting area PXA-R and the blue light-emitting area PXA-B, the sum of the opening ratio of the sensing area SA and the opening ratio of the green light-emitting area PXA-G can be the same as the opening ratio of each of the red light-emitting area PXA-R and the blue light-emitting area PXA-B.

[0184] The green light emitting region PXA-G, the red light emitting region PXA-R, and the blue light emitting region PXA-B may have substantially the same width in the first direction DR1. In an embodiment, the green light emitting region PXA-G may have a first width d1 in the first direction DR1, the red light emitting region PXA-R may have a second width d2 in the first direction DR1, and the blue light emitting region PXA-B may have a third width d3 in the first direction DR1. The first width d1, the second width d2, and the third width d3 may be substantially equal to each other.

[0185] The length of the green light emitting region PXA-G in the second direction DR2 may be greater than the lengths of the red light emitting region PXA-R and the blue light emitting region PXA-B in the second direction DR2. In an embodiment, the green light emitting region PXA-G may have a first length L1 in the second direction DR2, the red light emitting region PXA-R may have a second length L2 in the second direction DR2, and the first length L1 may be greater than the second length L2. Since the green light emitting region PXA-G has the sensing region SA disposed in the green light emitting region PXA-G and thus has a smaller aperture ratio than the red light emitting region PXA-R and the blue light emitting region PXA-B, the green light emitting region PXA-G may be longer than the red light emitting region PXA-R and the blue light emitting region PXA-B in the second direction DR2 to compensate for the aperture ratio of the green light emitting region PXA-G. For example, since the green light emitting region PXA-G is longer than the red light emitting region PXA-R in the second direction DR2, the lower side GL of the green light emitting region PXA-G may be disposed in a position lower than the lower side RL of the red light emitting region PXA-R based on the second direction DR2.

[0186] Figure 8 and Fig. 9 is a schematic cross-sectional view of a portion of a display area of ​​a display panel. Figure 8 Shown corresponding to Figure 7B The section of line I-I', and Fig. 9 Shown corresponding to Figure 7B Section along line II-II'.

[0187] Reference together Figure 7B , Figure 8 and Fig. 9 , the sensing area SA may be at least partially surrounded by the green light emitting area PXA-G in a plan view. Figure 8 As shown, in a cross section defined by the first direction DR1 and the third direction DR3, the sensing area SA may be disposed within the green light emitting area PXA-G based on the first direction DR1. Fig. 9As shown, in a cross section defined by the second direction DR2 and the third direction DR3, the green light emitting region PXA-G may be disposed on one side of the sensing region SA based on the second direction DR2. For example, in a cross section defined by the second direction DR2 and the third direction DR3, the wiring region SLA may be disposed on an opposite side of the sensing region SA based on the second direction DR2.

[0188] The first light emitting element ED1 may be disposed to correspond to the green light emitting region PXA-G, and the light sensing element OPD may be disposed to correspond to the sensing region SA. The first light emitting element ED1 may be disposed in a first opening PDLop1 disposed in the pixel defining layer PDL. The light sensing element OPD may be disposed in a second opening PDLop2 disposed in the pixel defining layer PDL. The first opening PDLop1 may define the green light emitting region PXA-G, and the second opening PDLop2 may define the sensing region SA. The first opening PDLop1 may surround at least a portion of the second opening PDLop2 in a plan view.

[0189] The first light emitting element ED1 may include a first electrode AE, a first hole control layer HFL1, a light emitting layer EL, a first electron control layer EFL1, and a second electrode CE. The light sensing element OPD may include a first electrode AE-S, a second hole control layer HFL2, a photoelectric conversion layer LRL, a second electron control layer EFL2, and a second electrode CE-S. In the present disclosure, the first hole control layer HFL1 and the first electron control layer EFL1 may be referred to as a "first functional layer". In the present disclosure, the second hole control layer HFL2 and the second electron control layer EFL2 may be referred to as a "second functional layer".

[0190] The first hole control layer HFL1 and the second hole control layer HFL2 may include a hole transport material. The first hole control layer HFL1 may include a hole injection layer adjacent to the first electrode AE ​​and a hole transport layer disposed between the hole injection layer and the light emitting layer EL, and the second hole control layer HFL2 may include a hole injection layer adjacent to the first electrode AE-S and a hole transport layer disposed between the hole injection layer and the photoelectric conversion layer LRL.

[0191] The first electron control layer EFL1 and the second electron control layer EFL2 may include an electron transport material. The first electron control layer EFL1 may include an electron injection layer adjacent to the second electrode CE and an electron transport layer disposed between the electron injection layer and the light emitting layer EL, and the second electron control layer EFL2 may include an electron injection layer adjacent to the second electrode CE-S and an electron transport layer disposed between the electron injection layer and the photoelectric conversion layer LRL.

[0192] The first hole control layer HFL1, the light emitting layer EL and the first electron control layer EFL1 included in the first light emitting element ED1 may be patterned and disposed in the first opening PDLop1. The second hole control layer HFL2, the photoelectric conversion layer LRL and the second electron control layer EFL2 included in the light sensing element OPD may be patterned and disposed in the second opening PDLop2.

[0193] The pixel defining layer PDL may include a barrier wall portion PDL-B disposed on the base layer BL and the circuit layer DP-CL and a liquid repellent portion PDL-L disposed on the barrier wall portion PDL-B. The liquid repellent portion PDL-L may be disposed at a top (or upper portion) of the pixel defining layer PDL, and an upper surface of the liquid repellent portion PDL-L may define an upper surface of the pixel defining layer PDL.

[0194] The liquid-repellent portion PDL-L may include a liquid-repellent organic material. The liquid-repellent portion PDL-L may include a liquid-repellent material and may have liquid-repellent properties. For example, the liquid-repellent portion PDL-L may include a fluorine-containing organic material and may have liquid-repellent properties. The liquid-repellent portion PDL-L may include a liquid-repellent material such as a perfluoropolyether (PFPE) derivative. Since the liquid-repellent portion PDL-L is disposed at the top (or upper portion) of the pixel defining layer PDL, the process of forming the first functional layer included in the first light-emitting element ED1 and the second functional layer included in the light sensing element OPD may be performed in one step. A detailed description related to this will be given below.

[0195] The encapsulation layer TFE may be disposed on the first light emitting element ED1 and the light sensing element OPD, and may cover the first light emitting element ED1 and the light sensing element OPD. The encapsulation layer TFE may include at least an inorganic layer or an organic layer. In an embodiment, the encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. In an embodiment, the encapsulation layer TFE may include inorganic layers and organic layers alternately stacked on each other.

[0196] Fig.10 is a schematic cross-sectional view of a portion of a display area of ​​a display panel. Fig.10 Shows the corresponding Figure 7B For example, in Fig.10 In the corresponding Figure 8 A cross section of a display panel according to an embodiment is shown in FIG.

[0197] refer to Fig. 7A , Figure 7B and Fig.10, the pixel defining layer PDL may include a first pixel defining portion PDL-1 disposed between the light emitting regions PXA-R, PXA-G, and PXA-B and a second pixel defining portion PDL-2 disposed between the green light emitting region PXA-G and the sensing region SA. The first pixel defining portion PDL-1 may be spaced apart from the sensing region SA using the green light emitting region PXA-G between the first pixel defining portion PDL-1 and the sensing region SA.

[0198] The first pixel defining portion PDL-1 and the second pixel defining portion PDL-2 may include barrier wall portions PDL-B1 and PDL-B2 and liquid repellent portions PDL-L1 and PDL-L2 respectively disposed on the barrier wall portions PDL-B1 and PDL-B2. The first pixel defining portion PDL-1 may include a first barrier wall portion PDL-B1 and a first liquid repellent portion PDL-L1. The second pixel defining portion PDL-2 may include a second barrier wall portion PDL-B2 and a second liquid repellent portion PDL-L2.

[0199] The first pixel defining portion PDL-1 and the second pixel defining portion PDL-2 may have different heights in cross section. The first pixel defining portion PDL-1 may have a first height h1 in the third direction DR3, and the second pixel defining portion PDL-2 may have a second height h2 in the third direction DR3. The first height h1 may be greater than the second height h2. In an embodiment, the second height h2 may be about 30% to about 70% of the first height h1. Since the second height h2 is less than the first height h1, the formation process of the first functional layer and the second functional layer performed in one step may be smoothly performed.

[0200] Fig.11 and Fig.12 1 is an enlarged schematic plan view showing a portion of a display area of ​​a display panel according to an embodiment. Fig.11 and Fig.12 In the corresponding Fig. 7A The plane of the pixel units PXU′ and PXU″ according to the embodiment is shown on the plane of FIG.

[0201] refer to Fig.11 ,and Fig. 7ADifferent from that shown in FIG. 1 , in a pixel unit (e.g., a single pixel unit) PXU', the sensing area SA may be surrounded by the red light emitting area PXA-R' instead of the green light emitting area PXA-G' (or the blue light emitting area PXA-B'). The sensing area SA may be disposed within the red light emitting area PXA-R'. The red light emitting area PXA-R' may surround at least a portion of the sensing area SA. The red light emitting area PXA-R' may surround at least three sides of the sensing area SA having a rectangular shape. The wiring area SLA may be disposed to be aligned with a second side SS2 (reference numeral 25) of the sensing area SA that is not surrounded by the red light emitting area PXA-R'. Figure 7B ). For example, since the sensing area SA is disposed in the red light emitting area PXA-R' instead of the green light emitting area PXA-G' (or the blue light emitting area PXA-B'), the lower side RL of the red light emitting area PXA-R' may be disposed in a position lower than the lower side GL of the green light emitting area PXA-G' (or the blue light emitting area PXA-B') based on the second direction DR2 (or positioned lower than the lower side GL of the green light emitting area PXA-G' (or the blue light emitting area PXA-B')).

[0202] refer to Fig.12 ,and Fig. 7A Different from the above, in the pixel unit PXU″, the sensing area SA may be completely surrounded by the green light emitting areas PXA-G. For example, the sensing area SA may be completely surrounded by the green light emitting areas PXA-G, and a separate wiring area SLA may not be provided (refer to Fig. 7A ). The green light emitting region PXA-G may surround all of four sides of the sensing region SA having a rectangular shape.

[0203] In the display panel of the embodiment, the sensing area in which the light sensing element is provided may be at least partially surrounded by one of the light emitting areas in which the light emitting element is provided. For example, the sensing area may be provided inside one of the light emitting areas. In the embodiment, the sensing area may be at least partially surrounded by a green light emitting area or a red light emitting area that emits light having a relatively wide wavelength range. Since according to the embodiment, the sensing area is at least partially surrounded by one of the light emitting areas in the display panel, it is not necessary to provide a separate pixel column in which the sensing area is provided. Therefore, the separation gap between the light emitting areas in the plan view can be minimized, and thus a display panel with excellent resolution can be provided.

[0204] Fig.13 is a flowchart illustrating a method for manufacturing a display panel according to an embodiment. Fig.14A , Fig. 14B , Fig. 14C , Fig.14D , Fig.14Eand Fig.14F Schematic cross-sectional views showing steps of a method for manufacturing a display panel according to an embodiment. Fig.14A , Fig. 14B , Fig. 14C , Fig.14D , Fig.14E and Fig.14F In each of Figure 8 The steps of the display panel manufacturing method are shown in the cross section shown in FIG.

[0205] refer to Fig.13 According to an embodiment, a display panel manufacturing method may include step S100 and step S200. Step S100 is to prepare a preliminary display panel including a base layer and a pixel defining layer. Step S200 is to form a first light emitting element and a light sensing element by providing an organic material on the preliminary display panel.

[0206] refer to Fig.13 and Fig.14A , the preliminary display panel DP-P may include a base layer BL, a circuit layer DP-CL and a pixel defining layer PDL. Fig.14A As shown, the first electrodes AE and AE-S are disposed on the circuit layer DP-CL. The pixel defining layer PDL may have a first opening PDLop1 and a second opening PDLop2 defined (or formed) in the pixel defining layer PDL. The first opening PDLop1 may define a light emitting area PXA (refer to FIG. 1 ) in a display panel manufactured by a display panel manufacturing method. Figure 5 ), and the second opening PDLop2 may define a sensing area SA in a display panel manufactured by a display panel manufacturing method (refer to Figure 5 ).

[0207] For example, the pixel defining layer PDL may include a barrier wall portion PDL-B disposed on the base layer BL and the circuit layer DP-CL and a liquid repellent portion PDL-L disposed on the barrier wall portion PDL-B. The liquid repellent portion PDL-L may be disposed at the top (or upper portion) of the pixel defining layer PDL, and an upper surface of the liquid repellent portion PDL-L may define an upper surface of the pixel defining layer PDL. The liquid repellent portion PDL-L may include a liquid repellent organic material. The liquid repellent portion PDL-L may include a fluorine-containing organic material and may have liquid repellent properties.

[0208] In the display panel manufacturing method, a step of providing organic materials OM1 and OM2 on the prepared preliminary display panel DP-P to form a first functional layer and a second functional layer may be performed. Figure 5 ) and the first functional layer included in the optical sensing element OPD (reference Figure 5) can be formed by providing the organic materials OM1 and OM2. Hereinafter, the steps of forming the light emitting element and the light sensing element, which include the steps of forming the first functional layer and the second functional layer, will be described in more detail.

[0209] refer to Fig.14A , Fig. 14B and Fig. 14C , a first organic material OM1 may be provided on the prepared preliminary display panel DP-P. The first organic material OM1 may include a hole transport material. The first organic material OM1 may be provided on the preliminary display panel DP-P by a printing process rather than a deposition process. For example, the first organic material OM1 may be provided by an inkjet printing process.

[0210] The first organic material OM1 may be provided in the second opening PDLop2 defined in the pixel defining layer PDL. The first organic material OM1 may be provided to the sensing area SA (refer to FIG. 1 ) of the display panel. Figure 8 ) is defined by the second opening PDLop2, and may be provided in excess to fill and overflow the second opening PDLop2. Fig. 14B As shown, the first organic material OM1 provided in the second opening PDLop2 may form a first preliminary functional layer HFL-P. The first preliminary functional layer HFL-P may overflow the second opening PDLop2 toward the outside and may fill the first opening PDLop1 surrounding at least a portion of the second opening PDLop2.

[0211] Since the liquid-repellent portion PDL-L is disposed at the top (or upper portion) of the pixel defining layer PDL, the overflowed first preliminary functional layer HFL-P may fill the first opening PDLop1 and may not remain on the pixel defining layer PDL. Thereafter, the first preliminary functional layer HFL-P may be dried, and a first hole control layer HFL1 disposed in the first opening PDLop1 and a second hole control layer HFL2 disposed in the second opening PDLop2 may be formed. Since the first hole control layer HFL1 and the second hole control layer HFL2 are formed of the same first organic material OM1, the first hole control layer HFL1 and the second hole control layer HFL2 may include the same material and may be formed by the same process.

[0212] refer to Fig. 14C and Fig.14D, after forming the first hole control layer HFL1 and the second hole control layer HFL2, the light emitting layer EL and the photoelectric conversion layer LRL may be formed by providing the light emitting material OM-E and the light sensing material OM-S. The light emitting material OM-E and the light sensing material OM-S may be provided by a printing process. The light emitting material OM-E and the light sensing material OM-S may be provided by an inkjet printing process. Unlike the first organic material OM1, the light emitting material OM-E and the light sensing material OM-S may be separately disposed in respective openings. The light emitting material OM-E may be patterned and disposed in the first opening PDLop1, and the light sensing material OM-S may be patterned and disposed in the second opening PDLop2.

[0213] refer to Fig.14D , Fig.14E and Fig.14F , the second organic material OM2 may be provided after forming the light emitting layer EL and the photoelectric conversion layer LRL. The second organic material OM2 may include an electron transport material. The second organic material OM2 may be provided on the photoelectric conversion layer LRL by a printing process rather than a deposition process. For example, the second organic material OM2 may be provided by an inkjet printing process.

[0214] The second organic material OM2 may be provided in the second opening PDLop2 defined in the pixel defining layer PDL. The second organic material OM2 may be provided to the sensing area SA (refer to FIG. 1 ) of the display panel. Figure 8 ) is defined by the second opening PDLop2, and may be provided in excess to fill and overflow the second opening PDLop2. Fig.14E As shown, the second organic material OM2 provided in the second opening PDLop2 may form a second preliminary functional layer EFL-P. The second preliminary functional layer EFL-P may overflow the second opening PDLop2 toward the outside and may fill the first opening PDLop1 surrounding at least a portion of the second opening PDLop2.

[0215] Since the liquid-repellent portion PDL-L is disposed at the top (or upper portion) of the pixel defining layer PDL, the overflowed second preliminary functional layer EFL-P may fill the first opening PDLop1 and may not remain on the pixel defining layer PDL. Thereafter, the second preliminary functional layer EFL-P may be dried, and a first electronic control layer EFL1 disposed in the first opening PDLop1 and a second electronic control layer EFL2 disposed in the second opening PDLop2 may be formed. Since the first electronic control layer EFL1 and the second electronic control layer EFL2 are formed of the same second organic material OM2, the first electronic control layer EFL1 and the second electronic control layer EFL2 may include the same material and may be formed by the same process.

[0216] After the step of forming the first and second electron control layers EFL1 and EFL2, second electrodes CE and CE-S may be formed on the first and second electron control layers EFL1 and EFL2 (refer to Figure 8 ). The second electrode may be disposed on the first electron control layer EFL1, the second electron control layer EFL2, and the pixel defining layer PDL in the form of a common electrode.

[0217] In the display panel manufacturing method, the second opening PDLop2 in which the light sensing element OPD is disposed in the manufactured display panel can be at least partially surrounded by the first opening PDLop1 in which the light emitting element ED is disposed. By this shape, in the display panel manufacturing method, in the case of forming functional layers such as a hole control layer and an electron control layer, the functional layers included in the light sensing element OPD and the functional layers of the light emitting element ED can be formed through one step by the same process. Therefore, the process steps required in the case of forming the functional layers included in the light sensing element OPD and the functional layers of the light emitting element ED by separate processes can be omitted. Therefore, the process can be simplified, and the process time and cost can be reduced.

[0218] For example, the display panel DP may include light emitting areas PXA-R, PXA-G, and PXA-B (refer to Fig. 7A ), and as described above, the sum of the area (or size) of the sensing area SA and the area (or size) of the light emitting area (e.g., the green light emitting area PXA-G) surrounding at least a portion of the sensing area SA can be designed to correspond to the area of ​​the other light emitting areas. Therefore, the number (or amount) of droplets of organic materials OM1 and OM2 forming the first functional layer and the second functional layer, respectively, can be substantially the same as the number (or amount) of droplets of organic materials forming the functional layers of the other light emitting areas (e.g., the red light emitting area PXA-R or the blue light emitting area PXA-B).

[0219] Fig.15A , Fig. 15B and Fig. 15C Schematic cross-sectional views showing steps of a method for manufacturing a display panel according to an embodiment. Fig.15A , Fig. 15B and Fig. 15C In the figure, it is shown that Fig.14A , Fig. 14B and Fig. 14C The steps on the cross section shown in correspondence to the steps.

[0220] refer to Fig.15A , Fig. 15B and Fig. 15C, the pixel defining layer PDL included in the preliminary display panel DP-P1 may include a first pixel defining portion PDL-1 and a second pixel defining portion PDL-2. The first pixel defining portion PDL-1 may be adjacent to the first opening PDLop1 and may be spaced apart from the second opening PDLop2. The second pixel defining portion PDL-2 may be disposed between the first opening PDLop1 and the second opening PDLop2. The first pixel defining portion PDL-1 and the second pixel defining portion PDL-2 may have different heights in cross section. The first pixel defining portion PDL-1 may have a first height h1 in the third direction DR3, and the second pixel defining portion PDL-2 may have a second height h2 in the third direction DR3. The first height h1 may be greater than the second height h2. In an embodiment, the second height h2 may be in the range of about 30% to about 70% of the first height h1.

[0221] In the display panel manufacturing method, a first organic material OM1 may be provided on the prepared preliminary display panel DP-P1. The first organic material OM1 may be provided through an inkjet printing process.

[0222] The first organic material OM1 may be provided in the second opening PDLop2 defined in the pixel defining layer PDL. The first organic material OM1 may be provided to the sensing area SA (refer to FIG. 1 ) of the display panel. Figure 8 ) is defined by the second opening PDLop2, and may be provided in excess to fill and overflow the second opening PDLop2. Fig. 15B As shown, the first organic material OM1 provided in the second opening PDLop2 may form a first preliminary functional layer HFL-P. The first preliminary functional layer HFL-P may overflow the second opening PDLop2 toward the outside and may fill the first opening PDLop1 surrounding at least a portion of the second opening PDLop2.

[0223] For example, since the second pixel defining portion PDL-2 adjacent to the second opening PDLop2 has a relatively small second height h2, the first preliminary functional layer HFL-P may more easily overflow the second pixel defining portion PDL-2. For example, in the display panel manufacturing method, the height of the second pixel defining portion PDL-2 may be formed to be small so that the first organic material OM1 disposed in the second opening PDLop2 easily overflows toward the first opening PDLop1.

[0224] The overflowed first preliminary functional layer HFL-P may fill the first opening PDLop1 and may not remain on the pixel defining layer PDL. Thereafter, the first preliminary functional layer HFL-P may be dried, and a first hole control layer HFL1 disposed in the first opening PDLop1 and a second hole control layer HFL2 disposed in the second opening PDLop2 may be formed. Since the first hole control layer HFL1 and the second hole control layer HFL2 are formed of the same first organic material OM1, the first hole control layer HFL1 and the second hole control layer HFL2 may include the same material and may be formed by the same process.

[0225] According to an embodiment, a separate pixel column in which a sensing region is disposed may be omitted. Therefore, a separation gap between light emitting regions in a display panel may be minimized.

[0226] According to an embodiment, the functional layer included in the light sensing element OPD and the functional layer of the light emitting element ED may be formed through one process (eg, a single process). Therefore, the display panel manufacturing method may reduce process time and cost.

[0227] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the embodiments without substantially departing from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used only in an overview and descriptive sense, not for a limiting purpose.

Claims

1. Display panel, including: a base layer including a plurality of light emitting regions and a sensing region spaced apart from each other in a plan view; A plurality of light emitting elements are respectively disposed on the base layer and overlap the plurality of light emitting regions; as well as A light sensing element is disposed on the base layer and overlaps the sensing area, wherein: The plurality of light emitting regions include a first light emitting region that emits light having a first wavelength, and At least a portion of the sensing area is surrounded by the first light emitting area in a plan view.

2. The display panel according to claim 1, wherein: In a first direction, the sensing region is disposed between portions of the first light emitting region, and In a second direction crossing the first direction, the sensing area is adjacent to at least one side of the first light emitting area.

3. The display panel according to claim 1, wherein: The sensing area has a rectangular shape including sides extending in a first direction and sides extending in a second direction crossing the first direction, and The first light emitting area surrounds at least three sides of the sensing area.

4. The display panel according to claim 1, wherein: The plurality of light emitting areas further include: a second light emitting region emitting light having a second wavelength different from the first wavelength; and The third light emitting region emits light having a third wavelength different from the first wavelength and the second wavelength.

5. The display panel according to claim 4, wherein: A sum of an area of ​​the first light emitting region and an area of ​​the sensing region is the same as an area of ​​the second light emitting region.

6. The display panel according to claim 4, wherein: A length of the first light emitting area in one direction is greater than a length of the second light emitting area in the one direction.

7. The display panel according to claim 4, wherein: The first light emitting area includes a plurality of first light emitting areas, The second light emitting area includes a plurality of second light emitting areas, The third light emitting area includes a plurality of third light emitting areas, The plurality of first light emitting regions are arranged side by side in one direction, The plurality of second light emitting regions are arranged side by side in the one direction, and The plurality of third light emitting regions are arranged side by side in the one direction.

8. The display panel according to claim 1, wherein: An area of ​​the sensing region is smaller than an area of ​​the first light emitting region.

9. The display panel according to claim 1, wherein: The sensing area includes a first side and a second side extending in a first direction, and a third side and a fourth side extending in a second direction intersecting the first direction, and The first light emitting area surrounds the first side, the third side, and the fourth side, and does not surround at least a portion of the second side.

10. The display panel according to claim 1, wherein: The light having the first wavelength is light having a green wavelength range.

11. The display panel according to claim 1, wherein: The light having the first wavelength is light having a red wavelength range.

12. The display panel according to claim 1, further comprising: A pixel defining layer is disposed on the base layer, and the pixel defining layer has a plurality of openings. The plurality of openings respectively define the plurality of light emitting areas and the sensing area.

13. The display panel according to claim 12, wherein: The pixel defining layer comprises: a barrier wall portion disposed on the base layer; and The liquid-repellent portion is disposed on the barrier wall portion, and the liquid-repellent portion includes a liquid-repellent organic material.

14. The display panel according to claim 12, wherein: The pixel defining layer comprises: a first pixel defining portion disposed between the plurality of light emitting regions; and a second pixel defining portion disposed between the first light emitting region and the sensing region, and A height of the second pixel defining portion is smaller than a height of the first pixel defining portion.

15. The display panel according to claim 1, wherein: The plurality of light emitting elements include a first light emitting element overlapping the first light emitting area, The first light emitting element comprises: A first light-emitting electrode is arranged on the base layer; A second light-emitting electrode is disposed on the first light-emitting electrode; and A first functional layer is provided between the first light-emitting electrode and the second light-emitting electrode, The light sensing element comprises: A first light sensing electrode is disposed on the base layer; A second light sensing electrode is disposed on the first light sensing electrode; and a second functional layer disposed between the first light sensing electrode and the second light sensing electrode, and The first functional layer and the second functional layer include the same material.

16. Display panel, comprising: A base layer including a first light emitting region and a sensing region spaced apart from each other in a plan view; A pixel defining layer, disposed on the base layer, wherein the pixel defining layer has a first opening defining the first light emitting area and a second opening defining the sensing area; a first light emitting element disposed on the base layer and in the first opening; as well as a light sensing element disposed on the base layer and in the second opening, At least a portion of the second opening is surrounded by the first opening in a plan view.

17. A method for manufacturing a display panel, the method comprising: preparing a preliminary display panel including a base layer and a pixel defining layer disposed on the base layer; as well as A first light emitting element and a light sensing element are formed by providing an organic material on the preliminary display panel, wherein: The pixel defining layer has a first opening and a second opening, wherein: The first opening defines a first light emitting area, and the first light emitting element is disposed in the first light emitting area. The second opening defines a sensing area, the light sensing element is disposed in the sensing area, and At least a portion of the second opening is surrounded by the first opening in a plan view.

18. The method according to claim 17, wherein: The first light-emitting element comprises a first functional layer, The light sensing element includes a second functional layer, and The first functional layer and the second functional layer are formed by the same process.

19. The method according to claim 18, wherein: Forming each of the first functional layer and the second functional layer includes providing the organic material in the second opening.

20. The method according to claim 17, wherein: The pixel defining layer comprises: a first pixel defining portion adjacent to the first opening and spaced apart from the second opening; and a second pixel defining portion disposed between the first opening and the second opening, and A height of the second pixel defining portion is smaller than a height of the first pixel defining portion.

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