Media scanning in a memory system

Abstract

The invention relates to a method and device for medium scanning in a storage system and a computer readable storage medium. In one example, a method for a memory system includes receiving a command from a host coupled to the memory system, where the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a plurality of memory cells. The method also includes performing an operation on the storage device based on the command. The method further includes scanning at least a memory cell group of the memory cell array by performing a plurality of scans within a scan period among the operations.

Description

Technical Field

[0001] The present disclosure relates generally to storage devices and storage systems, and more particularly to media scanning in storage systems. Background Art

[0002] Storage Class Memory (SCM), as a persistent memory, is a non-volatile memory and storage technology that provides faster access speeds and lower latency than NAND flash memory, and has greater storage capacity and higher durability than Dynamic Random Access Memory (DRAM) at a reduced cost. An example of SCM technology is Phase Change Memory (PCM). PCM devices use phase change materials to store information. Phase change materials have different levels of resistance in different physical states. For example, when the phase change material is in an amorphous state, it has a high resistance. When the phase change material changes to a crystalline state, the resistance becomes lower. Therefore, a PCM device may include a memory cell made of a phase change material. Changing the state of the phase change material of the memory cell stores information in the memory cell. The stored information can then be read from the memory cell by detecting the state of the phase change material. Summary of the invention

[0003] The present disclosure relates to methods, devices, and computer-readable storage media for media scanning in a storage system. In one example, a method for a storage system includes: receiving a command from a host coupled to the storage system, wherein the storage system includes a storage device, the storage device includes a storage cell array, and the storage cell array includes a plurality of storage cells. The method also includes: performing an operation on the storage device based on the command. The method also includes: scanning at least a group of storage cells of the storage cell array by performing a plurality of scans within a scan cycle during the operation.

[0004] Although generally described as computer-implemented software embodied on tangible media, processing and converting corresponding data, some or all aspects may be computer-implemented methods or further included in corresponding systems or other devices for performing the described functions. These and other aspects of the disclosure and details of implementation are set forth in the drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 Some examples of threshold voltage (Vt) drift are shown;

[0006] Figure 2 A block diagram showing an example system coupled to a host according to some aspects of the present disclosure;

[0007] Figure 3 A block diagram illustrating an example phase change memory (PCM) cell array coupled to peripheral circuits according to some aspects of the present disclosure;

[0008] Figure 4 An example of a method for media scanning in a storage system according to some aspects of the present disclosure is shown;

[0009] Figure 5 An example of time-based scanning according to some aspects of the present disclosure is shown;

[0010] Figure 6 An example of grouping storage cells based on electrical distance (Electrical distance, Ed) according to some aspects of the present disclosure is shown;

[0011] Figure 7 A swim lane diagram illustrating an example method for media scanning according to some aspects of the present disclosure; and

[0012] Figure 8 A diagram showing a storage device according to some aspects of the present disclosure.

[0013] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0014] Phase change memory (PCM) devices use phase change materials to store information. Applying voltage to the phase change material can change its state and conductivity. The phase change material can switch between an amorphous state and a crystalline state. In some embodiments, the amorphous state is referred to as a reset state and can correspond to a bit value of 0, while the crystalline state is referred to as a set state and can correspond to a bit value of 1. The switch between the amorphous state and the crystalline state can be triggered by melting and cooling caused by an electric pulse. The threshold voltage (Vt) represents the threshold at which the phase change material undergoes a change in conductivity. Amorphous phase change materials generally have a higher resistance. When a voltage higher than the amorphous Vt (reset Vt) is applied to the amorphous phase change material for a period of time, the phase change material may become conductive and melted by the heat generated by the current. After rapid cooling, the phase change material is in a crystalline state and has a low resistance. Similarly, applying a voltage higher than the Vt (set Vt) of the crystalline state to the crystalline phase change material for another period of time can change the phase change material to an amorphous state.

[0015] Applying a voltage above Vt across a PCM cell can produce a transient current that can be used to read the bit value stored by the PCM cell. For example, if the voltage applied to the PCM cell is between the set Vt and the reset Vt, the presence of the transient current can indicate that the PCM cell is in the set state. In other words, the bit value of the PCM cell is 1. On the other hand, the absence of the transient current may indicate that the PCM cell is in the reset state and is storing a bit value of 0.

[0016] The Vt of a phase change material tends to shift or drift over time. This phenomenon may be referred to as Vt drift. Reset Vt and set Vt may have different drift rates. Figure 1 As shown, in some cases, the reset Vt (102 or 104) drifts faster than the set Vt (106 or 108). Both the set Vt and the reset Vt may drift faster at higher temperatures. For example, the reset Vt at 85°C (102) drifts faster than the reset Vt at 25°C (104), and the set Vt at 85°C (106) also drifts faster than the set Vt at 25°C (108).

[0017] The performance of PCM memory devices may be affected by Vt drift. Vt drift may cause memory cell read errors and data corruption because the default read voltage between the original set Vt and reset Vt may not be suitable to distinguish the shifted set Vt and reset Vt. Sometimes the read error can be recovered by triggering the read error recovery flow. But the memory read speed may be reduced or slowed down due to the delay caused by the recovery process. Sometimes uncorrectable read errors may cause loss of read margin. In addition, long-term Vt drift may permanently damage the memory cell so that the memory cell cannot be set and reset again.

[0018] The present disclosure provides techniques for storage systems to detect Vt drift and prevent data corruption using media scanning. In some embodiments, a periodic media scan of the entire storage device of the storage system can be performed. In some embodiments, a periodic media scan of a portion of the storage device of the storage system can be performed. The portion of the storage device to be scanned can be programmed or otherwise specified. For example, a storage system can include a storage device having a plurality of storage cells. The storage system can receive commands from a host and perform operations on the storage device based on the commands. The periodic media scan of the entire storage device includes: scanning a group of storage cells of the storage device within a cycle during operation. In some embodiments, the periodic media scan of the entire storage system includes: scanning another group of storage cells of the storage device within another cycle. Different groups of storage cells can have different scanning periods or intervals, which can be determined based on, for example, the electrical distance of each group of storage cells or one or more other factors. The above aspects and some other aspects of the present disclosure are discussed in more detail below.

[0019] Figure 2 An example of a block diagram of a system 200 having a storage device according to some aspects of the present disclosure is shown. The system 200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 2 As shown, the system 200 may include a host 208 and a storage system 202 having one or more storage devices 204 and a memory controller 206. The host 208 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 208 may be configured to send data to the storage device 204 or receive data from the storage device 404.

[0020] According to some embodiments, the memory controller 206 is coupled to the storage device 204 and the host 208 and is configured to control the storage device 204. The memory controller 206 can manage the data stored in the storage device 204 and communicate with the host 208. In some embodiments, the memory controller 206 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 206 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded Multi-Media-Card (eMMC) used as data storage for mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 206 can be configured to control the operation of the storage device 204, such as read, erase, and program operations. The memory controller 206 may also be configured to manage various functions regarding data stored or to be stored in the storage device 204, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 206 is further configured to process error correction coding (ECC) for data read from or written to the storage device 204. Any other suitable functions may also be performed by the memory controller 206, such as formatting the storage device 204.

[0021] The memory controller 206 may communicate with an external device (e.g., the host 208) according to a specific communication protocol. For example, the memory controller 206 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a FireWire protocol, and the like.

[0022] In some implementations, the storage system 202 does not include the memory controller 206, and the host 208 is directly coupled to the storage device 204. The memory controller 206 may be located in the host 208. Alternatively, the host 208 may not include the memory controller 206, but may be configured to perform functions similar to those performed by the memory controller 206 as described above.

[0023] The storage device 204 may be any storage device disclosed in this disclosure. Figure 3 A block diagram of an example memory device 204 according to some aspects of the present disclosure is shown. The memory device 204 includes a set of memory banks 302. Each memory bank 302 includes a memory array 304 (also referred to as a memory cell array) having memory cells arranged in rows and columns. The memory array 304 can be divided into a plurality of memory sub-arrays 308 for efficient wiring and low power consumption. In some embodiments, each or at least one of the memory cells includes a PCM element. The PCM element can be programmed to a set state or a reset state to store data as described above. Each memory cell is connected to a bit line 310 and a word line 312. Each memory bank 302 includes a data buffer / sense amplifier 314, a column decoder / bit line driver 316, and a row decoder / word line driver 318. In some examples, it may also include Figure 3 Additional peripheral circuits not shown.

[0024] The data buffer / sense amplifier 314 may be configured to receive a signal from a memory controller (e.g., Figure 2The data buffer / sense amplifier 314 may read data from the memory cell array 304 and program (write) data to the memory cell array 304 in response to control signals of the memory controller 206 of the memory controller 206. In one example, the data buffer / sense amplifier 314 may store a codeword of programming data (write data) to be programmed into the memory cell array 304. In another example, the data buffer / sense amplifier 314 may perform a program verification operation to ensure that the data has been correctly programmed into the selected memory cell coupled to the selected word line 312. In yet another example, the data buffer / sense amplifier 314 may also sense a low power signal from the bit line 310, which represents a data bit stored in the memory cell, and the data buffer / sense amplifier 314 may also amplify a small voltage swing to a recognizable logic level in a read operation.

[0025] The column decoder / bit line driver 316 may be connected to the memory cell array 304 via bit lines and select / drive one or more bit lines to perform operations on the memory cells coupled to the selected bit lines. The row decoder / word line driver 318 may be connected to the memory cell array 304 via word lines and select / drive one or more word lines to perform operations on the memory cells coupled to the selected word lines.

[0026] Figure 4 4 is a flow chart of an example method 400 for a storage system to perform a media scan according to some aspects of the present disclosure. The method 400 may be performed by any suitable device disclosed herein, such as Figure 2 The operations shown in method 400 may not be exhaustive, and other operations may be performed before, after, or between any illustrated operations. In addition, some of these operations may be performed simultaneously or in parallel. Figure 4 The different orders are shown in .

[0027] At 402, a storage system receives a command from a host (e.g., host 208) coupled to the storage system (e.g., storage system 202). The storage system includes a storage device (e.g., storage device 204). The storage device includes a storage cell array (e.g., storage cell array 304). The storage cell array includes a plurality of storage cells. The storage system may include a memory controller (e.g., memory controller 206) coupled to the host.

[0028] In some embodiments, the command is received by the memory controller from the host. The command may be a typical memory operation command from the host. For example, the command includes at least one of the following: a memory read command, a memory write command, or a memory erase command.

[0029] In some embodiments, the plurality of memory cells are a plurality of PCM memory cells. As described, PCM memory cells may suffer from Vt drift.

[0030] In some implementations, the storage devices of the storage system are storage class memory (SCM) devices.

[0031] At 404, the storage system performs an operation on the storage device based on the command. For example, if the command includes one or more memory read commands and one or more memory write commands, the operation may include one or more memory read operations and one or more memory write operations accordingly. In some embodiments, at 404, the memory controller of the storage system sends the command received from the host to the storage device, so that the storage device can perform the corresponding memory operation according to the command.

[0032] At 406, the storage system scans at least a first group of storage cells of the storage cell array by performing multiple scans within a first scan cycle during operation. The present disclosure provides techniques for a storage system that uses periodic media scans to detect Vt drift and prevent data corruption. In some embodiments, at 406, the storage system scans some or all of the storage cells of the entire storage device within the first scan cycle. The storage system can repeat 406 periodically, from time to time, or on demand. For example, the storage system can perform a media scan of the entire storage system as a repeated sequence of behaviors. A media scan of the entire storage device can be performed within the first scan cycle. In some embodiments, the frequency of the periodic media scan is determined by the first scan cycle or one or more other factors.

[0033] Whether Vt drift occurs in a PCM cell depends on a variety of factors, such as the time that has passed since the last write operation was performed on the PCM cell, the specific state of the PCM cell, the temperature of the PCM cell, etc. It may be difficult to determine these factors in a storage device. For example, the temperature of the PCM cell may change continuously with the surrounding environment. It may be difficult to record the page time after programming in a table of the storage device because the size of the table is large. Sometimes it may not be feasible to record the time when the storage device is powered off. In another example, the storage device may store some cold data that has not been read by the host for a long time. At least for the above reasons, it is generally not easy to determine which storage cell in the storage device has Vt drift without scanning the entire storage device (referred to as a full media scan). Therefore, a periodic full media scan can allow the storage system to detect Vt drift, and even detect the degree of Vt drift in the PCM cell, which can prevent unnoticed data corruption in the storage system.

[0034] In some embodiments, the first scanning cycle is a cycle for scanning all storage units of the storage system, which may also be referred to as a media scanning cycle or a media scanning time interval (MS_TIME_INTERVAL). MS_TIME_INTERVAL may be a predetermined parameter and may be dynamically adjustable. An example of MS_TIME_INTERVAL is 24 hours, that is, each storage unit of the entire storage system is scanned once every 24 hours. In this way, the Vt drift of the storage unit can be detected and repaired in time before it becomes worse. A shorter MS_TIME_INTERVAL means more frequent media scanning, which may result in greater overhead for the storage device. The longer the MS_TIME_INTERVAL, the greater the possibility of Vt drift in some storage units. Therefore, in order to strike a balance between the performance of the storage system, a suitable MS_TIME_INTERVAL is required. In some embodiments, MS_TIME_INTERVAL may be determined based on one or more factors of the size of the storage device, reliability requirements, quality of service (QoS) requirements, or other factors of the storage system.

[0035] In some embodiments, scanning the storage unit during the media scan is controlled by the memory controller. In order to scan the storage unit, the memory controller may generate a scan command for the storage unit and send the scan command to the storage device. In some embodiments, the scan command may be in the form of a read command. From the perspective of the memory controller, the scan command is generated by the memory controller, not received from the host. From the perspective of the storage device, the scan command may be a memory read command, similar to a memory read command sent or requested by the host (also referred to as a conventional memory read command or a host memory read command). In some embodiments, the storage device may not be able to distinguish the memory scan command from the conventional memory read command. In some embodiments, the storage device can distinguish between the memory scan command and the conventional memory read command because the two commands can use different command codes. In some embodiments, multiple adjacent conventional memory read commands can use random addresses, and multiple adjacent memory scan commands can use continuous addresses. In some embodiments, each memory read command can return a result indicating how many bits were not read correctly. The number of bits that were not read correctly can be referred to as a fail bit count (Fail Bit Count, FBC). The FBC can be based on a portion or unit of the storage unit that has been scanned. For example, the codeword is scanned to generate the FBC of the codeword. The scan results may indicate that some Vt drift has occurred on the memory cell. For example, a small number of bit errors may indicate that the memory cell has no Vt drift or a small Vt drift. A large number of bit errors may indicate that there is a significant Vt drift on the memory cell.

[0036] When the host is idle (e.g., the host is not sending memory commands to the memory controller), media scanning may not affect the QoS of the storage device. If possible, the memory controller can scan as many memory cells as the memory controller is capable of performing (e.g., if the storage device is powered on and has a functioning power supply). When the host requests to read or write to the storage device, the storage system receives commands from the host (e.g., Figure 4 402). In this case, the media scan may increase the latency of the storage device's response to the host's regular memory read commands and regular memory write commands. In order to reduce this latency and maintain the QoS of the storage device, the storage system may spread or distribute the scan among the operations generated in response to the host commands.

[0037] In some embodiments, the memory controller forwards the host's commands (e.g., conventional memory read commands and conventional memory write commands) to the storage device. During the media scan, the memory controller may insert one or more scan commands among the conventional memory read commands and conventional memory write commands that the memory controller sends to the storage device. As an example embodiment, the memory controller may evenly distribute the scan commands among the host's commands so that the scan commands are dispersed among the host's commands in a uniform manner. As another example embodiment, the memory controller may distribute the scan commands among the host's commands in an uneven or uneven manner, for example based on the computational load of the operations performed by the storage device, to reduce such delays and maintain the QoS of the storage device.

[0038] In some implementations, the scan command or media scan is managed by a Data Management (DM) layer of the firmware of the memory controller.

[0039] In some embodiments, the scan command is volume-based (e.g., page-based). For example, each scan command may cause a read operation of a fixed number of memory cells (e.g., a page of memory cells) of the storage device. If a memory cell is not in a good state (e.g., it has significant Vt drift), the memory read operation will take longer because more than one read attempt is triggered by the initial read error that triggers the read error recovery process. In this case, the media scan based on a fixed number of memory cells may cause unexpected delays in the storage device's response to the host.

[0040] In some embodiments, the scan command is time-based. For example, each time-based scan command can cause a read operation to the storage device within a fixed time period. Although each time-based scan executes the same amount of time, it may scan or read a different number of storage units within the same amount of time. If the fixed time period has passed, the media scan will be paused even if the storage unit was not read correctly. The storage device may return after the scan command to respond to the next command (e.g., a regular memory read operation or a regular memory write operation from the host). When it is time to perform the next scheduled scan operation, the storage device can continue the media scan from the previously unsuccessful storage unit during another fixed time period.

[0041] Figure 5 A time-based media scan is shown in accordance with some aspects of the present disclosure. Memory operations 500 illustrate a plurality of memory operations that the memory controller sends to a storage device as the memory controller performs both a media scan and an operation requested by a host. In some embodiments, the memory controller may first determine a media scan frequency based on the total number of storage cells in the storage device and the MS_TIME_INTERVAL. In this example, the memory controller determines to perform a 2 μ second (μs) scan every 1000 μs to scan the entire storage device within the MS_TIME_INTERVAL. The memory controller may receive a read command 502 and a write command 504 from the host. The memory controller may then forward the read command 502 and the write command 504 to the storage device. As shown in FIG. Figure 5 As shown, each time period in time periods 512, 514, and 516 represents a time period of 1000 μs. Every 1000 μs, the memory controller inserts a 2 μs scan into the host's command and sends both the scan command and the host's command to the storage device. In this example, the 2 μs scan is located at the end of every 1000 μs. In some other embodiments, the 2 μs scan may be located elsewhere (e.g., at the beginning or middle of a 1000 μs cycle). In this example, the interval between two adjacent 2 μs scans is always 998 μs. In some embodiments, the interval between two adjacent 2 μs scans may vary, as long as a 2 μs scan occurs every 1000 μs.

[0042] In some embodiments, if the storage system knows that some storage cells may experience faster Vt drift, the storage system may scan these storage cells more frequently by assigning smaller MS_TIME_INTERVAL to these storage cells. In some embodiments, the storage device may divide the storage cells of the storage device into multiple regions or groups. Multiple regions or groups may have different Vt probabilities or levels. These groups of storage cells may use different MS_TIME_INTERVALs.

[0043] In some embodiments, the MS_TIME_INTERVAL may be determined based on an electrical distance (ED) between a memory cell and its driver (e.g., a bit line driver or a word line driver connected to the memory cell) or one or more other metrics. ED may not be the physical distance between the memory cell and the driver. In some embodiments, ED may be determined based on a conductive transmission line between the memory cell and the driver, a resistance of the conductive transmission line, and / or electronic components between the memory cell and the driver. Memory cells with different EDs may receive different levels of voltage or current. These voltage or current differences may accumulate and cause various Vt drifts in the memory cells. For example, memory cells with shorter EDs may tend to have faster or more significant Vt drifts.

[0044] Figure 6 An example of grouping storage cells based on ED according to some aspects of the present disclosure is shown. Figure 6 The memory array 600 in FIG. 1 has a word line driver 610 and a bit line driver 612. The word line driver 610 and the bit line driver 612 are located in the middle of the memory array 600 and divide the memory array 600 into four sub-arrays 602, 604, 606, and 608. In this example, placing the drivers in the middle of the memory array can optimize the performance of the memory array by reducing the distance between the memory cells and the drivers. In some other cases, the drivers of the memory array can be placed in different positions (e.g., on the side of the memory array). Reference Figure 6, the storage cells of the storage array 600 can be divided into three groups 614, 616 and 618. Each group can have its own ED, which can be an average, weighted average or other measure of one or more EDs of the storage cells in each group. As an example, the ED of group 614 is shorter than the ED of group 616, and the ED of group 616 is shorter than the ED of group 618. Therefore, groups 614, 616 and 618 can use different MS_TIME_INTERVAL. For example, the MS_TIME_INTERVAL of group 614 is less than the MS_TIME_INTERVAL of group 616, and the MS_TIME_INTERVAL of group 616 is less than the MS_TIME_INTERVAL of group 618. As an example, the MS_TIME_INTERVAL of group 614 can be set to 16 hours, the MS_TIME_INTERVAL of group 616 can be set to 24 hours, and the MS_TIME_INTERVAL of group 618 can be set to 32 hours. Other values ​​can be assigned to the MS_TIME_INTERVAL of different groups. Therefore, the memory cells in group 614 are scanned most frequently among the three groups, while the memory cells in group 618 are scanned least frequently among the three groups. This can help balance the QoS of the three groups and improve the QoS of the entire memory device because the memory cells in group 614 may experience faster Vt drift compared to the other two groups because a larger voltage or current is applied to the memory cells in group 614.

[0045] As an example implementation of classifying storage units into groups, Figure 6 As shown, the memory cells are classified into groups based on the ED (ED_b) between the memory cell and the bit line driver, the ED (ED_w) between the memory cell and the word line driver, and two thresholds T1 and T2. If ED_b+ED_w is less than T1, the memory cell belongs to group 614. If ED_b+ED_w is greater than T1 and less than T2, the memory cell belongs to group 616. If ED_b+ED_w is greater than T2, the memory cell belongs to group 618. In some embodiments, different grouping criteria can be applied. For example, the grouping criteria can be based on another function of ED_b and ED_w, including the maximum value of ED_b and ED_w, the minimum value of ED_b and ED_w, the average value of ED_b and ED_w, and the square root of ED_b×ED_b+ED_w×ED_w. In addition, different thresholds can be used for grouping.

[0046] In some other implementations, MS_TIME_INTERVAL may be determined based on one or more criteria or metrics other than ED, as long as the criteria or metrics affect the Vt drift of the memory cell.

[0047] Figure 7 700 is a swim lane diagram of an example method 700 for media scanning according to some aspects of the present disclosure. The method 700 may be performed by a host (e.g., Figure 2 host 208) and a storage system (e.g., Figure 2 Method 700 will be described as being performed by a storage system having a memory controller and a storage device appropriately programmed according to the present disclosure. The memory controller is coupled to the storage device and a host. The storage device includes a storage cell array having a plurality of storage cells. In some embodiments, some or all of the operations in method 700 may be based on a combination of Figure 2-Figure 6 The operations shown in method 700 may not be exhaustive, and other operations may be performed before, after, or between any of the illustrated operations. In addition, some of these operations may be performed simultaneously or in parallel. Figure 7 The different orders are shown in .

[0048] At 702, the memory controller determines one or more scan cycles. The memory controller may determine only one scan cycle for all memory cells in the memory device. Figure 6 ), the memory cells in the memory device are divided into a plurality of groups. The memory controller may determine a plurality of different scan cycles and assign each scan cycle to a corresponding memory cell group.

[0049] At 704, the memory controller schedules a scan in each of the one or more scan cycles. The memory controller may determine how many scans are required to cover one or more groups of memory cells in the memory device. For each of the one or more groups of memory cells, the number of scans may be determined based at least on the scan cycle of the group and the number of memory cells in the group.

[0050] At 706, the host sends a command to the memory controller in each of the one or more scan cycles. The command may be a conventional memory operation command and may include at least one of: a memory read command and a memory write command.

[0051] At 708, the memory controller receives a command from the host.

[0052] At 710, the memory controller inserts a scan command into the commands received by the memory controller from the host. The scan command may be Figure 5The time-based memory read command described in . The time-based memory read command can be evenly inserted into a regular memory read command, a memory write command, or other commands received from a host. The memory controller then sends the scan command and the command from the host to the storage device.

[0053] At 712, the storage device receives a scan command and a command from the host. The storage device performs corresponding scan operations and conventional memory operations based on the command from the host. For example, the storage device performs time-based memory read operations that are evenly inserted into conventional memory read commands and conventional memory write commands received from the host. In some embodiments, in the operation according to the command from the host, every adjacent two scans in the plurality of scans are performed at even intervals within a first scan cycle. In addition, the storage device determines the storage cells identified in each scan command and scans the storage cells by reading data from the storage cells.

[0054] At 714 , the storage device returns the scan result or the read result to the memory controller.

[0055] At 716 , the memory controller receives scan results or read results from the storage device.

[0056] At 718, the memory controller determines a fail bit count (FBC) in the read result. The FBC indicates how many bits were not read correctly when the memory device read the portion of the plurality of memory cells identified in the scan commands at 710 and 712. The portion of the plurality of memory cells can be configured in a flexible manner. For example, the portion of the plurality of memory cells can refer to memory cells connected by word lines. Sometimes, the portion of the plurality of memory cells can be a codeword. In another example, the portion of the plurality of memory cells refers to a memory block. In another example, the portion of the plurality of memory cells refers to a physical memory page. In yet another example, the portion of the plurality of memory cells refers to a subarray (e.g., Figure 3 subarray 308).

[0057] At 720, the memory controller compares the FBC to a refresh threshold. The refresh threshold may be referred to as MS_RF_FBC_TH. A large FBC may indicate that the corresponding memory cell is not in a good state due to Vt drift and therefore may need to be refreshed. If the FBC is greater than the refresh threshold, the memory determines that the corresponding memory may have a significant Vt drift (724) and therefore sends a refresh command to the memory device. In an example, the refresh threshold is 40 bits in the codeword.

[0058] At 726, the memory device receives a refresh command, for example, from a memory controller. A refresh command is a command requesting the memory device to read data from a memory cell and write the same data back to the memory cell. Upon receiving the refresh command, the memory device refreshes the memory cell identified by the refresh command. By performing a memory write operation, the memory cell reprograms its set Vt and resets Vt to its original value.

[0059] In some embodiments, a refresh command is triggered in response to determining that the FBC is greater than a refresh threshold. The refresh command can be executed to write correct data to the storage unit. For example, in response to determining that the scan result or the read result indicates erroneous or damaged data, the memory controller can, for example, based on ECC or other error recovery methods, correct the scan result or the read result from the storage device to obtain correct data. The memory controller sends a write command including the correct data and the corresponding address to the storage device. The storage device receives the write command and performs a write operation based on the write controller to refresh the storage unit.

[0060] In some cases, the FBC may be so large that it exceeds the error correction capability of the error correction code (ECC). For example, the FBC is 80, but the ECC error correction capability is only 60 per codeword. In this case, due to Vt drift, the data stored in the storage cell is too severely damaged to be recovered. Therefore, uncorrectable error correction code (UECC) may occur. In such a scenario, in some embodiments, the memory controller not only sends a refresh command to the storage device, it can also determine that the storage cell should be scanned more frequently to avoid possible unrecoverable read errors in the future. The memory controller can reduce or shorten the scan cycle of the group in which the storage cell generates a large FBC. A new scan cycle can be applied after the current scan cycle has passed.

[0061] At 730, the memory controller checks whether all storage units in the entire storage device have been scanned. If so, the memory controller ends the current scanning cycle and waits to perform operations in the next scanning cycle. If there are still storage units that have not been scanned in the storage device, the method returns to 708, and the memory controller continues to scan the remaining storage units according to the schedule in 704.

[0062] In some embodiments, the memory controller can dynamically change the media scan schedule within the current scan cycle based on the memory operation commands received by the memory controller from the host. Specifically, the memory controller can remove some unnecessary scan commands from the media scan schedule within the current scan cycle. For example, if a memory write command sent from the host to the memory controller requests the storage device to write data to a storage unit, and the storage unit has not been scanned within the current scan cycle, the memory controller can treat the storage unit as if the storage unit has been refreshed. There is no need to scan the storage unit during the media scan because the memory write operation will reset the set Vt and reset Vt of the storage unit anyway. This dynamic media scan schedule adjustment can reduce the scan commands and refresh commands sent to the storage device, and therefore can improve the QoS of the storage device, including delays in memory read and write operations.

[0063] In another example, if a memory read command from a host to a memory controller requests a storage device to read data from a storage unit, and the storage unit has not been scanned in the current scan cycle, the memory controller may not schedule and send a scan command for the storage unit. The memory controller may treat a memory read command for a conventional memory operation as a scan command and receive a read result from the storage device for the storage unit. The memory controller may check the read result and determine whether to send a refresh command and whether to reduce the scan cycle in a manner similar to the above discussion.

[0064] exist Figure 8 In another example shown, the memory controller 206 and the plurality of storage devices 204 may be integrated into a storage device 800. The storage device 800 may also include a storage device 800 that connects the storage device 800 to a host (eg, Figure 2 The storage device 800 is coupled to the host 208 in the storage device 800. In some embodiments, the storage capacity and / or operating speed of the storage device 800 is greater than the storage capacity and / or operating speed of the memory card. In some embodiments, the storage device 800 is a storage class memory (SCM) device. The storage device 800 can be an SSD. The interface 802 can be an SSD connector or a peripheral component interconnect express (PCI-E) interface.

[0065] Although some embodiments in the present disclosure are described in the context of PCM cells to mitigate data corruption caused by Vt drift, it should be appreciated that such description is not limited thereto and may also be applicable to memory devices or storage devices using any other technology known in the art with similar technical problems. For example, some embodiments in the present disclosure may be applied to dynamic random access memory (DRAM) devices to fix charge leakage problems or be applied to NAND flash memory for data retention purposes.

[0066] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular implementation. Certain features described in this specification in the context of separate implementations may also be implemented in combination, in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations, either individually or in any subcombination. In addition, although previously described features may be described as operating in certain combinations, or even initially claimed as such, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may involve subcombinations or variations of subcombinations.

[0067] As used in this disclosure, the terms "a", "an" or "the" are intended to include one or more than one, unless the context clearly dictates otherwise. The term "or" is used to refer to a non-exclusive "or" unless otherwise specified. "At least one of A and B" has the same meaning as "A, B, or A and B". In addition, the words or terms used in this disclosure, and not otherwise defined, are for descriptive purposes only and not limiting. Any use of section headings is intended to aid in reading the document and should not be construed as limiting; information related to a section heading may appear within or outside that particular section.

[0068] As used in this disclosure, the terms "about" or "approximately" can allow for a degree of variability in values ​​or ranges, for example, within 10%, within 5%, or within 1% of a stated value or a stated range limit.

[0069] As used in this disclosure, the term "substantially" means a majority or majority, at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0070] Values ​​expressed in range format should be interpreted in a flexible manner to include not only the values ​​explicitly cited as range limits, but also all individual values ​​or subranges encompassed within the range, as if each value and subrange were explicitly cited. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3% and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the specified range. Unless otherwise specified, the statement "X to Y" has the same meaning as "approximately X to approximately Y". Similarly, unless otherwise specified, the statement "X, Y or Z" has the same meaning as "about X, about Y, or about Z".

[0071] Specific embodiments of the subject matter have been described. Other embodiments, variations, and arrangements of the described embodiments are within the scope of the appended claims and will be apparent to those skilled in the art. Although operations are described in a particular order in the drawings or claims, the operations need not be performed in the particular order shown or in a sequential order, or all illustrated operations need not be performed (some operations may be considered optional) to achieve the desired results. In certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and is considered appropriate.

[0072] Furthermore, the separation or integration of the various system modules and components in the above-described embodiments is not required in all embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0073] Therefore, the previously described example embodiments do not define or limit the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

[0074] According to one aspect of the present disclosure, a method for a storage system is disclosed. The method includes: receiving a command from a host coupled to the storage system, wherein the storage system includes a storage device, the storage device includes a storage cell array, and the storage cell array includes a plurality of storage cells. The method also includes: performing an operation on the storage device based on the command. The method also includes: scanning at least a first group of storage cells of the storage cell array by performing a plurality of scans within a first scanning cycle during the operation. The foregoing and other described aspects of the present disclosure may each, optionally, include one or more of the following features.

[0075] In some embodiments, the method further includes: obtaining a scan result, the scan result including the FBC of a portion of the plurality of memory cells. The method further includes: determining whether the FBC is greater than a refresh threshold. The method further includes: in response to at least the FBC being greater than the refresh threshold, refreshing the portion of the plurality of memory cells to restore the voltage of the data stored in the portion of the plurality of memory cells.

[0076] In some implementations, the method further includes reducing the first scanning period when it is determined that the FBC exceeds the ECC capability.

[0077] In some embodiments, the method further includes: scanning a second group of memory cells of the memory cell array in a second scanning period, wherein the first scanning period is determined based on a first electrical distance of the first group of memory cells, and the second scanning period is determined based on a second electrical distance of the second group of memory cells.

[0078] In some embodiments, the first scanning period is shorter than the second scanning period based on that the first electrical distance of the first group of memory cells is smaller than the second electrical distance of the second group of memory cells.

[0079] In some embodiments, the plurality of scans are time-based scans, each scan in the plurality of scans occupies a fixed scan interval, and the plurality of scans and the fixed scan interval are determined based on the first scan period and a size of the first group of storage units.

[0080] In some embodiments, every two adjacent scans in the plurality of scans are performed at even intervals within a first scanning period during operation.

[0081] In some implementations, the command includes at least one of: a memory read command and a memory write command.

[0082] In some embodiments, the plurality of memory cells are PCM cells.

[0083] In some embodiments, scanning at least a first group of memory cells of the memory cell array includes scanning all memory cells of the entire memory device.

[0084] According to another aspect of the present disclosure, a storage system is disclosed. The storage system includes a storage device, the storage device includes a storage cell array, wherein the storage cell array includes a plurality of storage cells. The storage system also includes a memory controller coupled to the storage device. The memory controller is configured to: perform an operation, the operation including receiving a host command from a host coupled to the memory controller. The operation also includes: sending the host command to the storage device. The operation also includes: sending a first number of scan commands to the storage device to scan a first group of storage cells of the storage device within a first scan cycle, wherein the first number of scan commands are distributed among the host commands. The foregoing and other described aspects of the present disclosure may each optionally include one or more of the following features.

[0085] In some implementations, each scan command in the first number of scan commands is in the form of a memory read command.

[0086] In some embodiments, the operation also includes: receiving a scan result from a storage device, wherein the scan result includes an FBC of a portion of the plurality of storage cells; determining whether the FBC is greater than a refresh threshold; and sending a refresh command to the storage device to restore a voltage of data stored in a portion of the plurality of storage cells in response to at least the FBC being greater than the refresh threshold.

[0087] In some embodiments, the operation also includes: sending a second number of scan commands to the memory cell array to scan a second group of memory cells of the memory device within a second scan cycle, wherein the first scan cycle is determined based on a first electrical distance of the first group of memory cells, the second scan cycle is determined based on a second electrical distance of the second group of memory cells, and based on the first electrical distance being less than the second electrical distance, the first scan cycle is shorter than the second scan cycle.

[0088] In some embodiments, the plurality of memory cells are PCM cells.

[0089] In some embodiments, the storage device is a SCM device.

[0090] According to another aspect of the present disclosure, a storage system is disclosed. The storage system includes a storage device, which includes a storage cell array, wherein the storage cell array includes a plurality of storage cells. The storage system also includes a memory controller coupled to the storage device. The memory controller includes at least one processor and at least one non-transitory computer-readable storage medium. At least one non-transitory computer-readable storage medium stores program instructions, which are used to be executed by at least one processor to enable the memory controller to perform operations, the operations including: receiving a host command from a host coupled to the memory controller. The operation also includes sending the host command to the storage device. The operation also includes: sending a first number of scan commands to the storage device to scan a first group of storage cells of the storage device within a first scan cycle, wherein the first number of scan commands are distributed among the host commands. The foregoing and other described aspects of the present disclosure may each and optionally include one or more of the following features.

[0091] In some implementations, each scan command in the first number of scan commands is in the form of a memory read command.

[0092] In some embodiments, the operation also includes: receiving a scan result from a storage device, wherein the scan result includes an FBC of a portion of the plurality of storage cells; determining whether the FBC is greater than a refresh threshold; and sending a refresh command to the storage device to restore a voltage of data stored in a portion of the plurality of storage cells in response to at least the FBC being greater than the refresh threshold.

[0093] In some embodiments, the operation also includes: sending a second number of scan commands to the memory cell array to scan a second group of memory cells of the memory device within a second scan cycle, wherein the first scan cycle is determined based on a first electrical distance of the first group of memory cells, the second scan cycle is determined based on a second electrical distance of the second group of memory cells, and based on the first electrical distance being less than the second electrical distance, the first scan cycle is shorter than the second scan cycle.

[0094] In some embodiments, the plurality of memory cells are PCM cells.

[0095] In some embodiments, the storage device is a SCM device.

[0096] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium is disclosed. The non-transitory computer-readable storage medium includes program instructions, which are used to be executed by at least one processor of a storage system to cause the storage system to perform an operation, the operation including: receiving a command from a host coupled to the storage system, wherein the storage system includes a storage device, the storage device includes a storage cell array, and the storage cell array includes a plurality of storage cells. The operation also includes: performing a memory operation on the storage device based on the command. The operation also includes: scanning at least a first group of storage cells of the storage cell array by performing multiple scans within a first scan cycle in the memory operation. The foregoing and other described aspects of the present disclosure may each and optionally include one or more of the following features.

[0097] In some embodiments, the operation further includes: obtaining a scan result, the scan result including the FBC of a portion of the plurality of memory cells. The operation further includes: determining whether the FBC is greater than a refresh threshold. The operation further includes: in response to at least the FBC being greater than the refresh threshold, refreshing the portion of the plurality of memory cells to restore a voltage of data stored in the portion of the plurality of memory cells.

[0098] In some embodiments, the operation further includes: scanning a second group of memory cells of the memory cell array in a second scanning period, wherein the first scanning period is determined based on a first electrical distance of the first group of memory cells and the second scanning period is determined based on a second electrical distance of the second group of memory cells.

[0099] In some embodiments, the plurality of memory cells are PCM cells.

[0100] In some embodiments, the storage device is a SCM device.

[0101] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0102] The breadth and scope of the present disclosure should not be limited by any of the above-described example embodiments, but should be limited only in accordance with the following claims and their equivalents. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A method for a storage system, comprising: receiving a command from a host coupled to the storage system, wherein the storage system includes a storage device, the storage device includes a storage cell array, and the storage cell array includes a plurality of storage cells; performing an operation on the storage device based on the command; and At least a first group of memory cells of the memory cell array is scanned by performing a plurality of scans within a first scan period in the operation.

2. The method according to claim 1, further comprising: obtaining scan results, the scan results comprising fail bit counts (FBCs) of a portion of the plurality of memory cells; Determining whether the FBC is greater than a refresh threshold; as well as In response to at least the FBC being greater than the refresh threshold, the portion of the plurality of memory cells is refreshed to restore a voltage of data stored in the portion of the plurality of memory cells.

3. The method according to claim 2, further comprising: The first scanning period is reduced when it is determined that the FBC exceeds an error correction coding (ECC) capability.

4. The method according to any one of claims 1 to 3, further comprising: A second group of memory cells of the memory cell array is scanned in a second scanning period, wherein the first scanning period is determined based on a first electrical distance of the first group of memory cells, and the second scanning period is determined based on a second electrical distance of the second group of memory cells.

5. The method according to claim 4, wherein: Based on the fact that the first electrical distance of the first group of storage cells is smaller than the second electrical distance of the second group of storage cells, the first scanning period is shorter than the second scanning period.

6. The method according to any one of claims 1 to 5, wherein: The plurality of scans are time-based scans, each of the plurality of scans occupies a fixed scan interval, and the plurality of scans and the fixed scan interval are determined based on the first scan period and a size of the first group of storage units.

7. The method according to any one of claims 1 to 6, wherein: Every adjacent two scans of the plurality of scans are performed at even intervals within the first scanning period during the operation.

8. The method according to claim 1, wherein: The command includes at least one of: a memory read command and a memory write command.

9. The method according to claim 1, wherein: The plurality of memory cells are phase change memory (PCM) cells.

10. The method according to claim 1, wherein: Scanning at least a first group of memory cells of the memory cell array comprises: All storage units of the entire storage device are scanned.

11. A storage system comprising: A storage device, the storage device comprising a storage cell array, wherein the storage cell array comprises a plurality of storage cells; and A memory controller coupled to the memory device, wherein the memory controller is configured to perform operations, the operations comprising: receiving a host command from a host coupled to the memory controller; sending the host command to the storage device; and A first number of scan commands are sent to the storage device to scan a first group of storage units of the storage device within a first scan cycle, wherein the first number of scan commands are distributed among the host commands.

12. The storage system according to claim 11, wherein: Each scan command of the first number of scan commands is in the form of a memory read command.

13. The storage system according to claim 11 or 12, wherein: The operations also include: receiving scan results from the memory device, wherein the scan results include fail bit counts (FBCs) of a portion of the plurality of memory cells; determining whether the FBC is greater than a refresh threshold; and In response to at least the FBC being greater than the refresh threshold, a refresh command is sent to the memory device to restore a voltage of data stored in the portion of the plurality of memory cells.

14. The storage system according to any one of claims 11 to 13, wherein: The operations also include: A second number of scan commands are sent to the memory cell array to scan a second group of memory cells of the memory device within a second scan cycle, wherein the first scan cycle is determined based on a first electrical distance of the first group of memory cells, the second scan cycle is determined based on a second electrical distance of the second group of memory cells, and based on the first electrical distance being less than the second electrical distance, the first scan cycle is shorter than the second scan cycle.

15. The storage system according to claim 11, wherein: The plurality of memory cells are phase change memory (PCM) cells.

16. The storage system according to claim 11, wherein: The storage device is a storage class memory (SCM) device.

17. A non-transitory computer-readable storage medium comprising programmable instructions for execution by at least one processor of a storage system to cause the storage system to perform operations comprising: receiving a command from a host coupled to the storage system, wherein the storage system includes a storage device, the storage device includes a storage cell array, and the storage cell array includes a plurality of storage cells; performing a memory operation on the memory device based on the command; and At least a first group of memory cells of the memory cell array is scanned by performing a plurality of scans within a first scan cycle in the memory operation.

18. The non-transitory computer-readable storage medium of claim 17, wherein: The operations also include: obtaining scan results, the scan results comprising fail bit counts (FBCs) of a portion of the plurality of memory cells; determining whether the FBC is greater than a refresh threshold; and In response to at least the FBC being greater than the refresh threshold, the portion of the plurality of memory cells is refreshed to restore a voltage of data stored in the portion of the plurality of memory cells.

19. The non-transitory computer-readable storage medium according to claim 17 or 18, wherein: The operations also include: A second group of memory cells of the memory cell array is scanned in a second scanning period, wherein the first scanning period is determined based on a first electrical distance of the first group of memory cells, and the second scanning period is determined based on a second electrical distance of the second group of memory cells.

20. The non-transitory computer-readable storage medium according to any one of claims 17-19, wherein: The plurality of memory cells are phase change memory (PCM) cells.

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