Method, device and cell structure for testing parameters of trench field effect transistor

Abstract

The present application relates to a method and device for testing parameters of a trench field effect transistor, and a cell structure. The method comprises: applying different levels of gate-source voltage to each of a plurality of cell structures, obtaining a relationship curve between drain-source current and drain-source voltage, and calculating the on-resistance corresponding to different levels of gate-source voltage. The method for testing parameters of a trench field effect transistor can effectively analyze the performance of a trench field effect transistor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method and device for testing parameters of a trench field effect transistor, and a cellular structure. Background Art

[0002] The core part of the metal oxide semiconductor field effect transistor (MOSFET) is the oxide semiconductor interface. The characteristics of the oxide semiconductor interface located at the channel directly affect the channel mobility of the device, affect the channel on-state characteristic resistance of the MOSFET device, and further affect the on-state characteristic resistance of the MOSFET device. Therefore, it is expected to accurately evaluate the channel mobility of the device.

[0003] At present, MOSFET devices are mainly divided into two types: planar gate MOSFET and trench gate MOSFET. Among them, trench gate MOSFET has a higher channel density and eliminates the JFET region resistance, significantly reducing the on-state characteristic resistance of the device.

[0004] For semiconductor devices such as MOSFET, device reliability is an important indicator for evaluating device performance. Taking MOSFET as an example, the life of MOSFET gate dielectric under electrothermal stress and the threshold drift caused by electrothermal stress are important parameters for evaluating MOSFET device performance.

[0005] The gate dielectric layer and gate dielectric layer of a general planar gate MOSFET are all in one plane with the semiconductor surface, and the material properties are consistent overall. However, the channel and gate dielectric of a general trench gate MOSFET are located inside the trench, and the gate dielectric and gate dielectric and semiconductor surface exist on three planes in space. In order to accurately evaluate the reliability of the gate dielectric, etc., it is necessary to separate the planes. Summary of the invention

[0006] Based on this, it is necessary to provide a method and equipment, and a cellular structure for testing the parameters of trench gate MOSFETs in order to address the problem that the parameters of trench gate MOSFETs are difficult to accurately evaluate.

[0007] The present application provides a method for testing parameters of a trench field effect transistor, the method comprising: applying different levels of gate-source voltage to each of a plurality of cell structures; V GS , and obtain the relationship curve between drain-source current and drain-source voltage to calculate the on-resistance corresponding to different levels of gate-source voltage R t; Wherein, the cell structure includes a channel layer, a gate electrode, a gate dielectric layer, a first contact area and a second contact area, the channel layer includes a first step and a second step protruding from the first step along a first direction, the gate electrode includes a trench gate stacked on the first step and a plane gate stacked on the second step, the first contact area extends into the first step and extends into the second step along a second direction perpendicular to the first direction, the second contact area extends into the second step and is spaced from the sidewall of the second step, a sidewall length is provided between the planar dielectric portion of the planar gate corresponding to the gate dielectric layer and the first contact area, and a surface length is provided between the trench dielectric portion of the trench gate corresponding to the gate dielectric layer and the second contact area.

[0008] The method for testing parameters of trench field effect transistors of the present application can effectively analyze the performance of trench field effect transistors. Based on the two trenches of the cell structure, the sidewall trench mobility and the planar trench mobility can be separated later.

[0009] The present application provides a method for testing parameters of a trench field effect transistor, the method comprising: applying a gate-source voltage to each of a plurality of groups of cell structures at the same test environment temperature, and setting a failure standard leakage current, wherein the gate-source voltages of different groups are different; the cell structure comprises a channel layer, a gate electrode, a gate dielectric layer, a first contact region and a second contact region, the channel layer comprises a first step and a second step protruding from the first step along a first direction, the gate electrode comprises a trench gate stacked on the first step and a planar gate stacked on the second step, the first contact region extends into the first step and protrudes from the first step along a direction perpendicular to the first direction The gate dielectric layer comprises a first contact region, a second contact region, a second dielectric portion of the gate dielectric layer corresponding to the first contact region, a surface length between the trench dielectric portion of the trench gate of the gate dielectric layer and the second contact region, and the surface lengths of the plurality of cellular structures in each group are different from each other; a characteristic life of the cellular structure is obtained according to the failure time of the cellular structure under the corresponding gate-source voltage; characteristic parameters of the gate dielectric layer are extracted according to a time-dependent breakdown defect generation model; and a working life of the gate dielectric layer is obtained.

[0010] The method for testing parameters of a trench field effect transistor of the present application can obtain the working life of a gate dielectric layer, which is then conducive to more accurately analyzing the performance of the trench field effect transistor.

[0011] The present application provides a method for testing parameters of a trench field effect transistor, the method comprising: applying a first gate-source voltage to a cellular structure according to a time series; wherein the cellular structure comprises a channel layer, a gate electrode, a gate dielectric layer, a first contact region and a second contact region, the channel layer comprises a first step and a second step protruding from the first step along a first direction, the gate electrode comprises a trench gate stacked on the first step and a planar gate stacked on the second step, the first contact region extends into the first step and extends into the second step along a second direction perpendicular to the first direction, the second contact region extends into the second step and has a gap with the side wall of the second step; in response to the end of a period of pressure application time in the time series, applying a drain-source voltage and a second gate-source voltage to test a transfer curve of the cellular structure and obtain a time-based threshold voltage curve; and obtaining the threshold stability of the channel of the cellular structure.

[0012] The method for testing parameters of a trench field effect transistor of the present application can obtain the threshold stability of the channel, which is then conducive to more accurately analyzing the performance of the trench field effect transistor.

[0013] The present application provides a device for testing parameters of a trench field effect transistor, the device comprising: a memory storing a computer program; and a processor, which implements the steps of the aforementioned method when executing the computer program.

[0014] By connecting the gate electrode, the first contact region and the second contact region of the cell structure to the circuit, the cell structure can be tested, and then the parameters of the trench field effect transistor can be tested.

[0015] The present application provides a computer-readable storage medium storing a computer program, which implements the steps of the aforementioned method when executed by a processor.

[0016] The present application provides a cellular structure, which includes: a channel layer, including a first step and a second step protruding from the first step along a first direction; a first contact area, extending into the first step and extending into the second step; a second contact area, extending into the second step and having a gap with the side wall of the second step; a gate electrode, including a trench gate stacked on the first step and a planar gate stacked on the second step; and a gate dielectric layer, used to insulate the gate electrode from the channel layer.

[0017] By setting the first contact area at the first step and the second contact area at the second step, and setting the gate electrode, the channel is divided into two sections that can be designed to the required size. After the cellular structure is connected to the test equipment, it can be used to test the parameters of the trench field effect transistor. Based on the two sections of the channel, the sidewall trench mobility and the planar trench mobility can be separated; in addition, the cellular structure can controllably design parameters to achieve different performances.

[0018] The present application provides a device for testing parameters of a trench field effect transistor, the device comprising a plurality of the aforementioned cellular structures; the gate dielectric layer comprising a trench dielectric portion corresponding to a trench gate and a planar dielectric portion corresponding to a planar gate, a surface length being provided between the trench dielectric portion and a second contact region, and a sidewall length being provided between the planar dielectric portion and a first contact region; and a plurality of surface lengths of the plurality of cellular structures being different from one another.

[0019] By setting the surface lengths of the plurality of cell structures to be different from each other, the difference in surface length can be used to test the parameters of the trench field effect transistor, which is especially helpful to decouple the sidewall channel mobility and the planar channel mobility.

[0020] The present application provides a method for manufacturing a cell structure, which manufacturing method includes: forming a channel layer; forming a groove extending into the channel layer along a first direction; forming a first contact area extending from the bottom wall of the groove into the channel layer and extending into the side wall of the groove, forming a second contact area extending into the channel layer and having a gap with the groove; forming a gate dielectric layer covering the channel layer; and forming a gate electrode, the gate electrode including a trench gate extending into the groove and a planar gate stacked on the second contact area.

[0021] The method for manufacturing a cellular structure of the present application can manufacture a cellular structure having both a planar channel and a sidewall channel.

[0022] The present application provides a photolithography assembly, which is used in the steps of the aforementioned method for manufacturing a cellular structure. The photolithography assembly includes a groove plate and a gate electrode plate. The groove plate includes a groove pattern. The gate electrode pattern of the gate electrode plate includes a groove gate region corresponding to the groove pattern and a planar gate region extending from the groove pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A test structure diagram for evaluating the channel mobility of a planar gate field effect transistor according to a comparative example;

[0024] Figure 2 A test structure diagram for evaluating channel mobility of a trench gate field effect transistor according to a comparative example;

[0025] Figure 3 A test structure diagram for evaluating channel mobility of a trench gate field effect transistor according to a comparative example;

[0026] Figure 4 A schematic structural diagram of a device for testing parameters of a trench field effect transistor according to the present application;

[0027] Figure 5 A schematic circuit diagram of a cell structure of the present application;

[0028] Figure 6A schematic structural diagram of a device for testing parameters of a trench field effect transistor according to the present application;

[0029] Figure 7 A schematic structural diagram of a device for testing parameters of a trench field effect transistor according to the present application;

[0030] Figure 8 A schematic structural diagram of a device for testing parameters of a trench field effect transistor according to the present application;

[0031] Fig. 9 A schematic block diagram of a device for testing parameters of a trench field effect transistor according to the present application;

[0032] Fig.10 A schematic flowchart of a method for testing parameters of a trench field effect transistor according to the present application;

[0033] Fig.11 It is the scatter plot and fitting curve diagram of on-resistance;

[0034] Fig.12 A scatter diagram of sidewall channel mobility obtained by the method for testing parameters of trench field effect transistors of the present application and a curve diagram of sidewall channel mobility obtained by simulation;

[0035] Fig.13 A schematic flowchart of a method for testing parameters of a trench field effect transistor according to the present application;

[0036] Fig.14 A schematic flowchart of a method for testing gate structure reliability of the present application;

[0037] Fig.15 A schematic flowchart of a method for testing the threshold stability of a channel according to the present application;

[0038] Fig.16 A time series diagram of the threshold voltage drift test of the present application;

[0039] Fig.17 A schematic flowchart of a method for manufacturing a cellular structure of the present application;

[0040] Fig.18 A schematic diagram of the structure of the photomask assembly of the present application;

[0041] Fig.19 This is a schematic diagram of the structure of the photomask assembly of the present application.

[0042] Description of reference numerals: 1, first layer; 10, substrate electrode; 2, second layer; 21, first step; 22, second step; 3, gate electrode; 31, planar gate; 32, trench gate; 4, gate dielectric layer; 41, planar dielectric portion; 42, trench dielectric portion; 43, first dielectric portion; 44, second dielectric portion; 5, first contact region; 50, first electrode; 6, second contact region; 60, second electrode; 7, source contact region; 8, substrate;

[0043] 100, field effect transistor; 200, device for testing parameters of trench field effect transistor; 210, cell structure; 300, equipment for testing parameters of trench field effect transistor; 310, circuit; 311, first voltage source; 312, second voltage source; 313, switch; 320, processor; 330, memory; 400, photolithography assembly; 410, trench plate; 4101, trench pattern; 420, gate electrode plate; 4201, gate electrode pattern; 430, contact area plate; 440, gate dielectric plate; 450, source contact plate; 460, insulating dielectric plate. DETAILED DESCRIPTION

[0044] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments of the following disclosed implementation methods.

[0045] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0046] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0047] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. Exemplarily, the first cellular structure may also be referred to as the second cellular structure, and the second cellular structure may also be referred to as the first cellular structure. In the description of the present application, "multiple" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0048] In this application, unless otherwise clearly specified and limited, the terms "connected", "connected", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a flexible connection, or a rigid connection along at least one direction; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or directly connected with the presence of an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. The terms "install", "set", "fixed", etc. can be broadly understood as connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0049] The terms "layer" and "region" used in this application refer to a material portion that includes a certain area and has a certain thickness. The layer can extend horizontally, vertically and / or along a tapered surface. A layer can be an area of ​​a uniform or non-uniform continuous structure, and its thickness perpendicular to the extension direction may not be greater than the thickness of the continuous structure. A layer can include multiple layers, which can be multiple layers stacked or multiple layers extending discretely. The shapes of various areas and layers in the accompanying drawings and their relative sizes and positional relationships are only exemplary, and may actually deviate due to manufacturing tolerances or technical limitations, and the design can be adjusted according to actual needs.

[0050] refer to Figure 1In the lateral MOSFET design used to test the channel mobility of the planar gate MOSFET, when the field effect transistor 100 is in the on state, the current flows from the drain electrode to the source electrode. The main resistances on the flow path include: the contact resistance between the source and the drain R source and R drain , the sheet resistance of the first source contact region and the first drain contact region R sh and channel resistance R ch , other resistances except the channel resistance can be collectively referred to as other resistances Rs, and the channel mobility is mainly calculated by the channel resistance. In the design of lateral MOSFETs for testing the channel mobility of planar gate MOSFETs, the influence of other resistances on the extraction of channel mobility can be effectively avoided by increasing the channel length in the plane, and the channel mobility can be accurately characterized.

[0051] However, since the channel of the trench gate MOSFET device is generally formed on the trench sidewall, it also includes the drift region resistance in addition to the other resistance components described in the planar gate MOSFET above. R drift And the substrate resistance R sub Etc., specifically Figure 2 The field effect transistor 100 shown in FIG. Moreover, the trench depth of the trench gate MOSFET is generally less than 2 μm, and the channel length is also less than 2 μm. The shorter the channel length, the smaller the channel resistance, and the resistance of other parts may be greater than or equal to the channel resistance, resulting in that the channel mobility cannot be reliably characterized.

[0052] refer to Figure 3 As shown, the channel resistance includes the first channel resistance of the trench sidewall R c1 , the second channel resistance R c2 The third channel resistance at the bottom of the trench R c3 , it is necessary to characterize the channel mobility at the trench sidewall channel position, and it is necessary to accurately characterize and extract the first channel resistance, which is called the sidewall channel resistance R c1 The second channel resistor R c2 , by setting different widths of the bottom of the trench, the third channel resistance is changed R c3 This changes the overall resistance of the device when it is on. R total , due to the sidewall channel resistance R c1 andR c2 It will not change with the change of the bottom width of the trench. When only the bottom width of the trench is changed, the sidewall channel resistance at the sidewall of the trench can be changed by differential means. R c1 , R c2 The third channel resistance at the bottom of the trench R c3 However, the total resistance of the two side walls of the trench, i.e., the first channel resistance, is separated by the above method. R c1 The second channel resistor R c2 The sum of the two sidewall channel resistances, and the first channel resistance cannot be further realized R c1 The second channel resistor R c2 The two sidewall channel resistances are separated. The channel mobility of the trench sidewall characterized at this time is the result of the mobility coupling of the two sidewalls, and decoupling cannot be achieved at present. For some special semiconductor materials such as 4H-SiC materials, the crystal orientation of the trench sidewalls is different. For example, (11-20) and (-1-120) are relative crystal orientations. The channel mobility of the MOSFET channel with this crystal orientation may also be different. Figure 3 The test structure shown cannot achieve the separation of the channel resistance on both sides of the trench, so the mobility of the channel on one side of the trench cannot be accurately evaluated.

[0053] refer to Figure 4 , Figure 4 The device for testing the parameters of the trench field effect transistor in the present application is shown. In an exemplary embodiment, the device 200 for testing the parameters of the trench field effect transistor includes a plurality of cellular structures 210. The device 200 for testing the parameters of the trench field effect transistor may also include a cellular structure 210, and then a plurality of devices 200 for testing the parameters of the trench field effect transistor are used for testing.

[0054] The cell structure 210 of the present application is constructed as a trench metal oxide semiconductor field effect transistor. Two adjacent cell structures 210 along the X-axis direction may have a mirror-symmetrical structure. Specifically, the dimensions of the functional parts of the two cell structures 210 along the X-axis direction may be different. The cell structure 210 has a certain thickness in the vertical direction or projection direction of the XZ plane. W For example, the Z-axis direction may be parallel to the first direction, and the X-axis direction may be parallel to the second direction.

[0055] The cell structure 210 may include a first layer 1 and a second layer 2. For example, the cell structure 210 may further include a substrate 8. The first layer 1 may be an epitaxial layer stacked on the substrate 8 along the Z-axis direction. The second layer 2 may be a channel layer or a base region. The second layer 2 may be affected by a gate voltage to form a channel during operation.

[0056] The material of the substrate 8 may include at least one of silicon carbide, silicon, silicon germanium, germanium, gallium oxide, III-V compounds such as gallium nitride and gallium arsenide. The first layer 1 has a first doping type, and the first doping type may be electron doping or hole doping. The second layer 2 is stacked on the first layer 1, and the second layer 2 has a second doping type different from the first doping type, which may specifically correspond to hole doping or electron doping. Specifically, the second layer 2 includes a first step 21 and a second step 22, and the second step 22 is higher than the first step 21 along the Z-axis direction. On the other hand, it can be considered that a groove is formed in the second layer 2. Exemplarily, the total bottom width of the grooves of the two cellular structures 210 may be greater than 30μm, and the depth of the grooves may be less than 2μm. The first layer 1 and the second layer 2 are used to form a semiconductor structure, and the substrate 8 is also used to form a semiconductor structure.

[0057] The cell structure 210 further includes a gate electrode 3 and a gate dielectric layer 4. The gate electrode 3 includes a trench gate 32 stacked on the first step 21 and a planar gate 31 stacked on the second step 22. The gate electrode 3 may be an integrated structure, and its material may be metal or polysilicon, such as an aluminum electrode. The gate dielectric layer 4 is used to insulate the gate electrode from the second layer 2, and the material of the gate dielectric layer 4 may be an insulating dielectric material such as silicon oxide, aluminum oxide, etc.

[0058] The gate dielectric layer 4 includes a trench dielectric portion 42 corresponding to the trench gate 32 and a planar dielectric portion 41 corresponding to the planar gate 31. The second step 22, the planar dielectric portion 41 and the planar gate 31 are stacked in sequence along the Z-axis direction, and the planar gate 31 is used to form a planar channel at the second step 22; the second step 22, the trench dielectric portion 42 and the trench gate 32 are arranged in sequence along the X-axis direction, and the trench gate 32 is used to form a sidewall channel at the second step 22. The gate dielectric layer 4 also includes a bottom dielectric portion located between the gate electrode 3 and the first step 21.

[0059] Exemplarily, the gate electrode 3 is surrounded by a first dielectric portion 43 and a second dielectric portion 44, and the gate electrode 3 and the dielectric portions surrounding it can constitute a gate structure. The first dielectric portion 43 and the second dielectric portion 44 can constitute an insulating dielectric layer, and the insulating dielectric layer exposes a portion of the gate electrode 3 for electrical connection.

[0060] The cell structure 210 also includes a first contact region 5 and a second contact region 6. The first contact region 5 is stacked on the first step 21, and the first contact region 5 also extends into the second step 22 for a certain distance. The second contact region 6 extends into the second step 22, and the second contact region 6 is spaced from the sidewall of the second step 22 or the trench dielectric portion 42 along the second direction, so that the planar gate 31 can be used to form a planar channel. The sidewall of the second step 22 refers to the sidewall facing the first step 21 or the trench. Along the X-axis direction, the first contact region 5 and the second contact region 6 extend out of the gate structure respectively. In addition, the first contact region 5 and the second contact region 6 are also used to form a semiconductor structure.

[0061] like Figure 4 As shown, the trench dielectric portion 42 and the second contact region 6 have a surface length L1, and the planar dielectric portion 41 and the first contact region 5 have a sidewall length L2. Then, in the XZ plane, the planar channel has a surface length L1, and the sidewall channel has a sidewall length L2.

[0062] The cell structure 210 further includes a first electrode 50 and a second electrode 60. The first electrode 50 contacts the first contact region 5, and there is a gap between the first electrode 50 and the trench gate 32, with a first dielectric portion 43 therebetween. The second electrode 60 contacts the second contact region 6, and there is a gap between the second electrode 60 and the plane gate 31, with a second dielectric portion 44 therebetween.

[0063] The first contact region 5 and the second contact region 6 may both have the first doping type and may be formed to be heavily doped, and then ohmically contact the first electrode 50 and the second electrode 60, respectively. For example, the doping concentration range of the first contact region and the doping concentration range of the second contact region 6 may both be greater than 1e19 cm -3 , for example, 1e19cm -3 to 1e21cm -3 The ohmic contact resistivity between the first electrode 50 and the first contact region 5 is less than or equal to 0.001Ωcm 2 The ohmic contact resistivity between the second electrode 60 and the second contact region 6 is less than or equal to 0.001Ωcm 2 The first electrode 50 and the second electrode 60 can be made of metals such as nickel, aluminum, and titanium.

[0064] Exemplarily, the cell structure 210 further includes a substrate electrode 10 , which is located on a side of the substrate 8 facing away from the first layer 1 .

[0065] By providing the first contact region 5 at the first step 21 and the second contact region 6 at the second step 22, and providing the gate electrode 3, the channel is divided into two sections that can be designed to a desired size. Figure 5The cell structure 210 shown in the figure has the first electrode 50 as the source, the second electrode 60 as the drain, and a drain-source current is formed between the source and the drain. I d When the resistance in the circuit includes: drain contact resistance R drain , a square resistance R sh , Planar channel resistance R ch1 , sidewall channel resistance R ch2 Another square resistance R sh And the source contact resistance R source .

[0066] The cell structure 210 can be used to test the parameters of the trench field effect transistor after being connected to the test circuit; in addition, the cell structure 210 can controllably design parameters to achieve different performances.

[0067] refer to Figure 4 The cell structure 210 further includes a source contact region 7, which penetrates the first contact region 5 and contacts the first electrode 50, and the first electrode 50 serves as a source. The source contact region 7 is also used to laterally cut off the first contact region 5. In the device 200 for testing parameters of a trench field effect transistor, two first contact regions 5 in two adjacent cell structures 210 are separated by a source contact region 7, and the source contact region 7 has a second doping type, so that currents in the two cell structures 210 are formed separately.

[0068] refer to Figure 6 In other embodiments, the source contact region 7 of the cell structure 210 penetrates the second contact region 6 and contacts the second electrode 60. In this configuration, the second electrode 60 serves as a source. In the device 200 for testing parameters of a trench field effect transistor, two second contact regions 6 (one of which is not shown) in two adjacent cell structures 210 are separated by a source contact region 7. The source contact region 7 has a second doping type, so that currents in the two cell structures 210 are formed separately.

[0069] The device 200 for testing the parameters of the trench field effect transistor of the present application may also include a plurality of cellular structures 210 arranged vertically and spaced apart along the XZ plane. The plurality of surface lengths L1 of the plurality of cellular structures 210 are different from each other. For example, the range of the surface length L1 may be 0.5 μm to 10000 μm. Exemplarily, a plurality of cellular structures 210 with a surface length L1 within 50 μm and a difference of 1 μm from each other are designed; a plurality of cellular structures 210 with a surface length L1 within 500 μm and a difference of 10 μm from each other are designed; a plurality of cellular structures 210 with a surface length L1 above 5000 μm and a difference of 5 μm from each other are designed. Surface lengths L1 with different differences may also be set between the plurality of cellular structures 210. By setting the plurality of surface lengths L1 of the plurality of cellular structures 210 to be different from each other, the difference in surface length L1 can be used to test the parameters of the trench field effect transistor, especially to help decouple the sidewall channel mobility and the planar channel mobility.

[0070] Combination Figures 7 to 9 In order to execute the testing method, the device 200 for testing parameters of the trench field effect transistor may be connected to the testing circuit 310 .

[0071] In an exemplary embodiment, the apparatus 300 for testing parameters of a trench field effect transistor of the present application may include a circuit 310 , and the circuit 310 is electrically connected to the cell structure 210 in the device 200 for testing parameters of a trench field effect transistor described above.

[0072] refer to Figure 7 and Figure 8 The circuit 310 may include a first voltage source 311, a high potential end of the first voltage source 311 is electrically connected to the gate electrode 3, and a low potential end of the first voltage source 311 is electrically connected to the first contact region 5 through the first electrode 50. Figure 8 The circuit 310 may further include a second voltage source 312 and a switch 313. The high potential end of the second voltage source 312 may be electrically connected to the second contact region 6 through the second electrode 60, and the low potential end of the second voltage source 312 may be electrically connected to the first contact region 5 through the switch 313 and the first electrode 50. By connecting the gate electrode 3, the first contact region 5 and the second contact region 6 of the cell structure 210 to the circuit 310, the cell structure 210 may be controlled, the cell structure 210 may be tested, and then the parameters of the trench field effect transistor may be tested.

[0073] refer to Fig. 9The device 300 for testing parameters of a trench field effect transistor includes a processor 320. The processor 320 can be configured to: control the voltage applied by the circuit 310 to the device 200 for testing parameters of the trench field effect transistor, and obtain the current value of the device 200 for testing parameters of the trench field effect transistor. By controlling the circuit 310, the device 300 for testing parameters of the trench field effect transistor can perform different testing methods. The processor 320 can control the on and off of the switch 313.

[0074] Exemplarily, the device 300 for testing the parameters of the trench field effect transistor is a computer device, which can be a server or a terminal. The computer device includes a processor 320, a memory 330, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor 320, the memory 330 and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor 320 of the computer device is used to provide computing and control capabilities. The memory 330 of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program, and can also store a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the structural parameters or other test data of the cellular structure 210. The input / output interface of the computer device is used to exchange information between the processor 320 and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection.

[0075] Further, when the computer program is executed by the processor 320, all or part of the steps of the following method for testing are implemented. In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by the processor 320, all or part of the steps of the following method for testing are implemented. In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by the processor 320, all or part of the steps of the following method for testing are implemented.

[0076] Combination Fig.10 As shown, Fig.10 A method 1000 for testing parameters of a trench field effect transistor in an embodiment of the present application is shown. The method 1000 for testing may include step S110, and may also include steps 120 to S140.

[0077] The method 1000 for testing the parameters of a trench field effect transistor of the present application may be based on the cellular structure 210 in the device 200 for testing the parameters of a trench field effect transistor described above. In some embodiments, the method 1000 for testing the parameters of a trench field effect transistor further includes: designing the parameters of each functional area of ​​a plurality of cellular structures 210, for example, including the surface length L1 and the sidewall length L2; designing a process flow for manufacturing the cellular structure 210 and the device 200 for testing the parameters of a trench field effect transistor; designing a photolithography plate for manufacturing the cellular structure 210 and the device 200 for testing the parameters of a trench field effect transistor. The method 1000 further includes the step of manufacturing the cellular structure 210. In the plurality of cellular structures 210, the trench depth may be configured to be the same or the sidewall length L2 may be the same, and the surface length L1 may be configured to be different.

[0078] Step S110: applying different levels of gate-source voltage to each of the plurality of cell structures 210. V GS , and the drain-source current is obtained I d and drain-source voltage V DS The relationship curve is the IV curve. Among them, the drain-source voltage V DS Generally less than or equal to 0.1V. Then the gate-source voltage at different levels can be calculated V GS The corresponding on-resistance R t The method 1000 for testing parameters of a trench field effect transistor of the present application can effectively obtain the performance of the cell structure 210 .

[0079] refer to Figure 5 , on-resistance R t Including multi-segment resistors, except planar channel resistors R ch1 and sidewall channel resistance R ch2 The resistor outside can be called other resistor Rs. By configuring other resistor Rs to be smaller, it can be considered R t satisfy: R t ≈ R ch1 + R ch2 , which is helpful to reduce the difficulty of evaluation; the smaller the other resistance Rs is, the more accurate the channel mobility test can be improved. Based on the two channels of the cell structure 210, the sidewall trench mobility and the plane trench mobility can be separated later.

[0080] For example Fig.11As shown, the cell structure 210 with a surface length of 2 μm was tested at gate-source voltages of 5V, 10V, and 15V. V GS For example, three on-resistance values ​​can also be obtained for each other surface length of the cell structure 210.

[0081] Step S120, obtaining a fitting curve, further, may include obtaining an intercept of the fitting curve. For each level of gate-source voltage, a fitting curve of the corresponding on-resistance based on different surface lengths L1, namely, an Rt-L1 curve, is obtained. Fig.11 , respectively for 5V, 10V, 15V gate-source voltage V GS A fitting curve is obtained for each of the two fitting curves, and each fitting curve can be a linear equation fitting curve. After obtaining the fitting curve, the intercept of each fitting curve on the vertical axis can be obtained, wherein the intercept value is the sidewall channel resistance corresponding to the trench gate 32 R ch2 Exemplarily, step S120 may include: obtaining a fitting curve, and then obtaining the slope of each fitting curve k , and then R t ≈ k × L1 + R ch2 .

[0082] Specifically, for the cell structure 210:

[0083] ,

[0084] in, is the planar channel mobility, is the sidewall channel mobility, V TH1 is the planar threshold voltage, V TH2 is the sidewall threshold voltage.

[0085] Step S130, obtaining the size of the cell structure 210 along the projection direction W , Capacitance per unit area of ​​the trench dielectric part C ox2 , sidewall length L2 and the sidewall threshold voltage of the sidewall channel formed at the second step V TH2 In addition, step S130 may include: obtaining the capacitance per unit area of ​​the planar dielectric portion C ox1 and the planar threshold voltage of the planar channel formed at the second step V TH1 .

[0086] The vertical dimension of the cell structure 210 along the XZ plane W The sidewall length L2 may be a value set when the cell structure 210 is designed and manufactured.

[0087] C ox1 and C ox2 The thickness of the gate dielectric layer 4 is calculated and extracted by testing the capacitance voltage CV curve. In other embodiments, the thickness of the gate dielectric layer 4 is calculated by slicing the gate dielectric layer 4.

[0088] For example, when designing and manufacturing the cellular structure 210, a cellular structure 210 with a surface length L1 of zero is configured, and then the cellular structure 210 can be used to obtain V TH2 When designing and manufacturing the cellular structure 210, a cellular structure 210 with a sidewall length L2 of zero is configured, which can also be considered as designing and manufacturing the cellular structure 210. Figure 1 The field effect transistor 100 shown in FIG. 1 is obtained by testing the transfer curve of the field effect transistor 100. V TH1 .

[0089] Step S140, obtaining the sidewall channel mobility of the cell structure 210, wherein the sidewall channel mobility satisfy:

[0090] .

[0091] refer to Fig.12 , the method 1000 for testing the parameters of the trench field effect transistor obtains the sidewall channel mobility scatter plot. Compared with the sidewall channel mobility curve obtained by Sentaurus simulation, the data trend is more consistent and the data deviation is smaller.

[0092] The method 1000 for testing parameters of a trench field effect transistor of the present application can separate the sidewall trench mobility and the planar channel mobility, which is helpful for more accurate analysis of the performance of the trench field effect transistor, and is helpful for designing, manufacturing, using and analyzing the field effect transistor including the trench gate 32.

[0093] Compared with the comparative example, the method 1000 for testing parameters of a trench field effect transistor of the present application has at least one of the following beneficial effects:

[0094] By setting different surface lengths of the planar dielectric portion 41 on the surface of the semiconductor structure, the channel length of the trench gate MOSFET is increased, avoiding the problem that the channel length of the trench gate MOSFET is limited by the trench depth, resulting in a small channel resistance of the trench gate MOSFET and affecting the mobility extraction.

[0095] The gate electrode 3 , the source electrode and the drain electrode are all located on the same side of the semiconductor structure, thereby avoiding the influence of the drift region resistance and the substrate resistance.

[0096] By setting a source or drain at the bottom of the trench and isolating the two channels on the trench sidewalls through an insulating medium such as the first dielectric portion 43, the mobility of the single-side channel can be extracted without being affected by the other side channel, and the mobility characteristics of different crystal planes of the semiconductor can be reliably characterized, and further other characteristics of the single-side oxide semiconductor interface including gate reliability, threshold voltage drift, etc. can be characterized.

[0097] refer to Fig.13 The method 1000 for testing parameters of a trench field effect transistor in the embodiment of the present application may include steps S110 to S130, and may also include steps S150 and S160. In step S120, after obtaining the fitting curve, the slope can be obtained. k .

[0098] Step S150, based on the on-resistance and the sidewall channel resistance, R t ≈ R ch1 + R ch2 , and obtain the planar channel resistance corresponding to the planar gate R ch1 The value of .

[0099] Step S160, obtaining the planar channel mobility of the cell structure 210, wherein the planar channel mobility satisfy:

[0100] .

[0101] refer to Figure 7 and Fig.14 The present application provides another method for testing parameters of a trench field effect transistor, which may be specifically a method 2000 for testing the reliability of a gate structure. The method 2000 for testing the reliability of a gate structure is based on multiple groups of cell structures 210 or multiple groups of the aforementioned devices 200 for testing parameters of a trench field effect transistor. The method 2000 for testing the reliability of a gate structure includes steps S210 to S240.

[0102] Step S210, applying a gate-source voltage to each of the multiple groups of cell structures 210, and setting a failure standard leakage current. More than 10 groups of cell structures 210 or more than 10 devices 200 for testing parameters of trench field effect transistors can be used to obtain reliable statistical data. Specifically, at the same test environment temperature, different gate-source voltages are applied to different groups using the first voltage source 311, and at least three groups can be tested at each test environment temperature. The test environment temperature range can be 300K to 900K.

[0103] The gate-source voltage stress range applied can be set according to the thickness of the gate dielectric layer 4. For example, for the gate dielectric layer 4 of silicon oxide material, the gate-source voltage range is normalized to 4MV / cm to 12MV / cm. The normalization basis can be: V GS / T ox ,in, T ox is the thickness of the gate dielectric layer 4.

[0104] Step S220, obtain the characteristic life of the cell structure 210. The leakage current between the gate electrode 3 and the first electrode 50 as the source can be detected. In response to the leakage current exceeding the failure standard leakage current, it can be determined that the gate dielectric layer 4 has failed, and the failure time is recorded. The failure time of each group of cell structures 210 under the corresponding gate-source voltage can be subjected to Weibull statistical analysis, and the characteristic life of the cell structure 210 can be obtained according to the Weibull statistical analysis.

[0105] Step S230, extracting characteristic parameters of the gate dielectric layer 4 according to the time-dependent breakdown defect generation model. Optionally, the time-dependent breakdown defect generation model may be an E model or a 1 / E model, so that characteristic parameters can be extracted and failure influencing factors can be analyzed.

[0106] Step S240, combined with the analysis results of the previous step, can predict the working life of the gate dielectric layer 4 under normal working conditions. The method 2000 of testing the reliability of the gate structure of the present application can obtain the working life of the gate dielectric layer 4, which is conducive to more accurately analyzing the performance of the trench field effect transistor.

[0107] refer to Fig.15 The present application provides a method for testing parameters of a trench field effect transistor, which may be a method 3000 for testing the threshold stability of a channel. The method 3000 for testing the threshold stability of a channel is based on the cell structure 210 or the device 200 for testing parameters of a trench field effect transistor, and may be used as follows: Figure 8 The circuit 310 is shown. The method 3000 for testing the threshold stability of a channel may include steps S310 to S330.

[0108] Step S310, applying a first gate-source voltage according to a time sequence. Figure 8 , the switch 313 can be turned off, and the first gate-source voltage is applied by the first voltage source 311. Fig.16 The time sequence for applying the first gate-source voltage is, for example, 1 s, 2 s, 10 s, 60 s, etc. The length of each time segment in the time sequence may be different, and an interval is left between each time segment.

[0109] In step S320, in response to the end of a period of pressure application in the time sequence, a drain-source voltage and a second gate-source voltage are applied to test the transfer curve of the cell structure 210 to obtain a time-based threshold voltage curve, i.e., a VT curve. Specifically, after the end of a period of pressure application, the switch 313 can be closed so that the second voltage source 312 can apply the drain-source voltage to the cell structure 210.

[0110] Step S330, based on the VT curve, the threshold stability of the channel of the cell structure 210 can be analyzed. The method 3000 of testing the threshold stability of the channel of the present application can obtain the threshold stability of the channel, which is conducive to more accurately analyzing the performance of the trench field effect transistor.

[0111] For example, the test environment temperature of the method 3000 for testing the threshold stability of the channel may also be in the range of 300K to 900K. The gate-source voltage stress range applied may be set according to the thickness of the gate dielectric layer 4. For example, for the gate dielectric layer 4 of silicon oxide material, the gate-source voltage range is normalized to 4MV / cm to 12MV / cm. The normalization basis may be: V GS / T ox .

[0112] refer to Fig.17 The present application provides a method 4000 for manufacturing a cellular structure. Exemplarily, the method 4000 for manufacturing a cellular structure may include the following steps, which can be used to manufacture: Figure 4 or Figure 6 The cell structure 210 is shown. In the production process, the structure obtained in each step can be called the precursor of the structure in the next step. Exemplarily, the steps of the method 4000 for manufacturing the cell structure are also the steps of the method for manufacturing the device 200 for testing the parameters of the trench field effect transistor.

[0113] Optionally, in step S401, an epitaxial layer, i.e., a first layer 1, is formed on the substrate 8. The epitaxial layer may be formed by atomic layer deposition, chemical vapor deposition, or the like. The epitaxial layer may thicken the substrate 8 and improve the performance of the semiconductor structure. A semiconductor structure may also be manufactured based on the substrate 8.

[0114] Step S402, forming a channel layer, namely, a second layer 2. Optionally, the channel layer stacked on the epitaxial layer can be formed by in-situ doping or ion implantation.

[0115] Step S403, forming a groove, the groove extending into the second layer 2 along the Z-axis direction. Exemplarily, when two cellular structures 210 are formed simultaneously, two grooves of the two cellular structures 210 can be formed simultaneously and regarded as a large groove. The large groove can be formed by etching and can be a U-shaped or V-shaped structure.

[0116] Step S404, forming the first contact region 5 and the second contact region 6. The first contact region 5 and the second contact region 6 can be formed in the same ion implantation process. Alternatively, they can be formed separately, and the plurality of first contact regions 5 at the bottom of the trench can be formed simultaneously, and the plurality of second contact regions 6 on the top surface of the second layer 2 can be formed simultaneously.

[0117] Step S405: forming a source contact region 7. For example, Figure 4 As shown, a source contact region 7 is formed that penetrates the first contact region 5. Then, the first contact region 5 can be used as a source contact region to conduct electricity, and the second contact region 6 can be used as a drain contact region to conduct electricity. The source contact region 7 is located between the two first contact regions 5, that is, at the source, but its doping type is the same as that of the channel layer, in order to separate the two adjacent first contact regions 5 at the bottom of the trench. Figure 6 As shown, a source contact region 7 penetrating the second contact region 6 may be formed. Then, the second contact region 6 may be conductive as a source contact region, and the first contact region 5 may be conductive as a drain contact region. The source contact region 7 is located at the source to separate the second contact region 6 .

[0118] In step S406 , a gate dielectric layer 4 may be formed by oxidation or deposition.

[0119] Step S407, forming a gate electrode 3. The gate electrode 3 may be formed by deposition and photolithography. Exemplarily, two gate electrodes 3 are formed simultaneously, and two trench gates 32 separating the two gate electrodes 3 are etched in the trench.

[0120] Step S408 , forming an insulating dielectric layer, wherein the first dielectric portion 43 and the second dielectric portion 44 respectively surround two sides of the gate electrode 3 along the second direction.

[0121] In step S409, the first electrode 50 and the second electrode 60 can be formed by sputtering or evaporation, and the first electrode 50 is in ohmic contact with the first contact area 5 and the second electrode 60 is in ohmic contact with the second contact area 6 by laser annealing or rapid thermal annealing to achieve a lower resistance. The first electrode 50 and the second electrode 60 can be formed simultaneously. One of the first electrode 50 and the second electrode 60, which is a source electrode, also covers the source contact area 7.

[0122] Step S410, forming a substrate electrode 10. The substrate electrode 10 may be made of nickel or titanium, and may be in ohmic contact with the substrate 8 by laser annealing or rapid thermal annealing.

[0123] refer to Fig.18 The present application provides a photolithography assembly 400 that can be used in the steps of the aforementioned method 4000 for manufacturing a cellular structure.

[0124] The photomask assembly 400 may include a groove plate 410, a gate electrode plate 420, and may also include photomasks for other steps. Depending on the type of photoresist used, each plate of the photomask assembly 400 may be a negative plate or a positive plate.

[0125] The groove plate 410 is used for the step of forming grooves. The groove pattern 4101 included in the groove plate 410 may correspond to the large grooves shared by the two cellular structures 210 .

[0126] The gate electrode plate 420 can be used for the etching process of the gate electrode 3. According to the difference in the deposition process, the design of the gate electrode pattern 4201 can be adjusted according to the process requirements. Exemplarily, the gate electrode pattern 4201 is used in the step of cutting out two groove gates 32. Along the X-axis direction, the lengths of different gate electrode patterns 4201 can be different to form planar gates 31 of different lengths.

[0127] The gate electrode pattern 4201 includes a trench gate region corresponding to the trench pattern 4101 and a planar gate region extending out of the trench pattern.

[0128] Optionally, some gate electrode patterns 4201 may not include a planar gate region to form a cell structure 210 with zero surface length. Optionally, some locations of the groove plate 410 may not be provided with a groove pattern 4101, which can then be used to manufacture a cell structure 210 with zero sidewall length or groove depth.

[0129] refer to Fig.19 The photolithography assembly 400 further includes: a contact area plate 430 for forming the first contact area 5 and the second contact area 6, a gate dielectric plate 440 for forming the gate dielectric layer 4, a source contact plate 450 for forming the source contact area 7 penetrating the first contact area 5, and an insulating dielectric plate 460 for forming an insulating dielectric layer covering the gate electrode 3. In other embodiments, the source contact area 7 formed by the source contact plate 450 penetrates the second contact area 6.

[0130] Exemplarily, the photolithography assembly 400 may further include layout blocks for forming various functional areas, such as peripheral circuits.

[0131] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0132] The technical features of the embodiments disclosed above can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] In the embodiments disclosed above, unless otherwise clearly specified and limited, the execution order of each step is not limited, for example, it can be executed in parallel, or it can be executed successively in different orders. The sub-steps of each step can also be executed alternately. The above-mentioned various forms of processes can be used, and steps can be reordered, added or deleted. As long as the desired results of the technical solution provided by the application can be achieved, the application is not limited here.

[0134] The embodiments disclosed above only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of patent protection required by the present application. Therefore, the scope of patent protection of the present application shall be subject to the attached claims.

Claims

1. A method for testing parameters of a trench field effect transistor, characterized in that: include: Apply different levels of gate-source voltage to each of the multiple cell structures V GS , and obtain the relationship curve between drain-source current and drain-source voltage to calculate the on-resistance corresponding to different levels of gate-source voltage R t ; The cell structure includes a channel layer, a gate electrode, a gate dielectric layer, a first contact region, a second contact region, a first electrode and a second electrode, the channel layer includes a first step and a second step protruding from the first step along a first direction, the gate electrode includes a trench gate stacked on the first step and a planar gate stacked on the second step, the gate electrode is an integrated structure, the first contact region extends into the first step and extends into the second step along a second direction perpendicular to the first direction, the second contact region extends into the second step and has a gap with the sidewall of the second step, the first contact region contacts the first electrode, the second contact region contacts the second electrode, one of the first electrode and the second electrode serves as a source, and the other serves as a drain, a sidewall length is provided between the planar dielectric portion of the gate dielectric layer corresponding to the planar gate and the first contact region, and a surface length is provided between the trench dielectric portion of the gate dielectric layer corresponding to the trench gate and the second contact region.

2. The method for testing parameters of a trench field effect transistor according to claim 1, characterized in that: For each level of gate-source voltage, a fitting curve of the corresponding on-resistance based on different surface lengths L1 is obtained to obtain the intercept of the fitting curve on the vertical axis, wherein the value of the intercept is the sidewall channel resistance corresponding to the trench gate R ch2 The value of Get the size of the cell structure along the projection direction W , the capacitance per unit area of ​​the trench dielectric portion C ox2 , the sidewall length L2 and the sidewall threshold voltage of the sidewall channel formed at the second step V TH2 ;as well as Obtaining the sidewall channel mobility of the cell structure, wherein the sidewall channel mobility satisfy: 。 3. The method for testing parameters of a trench field effect transistor according to claim 1, characterized in that: For each level of gate-source voltage, a fitting curve of the corresponding on-resistance based on different surface lengths L1 is obtained to obtain the slope of the fitting curve: k ; Get the size of the cell structure along the projection direction W , the capacitance per unit area of ​​the planar dielectric portion C ox1 and the planar threshold voltage of the planar channel formed at the second step V TH1 ; as well as Obtaining the planar channel mobility of the cell structure, wherein the planar channel mobility satisfy: 。 4. A method for testing parameters of a trench field effect transistor, characterized in that: include: Under the same test environment temperature, a gate-source voltage is applied to each of the multiple groups of cell structures, and a failure standard leakage current is set, wherein the gate-source voltages of different groups are different; the cell structure comprises a channel layer, a gate electrode, a gate dielectric layer, a first contact region, a second contact region, a first electrode and a second electrode, the channel layer comprises a first step and a second step protruding from the first step along a first direction, the gate electrode comprises a trench gate stacked on the first step and a plane gate stacked on the second step, the gate electrode is an integrated structure, the first contact region extends into the first step and extends into the second step along a second direction perpendicular to the first direction, the second contact region extends into the second step and has a gap with the sidewall of the second step, the first contact region contacts the first electrode, the second contact region contacts the second electrode, one of the first electrode and the second electrode serves as a source, and the other serves as a drain, a sidewall length is provided between a plane dielectric portion of the gate dielectric layer corresponding to the plane gate and the first contact region, a surface length is provided between a trench dielectric portion of the gate dielectric layer corresponding to the trench gate and the second contact region, and multiple surface lengths of multiple cell structures in each group are different from each other; Obtaining a characteristic life of the cell structure according to the failure time of each group of the cell structures under the corresponding gate-source voltage condition; extracting characteristic parameters of the gate dielectric layer according to a time-dependent breakdown defect generation model; and The working life of the gate dielectric layer is obtained.

5. A method for testing parameters of a trench field effect transistor, characterized in that: include: Applying a first gate-source voltage to a cell structure according to a time sequence; wherein the cell structure comprises a channel layer, a gate electrode, a gate dielectric layer, a first contact region, a second contact region, a first electrode and a second electrode, the channel layer comprises a first step and a second step protruding from the first step along a first direction, the gate electrode comprises a trench gate stacked on the first step and a plane gate stacked on the second step, the gate electrode is an integrated structure, the first contact region extends into the first step and extends into the second step along a second direction perpendicular to the first direction, the second contact region extends into the second step and has a gap with a sidewall of the second step, the first contact region contacts the first electrode, the second contact region contacts the second electrode, one of the first electrode and the second electrode serves as a source, and the other serves as a drain, a sidewall length is provided between a plane dielectric portion of the gate dielectric layer corresponding to the plane gate and the first contact region, and a surface length is provided between a trench dielectric portion of the gate dielectric layer corresponding to the trench gate and the second contact region; In response to the end of a pressure application time in the time sequence, applying a drain-source voltage and a second gate-source voltage to test a transfer curve of the cell structure to obtain a time-based threshold voltage curve; and The threshold stability of the channel of the cell structure is obtained.

6. A device for testing parameters of a trench field effect transistor, characterized in that: include: a memory storing a computer program; and A processor, wherein when executing the computer program, the processor implements the steps of the method according to any one of claims 1 to 5.

7. The device for testing parameters of trench field effect transistors according to claim 6, characterized in that: It also includes a circuit, which includes a first voltage source, a second voltage source and a switch, wherein the high potential end of the first voltage source is electrically connected to the gate electrode, the low potential end of the first voltage source is electrically connected to the first contact area, the high potential end of the second voltage source is electrically connected to the second contact area, and the low potential end of the second voltage source is connected to the first contact area through the switch.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A cellular structure, characterized in that include: A channel layer, comprising a first step and a second step protruding from the first step along a first direction; a first contact region extending into the first step and extending into the second step along a second direction perpendicular to the first direction; a first electrode, contacting the first contact area; a second contact area extending into the second step and spaced apart from a side wall of the second step; a second electrode, contacting the second contact region, wherein one of the second electrode and the first electrode serves as a source electrode, and the other serves as a drain electrode; a gate electrode, comprising a trench gate stacked on the first step and a planar gate stacked on the second step, the gate electrode being an integrated structure; and A gate dielectric layer is used to insulate the gate electrode from the channel layer, a sidewall length is provided between a planar dielectric portion of the gate dielectric layer corresponding to the planar gate and the first contact region, and a surface length is provided between a trench dielectric portion of the gate dielectric layer corresponding to the trench gate and the second contact region.

10. The cellular structure according to claim 9, characterized in that: The doping type of the channel layer is one of electron doping and hole doping, and the doping type of the first contact region and the doping type of the second contact region are both the other.

11. The cellular structure according to claim 9, characterized in that: It also includes a source contact region, the first electrode contacts the first contact region and has a gap with the trench gate, the second electrode contacts the second contact region and has a gap with the planar gate, and the doping type of the source contact region is the same as the doping type of the channel layer; The source contact region penetrates the first contact region and contacts the first electrode, or the source contact region penetrates the second contact region and contacts the second electrode.

12. A device for testing parameters of a trench field effect transistor, characterized in that: comprising a plurality of cellular structures as claimed in any one of claims 9 to 11; The gate dielectric layer comprises a trench dielectric portion corresponding to the trench gate and a planar dielectric portion corresponding to the planar gate, a surface length is provided between the trench dielectric portion and the second contact region, and a sidewall length is provided between the planar dielectric portion and the first contact region; The plurality of surface lengths of the plurality of cellular structures are different from each other.

13. The device for testing parameters of a trench field effect transistor according to claim 12, characterized in that: The surface length ranges from 0.5 μm to 10000 μm, and the doping concentration of the first contact region ranges from 1e19 cm -3 to 1e21cm -3 , the ohmic contact resistivity at the first contact area is less than or equal to 0.001Ωcm 2 , the ohmic contact resistivity at the second contact region is less than or equal to 0.001Ωcm 2 .

14. The device for testing parameters of a trench field effect transistor according to claim 12, characterized in that: The plurality of cellular structures include at least one pair of cellular structures, and each pair of the cellular structures is arranged in a manner that two trench gates face each other and are spaced apart.

15. A method for manufacturing a cellular structure, characterized in that include: forming a channel layer; forming a groove extending into the channel layer along a first direction; forming a first contact region extending from a bottom wall of the trench into the channel layer and into a side wall of the trench, and forming a second contact region extending into the channel layer and spaced apart from the trench; forming a gate dielectric layer covering the channel layer; as well as forming a gate electrode, the gate electrode comprising a trench gate extending into the trench and a planar gate stacked on the second contact region, the gate electrode being an integrated structure, wherein a sidewall length is provided between a planar dielectric portion of the gate dielectric layer corresponding to the planar gate and the first contact region, and a surface length is provided between a trench dielectric portion of the gate dielectric layer corresponding to the trench gate and the second contact region; and A first electrode and a second electrode are formed by sputtering or evaporation, and the first electrode is ohmically contacted with a first contact area and the second electrode is ohmically contacted with a second contact area by laser annealing or rapid thermal annealing, wherein one of the first electrode and the second electrode is a source and the other is a drain.

16. The method for manufacturing a cellular structure according to claim 15, characterized in that: Also includes: forming an epitaxial layer stacked on a substrate; The channel layer stacked on the epitaxial layer is formed by in-situ doping or ion implantation; the U-shaped or V-shaped groove is formed by etching; the first contact region and the second contact region are formed by ion implantation; the gate dielectric layer is formed by oxidation or deposition; the gate electrode is formed by deposition and photolithography and etching; The method for manufacturing a cellular structure further comprises: forming a source contact region penetrating the first contact region or penetrating the second contact region, wherein the doping type of the source contact region is the same as the doping type of the channel layer; forming an insulating dielectric layer covering the gate electrode; and A substrate electrode is formed on a side of the substrate facing away from the epitaxial layer.

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