A method of compiler optimization and related products

Abstract

The application provides a compiling optimization method and related products, wherein the method comprises the following steps: running a first executable file, and collecting a hardware cache event, wherein the first executable file comprises an executable program and debugging information, the executable program is obtained by compiling program source code, and the debugging information comprises a corresponding relationship between the program source code and executable instructions in the executable program; obtaining first configuration information according to the hardware cache event and the debugging information, wherein the first configuration information comprises an identifier of the program source code and a cache miss number corresponding to the identifier; and compiling the program source code according to the first configuration information, and obtaining a second executable file. When the second executable file is executed, the optimization effect of improving the cache can be achieved while the cost of cache optimization is saved.

Description

[0001] This application is a divisional application of Chinese patent application No. 202110876986.9, filed on July 31, 2021, entitled "A method for compiling and optimizing program source code and related products". Technical Field

[0002] This application relates to the field of caching technology, and in particular to a compiler optimization method and related products. Background Technology

[0003] With the rapid development of caching technology, the speed at which the central processing unit (CPU) accesses memory objects (including data and instructions) is also increasing. A key factor affecting the speed of CPU memory access is whether the cache contains the objects that the CPU is about to access. Therefore, cache optimization is necessary to allow the CPU to read more objects from the cache, reducing the number of CPU accesses to main memory and thus improving the speed of CPU memory access.

[0004] However, current cache optimization methods all suffer from high optimization costs and low accuracy and timeliness. In other words, these cache optimization methods require high costs to optimize the cache, and the optimized cache may still contain a lot of redundant objects and objects with low access frequency, or the object may not be moved from memory to the cache in time before the CPU accesses the memory object.

[0005] Therefore, how to improve the effectiveness of cache optimization while reducing the optimization cost is an urgent problem to be solved in the current caching technology field. Summary of the Invention

[0006] This application provides a compiler optimization method and related products that can improve the accuracy and timeliness of cache optimization.

[0007] Firstly, this application provides a method for compiling and optimizing program source code. The method includes: running a first executable file and collecting hardware cache events. The first executable file includes an executable program and debugging information. The executable program is obtained by compiling the program source code, and the debugging information includes the correspondence between the program source code and the executable instructions in the executable program. Then, based on the hardware cache events and the debugging information, first configuration information is obtained. The first configuration information includes an identifier of the program source code and the number of cache misses corresponding to that identifier. Finally, the program source code is compiled according to the first configuration information to obtain a second executable file.

[0008] By implementing the method described in the first aspect, a second executable file can be obtained. When the CPU executes the second executable file, it can optimize the cache. Furthermore, this method determines the number of cache misses corresponding to the program source code by collecting hardware cache events. Then, it combines the number of cache misses with the number of cache misses to compile the program source code. This allows the compiled second executable file to more accurately and promptly inform the CPU how to optimize the cache, improving not only the accuracy and timeliness of cache optimization but also saving on cache optimization costs.

[0009] In one possible implementation, obtaining the first configuration information based on hardware cache events and debugging information includes: parsing hardware cache events to obtain the cache miss count corresponding to the executable instruction, and then determining the cache miss count corresponding to the source code associated with the executable instruction based on the cache miss count corresponding to the executable instruction and the debugging information, thereby obtaining the first configuration information.

[0010] Since the CPU can only execute executable instructions, it's possible to determine which executable instructions cause cache misses, thus determining the number of cache misses for each executable instruction. Furthermore, since executable instructions are compiled from program source code, the number of cache misses for executable instructions can determine the number of cache misses in the program source code. In other words, this implementation method allows for a simpler and more accurate determination of the number of cache misses in the program source code, thereby guiding the compilation of the program source code and resulting in better compilation performance.

[0011] In one possible implementation, the compilation of the program source code based on the first configuration information to obtain a second executable file includes: parsing the first configuration information to determine the source code that satisfies a first condition, wherein the first condition includes: the number of cache misses in the source code is greater than a first threshold, and the source code includes memory access objects. Then, the prefetch distance of the source code that satisfies the first condition is calculated, where the prefetch distance represents the lead time for moving the memory access objects from memory to the cache. Finally, prefetch instructions are generated based on the prefetch distance.

[0012] In the above implementation method, by selecting source code that meets the first condition and performing data prefetching on the source code that meets the first condition, the workload of the CPU can be reduced, and the overall optimization effect of the cache can also be improved.

[0013] In one possible implementation, the calculation of the prefetch distance of the source code satisfying the first condition includes: obtaining the control flow graph (CFG) of a first loop, where the first loop is the innermost loop containing the source code satisfying the first condition, the CFG of the first loop includes multiple basic blocks (BBs) and multiple directed edges, the directed edges indicating the execution order among the multiple BBs; then, determining the execution probability of each directed edge; calculating the single loop time of the first loop based on the execution probability of each directed edge; and then calculating the prefetch distance of the source code satisfying the first condition based on the single loop time of the first loop.

[0014] The above implementation considers that cache misses are most likely to occur when the CPU executes loop programs, especially the innermost nested loop. Therefore, calculating the single-cycle time of the innermost loop allows for a more accurate determination of the prefetch distance, thereby improving the timeliness and versatility of cache optimization. Furthermore, by determining the execution probability of each directed edge and thus calculating the single-cycle time of the first loop, the impact of low-probability bound edges (BBs) on the single-cycle time of the first loop can be reduced, thereby improving the accuracy of the calculated single-cycle time of the first loop.

[0015] In one possible implementation, obtaining the CFG of the first loop includes: parsing first configuration information, identifying functions in the program source code that satisfy a second condition, wherein the second condition is that the number of cache misses of the function is greater than a second threshold, and the number of cache misses of the function is the sum of the number of cache misses of the source code included in the function. Then, identifying the first loop in the functions that satisfy the second condition, wherein the first loop is the innermost loop in the functions that satisfy the second condition, and the execution probability of the first loop iteration is greater than a third threshold, and then constructing the CFG of the first loop.

[0016] In the above implementation, the first loop is further determined by identifying the function that satisfies the second condition. This improves the efficiency of determining the first loop, thereby saving the time of compiling the program source code and reducing the cost of compiling the program source code.

[0017] In one possible implementation, calculating the single-cycle time of the first loop based on the execution probability of each directed edge includes: identifying bounding blocks (BBs) and directed edges that are independent of the loop layer of the first loop, and then pruning these independent BBs and directed edges to obtain the second loop. Afterwards, the execution probability of each BB in the second loop is calculated based on the execution probability of each directed edge to obtain the single-cycle time of the first loop, where the single-cycle time of the first loop is the sum of the products of the execution probability of each BB and the execution time of each BB.

[0018] In the above implementation, the second loop is obtained by pruning the BBs and directed edges that are not related to the loop layer in the first loop. Then, the single loop time of the first loop is calculated based on the second loop, which can improve the accuracy of the calculated single loop time of the first loop.

[0019] In one possible implementation, before compiling the program source code according to the first configuration information to obtain the second executable file, the method further includes: obtaining multiple structures in the program source code, and the members of the multiple structures. Compiling the program source code according to the first configuration information to obtain the second executable file includes: parsing the first configuration information, determining the structures among the multiple structures that satisfy a third condition, the third condition including: no sequential dependency between the members of the structure in use, and the number of cache misses of the structure is greater than a fourth threshold; adjusting the order of the members in the structures that satisfy the third condition to obtain a new structure. Then, the new structure replaces the structure that satisfies the third condition.

[0020] Implementing the above method also allows for optimization of structures in the program source code, thereby improving cache utilization. Furthermore, this method determines the number of cache misses for structures in the program source code by collecting hardware cache events, thus improving the accuracy of structure member rearrangement.

[0021] In one possible implementation, each of the above structures includes source code from the program source code. The step of parsing the first configuration information to determine the structures that satisfy the third condition includes: parsing the first configuration information to determine the identifier of the program source code and the corresponding cache miss count; then, based on the identifier of the program source code and the corresponding cache miss count, obtaining the cache miss count for each structure, thereby determining the structures that satisfy the third condition. This saves time and reduces the cost of rearranging structure members in the program source code. Furthermore, filtering structures using the third condition can improve the accuracy of rearranging structure members in the program source code.

[0022] In one possible implementation, adjusting the order of members in the structure that satisfies the third condition includes: obtaining the cache miss counts of multiple members in the structure that satisfies the third condition, and then adjusting the order of the multiple members according to the magnitude of the cache miss counts. This can improve cache utilization.

[0023] In one possible implementation, adjusting the order of multiple members based on their cache miss counts involves: obtaining the size of each member and then adjusting the order of the members based on each member's size and cache miss count. This can further improve cache utilization.

[0024] Secondly, this application provides a program source code compilation and optimization apparatus, which includes a running unit, an event acquisition unit, a parsing unit, and a compilation unit. The running unit runs a first executable file, which includes an executable program and debugging information. The executable program is obtained by compiling the program source code, and the debugging information includes the correspondence between the program source code and the executable instructions in the executable program. The event acquisition unit acquires hardware cache events. The parsing unit obtains first configuration information based on the hardware cache events and the debugging information. The first configuration information includes an identifier of the program source code and the corresponding cache miss count. The compilation unit compiles the program source code according to the first configuration information to obtain a second executable file.

[0025] In one possible implementation, the parsing unit is specifically used to: parse hardware cache events, obtain the cache miss count corresponding to the executable instruction, and then determine the cache miss count corresponding to the source code associated with the executable instruction based on the cache miss count and debugging information, thereby obtaining the first configuration information.

[0026] In one possible implementation, the aforementioned compilation unit is specifically used to: parse the first configuration information, determine the source code in the program source code that satisfies a first condition, wherein the first condition includes: the number of cache misses in the source code is greater than a first threshold, and the source code includes memory access objects. Then, it calculates the prefetch distance of the source code that satisfies the first condition, where the prefetch distance represents the lead time for moving the memory access objects from memory to the cache. Finally, it generates prefetch instructions based on the prefetch distance.

[0027] In one possible implementation, the compilation unit is specifically used to: obtain the CFG of a first loop, the first loop being the innermost loop including the source code that satisfies the first condition, the CFG of the first loop including multiple BBs and multiple directed edges, the multiple directed edges being used to indicate the execution order among the multiple BBs; then, determine the execution probability of each directed edge; calculate the single loop time of the first loop based on the execution probability of each directed edge; and then calculate the prefetch distance of the source code that satisfies the first condition based on the single loop time of the first loop.

[0028] In one possible implementation, the aforementioned compilation unit is specifically used to: parse the first configuration information, determine the functions in the program source code that satisfy the second condition, wherein the second condition is that the number of cache misses of the function is greater than a second threshold, and the number of cache misses of the function is the sum of the number of cache misses of the source code included in the function. Then, determine the first loop in the functions that satisfy the second condition, wherein the first loop is the innermost loop in the functions that satisfy the second condition, and the execution probability of the first loop iteration is greater than a third threshold, and then construct the CFG of the first loop.

[0029] In one possible implementation, the compilation unit is specifically used to: determine the bounding boxes (BBs) and directed edges that are independent of the loop layer of the first loop, and then prune these independent BBs and directed edges to obtain the second loop. Afterwards, the execution probability of each BB in the second loop is calculated based on the execution probability of each directed edge, thus obtaining the single-loop time of the first loop. The single-loop time of the first loop is the sum of the products of the execution probability of each BB and the execution time of each BB.

[0030] In one possible implementation, the compilation unit is further configured to: obtain multiple structures in the program source code, and the members within those structures. The compilation unit is also configured to: parse the first configuration information, determine the structures among the multiple structures that satisfy a third condition, the third condition including: no sequential dependency between the members of the structure in use, and the number of cache misses of the structure being greater than a fourth threshold; adjust the order of the members in the structures that satisfy the third condition to obtain a new structure. Then, the new structure replaces the structure that satisfies the third condition.

[0031] In one possible implementation, each of the above structures includes the source code in the program source code, and the above compilation unit is specifically used to: parse the first configuration information, determine the identifier of the program source code and the cache miss count corresponding to the identifier, and then obtain the cache miss count of each of the above structures according to the identifier of the program source code and the cache miss count corresponding to the identifier, thereby determining the above structures that satisfy the third condition.

[0032] In one possible implementation, the above-mentioned compilation unit is specifically used to: obtain the cache miss count of multiple members in the structure that satisfies the third condition, and then adjust the order of the multiple members according to the magnitude of the cache miss count of the multiple members.

[0033] In one possible implementation, the aforementioned compilation unit is specifically used to: obtain the size of each of the multiple members, and then adjust the order of the multiple members based on the size of each member and the number of cache misses of each member.

[0034] Thirdly, this application provides a computing device including a processor and a memory, the memory storing computer instructions, and the processor executing the computer instructions to cause the computing device to perform the method provided in the first aspect or any possible implementation of the first aspect.

[0035] Fourthly, this application provides a computer-readable storage medium storing computer instructions that, when executed by a computing device, enable the computing device to perform the method provided by the first aspect or any possible implementation thereof. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a memory access process involved in this application;

[0037] Figure 2 This is a schematic diagram of the structure of a compiler optimization device provided in this application;

[0038] Figure 3 This is a flowchart illustrating a method for compiling and optimizing program source code provided in this application;

[0039] Figure 4 This is a flowchart illustrating a compilation operation for performing data prefetching on program source code, as provided in this application.

[0040] Figure 5 This application provides a cyclic 1 CFG;

[0041] Figure 6 This application provides a CFG of a loop after trimming loop 1;

[0042] Figure 7 This is a flowchart illustrating a compilation operation that performs structure member rearrangement on program source code, as provided in this application.

[0043] Figure 8 This is a schematic diagram of a second structure provided in this application;

[0044] Figure 9 This is a schematic diagram of the storage layout of a second structure provided in this application;

[0045] Figure 10 This is a structural diagram of a third structure provided in this application;

[0046] Figure 11 This is a schematic diagram of the storage layout of a third structure provided in this application;

[0047] Figure 12 This is a schematic diagram of another third structure provided in this application;

[0048] Figure 13 This is a schematic diagram of the storage layout of another third structure provided in this application;

[0049] Figure 14 This is a schematic diagram of the structure of a computing device provided in this application. Detailed Implementation

[0050] To facilitate understanding of the technical solutions provided in this application, some terms used in this application will be introduced before describing the technical solutions in detail.

[0051] A cache is a temporary storage device located between the CPU and main memory for high-speed data exchange. Its capacity is smaller than main memory, but it accesses objects (including data and instructions) much faster. Multiple levels of cache are typically set up between the CPU and main memory, such as... Figure 1 The diagram shows the L1, L2, and L3 caches. Based on the objects being cached, the L1 cache can be further divided into a data cache and an instruction cache. As the names suggest, the data cache caches data, and the instruction cache caches instructions. Therefore, CPU access to memory requires navigating through these multiple cache levels. Taking data access as an example, the CPU first accesses the L1 cache (specifically the data cache). If the data to be accessed is in the L1 cache, it is read from there. If the data is not in the L1 cache, it accesses the L2 cache. If the data is in the L2 cache, it is read from there. If the data is not in the L2 cache, it accesses the L3 cache. If the data is in the L3 cache, it is read from there. If the data is not in the L3 cache, the CPU accesses the data from memory. It should be understood that the process of the CPU accessing instructions is similar to the data access process described above, so it will not be elaborated upon here.

[0052] The above process involves two scenarios: First, the object accessed by the CPU is in the cache, meaning the CPU can read the object from the L1, L2, or L3 cache; this is called a cache hit. Second, if the object accessed by the CPU is not in the cache, meaning the CPU fails to read the object from the L1, L2, or L3 cache; this is called a cache miss.

[0053] Because memory access is delayed, when the object accessed by the CPU is not in the cache, the CPU needs to wait a considerable amount of time before accessing the data or instruction, thus causing a bottleneck in program execution. To address this, various cache optimization methods have emerged, including but not limited to the following:

[0054] 1. Data prefetching

[0055] Data prefetching refers to the process by which the CPU transfers data to be accessed from memory to the cache before actually accessing it. There are two main types of data prefetching: hardware prefetching and software prefetching. Hardware prefetching involves the CPU using historical memory access information to prefetch data that might be accessed in the future. Software prefetching involves the compiler inserting prefetch instructions into the program during the compilation process, allowing the program to prefetch potentially accessed data into the cache during runtime.

[0056] It's important to note that an effective data prefetching mechanism transfers data from memory to the cache precisely before the CPU uses it, allowing the CPU to access the data from the cache and reducing memory access latency. In other words, data prefetching should not be too early or too late. Only by moving data from memory to the cache in a timely manner within a specific time window can cache removal and cache pollution be minimized, preventing the overhead of data prefetching from outweighing its benefits.

[0057] 2. Structural optimization

[0058] A struct is a data structure, such as integer or floating-point numbers. A struct consists of one or more members, which can be of different types. For example, a struct S might contain integer data 'a', character variable 'b', and double-precision variable 'c', where data 'a', variable 'b', and variable 'c' are all members of struct S.

[0059] Structure optimization primarily involves two methods: structure member rearrangement and structure splitting. Structure member rearrangement involves adjusting the order of members within a structure so that frequently accessed members reside within the same cache line, thereby improving cache line utilization and achieving cache optimization. A cache line is a unit of memory storage that makes up the cache, and each cache line consists of one or more contiguous memory storage units. Structure splitting involves dividing a structure into multiple structures based on the access frequency of its members, thereby improving cache line utilization and achieving cache optimization.

[0060] 3. Function rearrangement

[0061] Function reordering refers to rearranging the code within or between functions so that functions with close calling relationships are arranged adjacently, thereby improving cache block utilization, reducing instruction fetching waits caused by instruction cache misses, and improving program execution efficiency.

[0062] It's easy to see that the cache optimization methods described above all involve the following problem: how to accurately determine which objects (data or instructions) in memory are likely to be frequently accessed by the CPU? After identifying these frequently accessed objects, how to calculate appropriate optimization strategies to optimize the cache? Currently, cache optimization is mainly based on instrumentation techniques. This involves instrumenting the CPU's memory access instructions (e.g., load operands, store operands) to determine the objects the CPU needs to read from memory, allowing for corresponding optimization operations during the compilation phase, such as data prefetching. However, this method requires software instrumentation, which increases the overhead of cache optimization. Furthermore, this method suffers from low accuracy and timeliness; after optimizing the cache using these methods, the object is not promptly moved from memory to the cache before the CPU accesses it.

[0063] To address the aforementioned issues, this application provides a method for compiling and optimizing program source code. By compiling the program source code using this method, a corresponding executable file can be obtained. When the CPU executes this executable file, it can not only optimize the cache but also reduce the overhead of cache optimization and improve the accuracy and timeliness of cache optimization.

[0064] The compilation method for the program source code provided in this application can be executed by a compiler optimization device. Figure 2 A schematic diagram of the compiler optimization device is shown. Figure 2 As shown, the compilation optimization device 100 includes a running unit 110, an event acquisition unit 120, a parsing unit 130, and a compilation unit 140. A brief description of each of these units follows.

[0065] (1) Operation Unit 110

[0066] The execution unit 110 is used to obtain a first executable file and run the first executable file. The first executable file includes an executable program and debugging information. The executable program is obtained by compiling the program source code, and the debugging information includes the correspondence between the program source code and the executable instructions in the executable program.

[0067] (2) Event Acquisition Unit 120

[0068] The event acquisition unit 120 is used to acquire hardware cache events when the first executable file is run. Hardware cache events refer to the status data when the CPU accesses the cache. It should be understood that since two situations may occur when the CPU accesses the cache: a cache hit and a cache miss, the aforementioned hardware cache events can include cache hit events and cache miss events. Specifically, a cache hit event refers to the event where the CPU retrieves the accessed object from the cache when accessing the cache; a cache miss event refers to the event where the CPU fails to retrieve the accessed object from the cache when accessing the cache.

[0069] In this embodiment, considering that current CPUs commonly have a performance monitor unit (PMU), which monitors various hardware execution status events (i.e., hardware events) on the CPU, and that these hardware events include the aforementioned hardware cache events, the event acquisition unit 120 may include a PMU 121 and a performance acquisition tool 122. The PMU 121 monitors hardware events on the CPU, and the performance acquisition tool 122 samples and records hardware cache events from the PMU 121. Optionally, the performance acquisition tool 122 may be a performance acquisition tool provided by Linux (e.g., perf, OProfile) or a performance acquisition tool provided by Windows (e.g., perfmon, VTune), etc., without specific limitations.

[0070] Optionally, PMU 121 can be configured to monitor only hardware cache events on the CPU. This reduces the workload of PMU 121.

[0071] The event acquisition unit 120 is also used to send the acquired hardware cache events to the parsing unit 130.

[0072] (3) Analysis Unit 130

[0073] The parsing unit 130 is used to acquire the first executable file and receive hardware cache events sent by the event acquisition unit 120. The parsing unit 130 is also used to parse the first executable file to obtain debugging information, and then obtain first configuration information based on the debugging information and the hardware cache events. The first configuration information includes an identifier of the program source code and the number of cache misses corresponding to that identifier. The parsing unit 130 is also used to send the first configuration information to the compilation unit 140.

[0074] (4) Compilation Unit 140

[0075] The compilation unit 140 is used to obtain the program source code and receive the first configuration information sent by the parsing unit 130, and compile the program source code according to the first configuration information to obtain the second executable file.

[0076] In one specific embodiment, the compilation unit 140 includes a data prefetch module 141. The data prefetch module 141 is used to perform a data prefetch compilation operation on the program source code according to first configuration information. Specifically, the data prefetch module 141 parses the first configuration information to determine the source code that satisfies condition A, where condition A includes: the number of cache misses in the source code is greater than a threshold A, and the source code includes memory access objects for the CPU. Then, the data prefetch module 141 calculates the prefetch distance of the source code that satisfies condition A, and generates a prefetch instruction based on the prefetch distance, so that the CPU can read the required memory access object from the cache when executing the executable instruction corresponding to the source code.

[0077] In a specific embodiment, the compilation unit 140 further includes a structure member rearrangement module 142. The structure member rearrangement module 142 is used to perform a structure member rearrangement compilation operation on the program source code according to the first configuration information. Specifically, the structure member rearrangement module 142 obtains all structures in the program source code, as well as the members in each structure, and then determines the structures that satisfy condition B by parsing the first configuration information. Condition B includes: there is no sequential dependency between the members in the structure, and the number of cache misses of the structure is greater than a threshold B. No sequential dependency between the members in the structure means that members in the structure are not accessed through structure pointers and offsets. Then, the order of the members in the structures that satisfy condition B is adjusted to obtain a new structure, and the new structure replaces the original structure (i.e., the structure that satisfies condition B).

[0078] Optionally, the compilation unit 140 may further include a structure splitting module 143 or a function reordering module 144. The structure splitting module 143 is used to split structures in the program source code that frequently exhibit cache miss events according to the first configuration information. The function reordering module 144 is used to perform a compilation operation to reorder functions in the program source code that frequently exhibit cache miss events according to the first configuration information.

[0079] The following is combined Figure 3 The specific process of the compilation optimization device 100 performing compilation optimization on the program source code will be described in more detail below. For example... Figure 3 As shown, Figure 3 The diagram illustrates a compilation optimization method for program source code provided in this application, which includes, but is not limited to, the following steps:

[0080] S101: Obtain the first executable file.

[0081] The first executable file is a file that the CPU can load and execute after compiling the program source code. Program source code refers to an uncompiled text file written according to the specifications of a specific programming language (e.g., C, C++), and is a series of human-readable computer language instructions. Optionally, the first executable file can be a binary executable file, and the executable instructions can be assembly instructions, machine instructions, etc.

[0082] In this embodiment, the first executable file includes an executable program and debugging information. The executable program is a program that can be loaded and executed by the CPU, and it includes executable instructions, which are instructions that can be loaded and executed by the CPU. The debugging information is generated during the compilation process of the program source code by the compiler and is used to represent the relationship between the program source code and the executable program. The debugging information includes the correspondence between the program source code and the executable instructions in the executable program.

[0083] In practical applications, considering people's habits of writing program source code, program source code can be regarded as composed of multiple lines of source code. After compilation, one executable instruction usually corresponds to one or more lines of source code. Therefore, the aforementioned debugging information, including the correspondence between the program source code and the executable instructions in the executable program, can specifically be the correspondence between the identifier of each line of source code and the identifier of each executable instruction. Here, the identifier of each line of source code can be the number of that line of source code, and the identifier of each executable instruction can be the number of that executable instruction. Optionally, the identifier of each line of source code can also be the storage address of that line of source code, and the identifier of each executable instruction can also be the storage address of that executable instruction.

[0084] S102: Run the first executable file and collect hardware cache events.

[0085] In some embodiments, during the execution of the first executable file, the compilation optimization device 100 monitors hardware events that occur and samples and records hardware cache events among the hardware events. For a detailed description of the hardware events and hardware cache events, please refer to the foregoing introduction regarding the event acquisition unit 120; for simplicity, it will not be described here again.

[0086] It should be understood that, since hardware events include not only hardware cache events, in some other embodiments, the compilation optimization apparatus 100 may monitor only the hardware cache events on the CPU and sample and record the monitored hardware cache events during the execution of the first executable file.

[0087] S103: Obtain the first configuration information based on hardware cache events and debugging information.

[0088] The first configuration information includes the identifier of the program source code and the number of cache misses corresponding to that identifier. The identifier of the program source code can be the identifier of all source code in the program source code (e.g., the identifier of each line of source code in the program source code), or it can be the identifier of a portion of the source code in the program source code; no specific limitation is made here.

[0089] In one specific embodiment, the compiler optimization device 100 obtains first configuration information based on hardware cache events and debugging information, including: parsing a first executable file to obtain debugging information; then, parsing the hardware cache events to obtain the cache miss count corresponding to the executable instructions in the executable program, wherein the cache miss count corresponding to the executable instructions refers to the number of times a cache miss event occurs when the CPU executes the executable instructions; subsequently, based on the cache miss count corresponding to the executable instructions and the aforementioned debugging information, determining the cache miss count corresponding to the source code associated with the executable instructions, thereby obtaining the aforementioned first configuration information.

[0090] It should be noted that the first configuration information is used to instruct the compiler to compile the program source code. Therefore, after obtaining the first configuration information, the compilation optimization device 100 also needs to store the first configuration information in a file format that the compiler can parse. For example, if the compiler used is the GCC compiler, which can read and parse .gcov format files, then the compilation optimization device 100 will store the first configuration information as a .gcov format file so that the GCC compiler can read and parse the first configuration information.

[0091] S104: Compile the program source code according to the first configuration information to obtain the second executable file.

[0092] Similar to the first executable file, the second executable file is also a file that the CPU can load and run. However, the second executable file is different from the first executable file. Compared to the first executable file, the CPU has better cache optimization when executing the second executable file, which results in less time spent accessing memory and higher program running efficiency.

[0093] In this embodiment of the application, after obtaining the first configuration information, the compilation optimization device 100 can compile the program source code according to the first configuration information in any of the following ways:

[0094] Method 1: The compilation optimization device 100 performs a data prefetching compilation operation on the program source code according to the first configuration information.

[0095] Specifically, the compiler optimization unit 100 parses the first configuration information and determines the source code in the program source code that satisfies condition A. Then, it calculates the prefetch distance of the source code that satisfies condition A, where the prefetch distance represents the lead time for moving the CPU's memory access object from memory to the cache. Finally, it generates a prefetch instruction based on the prefetch distance, enabling the CPU to read the corresponding memory access object from the cache when executing the executable instruction corresponding to the source code that satisfies condition A.

[0096] In one specific embodiment, the compiler optimization device 100 determines the source code in the program source code that satisfies condition A in various ways, for example:

[0097] ① Parse the first configuration information to obtain the identifier of the program source code and the corresponding cache miss count, thereby obtaining the cache miss count of multiple functions in the program source code. The cache miss count of each function is equal to the sum of the cache miss counts of the source code included in that function. Then, sort the above multiple functions in descending order according to the size of the cache miss count, and select at least one function that meets condition C (for simplicity, the above function that meets condition C will be referred to as the first function below). Condition C includes at least one of the following: the cache miss count of the function is greater than threshold C, and the sorting of the functions is less than threshold D. Then, determine the source code involving CPU memory access objects in each first function, and obtain the cache miss count of the source code involving CPU memory access objects according to the identifier of the program source code and the corresponding cache miss count. Then, sort the source code involving CPU memory access objects in descending order according to the size of the cache miss count, thereby determining the source code that meets condition A. Condition A here includes: the cache miss count of the source code is greater than threshold A, the sorting of the source code is less than threshold E, and the source code includes CPU memory access objects.

[0098] It should be understood that a function may include: source code involving CPU memory access objects, source code involving arithmetic operations, source code involving logical operations, source code involving decision-making and control, etc. Only the portion of the source code involving memory access objects will experience cache miss events. Therefore, to more accurately perform data prefetching operations, after selecting the first function, the compiler optimization device 100 also determines the source code within that first function that involves CPU memory access objects, thereby selecting the source code that satisfies condition A.

[0099] It should be noted that in practical applications, multiple functions in the program source code may not satisfy the above condition C, or the source code in the first function may not satisfy condition A in method ①. In this case, the compiler optimization device 100 will not perform data prefetching compilation optimization operations on the program source code.

[0100] ② Parse the first configuration information to obtain the identifier of the program source code and the corresponding cache miss count. Then, identify the source code that involves CPU memory access objects and the corresponding cache miss counts of these source codes. Next, sort the source codes involving CPU memory access objects in descending order according to the number of cache misses to determine at least one source code that satisfies condition A. Condition A includes: the number of cache misses of the source code is greater than threshold A, the order of the source code is less than threshold F, and the source code includes CPU memory access objects.

[0101] It should be noted that in practical applications, the source code in the program source code may not meet condition A in method ②. In this case, the compiler optimization device 100 will not perform data prefetching compilation optimization operation on the program source code.

[0102] In a specific embodiment, considering that the CPU is most likely to encounter cache miss events when executing loop programs, especially the innermost nested loop, the compiler optimization device 100 calculates the prefetch distance of the source code that satisfies condition A, including the following steps: obtaining the CFG of the first loop, wherein the first loop is the innermost loop containing the source code that satisfies condition A, the CFG of the first loop represents all paths that the CPU will traverse during the execution of the first loop, and the CFG of the first loop includes multiple BBs and multiple directed edges, the multiple directed edges being used to indicate the execution order between the multiple BBs. Then, the execution probability of each directed edge is determined, and the single loop time of the first loop is calculated based on the execution probability of each directed edge. Afterwards, the prefetch distance of the source code that satisfies condition A is calculated based on the single loop time of the first loop. The specific process of this step is described in S201-S206 below.

[0103] Method 2: The compilation optimization device 100 performs a compilation operation on the program source code by rearranging the structure members according to the first configuration information.

[0104] In a specific embodiment, before the compilation optimization device 100 performs the compilation operation of reordering structure members on the program source code, it also performs the following steps: obtaining multiple structures in the program source code and the members in the multiple structures, and then recording the type of each structure, the variables of each structure, and the members in each structure.

[0105] In a specific embodiment, the compiler optimization device 100 performs a compiler operation to rearrange the structure members of the program source code according to the first configuration information. This includes: parsing the first configuration information, determining the identifier of the program source code and the cache miss count corresponding to that identifier, and obtaining the cache miss count of each structure based on the identifier and the cache miss count, thereby determining the structure that satisfies condition B. Condition B includes: there is no sequential dependency between the members in the structure, and the cache miss count of the structure is greater than a threshold B. No sequential dependency between the members in the structure means that members are not accessed through structure pointers and offsets. Then, the order of the members in the structure that satisfies condition B is adjusted to obtain a new structure. Finally, the new structure replaces the structure that satisfies condition B. For the specific process of this step, please refer to S301-S306 below.

[0106] It should be understood that the compiler optimization device 100 can also perform compiler operations such as structure splitting or function rearrangement on the program source code according to the first configuration information. Its specific concept is similar to that of the above-mentioned method 1 and method 2. For the sake of simplicity, this application will not elaborate on it.

[0107] By implementing the above-described method for compiling the program source code, a second executable file can be obtained. When the CPU executes this second executable file, cache optimization can be achieved. Furthermore, as described above, this method determines the number of cache misses corresponding to the program source code by collecting hardware cache events. Then, it combines this number of cache misses with the compilation of the program source code, enabling the compiled second executable file to more accurately and promptly inform the CPU how to optimize the cache. Therefore, the program source code compilation method provided in this application not only improves the accuracy and timeliness of cache optimization but also saves on cache optimization costs.

[0108] The following is combined Figure 4 The process by which the compiler optimization device 100 calculates the prefetch distance of the source code that satisfies condition A in S104 above will be further described.

[0109] In this embodiment, considering that the at least one first function is a function in the program source code with a high number of cache miss events, the source code that satisfies condition A is most likely the source code of the innermost loop of the at least one first function. That is, the first loop is most likely the innermost loop of the at least one first function. Therefore, the compiler optimization device 100 will execute S201-S203 to obtain the first loop. For simplicity, a first function is used as an example for explanation here.

[0110] S201: Get at least one innermost loop in the first function.

[0111] It should be understood that in practice, the first function may include multiple innermost loops. Some innermost loops have a higher probability of execution during iteration, while others have a lower probability. Compared to the innermost loop with a lower probability of execution during iteration, the source code that satisfies condition A is more likely to be part of the innermost loop with a higher probability of execution during iteration. Therefore, the compiler optimization device 100 can still execute S202. It should be noted here that the probability of execution during innermost loop iteration refers to the probability of iterating within that loop, not the probability of executing that loop within the function.

[0112] S202: Determine the innermost loop that satisfies condition D among at least one of the above innermost loops, and obtain the first loop and the CFG of the first loop.

[0113] Condition D includes at least one of the following: the execution probability of loop iteration is greater than threshold G, and the execution probability of loop non-iteration is less than threshold H.

[0114] In one specific embodiment, the compiler optimization device 100 can calculate the execution probability or non-execution probability of each innermost loop in the first function in the following way, taking an innermost loop in the first function as an example:

[0115] First, construct the CFG (Cyclic Flow Gauge) for the loop, which represents all paths the CPU will traverse during loop execution. The CFG includes multiple BBs (Block Execution Groups) and multiple directed edges. Each directed edge indicates the execution order between two BBs within the loop. Each BB contains at least one instruction; it's important to note that the instructions in a BB are source code. Then, iterate through each BB, recording each BB, the number of times each BB is executed, and the execution probability of each directed edge. Finally, the execution probability and the probability of not executing the loop can be calculated using the following formula:

[0116]

[0117] y2 = 1 - y1

[0118] Where y1 represents the probability of not executing the loop, exit_edge_prob represents the probability of the directed edge exiting the loop, exit_BB_count represents the number of times the BB leading to the aforementioned directed edge is executed, header_BB_count represents the number of times the entry BB of the loop is executed, and y2 represents the execution probability of the loop. The aforementioned exit_edge_prob, exit_BB_count, and header_BB_count can be calculated by the compiler optimization device 100 using the compiler's built-in static analysis function, FDO, or AutoFDO, etc. For simplicity, this application will not describe them.

[0119] For example, suppose the first function includes loop 1, and the threshold G in condition D is 0.9 and the threshold H is 0.2. Figure 5 The function flow chart (CFG) for loop 1 is shown. The execution counts of BB1, BB2, BB3, BB4, and BB5 are 100, 99, 100, 99, and 1, respectively. The execution probabilities of directed edges BB1→BB2, BB1→BB3, BB2→BB3, BB3→BB4, BB3→BB5, and BB4→BB1 are 99%, 1%, 100%, 99%, 1%, and 100%, respectively. BB1 is the entry point BB of loop 1, and the directed edge BB3→BB5 is the exit point. Therefore, using the above formula, we can calculate y1 = (1% * 100) / 100 = 0.01 and y2 = 1 - 0.01 = 0.99. This means the probability of not executing loop 1 is 0.01, and the probability of executing loop 1 is 0.99, satisfying condition D. Therefore, loop 1 in the first function is a first loop.

[0120] S203: Determine the BBs and directed edges that are unrelated to the cycle layer of the first cycle, and prune the aforementioned unrelated BBs and directed edges to obtain the second cycle.

[0121] Specifically, the compiler optimization device 100 traverses all bounding boxes (BBs) in the first loop, identifies BBs and directed edges unrelated to the first loop, and prunes these unrelated BBs and directed edges to obtain the second loop. BBs unrelated to the loop level of the first loop can be BBs pointed to by directed edges exiting the first loop, and directed edges unrelated to the loop level of the first loop can be directed edges exiting the first loop. Figure 5 Taking cycle 1 as an example, BB5 is a BB independent of the cycle level of cycle 1, and the directed edge BB3→BB5 is a directed edge independent of the cycle level of cycle 1. After trimming BB5 and the directed edge BB3→BB5, we can obtain the following: Figure 6 The loop shown.

[0122] S204: Calculate the execution probability of each BB in the second loop.

[0123] Specifically, when executing S202 above, the compiler optimization device 100 constructs the CFG of each innermost loop in the first function and records the execution probabilities of the BBs and directed edges included in the CFG. Therefore, the compiler optimization device 100 can obtain the execution probability of each BB and each directed edge included in the CFG of the first loop, and then calculate the execution probability of each BB in the second loop based on the execution probability of each directed edge included in the CFG of the first loop.

[0124] In one possible implementation, for ease of calculation, we can assume the execution probability of the entry boundary (BB) in the second loop is 100%, and then calculate the execution probability of each BB in the second loop based on the execution probability of each directed edge included in the first loop's CFG. Figure 6 Taking the loop shown as an example, assuming the execution probability of BB1 is 100%, since the execution probabilities of directed edges BB1→BB2, BB1→BB3, BB2→BB3, BB3→BB4, and BB4→BB1 are 99%, 1%, 100%, 99%, and 100% respectively, the execution probability of BB2 is 99%, the execution probability of BB3 is 100% (1%+99%), and the execution probability of BB4 is 99%.

[0125] It should be noted here that for loops with high execution probability, even after pruning the exit branch (i.e., the block boundaries (BBs) unrelated to the loop's loop layer), the execution probability of each BB in the independent loop body can still be accurately reflected. However, for loops with low execution probability, after pruning the exit branch, since the exit branch has a high execution probability while the BBs in the loop layer have a low execution probability, the execution probability of each BB in the pruned loop does not represent its execution probability in the entire loop. In other words, the compiler optimization device 100 can further improve the accuracy of data prefetching by performing the above S102.

[0126] It should also be noted that, in the embodiments of this application, a more reasonable execution time for a single loop can be calculated by calculating the execution probability of the loop branch (i.e., the execution probability of the directed edge). For example, assuming... Figure 6BB2 may contain a large number of instructions, thus its execution time is relatively long. If the execution time of BB2 is not calculated based on the execution probability of the directed edge BB1→BB2, the calculated execution time for a single loop will be excessively long. However, in practical applications, the probability of the CPU executing BB2 is very low (1%). This means that in most cases, loop execution will directly jump from BB1 to BB3, significantly reducing the calculated execution time for a single loop. Therefore, combining the execution probability of the loop branch with the calculation of the execution time for a single loop yields a more reasonable value.

[0127] S205: Calculate the single loop time of the second loop based on the execution probability of each BB in the second loop and the number and type of instructions in each BB, which is the single loop time of the loop layer of the first loop (hereinafter referred to as the single loop time of the first loop).

[0128] Specifically, obtain the number and type of all instructions in each block of the second loop. Since instructions of the same type have the same execution time, the single loop time of the second loop can be calculated with reference to the following formula:

[0129] loop_time=sum(BB_prob*sum(inst_time))

[0130] Where loop_time represents the single loop time of the second loop, BB_prob represents the execution probability of BB, inst_time represents the execution time of one instruction in BB, and sum(inst_time) represents the sum of the execution times of all instructions in BB.

[0131] S206: Based on the single loop time of the first loop and the CPU memory access latency, calculate the prefetch distance of the source code that satisfies condition A in the first loop.

[0132] Specifically, the compiler optimization device 100 obtains the CPU memory access latency, determines the first source code present in the second loop, and then calculates the prefetch distance of the first source code in the second loop based on the single loop time of the second loop and the CPU memory access latency.

[0133] In a specific embodiment, the prefetch distance of the source code that satisfies condition A in the first loop can be calculated with reference to the following formula:

[0134] prefetch_dis=latency / loop_time

[0135] Where prefetch_dis represents the prefetch distance of the source code that satisfies condition A in the first loop, latency represents the CPU memory access latency, and loop_time represents the single loop time of the second loop.

[0136] The following is combined Figure 7 The process of the compilation optimization device 100 performing a structure member rearrangement compilation operation on the program source code according to the first configuration information in S104 is further described.

[0137] S301: Determine at least one first structure among the above plurality of structures. The members of the first structure do not have any order dependency in their use.

[0138] Specifically, the compiler optimization device 100 checks whether there is a sequential dependency in the usage of each member of each of the above structures. If any member of a structure has a sequential dependency in usage, the compiler optimization device 100 does not perform a structure member rearrangement operation for that structure. If there is no sequential dependency in usage among the members of a structure (i.e., the first structure), the compiler optimization device 100 executes the following steps S302-S306.

[0139] S302: Parse the first configuration file to obtain the identifier of the program source code and the number of cache misses corresponding to the identifier, thereby obtaining the number of cache misses of at least one of the first structures mentioned above.

[0140] S303: Sort at least one of the first structures according to the number of cache misses, and select the structure that satisfies condition E (hereinafter referred to as the second structure).

[0141] Wherein, if the at least one first structure is sorted in descending order according to the number of cache misses, then condition E includes at least one of the following: the number of cache misses of the structure is greater than threshold I, and the order of the structure is less than threshold J. If the at least one first structure is sorted in ascending order according to the number of cache misses, then condition E includes at least one of the following: the number of cache misses of the structure is greater than threshold I, and the order of the structure is greater than threshold K. It should be understood that condition B includes: condition E and the members in the structure do not have a sequential dependency in use.

[0142] S304: Determine the cache miss count of each member in the second structure based on the identifier in the program source code and the cache miss count corresponding to that identifier.

[0143] S305: Based on the number of cache misses of each member in the second structure, adjust the order of the members in the second structure to obtain the corresponding third structure.

[0144] In one specific embodiment, the compiler optimization device 100 adjusts the order of the members in the second structure according to the number of cache misses of each member in the second structure to obtain the corresponding third structure, including the following steps: according to the number of cache misses of each member in the second structure, the members with the largest number of cache misses in the structure are placed in the same cache block, thereby improving the utilization rate of the cache.

[0145] For example, such as Figure 8 As shown, the second structure includes 8 members: member a, member b, member c, member d, member e, member f, member g, and member h. These members do not have any order dependency in their use. Figure 9 A schematic diagram of the storage layout of the second structure is shown, as follows: Figure 9 As shown, the second structure is stored in the cache as two cache blocks. Assuming that when the CPU executes a program, it only needs to read members a and g from the cache, in this case, the CPU needs to read two cache blocks to obtain members a and g. However, if the method provided in the above embodiment is executed, that is, if the order of the members in the second structure is adjusted according to the number of cache misses (the members with the largest number of cache misses in descending order are: member a, member g, member b, member c, member d, member e, member f, member h), then the following can be obtained: Figure 10 The third structure shown and Figure 11 The diagram shows the storage layout of the third structure. In this case, the CPU only needs to read one cache block from the cache to obtain members a and g. Therefore, compared to Figure 8 The second structure shown is used when the cache stores... Figure 10 When the third structure is shown, the utilization rate of the cache can be improved.

[0146] Furthermore, the compiler optimization device 100 can also obtain the size of each member in the second structure, and adjust the order of each member in the second structure according to the cache miss count and the size of each member, to obtain the corresponding third structure. Specifically, when the cache miss counts of the members in the second structure are similar, the order of each member can be adjusted according to the size of the member, thereby obtaining the corresponding third structure.

[0147] For example, still using Figure 8 Taking the second structure shown as an example, assume that the cache miss counts of members b, c, d, e, f, and h in this second structure are all similar. Compared to other members in the second structure, members b and e occupy less memory space. Therefore, in Figure 10Based on the third structure shown, the order of members b, c, d, e, f, and h is further adjusted to obtain... Figure 12 Another third structure shown and Figure 13 The diagram shows another storage layout for a third structure. It can be seen that... Figure 8 and Figure 10 The structures shown are all 64 bytes in size, while Figure 12 The structure shown is only 56 bytes in size, therefore, compared to Figure 8 and Figure 10 The structure shown, Figure 12 The structure shown occupies less storage space, meaning that the above method can improve cache utilization.

[0148] S306: Replace the second structure with the third structure described above.

[0149] This application also provides a compiler optimization apparatus for executing or implementing the compiler optimization method of the above-mentioned program source code. The function of the compiler optimization apparatus can be implemented by a software system, a hardware device, or a combination of a software system and a hardware device.

[0150] As mentioned above Figure 2 As shown, the compilation optimization apparatus provided in this application may include a running unit 110, an event acquisition unit 120, a parsing unit 130, and a compilation unit 140. The running unit 110 is used to execute the steps in S101 and S102 involving running the first executable file. The event acquisition unit 120 is used to execute the step in S102 involving acquiring hardware cache events. The parsing unit 130 is used to execute S103. The compilation unit 140 is used to execute S104, S201-S206, and S301-S306. For simplicity, further details are omitted here.

[0151] This application also provides a computing device for executing the compilation optimization method of the above-mentioned program source code. When the above-mentioned compilation optimization device 100 is a software system, the computing device may also deploy the above-mentioned compilation optimization device 100 to realize the function of the above-mentioned compilation optimization device 100.

[0152] like Figure 14 As shown, Figure 14 A schematic diagram of a computing device provided in this application is shown. The computing device 200 includes a memory 210, a processor 220, a communication interface 230, and a bus 240. The memory 210, processor 220, and communication interface 230 are interconnected via the bus 240.

[0153] The memory 210 can be a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 210 can store computer instructions, such as those in the execution unit 110, the event acquisition unit 120, the parsing unit 130, and the compilation unit 140. When the computer instructions stored in the memory 210 are executed by the processor 220, the processor 220 and the communication interface 230 are used to execute some or all of the methods described in steps S101-S104, S201-206, and S301-S306. The memory 210 can also store data, such as intermediate or result data generated by the processor 220 during execution, such as debugging information, prefetch distances, structure members, and second executable files.

[0154] The processor 220 may be a CPU, a microprocessor, an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), or one or more integrated circuits.

[0155] Processor 220 can also be an integrated circuit chip with signal processing capabilities. In implementation, some or all of the functions of the aforementioned compiler optimization device 100 can be completed through integrated logic circuits in the hardware of processor 220 or instructions in software form. Processor 220 can also be a general-purpose processor, a digital signal processor (DSP), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, thereby implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory 210. Processor 220 reads information from memory 210 and, in conjunction with its hardware, completes some or all of the functions of the aforementioned compiler optimization device 100.

[0156] The communication interface 230 uses, for example but not limited to, transceivers to enable communication between the computing device 200 and other devices or communication networks. For example, a first executable file and program source code can be obtained through the communication interface 230, and a compiled second executable file can also be sent to other devices through the communication interface 230.

[0157] Bus 240 may include a pathway for transmitting information between various components in computing device 200 (e.g., memory 210, processor 220, communication interface 230).

[0158] The descriptions of the processes corresponding to the above-mentioned figures each have their own emphasis. For parts of a process that are not described in detail, please refer to the relevant descriptions of other processes.

[0159] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, or a combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer program product. The computer program product providing the model training system includes one or more computational instructions executed by the model training system. When these computer program instructions are loaded and executed on a computer, they generate, in whole or in part, the processes or functions described in the embodiments of this application.

[0160] The aforementioned computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The aforementioned computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the aforementioned computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic cable, twisted pair, or wireless (e.g., infrared, wireless, microwave)) means. The aforementioned computer-readable storage medium stores computer program instructions that provide a model training system. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more media. The aforementioned available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., optical disc), or a semiconductor medium (e.g., solid-state disk (SSD)).

Claims

1. A method of compiler optimization, characterized by, The method comprises: running a first executable file, wherein the first executable file comprises an executable program and debugging information, the executable program is obtained by compiling program source code, the executable program comprises executable instructions, and the debugging information comprises a correspondence between the program source code and the executable instructions; collecting a hardware cache event; obtaining first configuration information according to the hardware cache event and the debugging information, wherein the first configuration information comprises an identifier of the program source code and a cache miss number corresponding to the identifier; compiling the program source code according to the first configuration information to obtain a second executable file, wherein the second executable file comprises a prefetch instruction or a third structure, the prefetch instruction is generated based on a prefetch distance calculated according to a single loop time of a first loop in the program source code, the prefetch distance represents an advance amount of moving a memory access object from a memory to a cache, a cache miss number of the first loop is greater than a first threshold, and the third structure is obtained by adjusting an order of members in a second structure in the program source code, a cache miss number of the second structure is greater than a fourth threshold.

2. The method of claim 1, wherein, The method further comprises: parsing the hardware cache event to obtain a cache miss number corresponding to the executable instructions; determining a cache miss number corresponding to source code associated with the executable instructions according to the cache miss number corresponding to the executable instructions and the debugging information, thereby obtaining the first configuration information.

3. The method of claim 1, wherein the compiling the program source code according to the first configuration information to obtain a second executable file comprises: parsing the first configuration information to determine source code in the program source code that satisfies a first condition, wherein the first condition comprises that a cache miss number of the source code is greater than the first threshold and the source code comprises a memory access object; calculating a prefetch distance of the source code that satisfies the first condition, wherein the prefetch distance represents an advance amount of moving the memory access object from a memory to a cache; generating the prefetch instruction according to the prefetch distance.

4. The method of claim 3, wherein, The calculating the prefetch distance of the source code that satisfies the first condition comprises: obtaining a control flow graph (CFG) of the first loop, wherein the first loop is an innermost loop that comprises the source code that satisfies the first condition, the CFG of the first loop comprises a plurality of basic blocks (BBs) and a plurality of directed edges, and the plurality of directed edges are used to indicate an execution order between the plurality of BBs; determining an execution probability of each directed edge; calculating a single loop time of the first loop according to the execution probability of each directed edge; calculating the prefetch distance of the source code that satisfies the first condition according to the single loop time of the first loop.

5. The method of claim 4, wherein, The obtaining the CFG of the first loop comprises: parsing the first configuration information to determine a function in the program source code that satisfies a second condition, wherein the second condition is that a cache miss number of the function is greater than a second threshold, and the cache miss number of the function is a sum of cache miss numbers of source code included in the function. determining a first loop in the function satisfying the second condition, the first loop being an innermost loop in the function satisfying the second condition, and an execution probability of the first loop iteration being greater than a third threshold value; constructing a CFG of the first loop.

6. The method according to claim 4 or 5, characterized in that, the calculating the single-loop execution time of the first loop according to the execution probability of each directed edge, comprising: determining BBs and directed edges irrelevant to the loop level of the first loop; trimming the irrelevant BBs and directed edges to obtain a second loop; calculating the execution probability of each BB in the second loop according to the execution probability of each directed edge, to obtain the single-loop execution time of the first loop, the single-loop execution time of the first loop being a sum of products of the execution probability of each BB and the execution time of each BB.

7. The method of claim 1, wherein, before the compiling the program source code according to the first configuration information to obtain a second executable file, the method further comprising: obtaining a plurality of structures in the program source code, and members in the plurality of structures; the compiling the program source code according to the first configuration information to obtain a second executable file, comprising: parsing the first configuration information to determine a structure satisfying a third condition in the plurality of structures, the third condition comprising: there is no sequential dependency in use among members in the structure, and the cache miss times of the structure are greater than the fourth threshold value; adjusting the order of the members in the structure satisfying the third condition to obtain a new structure; replacing the structure satisfying the third condition with the new structure.

8. The method of claim 7, wherein, each structure comprising source code in the program source code, the parsing the first configuration information to determine the structure satisfying the third condition, comprising: parsing the first configuration information to determine the identifier of the program source code and the cache miss times corresponding to the identifier; obtaining the cache miss times of each structure according to the identifier of the program source code and the cache miss times corresponding to the identifier, to determine the structure satisfying the third condition.

9. The method according to claim 7 or 8, characterized in that, the adjusting the order of the members in the structure satisfying the third condition, comprising: obtaining the cache miss times of a plurality of members in the structure satisfying the third condition; adjusting the order of the plurality of members according to the size of the cache miss times of the plurality of members.

10. The method of claim 9, wherein, the adjusting the order of the plurality of members according to the size of the cache miss times of the plurality of members, comprising: obtaining the size of each member in the plurality of members; adjusting the order of the plurality of members according to the size of each member and the cache miss times of each member.

11. A compiler optimization apparatus, characterized by, the apparatus comprising: a running unit configured to run a first executable file, wherein the first executable file comprises an executable program and debugging information, the executable program being obtained by compiling a program source code, the executable program comprising executable instructions, and the debugging information comprising a correspondence between the program source code and the executable instructions; an event collection unit configured to collect a hardware cache event; An analyzing unit is configured to obtain first configuration information according to the hardware cache event and the debugging information, the first configuration information including identification of the program source code and cache miss times corresponding to the identification; A compiling unit is configured to compile the program source code according to the first configuration information to obtain a second executable file, the second executable file including a prefetch instruction or a third structure, wherein the prefetch instruction is generated based on a prefetch distance calculated according to a single loop time of a first loop in the program source code, the prefetch distance representing an advance amount of moving a memory access object from a memory to a cache, the cache miss times of the first loop being greater than a first threshold, and the third structure is obtained by adjusting an order of members in a second structure in the program source code, the cache miss times of the second structure being greater than a fourth threshold.

12. The apparatus of claim 11, wherein, The analyzing unit is specifically configured to: analyze the hardware cache event to obtain cache miss times corresponding to the executable instruction; and determine cache miss times corresponding to source code associated with the executable instruction according to the cache miss times corresponding to the executable instruction and the debugging information, so as to obtain the first configuration information.

13. The apparatus of claim 11, wherein the compiling unit is specifically configured to: parsing the first configuration information, determining source code in the program source code satisfying a first condition, wherein, the first condition includes that the cache miss times of the source code are greater than the first threshold, and the source code includes a memory access object; calculate a prefetch distance of the source code satisfying the first condition, the prefetch distance representing an advance amount of moving the memory access object from a memory to a cache; generate the prefetch instruction according to the prefetch distance.

14. The apparatus of claim 13, wherein, The compiling unit is specifically configured to: obtain a control flow graph (CFG) of the first loop, the first loop being a most inner loop including the source code satisfying the first condition, the CFG of the first loop including a plurality of basic blocks (BBs) and a plurality of directed edges, the plurality of directed edges being used to indicate an execution order between the plurality of BBs; determine an execution probability of each directed edge in the plurality of directed edges; calculate a single loop time of the first loop according to the execution probability of each directed edge; calculate the prefetch distance of the source code satisfying the first condition according to the single loop time of the first loop.

15. The apparatus of claim 14, wherein, The compiling unit is specifically configured to: analyze the first configuration information to determine a function satisfying a second condition in the program source code, wherein the second condition is that cache miss times of the function are greater than a second threshold, and the cache miss times of the function are a sum of cache miss times of source codes included in the function; determine a first loop in the function satisfying the second condition, the first loop being a most inner loop in the function satisfying the second condition, and an execution probability of iteration of the first loop being greater than a third threshold; construct a CFG of the first loop.

16. The apparatus of claim 14 or 15, wherein, The compiling unit is specifically configured to: determine BBs and directed edges irrelevant to a loop layer of the first loop; trim the irrelevant BBs and directed edges to obtain a second loop. According to the execution probability of each directed edge, an execution probability of each BB in the second loop is calculated, and a single-cycle time of the first loop is obtained, which is a sum of products of the execution probability of each BB and an execution time of each BB.

17. The apparatus of claim 11, wherein, The compiling unit is further configured to: obtain a plurality of structures in the program source code, and members in the plurality of structures; The compiling unit is further configured to: analyze the first configuration information to determine a structure in the plurality of structures that satisfies a third condition, the third condition comprising that each member in the structure has no sequential dependency in use, and a cache miss number of the structure is greater than the fourth threshold value; adjust an order of the members in the structure that satisfies the third condition to obtain a new structure; replace the structure that satisfies the third condition with the new structure.

18. The apparatus of claim 17, wherein, Each structure comprises source code in the program source code, and the compiling unit is specifically configured to: analyze the first configuration information to determine a cache miss number corresponding to source code associated with the executable instruction; obtain a cache miss number of each structure according to the cache miss number corresponding to the source code associated with the executable instruction, so as to determine the structure that satisfies the third condition.

19. The apparatus of claim 17 or 18, wherein, The compiling unit is specifically configured to: obtain cache miss numbers of a plurality of members in the structure that satisfies the third condition; adjust an order of the plurality of members according to sizes of the cache miss numbers of the plurality of members.

20. The apparatus of claim 19, wherein, The compiling unit is specifically configured to: obtain a size of each member in the plurality of members; adjust an order of the plurality of members according to the size of each member and the cache miss number of each member.

21. A computing device, comprising: The computing device comprises a processor and a memory, the memory stores computer instructions, and the processor executes the computer instructions to enable the computing device to perform the method in any one of the preceding claims 1-10.

22. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, and when the computer instructions are executed by a computing device, the computing device performs the method in any one of the preceding claims 1-10. The computer readable storage medium stores computer instructions, and when the computer instructions are executed by a computing device, the computing device performs the method in any one of the preceding claims 1-10.

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