Method for adding time sequence monitoring circuit of chip and chip

Abstract

The invention discloses an adding method of a time sequence monitoring circuit of a chip and the chip, and belongs to the technical field of chips. The method comprises the following steps: determining time sequence influence parameters of N first time sequence critical paths of a chip; based on the design parameters of the chip and the time sequence influence parameters of the N first time sequence critical paths, M second time sequence critical paths of the chip are generated, and M is larger than or equal to N; and adding a time sequence monitoring circuit to each second time sequence critical path.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a method for adding a timing monitoring circuit to a chip and a chip. Background Art

[0002] As chip functions become increasingly powerful, chip power consumption is also increasing, and energy saving has become an important design factor in chip development. In order to achieve chip energy saving, adaptive voltage regulation is currently mainly performed by monitoring the timing status of the chip. The commonly used method is: first obtain the critical path of the chip through preliminary simulation, and add a timing monitoring circuit near the critical path to monitor the working margin of the timing circuit, and perform voltage regulation control based on this. However, the path obtained through preliminary simulation may not be the actual critical path of the chip, which results in the monitored timing circuit not being able to accurately reflect the actual working status of the chip. Summary of the invention

[0003] The embodiments of the present application provide a method for adding a timing monitoring circuit to a chip and a chip, which can solve the problem of how to make the timing monitoring results closer to the actual state of chip operation.

[0004] In order to solve the above technical problems, this application is implemented as follows:

[0005] In a first aspect, a method for adding a timing monitoring circuit to a chip is provided, comprising: determining the timing influencing parameters of N first timing critical paths of the chip; generating M second timing critical paths of the chip based on the design parameters of the chip and the timing influencing parameters of the N first timing critical paths, where M is greater than or equal to N; and adding a timing monitoring circuit to each of the second timing critical paths.

[0006] In a second aspect, a chip is provided, comprising: M second timing critical paths, wherein the M second timing critical paths are regenerated based on the manufacturing parameters of the chip and the acquired timing influencing parameters of N first timing critical paths; M timing monitoring circuits, wherein each of the timing monitoring circuits corresponds to one of the second timing critical paths, and the timing monitoring circuits are generated using the method described in the first aspect.

[0007] According to a third aspect, an electronic device is provided, comprising a processor and a memory, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the steps of the method described in the first aspect.

[0008] In a fourth aspect, a computer-readable storage medium is provided, wherein at least one computer program is stored in the computer-readable storage medium, and the computer program is loaded and executed by a processor to implement the steps of the method described in the first aspect above.

[0009] In a fifth aspect, a computer program product is provided, the computer program product comprising at least one computer program, the computer program being loaded and executed by a processor to implement the steps of the method described in the first aspect above.

[0010] The technical solution provided by this application may have the following beneficial effects:

[0011] In an embodiment of the present application, the timing influencing parameters of the N first timing critical paths are obtained by analyzing the N first timing critical paths, and then the M second timing critical paths of the chip are generated according to the design parameters of the chip and the timing influencing parameters of the N first timing critical paths. Finally, a timing monitoring circuit is added to each second timing critical path, which makes the generated second timing critical path closer to the actual critical path of the chip, and the final timing monitoring result is also closer to the actual state of the chip operation.

[0012] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0014] Figure 1 A schematic diagram of a chip design is shown;

[0015] Figure 2 A schematic diagram showing a method for implementing a timing monitoring circuit in a traditional AVS design is shown;

[0016] Figure 3 A schematic flow chart of a method for adding a timing monitoring circuit to a chip provided by an exemplary embodiment of the present application is shown;

[0017] Figure 4 A schematic diagram of the structure of a chip provided by an exemplary embodiment of the present application is shown;

[0018] Figure 5 Another schematic flow chart of a method for adding a timing monitoring circuit to a chip provided by an exemplary embodiment of the present application is shown;

[0019] Figure 6Another schematic flow chart of a method for adding a timing monitoring circuit to a chip provided by an exemplary embodiment of the present application is shown;

[0020] Figure 7 Another schematic flow chart of a method for adding a timing monitoring circuit to a chip provided by an exemplary embodiment of the present application is shown;

[0021] Figure 8 Another schematic flow chart of a method for adding a timing monitoring circuit to a chip provided by an exemplary embodiment of the present application is shown;

[0022] Fig. 9 Another schematic flow chart of a method for adding a timing monitoring circuit to a chip provided by an exemplary embodiment of the present application is shown;

[0023] Fig.10 A schematic diagram of the structure of a chip provided by an exemplary embodiment of the present application is shown;

[0024] Fig.11 A schematic diagram of the structure of a chip provided by an exemplary embodiment of the present application is shown;

[0025] Fig.12 A schematic diagram of the structure of a chip provided by an exemplary embodiment of the present application is shown;

[0026] Fig.13 A schematic diagram showing a working principle of a chip provided by an exemplary embodiment of the present application is shown;

[0027] Fig.14 A structural block diagram of an electronic device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0029] In order to better understand the technical solution provided by this application, the technology involved in this application is first introduced.

[0030] In order to cope with the impact of process, voltage, temperature, aging and other factors on the timing of internal logic circuits during chip design, a certain design margin is usually reserved, resulting in the power supply voltage required by the chip being greater than the operating voltage required for logic operation under normal conditions. Figure 1 The voltagemargin part shown is the additional core voltage that the chip adds to ensure that it can work normally under various changing factors.

[0031] Adaptive Voltage Scaling (AVS) is a commonly used chip adaptive voltage regulation solution. The principle is to monitor the timing circuit status of the chip in real time. When there is a large margin in the timing, the chip core voltage is reduced to consume these design margins, thereby ensuring the normal operation of the chip while saving energy. In the traditional AVS implementation, in order to ensure that the monitored timing circuit can reflect the actual working status of the chip as accurately as possible, the commonly used method is: first obtain the critical path of the chip (the place with the most stringent timing) through preliminary simulation, and add a timing monitoring circuit near the critical path to monitor the working margin of the timing circuit, and perform voltage regulation control based on this, such as Figure 2 As shown in the figure, it is the implementation scheme of the timing monitoring circuit in the traditional AVS design. However, this scheme has the following problems:

[0032] (1) The chip manufacturing process is very complicated, and the critical path obtained through simulation in the early stage may not be the actual critical path of the chip.

[0033] (2) During operation, the chip is affected by factors such as temperature, voltage drop, and aging, and the location of the critical path may change with the operating environment.

[0034] In order to solve the above problems, a certain protection margin is usually reserved on top of the timing detection result when regulating the voltage. However, excessive protection margin actually reduces the voltage regulation capability and reduces energy-saving efficiency.

[0035] In view of this, the present application proposes a method for adding a timing monitoring circuit to a chip and a chip, which can make the timing monitoring results closer to the actual state of chip operation, reduce the design of protection margin, and improve energy saving efficiency.

[0036] Figure 3 A flow chart showing a method for adding a timing monitoring circuit to a chip in an embodiment of the present application is shown. Figure 3 As shown, the method may include the following steps.

[0037] S310: Determine the timing influencing parameters of N first timing critical paths of the chip.

[0038] It can be understood that N first timing critical paths of the chip can be obtained through simulation processing, and the N first timing critical paths can appear at any position in the chip, such as Figure 4 As shown, the layout position of the first timing critical path 401 in the chip 400 is shown. Figure 4 This is only an example. Among them, chip simulation processing refers to the process of computer simulation and analysis of chip circuits using Electronic Design Automation (EDA) tools. Through simulation processing, the circuit function, performance and reliability of the chip can be predicted and evaluated before the chip design is implemented. Since the chip may be affected by factors such as temperature, voltage drop, aging, etc. during operation, the position of the actual critical path of the chip may change with the operating environment. In order to analyze the impact of the above factors on the actual critical path of the chip, the timing impact parameters of the N first timing critical paths can be determined first.

[0039] S320: Generate M second timing critical paths of the chip based on the design parameters of the chip and the timing impact parameters of the N first timing critical paths, where M is greater than or equal to N.

[0040] Among them, one or more second timing critical paths can be generated according to a first timing critical path.

[0041] It is understandable that the design of each chip may be different. In order to accurately obtain the real critical timing path corresponding to the chip, it is necessary to generate M second critical timing paths based on the design parameters of the chip and the timing impact parameters of the N first critical timing paths determined in S320. By comprehensively considering the design parameters of the chip itself and the timing impact parameters of the N first critical timing paths, the reliability of the second critical timing path can be improved, so that when performing timing monitoring, the timing monitoring results obtained are closer to the actual state of chip operation.

[0042] S330: Add a timing monitoring circuit to each of the second timing critical paths.

[0043] It is understandable that by adding one or more timing monitoring circuits to each of the second timing critical paths, the power consumption on the second timing critical paths can be monitored through the timing monitoring circuits, and corresponding power consumption management strategies can be adopted to reduce the overall power consumption of the chip.

[0044] In an embodiment of the present application, the timing influencing parameters of the N first timing critical paths are obtained by analyzing the N first timing critical paths, and then the M second timing critical paths of the chip are generated according to the design parameters of the chip and the timing influencing parameters of the N first timing critical paths. Finally, a timing monitoring circuit is added to each second timing critical path, which makes the generated second timing critical path closer to the actual critical path of the chip, and the final timing monitoring result is also closer to the actual state of the chip operation.

[0045] In one implementation, determining the timing impact parameters of the N first timing critical paths may include: obtaining the static voltage drop, dynamic voltage drop and area density parameters of each of the first critical paths according to the position, structure and function of each of the first critical paths in the chip. That is, the timing impact parameters may include static voltage drop, dynamic voltage drop and area density parameters, wherein the static voltage drop and dynamic voltage drop are mainly used to extract voltage drop data, and the area density parameters are mainly used to extract temperature data. The timing impact parameters can be determined by analyzing the position, structure and function of each first timing critical path in the chip. Optionally, the timing impact parameters can also be determined by at least one of the position, structure and function.

[0046] Figure 5 Another flow chart of the method for adding a timing monitoring circuit to a chip in an embodiment of the present application is shown. Figure 5 As shown, the method may include the following steps.

[0047] S510: Determine timing influencing parameters of N first timing critical paths of the chip.

[0048] For more information about S510, please refer to Figure 1 The description of S310 in the embodiment is not repeated here.

[0049] S522: Based on the simulation result of the chip, obtain the influence range of the design parameters of the chip on the timing.

[0050] The design parameters of the chip may include at least one of the following: process, temperature, and aging.

[0051] It is understandable that factors such as process, temperature, and aging are considered during the chip design process. These factors will affect the timing, and the scope of the impact can be determined based on the simulation results of the chip, that is, the minimum and maximum changes that affect the timing.

[0052] S524: Based on the impact range of the chip design parameters on timing and the timing impact parameters of the N first timing critical paths, obtain the timing degradation range of the chip in each area.

[0053] That is, after determining the influence range of the chip design parameters on the timing, the timing degradation range of the chip in each region can be determined according to the timing influence parameter of each first timing critical path.

[0054] S526: Based on a preset screening condition, copy n of the N first timing critical paths to obtain M timing copy paths.

[0055] Wherein, n is less than or equal to N.

[0056] That is to say, n timing critical paths are selected from the N first timing critical paths for replication to obtain M timing replication paths, wherein the n timing critical paths are typical and representative paths, and the preset screening conditions can be set according to the specific circumstances, which is not limited in this application.

[0057] S528: Based on the timing degradation range of the chip in each area, the M timing replication paths are corrected to obtain the M second timing critical paths.

[0058] In one implementation, S528 may include: based on the timing degradation range of the chip in each region, adding a variable delay chain to the timing replication path in each region, and using the timing replication path with the added variable delay chain as the second timing critical path. In other words, the M timing replication paths are corrected by adding a variable delay chain.

[0059] S530: Add a timing monitoring circuit to each of the second timing critical paths.

[0060] For more information about S530, please refer to Figure 1 The description of S330 in the embodiment is not repeated here.

[0061] Below through Figure 6 right Figure 5 The embodiment shown is specifically described, referring to Figure 6, through the preliminary simulation, multiple timing critical paths in a certain area of ​​the chip are obtained; according to the position, structure and function of each path in the chip, the static voltage drop, dynamic voltage drop and regional density parameters corresponding to each critical path are extracted. Among them, the effects of process, ambient temperature and aging should also be considered in the parameter extraction process. These parameters are extracted in units of chips and do not need to be extracted from each selected critical path. By normalizing the aforementioned extracted parameters, the possible timing deterioration range in different areas of the chip can be obtained. The range refers to the interval between the minimum change that affects the timing and the maximum change that affects the timing. Then, a typical path is selected from the multiple timing critical paths in a certain area of ​​the chip obtained through the preliminary simulation for replication, and the replication circuit is modified according to the timing deterioration range, and a new critical path is obtained by adding an additional variable delay chain. Finally, a timing monitoring circuit is added to the new critical path.

[0062] Based on the above Figure 3 or Figure 5 The embodiment shown, further, as Figure 7 As shown, after adding a timing monitoring circuit to each of the second timing critical paths, the method may further include the following steps:

[0063] S710: Based on the resource distribution and structural characteristics of the chip, obtain the arrangement positions of M timing detection modules inside the chip.

[0064] Wherein, the timing detection module includes a second timing critical path and a timing monitoring circuit of the second timing critical path.

[0065] In one implementation, S710 may include:

[0066] S712: Divide the chip into regions according to resource distribution and voltage regulation benefit of the chip to obtain a plurality of target regions.

[0067] Among them, in another implementation, S712 may include determining the placement accuracy of the timing monitoring circuit according to the resource distribution and voltage regulation benefit of the chip; based on the placement accuracy of the timing monitoring circuit, the chip is divided into regions to obtain multiple target regions. It is understandable that different regions inside the chip may have different power consumption requirements. By dividing the chip into regions to obtain multiple target regions, the power consumption of each region can be independently controlled to achieve overall power consumption optimization.

[0068] S714: Determine the number of timing monitoring circuits arranged in each of the target areas according to the structural characteristics of the chip and the simulation processing results.

[0069] Wherein, in another implementation, S714 may include determining the heat density distribution in each of the target areas according to the structural characteristics of the chip and the simulation processing results; and determining the number of timing monitoring circuits arranged in each of the target areas according to the heat density distribution in each of the target areas. Wherein, the heat density distribution refers to the spatial distribution of the heat generated in each target area. Since local overheating of the chip will increase the risk of internal circuit timing deterioration, it is necessary to arrange more monitoring circuits in areas with higher heat density to monitor the deterioration state in the area in real time, and to boost the voltage when the timing deteriorates seriously to ensure the normal function of the circuit. Therefore, it is necessary to determine the number of timing monitoring circuits arranged in each of the target areas according to the heat density distribution of each target area to ensure the reliability of the circuit.

[0070] In S714, the number of timing monitoring circuits arranged in each of the target areas is determined according to the structural characteristics of the chip and the simulation results, so as to improve the performance and reliability of the chip.

[0071] S716: Determine the arrangement positions of the M timing detection modules inside the chip according to the target regions and the number of timing monitoring circuits arranged in each of the target regions.

[0072] In this implementation, by comprehensively considering the chip's resource distribution, voltage regulation benefits, structural characteristics, simulation processing results, and heat density distribution, the arrangement positions of M timing detection modules inside the chip are given, which effectively improves the chip's performance and reliability.

[0073] S720: Arrange each of the timing detection modules inside the chip according to the arrangement position of each of the timing detection modules.

[0074] That is to say, each second timing critical path and the corresponding timing monitoring circuit are laid out in the chip.

[0075] exist Figure 7 In the illustrated embodiment, the arrangement positions of the M timing detection modules inside the chip are determined by comprehensively considering the resource distribution and structural characteristics of the chip, and then each timing detection module is arranged inside the chip according to the arrangement position of each timing detection module, so that the layout of the M timing detection modules in the chip is more reasonable.

[0076] Below through Figure 8 The above embodiments are described in detail. Figure 8 As shown, the following steps may be included:

[0077] S810: Chip power-on initialization is completed.

[0078] S820: Divide the chips into areas according to placement accuracy.

[0079] S830: Determine the heat density distribution in each area according to the chip structure and simulation results.

[0080] S840: Determine placement data of monitoring circuits in each area according to the heat density distribution.

[0081] S850: Placing the monitoring circuits in each area according to the placement data of the monitoring circuits in each area.

[0082] exist Figure 8 In the illustrated embodiment, placement data of the monitoring circuits in each area are given by comprehensively considering the chip resources, voltage regulation benefits, chip structure, simulation processing results and heat density distribution, so that the monitoring circuits are placed at corresponding positions according to the placement data, so that the generated second timing critical path is closer to the actual critical path of the chip, and the final timing monitoring result is also closer to the actual state of the chip operation.

[0083] Further, after each of the timing detection modules is arranged inside the chip according to the arrangement position of each of the timing detection modules, the method further includes: calibrating the actual circuit on the chip by setting X calibration circuits, where X is an integer less than or equal to M. It can be understood that the calibration circuit can dynamically adjust and optimize the actual circuit on the chip to ensure that the chip can maintain good performance and stability under various conditions, wherein the actual circuit in this application is the circuit that the chip actually works on.

[0084] In one implementation, the actual circuit on the chip is calibrated by setting X calibration circuits, including: when it is determined to start the timing calibration, the power supply voltage of the chip is reduced in sequence; in the process of reducing the power supply voltage of the chip each time, the working state of the actual circuit corresponding to the current voltage reduction is obtained, and the working state corresponding to the previous voltage reduction is compared with the working state corresponding to the current voltage reduction. When it is determined that the working state corresponding to the current voltage reduction is abnormal and the working state corresponding to the previous voltage reduction is normal, the voltage reduction is stopped, and the supply voltage value corresponding to the previous voltage reduction is used as the lower limit of the input voltage of the chip.

[0085] It is understandable that each of the timing detection modules is placed around the actual circuit in certain positions in the chip. By gradually reducing the voltage until the actual working circuit function is just abnormal, the data of the actual circuit surrounded by the timing detection module is analyzed to see if it is correct. When the voltage is reduced and it is found that the output of the actual circuit is incorrect, the voltage is read from the initial value to the current value, and the result of the timing monitoring circuit is read to make corrections. In other words, this process can be called determining the voltage lower limit of the calibration circuit. For example, assuming that the calibration circuit has 10 reporting states from 0 to 9, the smaller the value, the worse the timing. Usually, the lower limit of all calibration circuits can be 0, but the actual situation will not be consistent with the design expectations. The above calibration process is to read which level of 0 to 9 the current state of the detection circuit is in after the actual circuit error is found, and then use the input voltage lower limit value corresponding to this level as the actual lower limit.

[0086] Furthermore, the method also includes: performing corrections by setting up X calibration circuits and M timing monitoring circuits. Wherein, in another implementation, performing calibrations by setting up X calibration circuits and M timing monitoring circuits includes: in the case of determining to start the timing calibration, sequentially reducing the power supply voltage of the chip; in the process of reducing the power supply voltage of the chip each time, obtaining the working state of the chip corresponding to the current voltage reduction, comparing the working state corresponding to the previous voltage reduction with the working state corresponding to the current voltage reduction, and stopping the voltage reduction when it is determined that the working state corresponding to the current voltage reduction is abnormal and the working state corresponding to the previous voltage reduction is normal; obtaining the detection results output by the M timing monitoring circuits after each voltage reduction; and correcting the mapping relationship between the voltage drop and the timing deterioration of the M timing monitoring circuits according to the reduction value of the power supply voltage each time and the detection results output by the M timing monitoring circuits. The following is through Fig. 9 The implementation method is described in detail, such as Fig. 9 As shown, the following steps may be included:

[0087] S910: Chip power-on initialization is completed.

[0088] S920: Whether to start timing calibration.

[0089] S930: Reduce the chip power supply voltage.

[0090] S940: Determine whether the functional module works normally.

[0091] S950: Stop voltage regulation.

[0092] S960: Read the timing monitoring circuit result.

[0093] S970: Determine whether the timing monitoring result meets expectations.

[0094] S980: Correct the timing monitoring.

[0095] S990: End.

[0096] It can be understood that by gradually reducing the operating voltage of the chip until the actual working circuit function is just abnormal, since the actual circuit is a known state for the chip design, the timing state of the monitoring circuit is read again at this time to determine whether it is consistent with the timing state of the actual circuit. If the two are consistent, it means that the design performance of the timing monitoring circuit is the same as the actual circuit, and no calibration is required. If the two are different, the result of the timing monitoring circuit is corrected and matched with the actual circuit to complete the calibration.

[0097] That is to say, when performing timing detection on the second timing critical path, it is necessary to configure the minimum threshold and voltage regulation accuracy of the voltage regulation. These parameters can be predicted in the early simulation, but since the design may deviate from expectations due to differences in temperature, pressure, dopant concentration, etc. during the chip production process, these parameters need to be corrected through calibration during the chip initialization stage.

[0098] Fig.10 A schematic diagram of the structure of the chip disclosed in the embodiment of the present application is shown, Fig.10 As shown, the chip 1000 may include M second timing critical paths 1001 and M timing monitoring circuits 1002, wherein the M second timing critical paths 1001 are regenerated based on the manufacturing parameters of the chip and the timing influencing parameters of the N first timing critical paths obtained, each of the timing monitoring circuits 1002 corresponds to one of the second timing critical paths 1001, and the timing monitoring circuits 1002 adopt Figures 3 to 9 The method of any of the illustrated embodiments generates.

[0099] In an embodiment of the present application, the second timing critical path is regenerated based on the manufacturing parameters of the chip and the timing influencing parameters of the N first timing critical paths obtained, and each second timing critical path corresponds to a timing monitoring circuit, which can ensure that the chip can meet the timing requirements during the design, verification and operation stages, thereby achieving energy saving.

[0100] Further, Fig.11 Another schematic diagram of the structure of the chip disclosed in the embodiment of the present application is shown, Fig.11 As shown, M timing detection modules 1110 are arranged around the actual circuit of the chip, wherein the timing detection module includes Fig.10The second critical timing path 1001 and the timing monitoring circuit 1002 of the second critical path in the illustrated embodiment. It can be understood that the actual circuit is an actual working circuit, and by arranging the M timing detection modules 1110 around the actual circuit, it is more convenient to test and debug, because the timing detection module can directly access and monitor the signal of the actual circuit, which is convenient for observing and analyzing the behavior of the chip during operation, and is conducive to performance optimization and calibration.

[0101] Further, Fig.12 Another schematic diagram of the structure of the chip disclosed in the embodiment of the present application is shown, Fig.12 As shown, the chip further includes X calibration circuits 1201, each calibration circuit is connected to at least one actual circuit, X is an integer less than or equal to M, and is used to calibrate one or more actual circuits on the chip.

[0102] In one implementation, the calibration circuit includes: a functional correctness judgment circuit, wherein the functional correctness judgment circuit is connected to at least one of the actual circuits and is used to perform correctness verification on data output when the chip operates through the actual circuit.

[0103] In another implementation, the calibration circuit further includes: a timing calibration circuit; the timing calibration circuit is connected to the function correctness judgment circuit and the timing monitoring circuit respectively, and is used to obtain the verification result output by the function correctness judgment circuit and the detection result output by the timing monitoring circuit, and to correct the mapping relationship between the voltage drop and the timing degradation of the M timing monitoring circuits. Fig.13 The implementation method is described as follows: Fig.13 As shown, it is a working schematic diagram of the calibration circuit, the output data of the actual working circuit is obtained through the functional correctness judgment circuit, and the output data is judged to obtain the functional judgment result, and then the output data of each actual working circuit is obtained and analyzed through each timing monitoring circuit to obtain the timing detection result, and finally the timing calibration circuit is used to calibrate according to the functional judgment result and the timing detection result.

[0104] Optional, such as Fig.14 As shown, the embodiment of the present application also provides an electronic device 1400, including a processor 1401 and a memory 1402, the memory 1402 stores a program or instruction that can be run on the processor 1401, and the program or instruction is executed by the processor 1401 to implement the above Figures 3 to 9 The various steps of the illustrated embodiments can achieve the same technical effect, and will not be described again here to avoid repetition.

[0105] The embodiment of the present application also provides a readable storage medium on which a program or instruction is stored. When the program or instruction is executed by a processor, the above Figures 3 to 9 The various processes of the illustrated embodiments can achieve the same technical effect, and will not be described again here to avoid repetition.

[0106] The processor is the processor in the terminal described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk. In some examples, the readable storage medium may be a non-transient readable storage medium.

[0107] The present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the above Figures 3 to 9 The various processes of the illustrated embodiments can achieve the same technical effect, and will not be described again here to avoid repetition.

[0108] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0109] The present application embodiment further provides a computer program / program product, wherein the computer program / program product is stored in a storage medium, and the computer program / program product is executed by at least one processor to implement the above Figures 3 to 9 The various processes of the illustrated embodiments can achieve the same technical effect, and will not be described again here to avoid repetition.

[0110] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0111] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of a computer software product plus a necessary general hardware platform, and of course, can also be implemented by hardware. The computer software product is stored in a storage medium (such as ROM, RAM, disk, CD, etc.), including several instructions to enable a terminal or a network-side device to execute the methods described in each embodiment of the present application.

[0112] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms of implementation methods without departing from the purpose of the present application and the scope of protection of the claims, and these implementation methods are all within the protection of the present application.

Claims

1. A method for adding a timing monitoring circuit to a chip, characterized in that: include: Determine the timing influencing parameters of N first timing critical paths of the chip; Based on the design parameters of the chip and the timing impact parameters of the N first timing critical paths, M second timing critical paths of the chip are generated, where M is greater than or equal to N; A timing monitoring circuit is added to each of the second timing critical paths.

2. The method according to claim 1, characterized in that The determining of the timing impact parameters of the N first timing critical paths includes: According to the position, structure and function of each of the first timing critical paths in the chip, the static voltage drop, dynamic voltage drop and area density parameters of each of the first critical paths are obtained.

3. The method according to claim 1, characterized in that Based on the design parameters of the chip and the timing impact parameters of the N first timing critical paths, M second timing critical paths of the chip are generated, including: Based on the simulation results of the chip, obtaining the influence range of the design parameters of the chip on the timing; Based on the influence range of the chip design parameters on the timing and the timing influence parameters of the N first timing critical paths, obtaining the timing degradation range of the chip in each area; Based on a preset screening condition, copy n of the N first timing critical paths to obtain M timing copy paths, where n is less than or equal to N; Based on the timing degradation range of the chip in each area, the M timing replication paths are corrected to obtain the M second timing critical paths.

4. The method according to claim 3, characterized in that Based on the timing degradation ranges in different regions of the chip, the M timing replication paths are corrected to obtain the M second timing critical paths, including: Based on the timing degradation range of the chip in each region, a variable delay chain is added to the timing replication path located in each region, and the timing replication path with the variable delay chain added is used as the second timing critical path.

5. The method according to any one of claims 1 to 4, characterized in that: After adding a timing monitoring circuit to each of the second timing critical paths, the method further includes: Based on the resource distribution and structural characteristics of the chip, obtaining the arrangement positions of M timing detection modules inside the chip, wherein the timing detection module includes a second timing critical path and a timing monitoring circuit of the second timing critical path; According to the arrangement position of each timing detection module, each timing detection module is arranged inside the chip.

6. The method according to claim 5, characterized in that The obtaining, based on the resource distribution and structural characteristics of the chip, the arrangement positions of the M timing detection modules inside the chip includes: According to the resource distribution and voltage regulation benefit of the chip, the chip is divided into regions to obtain a plurality of target regions; Determining the number of timing monitoring circuits arranged in each of the target areas according to the structural characteristics of the chip and the simulation processing results; The arrangement positions of the M timing detection modules inside the chip are determined according to the target regions and the number of timing monitoring circuits arranged in each of the target regions.

7. The method according to claim 6, characterized in that According to the resource distribution and voltage regulation benefit of the chip, the chip is divided into regions to obtain multiple target regions, including: Determining the placement accuracy of the timing monitoring circuit according to the resource distribution and voltage regulation benefit of the chip; Based on the placement accuracy of the timing monitoring circuit, the chip is divided into regions to obtain a plurality of target regions.

8. The method according to claim 6, characterized in that The step of determining the number of timing monitoring circuits arranged in each of the target areas according to the structural characteristics of the chip and the simulation processing result includes: Determining the heat density distribution in each of the target areas according to the structural characteristics of the chip and the simulation processing results; The number of timing monitoring circuits arranged in each of the target areas is determined according to the heat density distribution in each of the target areas.

9. The method according to claim 5, characterized in that After arranging each of the timing detection modules inside the chip according to the arrangement position of each of the timing detection modules, the method further includes: The actual circuit on the chip is calibrated by setting X calibration circuits, where X is an integer less than or equal to M.

10. The method according to claim 9, characterized in that The actual circuit on the chip is calibrated by setting X calibration circuits, including: When determining to start the timing calibration, sequentially reducing the supply voltage of the chip; In the process of reducing the power supply voltage of the chip each time, the working state of the actual circuit corresponding to the current voltage reduction is obtained, and the working state corresponding to the previous voltage reduction is compared with the working state corresponding to the current voltage reduction. When it is determined that the working state corresponding to the current voltage reduction is abnormal and the working state corresponding to the previous voltage reduction is normal, the voltage reduction is stopped, and the supply voltage value corresponding to the previous voltage reduction is used as the lower limit value of the input voltage of the chip.

11. The method according to claim 9, characterized in that The method further comprises: The correction is performed by setting X calibration circuits and M timing monitoring circuits.

12. The method according to claim 11, characterized in that Calibration is performed by setting X calibration circuits and M timing monitoring circuits, including: When determining to start the timing calibration, sequentially reducing the supply voltage of the chip; In each process of reducing the power supply voltage of the chip, the working state of the chip corresponding to the current voltage reduction is obtained, the working state corresponding to the previous voltage reduction is compared with the working state corresponding to the current voltage reduction, and when it is determined that the working state corresponding to the current voltage reduction is abnormal and the working state corresponding to the previous voltage reduction is normal, the voltage reduction is stopped; Obtaining the detection results output by the M timing monitoring circuits after each voltage reduction; According to the decrease value of the power supply voltage each time and the detection results output by the M timing monitoring circuits, the mapping relationship between the voltage drop and the timing degradation of the M timing monitoring circuits is corrected.

13. A chip, characterized in that: include: M second timing critical paths, wherein the M second timing critical paths are regenerated based on the manufacturing parameters of the chip and the acquired timing impact parameters of the N first timing critical paths; M timing monitoring circuits, wherein each of the timing monitoring circuits corresponds to one of the second timing critical paths, and the timing monitoring circuits are generated by the method described in any one of claims 1 to 12.

14. The chip according to claim 13, characterized in that: M timing detection modules are arranged around the actual circuit of the chip, wherein the timing detection module includes a second critical path and a timing monitoring circuit of the second critical path.

15. The chip according to claim 13 or 14, characterized in that: Also includes: There are X calibration circuits, each of which is connected to at least one actual circuit, and X is an integer less than or equal to M.

16. The chip according to claim 15, characterized in that: The calibration circuit comprises: a function correctness judgment circuit, wherein the function correctness judgment circuit is connected to at least one of the actual circuits.

17. The chip according to claim 15, characterized in that: The calibration circuit also includes: a timing calibration circuit; the timing calibration circuit is connected to the function correctness judgment circuit and the timing monitoring circuit respectively.

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