Test acceptance wiring scheme generation method and device, electronic equipment and storage medium

Abstract

The application discloses a kind of test acceptance wiring scheme generation method, device, electronic equipment and storage medium.The method includes obtaining the description file of the secondary system to be accepted, including primary wiring diagram and secondary equipment description diagram;First type representation vector is obtained by graph information analysis to primary wiring diagram, and second type representation vector is obtained by graph information analysis to secondary equipment description diagram;With first type representation vector as the feature vector of simulation query, and with second type representation vector as the feature vector of simulation key, the query analysis based on local neighborhood optimization is carried out to simulation query feature vector and simulation key feature vector to capture the deployment relationship of primary equipment and secondary equipment and obtain wiring scheme semantic representation;Test acceptance wiring scheme diagram of the secondary system to be accepted is generated based on wiring scheme semantic representation.The technical scheme of the application ensures that the generated wiring scheme has comprehensiveness and reliability.

Description

Technical Field

[0001] This invention relates to the field of power system technology, and in particular to a method, apparatus, electronic device, and storage medium for generating test and acceptance wiring schemes. Background Technology

[0002] With the continuous development and increasing complexity of power systems, the construction and maintenance of substations face increasingly greater challenges. In the construction and operation of substation secondary systems, the three remote functions (remote signaling, remote measurement, and remote control) are crucial for achieving remote monitoring and control. Correct wiring is the foundation for ensuring the normal operation of these three remote functions; any minor error can lead to secondary system malfunctions or safety hazards.

[0003] However, traditional test and acceptance wiring scheme design often relies on the experience and personal skills of engineers. Different engineers may propose different design schemes based on their own experience and habits, which makes it difficult to guarantee the consistency and standardization of the design results. Moreover, manually drawing wiring diagrams is a time-consuming task, especially for large substations, which requires a lot of time and effort to complete the design, and modifications and adjustments are also very inconvenient. In addition, due to the high degree of human involvement, the entire design process is prone to problems such as misreading drawings and missing wiring. Even experienced engineers cannot avoid oversights in the complex work. Inaccurate wiring designs may lead to misoperation or even damage to substation secondary equipment, and in severe cases, may cause safety accidents and threaten the lives of staff. Summary of the Invention

[0004] This invention provides a method, apparatus, electronic device, and storage medium for generating test and acceptance wiring schemes to ensure that the generated wiring schemes are comprehensive and reliable.

[0005] According to one aspect of the present invention, a method for generating a test and acceptance wiring scheme is provided, the method comprising:

[0006] Obtain the description file of the secondary system to be accepted, which includes the primary wiring diagram and the secondary equipment description diagram;

[0007] The primary wiring diagram is graphically parsed to obtain a first type of representation vector, and the secondary equipment description diagram is graphically parsed to obtain a second type of representation vector;

[0008] Using the first type of representation vector as the pseudo-query feature vector and the second type of representation vector as the pseudo-key feature vector, a query parsing based on local neighborhood optimization is performed on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between primary and secondary equipment and obtain the semantic representation of the wiring scheme.

[0009] Based on the semantic representation of the wiring scheme, a test and acceptance wiring scheme diagram for the secondary system to be accepted is generated.

[0010] According to another aspect of the present invention, a test and acceptance wiring scheme generation apparatus is provided, the apparatus comprising:

[0011] The file acquisition module is used to acquire the description file of the secondary system to be accepted. The description file includes a primary wiring diagram and a secondary equipment description diagram.

[0012] The representation vector acquisition module is used to perform graphical information parsing on the primary main wiring diagram to obtain a first type of representation vector, and to perform graphical information parsing on the secondary equipment description diagram to obtain a second type of representation vector;

[0013] The semantic representation acquisition module is used to perform query parsing based on local neighborhood optimization on the first type of representation vector as the pseudo-query feature vector and the second type of representation vector as the pseudo-key feature vector to capture the deployment relationship between primary and secondary equipment and obtain the semantic representation of the wiring scheme.

[0014] The wiring scheme diagram generation module is used to generate a test and acceptance wiring scheme diagram for the secondary system to be accepted based on the semantic representation of the wiring scheme.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] At least one processor; and

[0017] A memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to execute the test and acceptance wiring scheme generation method according to any embodiment of the present invention.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being configured to cause a processor to execute and implement the test and acceptance wiring scheme generation method according to any embodiment of the present invention.

[0020] The technical solution of this invention involves obtaining a description file of the secondary system to be accepted, including a primary main wiring diagram and a secondary equipment description diagram; performing graphical information parsing on the primary main wiring diagram to obtain a first type of representation vector, and performing graphical information parsing on the secondary equipment description diagram to obtain a second type of representation vector; using the first type of representation vector as a simulated query feature vector and the second type of representation vector as a simulated key feature vector, performing query parsing based on local neighborhood optimization on the simulated query feature vector and the simulated key feature vector to capture the deployment relationship between the primary and secondary equipment and obtain a semantic representation of the wiring scheme; generating a test acceptance wiring scheme diagram of the secondary system to be accepted based on the semantic representation of the wiring scheme. This method uses graphical information parsing of the primary main wiring diagram and the secondary equipment description diagram to identify necessary features from the description file of the secondary system to be accepted, understand the functions of the primary and secondary equipment and their interconnections, and thus automatically generate a wiring scheme. This solves the problem of inefficiency caused by relying on engineers' experience and personal skills in the prior art, which is also prone to inaccurate wiring schemes due to misreading drawings or missing wiring. It reduces the inefficiency and errors caused by human factors, ensuring the comprehensiveness and reliability of the generated wiring scheme.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1a This is a flowchart of a test and acceptance wiring scheme generation method provided in Embodiment 1 of the present invention;

[0024] Figure 1b This is a flowchart of obtaining the semantic representation of a wiring scheme provided in Embodiment 1 of the present invention;

[0025] Figure 2 This is a schematic diagram of a test and acceptance wiring scheme generation device provided in Embodiment 2 of the present invention;

[0026] Figure 3 This is a schematic diagram of the structure of an electronic device that implements the test and acceptance wiring scheme generation method of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] Example 1

[0030] Figure 1a This is a flowchart of a test and acceptance wiring scheme generation method provided in Embodiment 1 of the present invention. This embodiment is applicable to the testing and acceptance of the three remote functions of a secondary system. The method can be executed by a test and acceptance wiring scheme generation device, which can be implemented in hardware and / or software and can be configured in a server. Figure 1a As shown, the method includes:

[0031] S110. Obtain the description file of the secondary system to be accepted. The description file includes the primary wiring diagram and the secondary equipment description diagram.

[0032] The secondary system to be accepted can refer to the secondary system of the substation to be accepted. The description file can be externally imported into the server executing this method. The primary main wiring diagram can be a diagram depicting the physical connections between electrical equipment in the substation, showing in detail the connections of various primary devices. Primary equipment can refer to equipment that directly produces, transmits, and distributes high-voltage electrical energy, including generators, transformers, circuit breakers, disconnectors, busbars, power cables, and transmission lines. The secondary equipment description diagram can refer to all related CAD (Computer-Aided Design) drawings of the secondary equipment. These drawings can include information such as the specific location, model specifications, interface types, and connection methods with other equipment. Secondary equipment can refer to equipment that measures, controls, monitors, and protects the operating status of primary equipment and systems, such as relay protection devices, automated control systems, and measuring instruments.

[0033] S120. Perform graphical information parsing on the primary main wiring diagram to obtain the first type of representation vector, and perform graphical information parsing on the secondary equipment description diagram to obtain the second type of representation vector.

[0034] The first type of representation vector can refer to the graphical analytical encoding representation vector of the primary main wiring diagram. The second type of representation vector can refer to the set of graphical analytical encoding representation vectors of secondary equipment.

[0035] In this embodiment, to convert the graphical primary wiring diagram and all related CAD drawings of secondary equipment into a form that a computer can understand and process—that is, to convert visual information into digital information and capture the semantic parsing features in each graphical piece of information—machine learning and image processing algorithms based on artificial intelligence and image recognition technologies can be used to parse the graphical information of the primary wiring diagram and secondary equipment description diagram. For example, a dilated convolutional neural network model can be used to parse the graphical information of the primary wiring diagram and each secondary equipment CAD drawing to extract key features from the graphics, such as the connection status between primary equipment and the specific location, model specifications, interface type, and other feature information of the secondary equipment. Of course, other deep neural network models can also be used for graphical information parsing, and this embodiment does not limit this approach.

[0036] S130. Using the first type of representation vector as the pseudo-query feature vector and the second type of representation vector as the pseudo-key feature vector, perform query parsing based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between primary and secondary equipment and obtain the semantic representation of the wiring scheme.

[0037] Among them, the query parsing processing operation based on local neighborhood optimization can capture the complex relationship between primary and secondary devices through a multi-granularity attention mechanism, and extract implicit semantic information that is crucial to the wiring scheme.

[0038] In this embodiment, the graphical parsing and encoding representation vector of the primary wiring diagram contains basic attributes and connection feature information about the primary equipment, while the graphical parsing and encoding representation vectors of each secondary equipment contain feature information such as the location, function, and implicit relationship with the primary equipment. The primary equipment provides the basic electrical connection framework, while the secondary equipment is responsible for monitoring, controlling, and protecting these primary devices. Therefore, to design and generate a reasonable wiring scheme, it is necessary to understand the correspondence between the primary and secondary equipment. Based on this, in this embodiment, the graphical parsing and encoding representation vector of the primary wiring diagram is used as the pseudo-query feature vector, and the set of graphical parsing and encoding representation vectors of the secondary equipment is used as the set of pseudo-key feature vectors. A query parsing based on local neighborhood optimization is performed on the sets of pseudo-query feature vectors and pseudo-key feature vectors to obtain the semantic representation of the wiring scheme.

[0039] In one optional implementation, operation S130 may include: embedding and encoding the first type of representation vector to obtain a first type of feature vector; performing one-dimensional convolutional encoding on the second type of representation vector to obtain a second type of feature vector; using the first type of representation vector as a simulated query feature vector, the second type of representation vector and the second type of feature vector as a simulated key feature vector, and the first type of feature vector as a value vector, performing query-match-based feature fusion processing on the simulated query feature vector, the value vector and the simulated key feature vector to obtain a semantic representation of the wiring scheme.

[0040] The first type of feature vector can refer to the feature vector of the graphical analysis value of the primary main wiring diagram. The second type of feature vector can refer to the feature vector of the semantic association of the local neighborhood in the graphical analysis of secondary equipment.

[0041] Optionally, the first-class representation vector is embedded and encoded to obtain the first-class feature vector. Specifically, the first-class representation vector can be embedded and encoded according to a preset value embedding and encoding matrix to obtain the first-class feature vector. Specifically, the first-class representation vector can be multiplied by the preset value embedding and encoding matrix to obtain the first-class embedded vector; the first-class embedded vector can be added to the preset value bias vector positionally to obtain the first-class feature vector. Here, the first-class embedded vector can refer to the embedding vector obtained from the graphical parsing of the main wiring diagram.

[0042] In this embodiment, the scale of the one-dimensional convolutional encoding is equal to an integer multiple of the length of the second type of representation vector. This is to ensure that the contextual information between secondary devices within a specific range can be captured, thereby better reflecting the local neighborhood information in the secondary devices.

[0043] Based on the above optional implementation methods, using the first type of representation vector as the pseudo-query feature vector, the second type of representation vector and the second type of feature vector as the pseudo-key feature vector, and the first type of feature vector as the value vector, a query-match-based feature fusion process is performed on the pseudo-query feature vector, the value vector, and the pseudo-key feature vector to obtain the semantic representation of the wiring scheme, which can be as follows: Figure 1b As shown, it includes:

[0044] S1001. Using the first type of representation vector as the pseudo-query feature vector, the first type of feature vector as the value vector, and the second type of representation vector as the pseudo-key feature vector, the first multi-head attention query module is used to process the pseudo-query feature vector, the value vector, and the pseudo-key feature vector to obtain a sequence of feature value time-series key granularity query matching implicit vectors.

[0045] S1002. Using the first type of representation vector as the pseudo-query feature vector, the first type of feature vector as the value vector, and the second type of feature vector as the pseudo-key feature vector, the second multi-head attention query module is used to process the pseudo-query feature vector, the value vector, and the pseudo-key feature vector to obtain a sequence of feature value time-series key neighborhood granularity query matching implicit vectors.

[0046] S1003. Calculate the positional mean vector of the sequence of eigenvalue time-series key granular query matching latent vectors to obtain the eigenvalue time-series key granular query matching feature vector, and calculate the positional mean vector of the sequence of eigenvalue time-series key neighborhood granular query matching latent vectors to obtain the eigenvalue time-series key neighborhood granular query matching feature vector.

[0047] S1004. The feature vector of granular query matching of feature value time key and the feature vector of granular query matching of feature value time key neighborhood are fused to obtain the implicit semantic representation vector of the wiring scheme and the implicit semantic representation vector of the wiring scheme is used as the semantic representation of the wiring scheme.

[0048] Optionally, the S1001 operation may specifically include: calculating the implicit association matrix between the primary main wiring and the secondary equipment based on the transpose of the first type of representation vector and the second type of representation vector; calculating the implicit association modulation matrix between the primary main wiring and the secondary equipment based on the implicit association matrix and the square root of the length of the second type of representation vector; processing the implicit association modulation matrix using a preset activation function to obtain the implicit association activation matrix between the primary main wiring and the secondary equipment; and calculating the sequence of implicit vectors matched by the eigenvalue time key granularity query based on the implicit association activation matrix and the first type of feature vector.

[0049] In this embodiment, the product of the first type of representation vector and the transpose of the second type of representation vector can be calculated to obtain the graphical analytical implicit association matrix (i.e., implicit association evidence) between the primary main wiring and the secondary equipment; the graphical analytical implicit association matrix is ​​divided by the square root of the length of the second type of representation vector according to the position to obtain the graphical analytical implicit association modulation matrix (i.e., implicit association modulation matrix) between the primary main wiring and the secondary equipment; the graphical analytical implicit association modulation matrix is ​​input into a preset activation function (e.g., the softmax function) to obtain the graphical analytical implicit association activation matrix (i.e., implicit association activation matrix) between the primary main wiring and the secondary equipment; the graphical analytical implicit association activation matrix is ​​multiplied by the first type of feature vector to obtain the sequence of feature value time key granularity query matching implicit vectors.

[0050] Optionally, operation S1004 may specifically include: querying and matching feature vectors at the granularity of feature value time key and querying and matching feature vectors at the granularity of feature value time key neighborhood, and calculating the difference vector, dot product vector, and sum vector between the primary main wiring and the secondary equipment respectively; concatenating the difference vector, dot product vector, and sum vector to obtain the concatenated vector between the primary main wiring and the secondary equipment; performing one-dimensional convolutional encoding on the concatenated vector to obtain the convolutional encoded vector between the primary main wiring and the secondary equipment; performing max pooling on the convolutional encoded vector to obtain the implicit semantic representation vector of the wiring scheme, and using the implicit semantic representation vector of the wiring scheme as the semantic representation of the wiring scheme.

[0051] The difference vector can refer to the graphical analytical key-neighborhood granularity difference vector between the primary main wiring and the secondary equipment. This difference vector is obtained by subtracting the eigenvalue time-series key-granularity query matching feature vector and the eigenvalue time-series key-neighborhood granularity query matching feature vector positionally. The dot product vector can refer to the graphical analytical key-neighborhood granularity dot product vector between the secondary main wiring and the secondary equipment. This dot product vector is obtained by multiplying the eigenvalue time-series key-granularity query matching feature vector and the eigenvalue time-series key-neighborhood granularity query matching feature vector positionally. The summation vector can refer to the graphical analytical key-neighborhood granularity summation vector between the primary main wiring and the secondary equipment. This summation vector is obtained by adding the eigenvalue time-series key-granularity query matching feature vector and the eigenvalue time-series key-neighborhood granularity query matching feature vector positionally.

[0052] The concatenated vector of primary wiring and secondary equipment can refer to the graphically parsed key-to-key-neighborhood granularity concatenated vector of primary wiring and secondary equipment. The convolutional encoding vector of primary wiring and secondary equipment can also refer to the graphically parsed key-to-key-neighborhood granularity convolutional encoding vector of primary wiring and secondary equipment. Max pooling based on a local window can be applied to the convolutional encoding vector of primary wiring and secondary equipment to obtain the implicit semantic representation vector of the wiring scheme.

[0053] Based on the above, in this embodiment, the simulated query feature vector and simulated key feature vector of S130 can be subjected to query parsing based on local neighborhood optimization using the following optimized query parsing formula to capture the deployment relationship between primary and secondary equipment and obtain the semantic representation of the wiring scheme.

[0054] The optimized query parsing formula can be:

[0055] K = {k1, k2, ..., k} i , ..., k n}; where K represents the set of graphical parsing encoding representation vectors (second-class representation vectors) of secondary devices, k1, k2, ..., k i , ..., k n Let n represent the 1st, 2nd, ..., ith, ..., nth second-order graphical parsing representation vector in the set of second-order graphical parsing representation vectors, where n represents the number of representation vectors in the set of second-order graphical parsing representation vectors.

[0056] K′=Conv 1×l ({k1, k2, ..., k i , ...,k n}); where Conv 1×l (·) represents one-dimensional convolutional coding, l represents an integer multiple of the length of the quadratic device graphical parsing representation vector, and K′ represents the set of quadratic device graphical parsing local neighborhood semantic association feature vectors (i.e., second-class feature vectors).

[0057] K′={k1′,k2′,...,k i ′,...,k m ′};where k1′, k′2, ..., k i ′,...,k m 'surface

[0058] Let m represent the 1st, 2nd, ..., ith, ..., mth feature vectors in the set of feature vectors for graphical parsing of local neighborhood semantic associations of secondary devices, where m represents the number of feature vectors in the set of feature vectors for graphical parsing of local neighborhood semantic associations of secondary devices.

[0059] v v =v q W q +b q ; where v q W represents the graphical analytical encoding representation vector of a primary wiring diagram (i.e., the first type of representation vector). q b represents the preset value embedded in the encoding matrix. qV represents the preset bias vector. v This represents the eigenvector of the graphical analytical value of a primary wiring diagram (i.e., the first type of eigenvector).

[0060] Where, k i T Indicates k i The transpose of the vector, d1 represents the length of the vector in the graphical parsing encoding of the secondary device, softmax(·) represents the softmax function, v ki This represents the i-th eigenvalue time-key granularity query matching latent vector in the sequence of eigenvalue time-key granularity query matching latent vectors.

[0061] Where, k i ′ T Indicates k i The transpose of , d2 represents the length of the feature vector of the local neighborhood semantic association in the graphical parsing of the secondary device, v ni This represents the i-th eigenvalue in the sequence of eigenvalue temporal key neighborhood granularity query matching latent vectors.

[0062] Among them, v k This indicates a time-series key granularity query matching feature vector. Among them, v n This represents the feature vector matching the time-series key neighborhood granularity query.

[0063] in, ⊙ and These represent subtraction by position, dot product by position, and addition by position, respectively. [·, ·, ·] indicates concatenation. `conv1D(·)` represents a one-dimensional convolutional encoding operation, and `MaxPool(·)` represents a max-pooling operation. p The implicit semantic representation vector represents the wiring scheme.

[0064] In summary, the query parsing process based on local neighborhood optimization in S130 can be generally understood as follows:

[0065] By employing one-dimensional convolution operations, the implicit relationships between the graphical parsing representation vectors of each secondary device are extracted, which helps enhance the understanding of the relationships between these devices. The kernel size of the one-dimensional convolution is set to an integer multiple of the length of the graphical parsing representation vector of the secondary device to ensure that contextual information between secondary devices within a specific range is captured, thereby better reflecting the local neighborhood information within each secondary device. This means considering not only the individual secondary device itself but also how its surrounding devices are connected, which is crucial for understanding the interactions between devices.

[0066] Furthermore, the graphical representation vector of the primary main wiring diagram is processed using a value embedding encoding matrix to generate a graphical feature vector of the primary main wiring diagram. This transforms the query feature vector into a form more suitable for use as a value vector in the attention mechanism. Through embedding encoding, the graphical representation vector of the primary main wiring diagram can be mapped to a higher-dimensional space, enabling these feature vectors to better express the graphical semantics and query intent of the primary main wiring diagram in the subsequent attention mechanism, and to effectively interact with the graphical semantics of other secondary devices.

[0067] Furthermore, the processed simulated query feature vector, value vector, and simulated key feature vector are input into a multi-head attention query module based on a converter structure. This multi-head attention mechanism focuses on the relationship between the query vector (primary device) and the key vector (secondary device) from different perspectives. This helps to capture the complex connections and relationships between primary devices at different levels and different secondary devices, providing a basis for the subsequent generation of automatic wiring schemes.

[0068] Furthermore, the positional mean vectors of the sequence of latent vectors for feature value time-key granularity query matching and the sequence of latent vectors for feature value time-key neighborhood granularity query matching are calculated and fused into the final implicit semantic representation vector of the wiring scheme. This yields a representation that integrates features at different granularity levels. The purpose of this fusion is to combine the graphical analytical features of the primary main wiring diagram at two different granularity levels with the graphical analytical feature information of each secondary device, ensuring that the final semantic representation of the wiring scheme can fully reflect the multiple relationships between the semantics of the primary main wiring and the semantics of the secondary devices. This provides a more reliable data foundation for the generation of wiring schemes for subsequent remote testing and acceptance of the secondary system.

[0069] S140. Generate the test and acceptance wiring diagram of the secondary system to be accepted based on the semantic representation of the wiring scheme.

[0070] Optionally, the implicit semantic representation vector of the wiring scheme can be input into a wiring scheme renderer based on a diffusion model to obtain a test and acceptance wiring scheme diagram.

[0071] It is understandable that the implicit semantic representation of the wiring scheme, which includes the complex dependencies and connections between primary and secondary equipment, is used to render the wiring scheme, thereby automatically generating CAD drawings of the wiring scheme. This not only covers all necessary remote signal points but also considers how to most effectively arrange analog terminals for subsequent practical operations. This enables more intelligent automatic generation of wiring schemes for the remote testing and acceptance of substation secondary systems, reducing inefficiencies and errors caused by human factors and ensuring the comprehensiveness and reliability of the generated wiring scheme.

[0072] The technical solution of this invention involves obtaining a description file of the secondary system to be accepted, including a primary main wiring diagram and a secondary equipment description diagram; performing graphical information parsing on the primary main wiring diagram to obtain a first type of representation vector, and performing graphical information parsing on the secondary equipment description diagram to obtain a second type of representation vector; using the first type of representation vector as a simulated query feature vector and the second type of representation vector as a simulated key feature vector, performing query parsing based on local neighborhood optimization on the simulated query feature vector and the simulated key feature vector to capture the deployment relationship between the primary and secondary equipment and obtain a semantic representation of the wiring scheme; generating a test acceptance wiring scheme diagram of the secondary system to be accepted based on the semantic representation of the wiring scheme. This method uses graphical information parsing of the primary main wiring diagram and the secondary equipment description diagram to identify necessary features from the description file of the secondary system to be accepted, understand the functions of the primary and secondary equipment and their interconnections, and thus automatically generate a wiring scheme. This solves the problem of inefficiency caused by relying on engineers' experience and personal skills in the prior art, which is also prone to inaccurate wiring schemes due to misreading drawings or missing wiring. It reduces the inefficiency and errors caused by human factors, ensuring the comprehensiveness and reliability of the generated wiring scheme.

[0073] Example 2

[0074] Figure 2 This is a schematic diagram of a test and acceptance wiring scheme generation device provided in Embodiment 2 of the present invention. Figure 2 As shown, the device includes: a file acquisition module 210, a representation vector acquisition module 220, a semantic representation acquisition module 230, and a wiring diagram generation module 240. Wherein:

[0075] The file acquisition module 210 is used to acquire the description file of the secondary system to be accepted, the description file including the primary wiring diagram and the secondary equipment description diagram.

[0076] The representation vector acquisition module 220 is used to perform graphical information parsing on the primary main wiring diagram to obtain a first type of representation vector, and to perform graphical information parsing on the secondary equipment description diagram to obtain a second type of representation vector;

[0077] The semantic representation acquisition module 230 is used to perform query parsing based on local neighborhood optimization on the first type of representation vector as the pseudo-query feature vector and the second type of representation vector as the pseudo-key feature vector to capture the deployment relationship between primary and secondary equipment and obtain the semantic representation of the wiring scheme.

[0078] Wiring scheme diagram generation module 240 is used to generate a test and acceptance wiring scheme diagram of the secondary system to be accepted based on the semantic representation of the wiring scheme.

[0079] The technical solution of this invention involves obtaining a description file of the secondary system to be accepted, including a primary main wiring diagram and a secondary equipment description diagram; performing graphical information parsing on the primary main wiring diagram to obtain a first type of representation vector, and performing graphical information parsing on the secondary equipment description diagram to obtain a second type of representation vector; using the first type of representation vector as a simulated query feature vector and the second type of representation vector as a simulated key feature vector, performing query parsing based on local neighborhood optimization on the simulated query feature vector and the simulated key feature vector to capture the deployment relationship between the primary and secondary equipment and obtain a semantic representation of the wiring scheme; generating a test acceptance wiring scheme diagram of the secondary system to be accepted based on the semantic representation of the wiring scheme. This method uses graphical information parsing of the primary main wiring diagram and the secondary equipment description diagram to identify necessary features from the description file of the secondary system to be accepted, understand the functions of the primary and secondary equipment and their interconnections, and thus automatically generate a wiring scheme. This solves the problem of inefficiency caused by relying on engineers' experience and personal skills in the prior art, which is also prone to inaccurate wiring schemes due to misreading drawings or missing wiring. It reduces the inefficiency and errors caused by human factors, ensuring the comprehensiveness and reliability of the generated wiring scheme.

[0080] Optionally, the semantic representation acquisition module 230 may include:

[0081] The first type of feature vector acquisition unit is used to embed and encode the first type of representation vector to obtain the first type of feature vector;

[0082] The second type of feature vector acquisition unit is used to perform one-dimensional convolutional encoding on the second type of representation vector to obtain the second type of feature vector, wherein the scale of the one-dimensional convolutional encoding is equal to an integer multiple of the length of the second type of representation vector;

[0083] The semantic representation acquisition unit is used to perform query-match-based feature fusion processing on the simulated query feature vector, the value vector, and the simulated key feature vector, using the first type of representation vector as the simulated query feature vector, the second type of representation vector and the second type of feature vector as the simulated key feature vector, and the first type of feature vector as the value vector, to obtain the semantic representation of the wiring scheme.

[0084] Optionally, the first type of feature vector acquisition unit can be used for:

[0085] Multiply the first type of representation vector by the preset value embedding encoding matrix to obtain the first type of embedding vector;

[0086] The first type of embedding vector is added to the preset value bias vector according to their positions to obtain the first type of feature vector.

[0087] Optionally, the semantic representation acquisition unit may include:

[0088] The first sequence acquisition subunit is used to process the simulated query feature vector, the value vector, and the simulated key feature vector using the first type of representation vector as the simulated query feature vector, the first type of feature vector as the value vector, and the second type of representation vector as the simulated key feature vector using the first multi-head attention query module to obtain a sequence of feature value time key granularity query matching implicit vectors.

[0089] The second sequence acquisition subunit is used to process the simulated query feature vector, the value vector, and the simulated key feature vector using the first type of representation vector as the simulated query feature vector, the first type of feature vector as the value vector, and the second type of feature vector as the simulated key feature vector using the second multi-head attention query module to obtain a sequence of feature value time key neighborhood granularity query matching implicit vectors.

[0090] The feature vector acquisition subunit is used to calculate the positional mean vector of the sequence of the feature value time-series key granularity query matching latent vectors to obtain the feature value time-series key granularity query matching feature vector, and to calculate the positional mean vector of the sequence of the feature value time-series key neighborhood granularity query matching latent vectors to obtain the feature value time-series key neighborhood granularity query matching feature vector.

[0091] The semantic representation acquisition subunit is used to fuse the feature value time-series key granularity query matching feature vector and the feature value time-series key neighborhood granularity query matching feature vector to obtain the wiring scheme implicit semantic representation vector and use the wiring scheme implicit semantic representation vector as the wiring scheme semantic representation.

[0092] Optionally, the first sequence obtains sub-units, which can be specifically used for:

[0093] Calculate the implicit association matrix between the primary main wiring and the secondary equipment based on the transpose of the first type of representation vector and the second type of representation vector;

[0094] The implicit correlation modulation matrix between the primary main wiring and the secondary equipment is calculated based on the implicit correlation matrix and the square root of the length of the second type of representation vector.

[0095] The implicit correlation modulation matrix is ​​processed using a preset activation function to obtain the implicit correlation activation matrix between the primary main wiring and the secondary equipment;

[0096] Based on the implicit association activation matrix and the first type of feature vector, calculate the sequence of the feature value time key granularity query matching the implicit vector.

[0097] Optionally, semantic representation can be used to obtain sub-units, specifically for:

[0098] Based on the eigenvalue time-key granularity query matching feature vector and the eigenvalue time-key neighborhood granularity query matching feature vector, calculate the difference vector, dot product vector, and summation vector between the primary main wiring and the secondary equipment, respectively;

[0099] The difference vector, the dot product vector, and the summation vector are concatenated to obtain the concatenated vector of the primary main wiring and the secondary equipment.

[0100] Perform one-dimensional convolutional coding on the concatenated vector to obtain the convolutional coding vector of the primary main wiring and the secondary equipment;

[0101] The convolutional coding vector is subjected to max pooling to obtain the implicit semantic representation vector of the wiring scheme, and the implicit semantic representation vector of the wiring scheme is used as the semantic representation of the wiring scheme.

[0102] Optionally, the wiring diagram generation module 240 can be used for:

[0103] The implicit semantic representation vector of the wiring scheme is input into the wiring scheme renderer based on the diffusion model to obtain the test and acceptance wiring scheme diagram.

[0104] The test and acceptance wiring scheme generation device provided in this embodiment of the invention can execute the test and acceptance wiring scheme generation method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0105] Example 3

[0106] Figure 3 A schematic diagram of an electronic device 300 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers or various forms of mobile devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0107] like Figure 3As shown, the electronic device 300 includes at least one processor 301 and a memory, such as a read-only memory (ROM) 302 or a random access memory (RAM) 303, communicatively connected to the at least one processor 301. The memory stores computer programs executable by the at least one processor. The processor 301 can perform various appropriate actions and processes based on the computer program stored in the ROM 302 or loaded into the RAM 303 from storage unit 308. The RAM 303 can also store various programs and data required for the operation of the electronic device 300. The processor 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0108] Multiple components in electronic device 300 are connected to I / O interface 305, including: input unit 306, such as keyboard, mouse, etc.; output unit 307, such as various types of displays, speakers, etc.; storage unit 308, such as disk, optical disk, etc.; and communication unit 309, such as network card, modem, wireless transceiver, etc. Communication unit 309 allows electronic device 300 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0109] Processor 301 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 301 performs the various methods and processes described above, such as the test acceptance wiring scheme generation method.

[0110] In some embodiments, the test acceptance wiring scheme generation method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 308. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 300 via ROM 302 and / or communication unit 309. When the computer program is loaded into RAM 303 and executed by processor 301, one or more steps of the test acceptance wiring scheme generation method described above may be performed. Alternatively, in other embodiments, processor 301 may be configured to perform the test acceptance wiring scheme generation method by any other suitable means (e.g., by means of firmware).

[0111] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0112] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0113] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0114] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0115] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0116] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0117] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0118] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for generating a test and acceptance wiring scheme, characterized in that, include: Obtain the description file of the secondary system to be accepted, which includes the primary wiring diagram and the secondary equipment description diagram; The primary wiring diagram is graphically parsed to obtain a first type of representation vector, and the secondary equipment description diagram is graphically parsed to obtain a second type of representation vector; The first type of representation vector is embedded and encoded to obtain the first type of feature vector; One-dimensional convolutional encoding is performed on the second type of representation vector to obtain the second type of feature vector, wherein the scale of the one-dimensional convolutional encoding is equal to an integer multiple of the length of the second type of representation vector; Using the first type of representation vector as the pseudo-query feature vector, the first type of feature vector as the value vector, and the second type of representation vector as the pseudo-key feature vector, the first multi-head attention query module processes the pseudo-query feature vector, the value vector, and the pseudo-key feature vector to obtain a sequence of feature value time-series key granularity query matching implicit vectors; Using the first type of representation vector as the pseudo-query feature vector, the first type of feature vector as the value vector, and the second type of feature vector as the pseudo-key feature vector, the second multi-head attention query module processes the pseudo-query feature vector, the value vector, and the pseudo-key feature vector to obtain a sequence of feature value time-series key neighborhood granularity query matching implicit vectors; Calculate the positional mean vector of the sequence of the latent vector matched by the eigenvalue time-series key granularity query, to obtain the eigenvalue time-series key granularity query matching feature vector; and calculate the positional mean vector of the sequence of the latent vector matched by the neighborhood granularity query, to obtain the eigenvalue time-series key neighborhood granularity query matching feature vector. By fusing the feature value time-series key granularity query matching feature vector and the feature value time-series key neighborhood granularity query matching feature vector, a wiring scheme implicit semantic representation vector is obtained, and the wiring scheme implicit semantic representation vector is used as the wiring scheme semantic representation; Based on the semantic representation of the wiring scheme, a test and acceptance wiring scheme diagram for the secondary system to be accepted is generated.

2. The method according to claim 1, characterized in that, Embedding encoding is performed on the first type of representation vector to obtain the first type of feature vector, including: Multiply the first type of representation vector by the preset value embedding encoding matrix to obtain the first type of embedding vector; The first type of embedding vector is added to the preset value bias vector according to their positions to obtain the first type of feature vector.

3. The method according to claim 1, characterized in that, Using the first type of representation vector as the simulated query feature vector, the first type of feature vector as the value vector, and the second type of representation vector as the simulated key feature vector, the simulated query feature vector, the value vector, and the simulated key feature vector are processed by the first multi-head attention query module to obtain a sequence of feature value time-series key granularity query matching latent vectors, including: Calculate the implicit association matrix between the primary main wiring and the secondary equipment based on the transpose of the first type of representation vector and the second type of representation vector; The implicit correlation modulation matrix between the primary main wiring and the secondary equipment is calculated based on the implicit correlation matrix and the square root of the length of the second type of representation vector. The implicit correlation modulation matrix is ​​processed using a preset activation function to obtain the implicit correlation activation matrix between the primary main wiring and the secondary equipment; Based on the implicit association activation matrix and the first type of feature vector, calculate the sequence of the feature value time key granularity query matching the implicit vector.

4. The method according to claim 3, characterized in that, By fusing the feature value time-series key granularity query matching feature vector and the feature value time-series key neighborhood granularity query matching feature vector, a wiring scheme implicit semantic representation vector is obtained, and this wiring scheme implicit semantic representation vector is used as the wiring scheme semantic representation, including: Based on the eigenvalue time-key granularity query matching feature vector and the eigenvalue time-key neighborhood granularity query matching feature vector, calculate the difference vector, dot product vector, and summation vector between the primary main wiring and the secondary equipment, respectively; The difference vector, the dot product vector, and the summation vector are concatenated to obtain the concatenated vector of the primary main wiring and the secondary equipment. Perform one-dimensional convolutional coding on the concatenated vector to obtain the convolutional coding vector of the primary main wiring and the secondary equipment; The convolutional coding vector is subjected to max pooling to obtain the implicit semantic representation vector of the wiring scheme, and the implicit semantic representation vector of the wiring scheme is used as the semantic representation of the wiring scheme.

5. The method according to claim 4, characterized in that, Based on the semantic representation of the wiring scheme, a test and acceptance wiring scheme diagram for the secondary system to be accepted is generated, including: The implicit semantic representation vector of the wiring scheme is input into the wiring scheme renderer based on the diffusion model to obtain the test and acceptance wiring scheme diagram.

6. A test and acceptance wiring scheme generation device, characterized in that, include: The file acquisition module is used to acquire the description file of the secondary system to be accepted. The description file includes a primary wiring diagram and a secondary equipment description diagram. The representation vector acquisition module is used to perform graphical information parsing on the primary main wiring diagram to obtain a first type of representation vector, and to perform graphical information parsing on the secondary equipment description diagram to obtain a second type of representation vector; A semantic representation acquisition module is used to embed and encode the first type of representation vector to obtain a first type of feature vector; to perform one-dimensional convolutional encoding on the second type of representation vector to obtain a second type of feature vector, wherein the scale of the one-dimensional convolutional encoding is an integer multiple of the length of the second type of representation vector; using the first type of representation vector as a simulated query feature vector, the first type of feature vector as a value vector, and the second type of representation vector as a simulated key feature vector, the first multi-head attention query module processes the simulated query feature vector, the value vector, and the simulated key feature vector to obtain a sequence of feature value time-series key granularity query matching latent vectors; using the first type of representation vector as the simulated query feature vector, the first type of feature vector as a value vector, and the second type of feature vector as... The simulated key feature vector is processed by the second multi-head attention query module to obtain a sequence of feature value time-series key neighborhood granularity query matching latent vectors. The positional mean vector of the sequence of feature value time-series key granularity query matching latent vectors is calculated to obtain the feature value time-series key granularity query matching feature vector. The positional mean vector of the sequence of feature value time-series key neighborhood granularity query matching latent vectors is also calculated to obtain the feature value time-series key neighborhood granularity query matching feature vector. The feature value time-series key granularity query matching feature vector and the feature value time-series key neighborhood granularity query matching feature vector are fused to obtain the wiring scheme latent semantic representation vector, which is then used as the wiring scheme semantic representation. The wiring scheme diagram generation module is used to generate a test and acceptance wiring scheme diagram for the secondary system to be accepted based on the semantic representation of the wiring scheme.

7. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the test and acceptance wiring scheme generation method according to any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the test and acceptance wiring scheme generation method according to any one of claims 1-5.

Images