Pixel circuit, pixel circuit driving method, display panel and display device

Abstract

This application relates to the field of display technology, specifically providing a pixel circuit, a pixel circuit driving method, a display panel, and a display device. It aims to solve the problems of existing methods for achieving 3D display, which require separate pixel circuits for the left and right eye display areas, resulting in large space requirements, layout difficulties, and low resolution. To this end, the pixel circuit of this application provides driving current to a first light-emitting control sub-circuit and a second light-emitting control sub-circuit through a shared sub-circuit. The first light-emitting control sub-circuit, in response to a first light-emitting control signal, provides driving current to a first light-emitting device. The second light-emitting control sub-circuit, in response to a second light-emitting control signal, provides driving current to a second light-emitting device. The first and second light-emitting devices correspond to different pixels. This solution allows for driving different pixels based on a shared sub-circuit, which is beneficial for saving space, simplifying layout, and improving resolution.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically providing a pixel circuit, a pixel circuit driving method, a display panel, and a display device. Background Technology

[0002] With the development of display technology, glasses-free 3D display has become a key focus. To achieve glasses-free 3D display, it is typically necessary to control the display panel to provide images to the user's left and right eyes separately. Accordingly, the display panel needs to include left-eye pixels for providing the image to the left eye and right-eye pixels for providing the image to the right eye, and it also needs to have pixel circuits for driving the left-eye pixels and the right-eye pixels.

[0003] However, setting separate pixel circuits for the left and right eye pixels takes up a lot of space, which can easily lead to layout difficulties and low resolution, thus affecting the 3D display effect. Summary of the Invention

[0004] This application aims to solve the above-mentioned technical problems, namely, to solve the problems that existing methods of realizing 3D display require setting up pixel circuits for the display areas of the left and right eyes separately, which occupies a large space and is prone to layout difficulties and low resolution.

[0005] In a first aspect, this application provides a pixel circuit, which includes a common sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a first light-emitting device, and a second light-emitting device. The first terminal of the first light-emitting control sub-circuit and the first terminal of the second light-emitting control sub-circuit are both connected to the common sub-circuit through a common connection terminal.

[0006] The shared sub-circuit is used to provide driving current to the first light-emitting control sub-circuit and the second light-emitting control circuit through the common connection terminal;

[0007] The second terminal of the first light-emitting control sub-circuit is used to connect to the first light-emitting device and to provide the driving current to the first light-emitting device in response to the first light-emitting control signal.

[0008] The second terminal of the second light-emitting control sub-circuit is used to connect to the second light-emitting device and to provide the driving current to the second light-emitting device in response to the second light-emitting control signal being turned on;

[0009] The first light-emitting device and the second light-emitting device correspond to different pixels.

[0010] In some embodiments, the effective potentials of the first light emission control signal and the second light emission control signal do not overlap in time, and the first light emission control sub-circuit and the second light emission control sub-circuit are used to alternately conduct in response to the effective potentials of their respective light emission control signals.

[0011] In some embodiments, the first light-emitting control sub-circuit includes a first transistor, a first terminal of the first transistor is connected to the common connection terminal, a second terminal of the first transistor is connected to the first light-emitting device, and a control terminal of the first transistor is used to receive the first light-emitting control signal.

[0012] In some embodiments, the second light-emitting control sub-circuit includes a second transistor, a first terminal of the second transistor is connected to the common connection terminal, a second terminal of the second transistor is connected to the second light-emitting device, and a control terminal of the second transistor is used to receive the second light-emitting control signal.

[0013] In some embodiments, the shared sub-circuit includes a reset unit, an energy storage unit, a data writing unit, a driving unit, a compensation unit, and a light-emitting control unit;

[0014] The first end of the reset unit is used to receive an initial signal, and the second end of the reset unit is connected to the first node, and is used to transmit the initial signal to the first node during the reset phase of each pixel driving cycle;

[0015] The first end of the energy storage unit is used to receive a first power signal, and the second end of the energy storage unit is connected to the first node.

[0016] The first end of the compensation unit is connected to the common connection end, and the second end of the compensation unit is connected to the first node;

[0017] The first end of the data writing unit is used to receive data signals, and the second end of the data writing unit is connected to the second node, and is used to provide the data signals and threshold voltage to the first node through the compensation unit during the writing phase of each pixel driving cycle.

[0018] The first end of the drive unit is connected to the second node, the second end of the drive unit is connected to the common connection end, and the control end of the drive unit is connected to the first node;

[0019] The first terminal of the light-emitting control unit is used to receive the first power signal, and the second terminal of the light-emitting control unit is connected to the second node and is used to turn on during the light-emitting phase of each pixel driving cycle to provide the first power signal to the second node; the driving unit is used to provide driving current to the common connection terminal based on the signals provided by the first node and the second node.

[0020] In some embodiments,

[0021] The reset unit includes a third transistor, the first terminal of the third transistor is used to receive the initial signal, the second terminal of the third transistor is connected to the first node, and the control terminal of the third transistor is used to receive the first gate drive signal.

[0022] The energy storage unit includes a storage capacitor, a first terminal of which is used to receive the first power signal, and a second terminal of which is connected to the first node.

[0023] The compensation unit includes a fourth transistor, the first terminal of which is connected to the common connection terminal, and the second terminal of which is connected to the first node;

[0024] The data writing unit includes a fifth transistor, the first terminal of which is used to receive the data signal, the second terminal of which is connected to the second node, and the control terminals of the fifth transistor and the fourth transistor are both used to receive the second gate drive signal.

[0025] The driving unit includes a sixth transistor, a first terminal of which is connected to the second node, a second terminal of which is connected to the common connection terminal, and a control terminal of the driving unit is connected to the first node.

[0026] The light-emitting control unit includes a seventh transistor, the first terminal of which is used to receive the first power signal, the second terminal of which is connected to the second node, and the control terminal of which is used to receive the third light-emitting control signal.

[0027] In some embodiments, the pixel circuit further includes:

[0028] The first reset sub-circuit is used to reset the second terminal of the first light emission control sub-circuit during the reset phase of the pixel driving cycle.

[0029] In some embodiments, the first reset sub-circuit includes an eighth transistor, the first terminal of which is used to receive an initial signal, the second terminal of which is connected to the second terminal of the first light-emitting control sub-circuit, and the control terminal of which is used to receive a first gate drive signal.

[0030] In some embodiments, the pixel circuit further includes:

[0031] The second reset sub-circuit is used to reset the second terminal of the second light emission control sub-circuit during the reset phase of the pixel driving cycle.

[0032] In some embodiments, the second reset sub-circuit includes a ninth transistor, a first terminal of which is used to receive an initial signal, a second terminal of which is connected to a second terminal of the second light-emitting control sub-circuit, and a control terminal of which is used to receive a first gate drive signal.

[0033] In a second aspect, this application provides a display panel comprising multiple gate lines, multiple data lines, and multiple pixel unit groups arranged in an array. Multiple pixel unit groups located in the same row direction are connected to the same gate line, and multiple pixel unit groups located in the same column direction are connected to the same data line. Each pixel unit group includes a left-eye pixel and a right-eye pixel, and the left-eye pixel and the right-eye pixel in the same pixel unit group are driven by the pixel circuit described in any of the above claims.

[0034] In some embodiments, the left-eye pixels and right-eye pixels in each pixel unit group are arranged at intervals in the column direction; or, the left-eye pixels and right-eye pixels in each pixel unit group are arranged at intervals in the row direction.

[0035] In some embodiments, the plurality of gate lines include a first gate drive signal line and a second gate drive signal line;

[0036] The display panel also includes an initial signal line, a first light emission control signal line, a second light emission control signal line, and a third light emission control signal line;

[0037] The initial signal line, the first gate drive signal line, the second gate drive signal line, the third light emission control signal line, the first light emission control signal line, and the second light emission control signal line are arranged in parallel order in the column direction.

[0038] The common sub-circuit of the pixel circuit is disposed in the area between the initial signal line and the first light emission control signal line and between two adjacent data lines, and partially overlaps with the corresponding connected data lines; the first light emission control sub-circuit and the second light emission control sub-circuit of the pixel circuit are disposed between the two adjacent data lines and arranged at intervals in the row direction, the first light emission control sub-circuit partially overlaps with the first light emission control signal line, and the second light emission control sub-circuit partially overlaps with the second light emission control signal line.

[0039] A common connection terminal is located between the third light-emitting control signal line and the first light-emitting control signal line. The first light-emitting control sub-circuit and the second light-emitting control sub-circuit are connected to the common connection terminal and are connected to the common sub-circuit through a connecting wire that is connected to the common connection terminal at one end and extends parallel to the column direction.

[0040] In a third aspect, this application provides a display device comprising the display panel described in any of the preceding claims.

[0041] In some embodiments, the display device further includes a prism array located on the light-emitting side of the display panel.

[0042] In some embodiments, the prism array is a liquid crystal prism array, and the display device further includes a liquid crystal driving circuit, which provides voltage to the liquid crystal prism array to achieve switching between two-dimensional display and three-dimensional display.

[0043] In a fourth aspect, this application provides a pixel circuit driving method, which includes:

[0044] During the light-emitting phase of the pixel driving cycle, the shared sub-circuit provides driving current to the first light-emitting control sub-circuit and the second light-emitting control sub-circuit through a common connection terminal;

[0045] The first light-emitting control sub-circuit responds to the first light-emitting control signal by being turned on or off. When the first light-emitting control sub-circuit is turned on, it provides the driving current to the first light-emitting device.

[0046] The second light-emitting control sub-circuit responds to the second light-emitting control signal by being turned on or off. When the first light-emitting control sub-circuit is turned on, it provides the driving current to the second light-emitting device.

[0047] The first light-emitting device and the second light-emitting device correspond to different pixels.

[0048] In some embodiments, the effective operating potentials of the first light emission control signal and the second light emission control signal do not overlap in time, and the first light emission control sub-circuit and the second light emission control sub-circuit alternately turn on in response to the effective potential of their respective light emission control signals.

[0049] By adopting the above technical solution, this application can provide a pixel circuit, which includes a common sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a first light-emitting device, and a second light-emitting device. The first terminals of both the first and second light-emitting control sub-circuits are connected to the common sub-circuit via a common connection terminal. The common sub-circuit provides driving current to the first and second light-emitting control sub-circuits through the common connection terminal. The second terminal of the first light-emitting control sub-circuit is connected to the first light-emitting device and provides driving current to the first light-emitting device in response to a first light-emitting control signal. The second terminal of the second light-emitting control sub-circuit is connected to the second light-emitting device and provides driving current to the second light-emitting device in response to a second light-emitting control signal. The first and second light-emitting devices correspond to different pixels. This solution can drive different pixels based on the common sub-circuit, which is beneficial for saving space, simplifying layout, and improving resolution. When applied to a three-dimensional display mode, it can effectively improve the three-dimensional display effect. Attached Figure Description

[0050] The preferred embodiments of this application are described below with reference to the accompanying drawings, in which:

[0051] Figure 1 This is a schematic diagram of the display panel structure provided in this application;

[0052] Figure 2 This is a schematic diagram of a pixel circuit structure provided in an embodiment of this application;

[0053] Figure 3 This is a schematic diagram of a pixel circuit structure provided in another embodiment of this application;

[0054] Figure 4 This is a schematic diagram of a pixel circuit structure provided in another embodiment of this application;

[0055] Figure 5 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0056] Figure 6 This is a schematic flowchart of the pixel circuit driving method provided in the embodiments of this application;

[0057] Figure 7 This is a timing diagram of each signal in the pixel circuit driving process provided in the embodiments of this application;

[0058] Figure 8 This is a schematic diagram of a display panel provided in an embodiment of this application;

[0059] Figure 9 This is a schematic diagram of a display panel provided in another embodiment of this application;

[0060] Figure 10 This is a partial layout structure diagram of the display panel provided in an embodiment of this application;

[0061] Figure 11 This is a cross-sectional structural schematic diagram of a display device provided in an embodiment of this application;

[0062] Figure 12 This is a cross-sectional structural schematic diagram of a display device provided in another embodiment of this application. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0064] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0065] As described in the background section, in achieving glasses-free 3D display, it is typically necessary to control the display panel to provide separate display images for the user's left and right eyes. Accordingly, see [link to relevant documentation]. Figure 1 As shown, Figure 1This is a schematic diagram of the display panel structure provided in this application. The display panel needs to include a left-eye pixel L for providing the display image to the left eye and a right-eye pixel R for providing the display image to the right eye, and is provided with pixel circuits for driving the left-eye pixel L and the right-eye pixel R. Multiple left-eye pixels L and multiple right-eye pixels R are arranged alternately in the column direction. Each pixel is connected to a pixel circuit (white rectangle shown in the figure). Pixel circuits located in the same row are connected to the same gate line G_M (M is an integer greater than or equal to 1), and the gate driving circuit GOA (Gate On Array, GOA) located on both sides of the corresponding row provides gate driving signals to the pixel circuits through the gate line G_M. Pixel circuits located in the same column are connected to the same data line D_N (N is an integer greater than or equal to 1), and the data line D_N provides data signals to the pixel circuits in the corresponding column. Setting separate pixel circuits for the left-eye pixel L and the right-eye pixel R occupies a large space, which can easily lead to layout difficulties and low resolution, thus affecting the three-dimensional display effect.

[0066] In view of this, this application provides a pixel circuit that can drive different pixels based on a shared sub-circuit, which helps to save space, simplify layout, and improve resolution. When applied to 3D display mode, it can effectively improve the 3D display effect.

[0067] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between them. In the embodiments of this application, to distinguish the source and drain of the transistor, one of the terminals is called the first terminal, the other terminal is called the second terminal, and the gate is called the control terminal. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments use P-type transistors for illustration. When using a P-type transistor, the first terminal is the source, the second terminal is the drain, and when the gate input is low, the source and drain are conducting; the low level is the effective level. When the gate input is high, the source and drain are cut off; the high level is the ineffective level. The N-type transistor is the opposite. It is conceivable that using an N-type transistor is something that those skilled in the art can easily conceive of without creative effort, and therefore it is within the protection scope of the embodiments of this application.

[0068] See Figure 2 As shown, Figure 2This is a schematic diagram of a pixel circuit structure provided in an embodiment of this application. It may include a common sub-circuit 21, a first light-emitting control sub-circuit 22, a second light-emitting control sub-circuit 23, a first light-emitting device 24, and a second light-emitting device 25. The first end of the first light-emitting control sub-circuit 22 and the first end of the second light-emitting control sub-circuit 23 are both connected to the common sub-circuit 21 through a common connection terminal N.

[0069] The shared sub-circuit 21 is used to provide drive current to the first light-emitting control sub-circuit 22 and the second light-emitting control sub-circuit 23 through the common connection terminal N;

[0070] The second terminal of the first light-emitting control sub-circuit 22 is used to connect to the first light-emitting device 24 and to provide driving current to the first light-emitting device 24 in response to the first light-emitting control signal EM1 being turned on.

[0071] The second terminal of the second light-emitting control sub-circuit 23 is used to connect to the second light-emitting device 25 and to provide driving current to the second light-emitting device 25 in response to the second light-emitting control signal EM2 being turned on.

[0072] The first light-emitting device 24 and the second light-emitting device 25 correspond to different pixels.

[0073] In some embodiments, the first light-emitting device 24 and the second light-emitting device 25 correspond to different pixels, which can be different pixels with the same corresponding light emission color. These different pixels can be turned on simultaneously or separately.

[0074] In some embodiments, when applied to a two-dimensional display, based on the pixel circuit provided in this application, by controlling the effective potentials of the first light emission control signal EM and the second light emission control signal EM2 to overlap in time, the first light emission control sub-circuit 22 and the second light emission control sub-circuit 23 can be controlled to be turned on simultaneously, so that different pixels corresponding to the current pixel circuit are displayed simultaneously.

[0075] In other embodiments, the effective potentials of the first light-emitting control signal EM1 and the second light-emitting control signal EM2 do not overlap in time, and the first light-emitting control sub-circuit 22 and the second light-emitting control sub-circuit 23 are used to alternately conduct in response to the effective potentials of their respective light-emitting control signals. When applied to 3D display, the pixels corresponding to the first light-emitting control sub-circuit 22 and the pixels corresponding to the second light-emitting control sub-circuit 23 are displayed in time segments. In some embodiments, the pixel corresponding to the first light-emitting control sub-circuit 22 can be the left-eye pixel L, and the pixel corresponding to the second light-emitting control sub-circuit 23 can be the right-eye pixel R. By setting corresponding control sub-circuits and light-emitting control signals for different pixels, the alternating display of the left-eye pixel L and the right-eye pixel R can be achieved based on the shared part circuit, i.e., the shared sub-circuit 21.

[0076] In some embodiments, see Figure 3 As shown, Figure 3 This is a schematic diagram of a pixel circuit structure provided in another embodiment of this application. The first light-emitting control sub-circuit 22 includes a first transistor T1. The first terminal of the first transistor T1 is connected to a common connection terminal N, and the second terminal of the first transistor T1 is connected to a first light-emitting device 24. The control terminal of the first transistor T1 is used to receive a first light-emitting control signal EM1. The second light-emitting control sub-circuit 23 includes a second transistor T2. The first terminal of the second transistor T2 is connected to a common connection terminal N, and the second terminal of the second transistor T2 is connected to a second light-emitting device 25. The control terminal of the second transistor T2 is used to receive a second light-emitting control signal EM2.

[0077] In some embodiments, the first light-emitting device 24 and the second light-emitting device 25 can be electronic devices with light-emitting properties, such as organic light-emitting diodes (OLEDs), active matrix quantum dot light-emitting diodes (QLEDs), or light-emitting diodes (LEDs).

[0078] The second terminal of the first transistor T1 can be connected to the anode of the first light-emitting device 24, and the cathode of the first light-emitting device 24 can be connected to the second power signal terminal (VSS terminal); the second terminal of the second transistor T2 can be connected to the anode of the second light-emitting device 25, and the cathode of the second light-emitting device 25 can be connected to the second power signal terminal (VSS terminal).

[0079] In some embodiments, the shared sub-circuit 21 can be implemented based on conventional pixel circuits in the art, such as 6TIC (6 transistors and 1 capacitor), 7TIC (7 transistors and 1 capacitor), and 9T1C (9 transistors and 1 capacitor) circuits. Taking the 7TIC circuit as an example, the remaining part except for the light-emitting device and the branch containing the transistor directly connected to the light-emitting device can be used as the shared sub-circuit 21.

[0080] In some embodiments, see Figure 4 and Figure 5 , Figure 4 This is a schematic diagram of a pixel circuit structure provided in another embodiment of this application. Figure 5 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. It should be noted that this embodiment can be based on the above... Figure 2 or Figure 3 Implementation, based on Figure 3 The implementation will be described using an example.

[0081] In this embodiment, the shared sub-circuit 21 includes a reset unit, an energy storage unit, a data writing unit, a driving unit, a compensation unit, and a light-emitting control unit.

[0082] The first end of the reset unit is used to receive the initial signal Vinit, and the second end of the reset unit is connected to the first node N1 to transmit the initial signal Vinit to the first node N1 during the reset phase of each pixel driving cycle.

[0083] In some embodiments, such as Figure 5 As shown, the reset unit may include a third transistor T3. The first terminal of the third transistor T3 is used to receive an initial signal, the second terminal of the third transistor T3 is connected to the first node N1, and the control terminal of the third transistor T3 is used to receive the first gate drive signal GateM1.

[0084] The first end of the energy storage unit is used to receive the first power signal VDD, and the second end of the energy storage unit is connected to the first node N1.

[0085] In some embodiments, such as Figure 5 As shown, the energy storage unit includes a storage capacitor C. The first end of the storage capacitor C is used to receive a first power signal VDD, and the second end of the storage capacitor C is connected to the first node N1.

[0086] The first end of the compensation unit is connected to the common connection terminal N, and the second end of the compensation unit is connected to the first node N1.

[0087] In some embodiments, such as Figure 5 As shown, the compensation unit includes a fourth transistor T4, the first terminal of the fourth transistor T4 is connected to the common connection terminal N, and the second terminal of the fourth transistor T4 is connected to the first node N1.

[0088] The first end of the data writing unit is used to receive the data signal Data, and the second end of the data writing unit is connected to the second node N2. It is used to provide the data signal Data and the threshold voltage to the first node N1 through the compensation unit during the writing phase of each pixel driving cycle.

[0089] In some embodiments, such as Figure 5 As shown, the data writing unit includes a fifth transistor T5. The first terminal of the fifth transistor T5 is used to receive the data signal Data, and the second terminal of the fifth transistor T5 is connected to the second node N2. The control terminals of the fifth transistor T5 and the fourth transistor T4 are both used to receive the second gate drive signal GateM2.

[0090] The first end of the drive unit is connected to the second node N2, the second end of the drive unit is connected to the common connection terminal N, and the control terminal of the drive unit is connected to the first node N1.

[0091] In some embodiments, such as Figure 5 As shown, the driving unit includes a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the second node N2, the second terminal of the sixth transistor T6 is connected to the common connection terminal N, and the control terminal of the driving unit is connected to the first node N1.

[0092] The first terminal of the light-emitting control unit is used to receive the first power signal VDD, and the second terminal of the light-emitting control unit is connected to the second node N2 and is used to turn on during the light-emitting phase of each pixel driving cycle to provide the first power signal VDD to the second node N2; the driving unit is used to provide driving current to the common connection terminal N based on the signals provided by the first node N1 and the second node N2.

[0093] In some embodiments, such as Figure 5 As shown, the light-emitting control unit includes a seventh transistor T7. The first terminal of the seventh transistor T7 is used to receive a first power supply signal VDD. The second terminal of the seventh transistor T7 is connected to the second node N2. The control terminal of the seventh transistor T7 is used to receive a third light-emitting control signal EM3.

[0094] When the initial signal Vinit is transmitted to the first node N1, the potential of the control terminal of the drive unit and the second terminal of the energy storage unit can be reset.

[0095] The threshold voltage can be the threshold voltage of the transistor in the driving unit. By providing the threshold voltage to the first node N1, it is beneficial to compensate the driving current during the light emission stage and ensure the consistency of brightness between different pixels.

[0096] In this application, the timing signal used to control the on or off of the light-emitting control unit is the third light-emitting control signal EM3. When applied to the three-dimensional display mode, the third light-emitting control signal EM3 may be different from both the first light-emitting control signal EM1 and the second light-emitting control signal EM2. The periods of the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both twice the period of the third light-emitting control signal EM3.

[0097] It should be noted that the above description is merely exemplary, and the shared sub-circuit 21 of this application is not limited to... Figure 5 The specific circuit shown.

[0098] In some embodiments, such as Figure 4 As shown, the pixel circuit provided in this application may further include a first reset sub-circuit. The first reset sub-circuit is used to reset the second terminal of the first light-emitting control sub-circuit 22 during the reset phase of the pixel driving cycle. This resets the anode potential of the first light-emitting device 24, which helps ensure minimal brightness difference after each charge, thus improving display quality.

[0099] It should be noted that this embodiment can be based on the above. Figures 2 to 5 The implementation of any of the corresponding embodiments is described here based on Figure 5 The implementation is described using an example, such as Figure 5 As shown, the first reset sub-circuit includes an eighth transistor T8. The first terminal of the eighth transistor T8 is used to receive the initial signal Vinit. The second terminal of the eighth transistor T8 is connected to the second terminal of the first light-emitting control sub-circuit 22. The control terminal of the eighth transistor T8 is used to receive the first gate drive signal GateM1.

[0100] In some embodiments, such as Figure 4 As shown, the pixel circuit provided in this application may further include a second reset sub-circuit. This second reset sub-circuit is used to reset the second terminal of the second light-emitting control sub-circuit 23 during the reset phase of the pixel driving cycle. This resets the anode potential of the second light-emitting device 25, which helps ensure minimal brightness difference after each charge and improves display quality.

[0101] It should be noted that this embodiment can be based on the above. Figures 2 to 5 The implementation of any of the corresponding embodiments is described here based on Figure 5 The implementation is described using an example, such as Figure 5 As shown, the second reset sub-circuit includes a ninth transistor T9. The first terminal of the ninth transistor T9 is used to receive the initial signal Vinit. The second terminal of the ninth transistor T9 is connected to the second terminal of the second light-emitting control sub-circuit 23. The control terminal of the ninth transistor T9 is used to receive the first gate drive signal GateM1.

[0102] The above describes the pixel circuit provided in this application, which may include a common sub-circuit 21, a first light-emitting control sub-circuit 22 and a first light-emitting device 24 respectively configured for different pixels, a second light-emitting control sub-circuit 23 and a second light-emitting device 25. This pixel circuit can drive different pixels, which is beneficial for saving space, simplifying layout, and improving resolution. When applied to three-dimensional display mode, it can effectively improve the three-dimensional display effect.

[0103] In another aspect, based on the pixel circuit provided in the embodiments of this application, a pixel circuit driving method is also provided, see [link to relevant documentation]. Figure 6 As shown, Figure 6 This is a schematic flowchart of a pixel circuit driving method provided in an embodiment of this application, which may include:

[0104] Step S61: During the light emission phase of the pixel driving cycle, the shared sub-circuit 21 provides driving current to the first light emission control sub-circuit 22 and the second light emission control sub-circuit 23 through the common connection terminal N;

[0105] Step S62: The first light-emitting control sub-circuit 22 is turned on or off in response to the first light-emitting control signal EM1. When the first light-emitting control sub-circuit 22 is turned on, it provides driving current to the first light-emitting device 24.

[0106] Step S63: The second light-emitting control sub-circuit 23 responds to the second light-emitting control signal EM2 by turning on or off. When the first light-emitting control sub-circuit 22 is turned on, it provides driving current to the second light-emitting device 25.

[0107] The first light-emitting device 24 and the second light-emitting device 25 correspond to different pixels.

[0108] In some embodiments, when applied to a two-dimensional display, the effective potentials of the first light emission control signal EM1 and the second light emission control signal EM2 overlap in time, which can control the first light emission control sub-circuit 22 and the second light emission control sub-circuit 23 to be turned on simultaneously, so that different pixels corresponding to the current pixel circuit are displayed simultaneously.

[0109] In other embodiments, the effective potentials of the first light-emitting control signal EM1 and the second light-emitting control signal EM2 do not overlap in time, and the first light-emitting control sub-circuit 22 and the second light-emitting control sub-circuit 23 are used to alternately conduct in response to the effective potentials of their respective light-emitting control signals. When applied to 3D display, the pixels corresponding to the first light-emitting control sub-circuit 22 and the pixels corresponding to the second light-emitting control sub-circuit 23 are displayed in time segments. In some embodiments, the pixel corresponding to the first light-emitting control sub-circuit 22 can be the left-eye pixel L, and the pixel corresponding to the second light-emitting control sub-circuit 23 can be the right-eye pixel R. By setting corresponding control sub-circuits and light-emitting control signals for different pixels, the alternating display of the left-eye pixel L and the right-eye pixel R can be achieved based on the shared part circuit, i.e., the shared sub-circuit 21.

[0110] In some embodiments, the periods of the first light emission control signal EM1 and the second light emission control signal EM2 are both twice that of the third light emission control signal EM3. One period of the third light emission control signal EM3 can be used as a pixel driving period. Two adjacent pixel driving periods control the first light emission control sub-circuit 22 and the second light emission control sub-circuit 23 to be turned on, thereby realizing the alternating display of the left eye pixel L and the right eye pixel R.

[0111] In some embodiments, with Figure 5 The pixel circuit shown is described using an example of its application in a 3D display mode. See [link / reference]. Figure 7 As shown, Figure 7 This is a timing diagram of each signal in the pixel circuit driving process provided in the embodiments of this application.

[0112] The driving process of this pixel circuit can include a driving process corresponding to the left-eye pixel L and a driving process corresponding to the right-eye pixel R, and the driving processes for the left-eye pixel L and the right-eye pixel R are performed alternately. Each driving process can be considered as a pixel driving cycle, which can include a reset phase, a write phase, and a light emission phase. Specifically, taking the Nth-level pixel circuit as an example, the first gate driving signal GateM1 can be provided by the previous-level gate driving signal Gate_N-1, and the second gate driving signal GateM2 can be provided by the current-level gate driving signal Gate_N.

[0113] The driving process for the right eye pixel R:

[0114] During the reset phase, tR1 and Gate_N-1 are at a low level, while EM1, EM2, EM3 and Gate_N are all at a high level.

[0115] When transistor T3 is turned on, the initial signal Vinit is written to the first node N1, and transistor T6 is turned on. When transistor T9 is turned on, the initial signal Vinit is written to the second terminal of transistor T2, resetting the potential of the anode of the second light-emitting device 25. Transistors T1, T2, T4, T5, and T7 are all turned off. In addition, transistor T8 is also turned on, and the initial signal Vinit is written to the second terminal of transistor T1, resetting the potential of the anode of the first light-emitting device 24.

[0116] During the write phase tR2, Gate_N is low, while EM1, EM2, EM3, and Gate_N-1 are all high.

[0117] When circuits T5 and T4 are turned on, the data signal Data is written to the first node N1 through T5, T6, and T4 until the write voltage of the first node N1 is the sum of the data signal voltage and the threshold voltage, thus charging the energy storage unit and supplementing the drive current during the light emission phase. Circuits T1, T2, T3, T7, T8, and T9 are all turned off.

[0118] During the light emission phase tR3, EM2 and EM3 are both at low level, while EM1, Gate_N and Gate_N-1 are all at high level.

[0119] When T7 is turned on, the first power signal VDD is provided to the first terminal of T6 through the second node N2. T6 conducts based on the signals from the first node N1 and the second node N2 and provides driving current. When T2 is turned on, the driving current drives the second light-emitting device 25 to emit light, displaying the right eye pixel R. T1, T3, T4, T5, T8, and T9 are all turned off.

[0120] The reset phase tL1 and write phase tL2 of the driving process for the left eye pixel L are the same as the corresponding phases of the driving process for the right eye pixel R. The following mainly describes the light emission phase tL3 of the driving process for the left eye pixel L:

[0121] EM1 and EM3 are both low level, while EM2, Gate_N and Gate_N-1 are all high level.

[0122] When T7 is turned on, the first power signal VDD is provided to the first terminal of T6 through the second node N2. T6 conducts based on the signals from the first node N1 and the second node N2 and provides driving current. When T1 is turned on, the driving current drives the first light-emitting device 24 to emit light, displaying the left eye pixel L. T2, T3, T4, T5, T8, and T9 are all turned off.

[0123] Another aspect of this application provides a display panel, see [link to application]. Figure 8 As shown, Figure 8 This is a schematic diagram of a display panel provided in an embodiment of this application, which may include:

[0124] Multiple gate lines G_M, multiple data lines D_N, and multiple pixel unit groups arranged in an array are provided. Multiple pixel unit groups located in the same row direction are connected to the same gate line G_M, and multiple pixel unit groups located in the same column direction are connected to the same data line D_N. Each pixel unit group includes a left-eye pixel L and a right-eye pixel R. The left-eye pixel L and the right-eye pixel R in the same pixel unit group have the same emission color and are driven by the pixel circuit of any of the above embodiments. The white rectangle represents the pixel circuit.

[0125] By employing the pixel circuit provided in the embodiments of this application, the display panel can effectively improve resolution, simplify layout, and enhance display effect.

[0126] In some embodiments, such as Figure 8 As shown, the left-eye pixel L and right-eye pixel R in each pixel unit group are arranged alternately in the column direction. Both the left-eye pixel L and right-eye pixel R can include different emission colors; for example, the left-eye pixel L can include a red left-eye pixel L, a green left-eye pixel L, and a blue left-eye pixel L. The red left-eye pixel L and red right-eye pixel R are arranged alternately in the column direction and connected to the same pixel circuit; the green left-eye pixel L and green right-eye pixel R are arranged alternately in the column direction and connected to the same pixel circuit; and the blue left-eye pixel L and blue right-eye pixel R are arranged alternately in the column direction and connected to the same pixel circuit. In each row, three pixel unit groups with emission colors of red, green, and blue arranged in sequence are arranged repeatedly in the row direction as the smallest repeating unit.

[0127] In other embodiments, see Figure 9 As shown, Figure 9This is a schematic diagram of a display panel according to another embodiment of this application. In each pixel unit group, the left-eye pixel L and right-eye pixel R are arranged at intervals in the row direction. Both the left-eye pixel L and the right-eye pixel R can include different emission colors. For example, the left-eye pixel L can include red, green, and blue left-eye pixels, and the right-eye pixel R can include red, green, and blue right-eye pixels. In each row, the red, green, and blue left-eye pixels L, red, green, and blue right-eye pixels R are arranged sequentially in the row direction, and this arrangement is repeated in the row direction using this as the smallest repeating unit. The red, green, and blue left-eye pixels L are each connected to their respective pixel circuits. The red right-eye pixel R is connected to the same pixel circuit as the red left-eye pixel L, the green right-eye pixel R is connected to the same pixel circuit as the green left-eye pixel L, and the blue right-eye pixel R is connected to the same pixel circuit as the blue left-eye pixel L.

[0128] It should be noted that the pixels with different emission colors and the arrangement of the pixels can be flexibly set according to actual needs and display effect requirements. This is just an example of the arrangement of the left eye pixel L and the right eye pixel R with different emission colors.

[0129] In some embodiments, see Figure 10 As shown, Figure 10 This is a partial layout structure diagram of the display panel provided in an embodiment of this application.

[0130] Multiple gate lines include a first gate drive signal line and a second gate drive signal line; the first gate drive signal line can be provided by the previous stage gate drive signal Gate_N-1 line, and the second gate drive signal line can be provided by the current stage gate drive signal Gate_N line;

[0131] The display panel also includes an initial signal Vinit line, a first light emission control signal EM1 line, a second light emission control signal EM2 line, and a third light emission control signal EM3 line;

[0132] Among them, the initial signal Vinit line, the first gate drive signal line, the second gate drive signal line, the third light emission control signal EM3 line, the first light emission control signal EM1 line, and the second light emission control signal EM2 line are arranged in parallel in the column direction.

[0133] The common sub-circuit 21 of the pixel circuit is located in the area between the initial signal Vinit line and the first light emission control signal EM1 line and between two adjacent data lines, and partially overlaps with the corresponding connected data lines; the first light emission control sub-circuit 22 and the second light emission control sub-circuit 23 of the pixel circuit are located between two adjacent data lines and are arranged at intervals in the row direction. The first light emission control sub-circuit 22 partially overlaps with the first light emission control signal EM1 line, and the second light emission control sub-circuit 23 partially overlaps with the second light emission control signal EM2 line.

[0134] The common connection terminal N is located between the third light-emitting control signal EM3 line and the first light-emitting control signal EM1 line. The first light-emitting control sub-circuit 22 and the second light-emitting control sub-circuit 23 are connected to the common connection terminal N and are connected to the common sub-circuit 21 through a connecting wire that is connected to the common connection terminal N at one end and extends parallel to the column direction.

[0135] By connecting the first light-emitting control sub-circuit 22 and the second light-emitting control sub-circuit 23 to the same common sub-circuit 21, layout space can be effectively saved and the layout simplified.

[0136] See Figure 10 As shown, it illustrates the pixel circuit layout structure diagram corresponding to pixel unit groups with emission colors of red, green, and blue. The corresponding multiple data lines include a first data line Data_R for providing data signals to pixel unit groups with emission colors of red, a second data line Data_G for providing data signals Data to pixel unit groups with emission colors of green, and a third data line Data_B for providing data signals Data to pixel unit groups with emission colors of blue.

[0137] In the following text, the first gate drive signal line is referred to as Gate_N-1, the second gate drive signal line as Gate_N, and the emitted light color is red. Figure 5 The layout structure of the corresponding pixel circuit will be described using an example.

[0138] The first light-emitting control sub-circuit 22 includes a first transistor T1. The projections of the first transistor T1 and the first light-emitting control signal EM1 line on the display panel overlap, and the control terminal of the first transistor T1 is connected to the first light-emitting control signal EM1 line. The first terminal of the first transistor T1 is connected to the common connection terminal N, and the second terminal of the first transistor T1 is connected to the second terminal of the eighth transistor T8. The eighth transistor T8 and the first transistor T1 are arranged at intervals in the column direction. The projection of the eighth transistor T8 and the Gate_N-1 line on the display panel overlap, and the control terminal of the eighth transistor T8 is connected to the Gate_N-1 line. The first terminal of the eighth transistor T8 is connected to the initial signal Vinit line (not shown in the figure).

[0139] The second light-emitting control sub-circuit 23 includes a second transistor T2. In the row direction, the second transistor T2 is disposed between the first data line Data_R and the first transistor T1. The projections of the second transistor T2 and the second light-emitting control signal EM2 line on the display panel overlap, and the control terminal of the second transistor T2 is connected to the second light-emitting control signal EM2 line. The first terminal of the second transistor T2 is connected to the common connection terminal N through a bent connecting wire, and the second terminal of the second transistor T2 is connected to the second terminal of the ninth transistor T9. The ninth transistor T9 and the second transistor T2 are arranged at intervals in the column direction. The projection of the ninth transistor T9 on the display panel overlaps with the Gate_N-1 line, and the control terminal of the ninth transistor T9 is connected to the Gate_N-1 line. The first terminal of the ninth transistor T9 is connected to the initial signal Vinit line (not shown in the figure).

[0140] The shared sub-circuit 21 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C (not shown in the figure).

[0141] The projection of the third transistor T3 onto the display panel overlaps with that of the Gate_N-1 line. The control terminal of the third transistor T3 is connected to the Gate_N-1 line. The first terminal of the third transistor T3 is connected to the initial signal Vinit line, and the second terminal of the third transistor T3 is connected to the first node N1. The projection of the fourth transistor T4 onto the display panel overlaps with that of the Gate_N line. The control terminal of the fourth transistor T4 is connected to the Gate_N line. The first terminal of the fourth transistor T4 is connected to the common connection terminal N via a connecting wire extending parallel to the column direction. The second terminal of the fourth transistor T4 is connected to the first node N1 via a bent connecting wire. The projection of the fifth transistor T5 onto the display panel overlaps with the projections of the first data line Date_R and the Gate_N line. The control terminal of the fifth transistor T5 is connected to the Gate_N line. The first terminal of the fifth transistor T5 is connected to the first data line Date_R. The second terminal of the fifth transistor T5 is connected to the first terminal of the sixth transistor T6 via the second node N2 and to the second terminal of the seventh transistor T7. The sixth transistor T6 is aligned with and spaced apart from the third transistor T3 in the column direction. The sixth transistor T6 is positioned between the Gate_N line and the third light emission control signal EM3 line. The second end of the sixth transistor T6 is connected to the first end of the fourth transistor T4 via a bent connecting wire. The projection of the seventh transistor T7 on the display panel overlaps with the projection of the first data line Date_R and the third light emission control signal EM3 line on the display panel. The control terminal of the seventh transistor T7 is connected to the third light emission control signal EM3, and the first end of the seventh transistor T7 is connected to the first power signal VDD line (not shown in the figure).

[0142] In another aspect of this application, a display device is also provided, which may include the display panel described above.

[0143] In some embodiments, the display device may include any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments disclosed herein do not limit this.

[0144] In some embodiments, the display device may further include a prism array located on the light-emitting side of the display panel. By driving the left-eye pixel L and the right-eye pixel R respectively, and using the prism array to refract the image of the left-eye pixel L into the user's left eye and the image of the right-eye pixel R into the user's right eye, the user's eyes can receive two images with parallax information and synthesize a stereoscopic image in the brain, realizing a three-dimensional display mode and providing the user with a three-dimensional display image.

[0145] In some embodiments, see Figure 11 As shown, Figure 11 This is a cross-sectional structural diagram of a display device provided in an embodiment of this application. The display panel may include multiple pixel unit groups, and each pixel unit group may include a left-eye pixel L and a right-eye pixel R. The prism array may include multiple prisms, and the projection of each prism onto the display panel may overlap with a pixel unit group.

[0146] In some embodiments, the display effect can be adjusted by adjusting the position or angle of the prism, thereby adjusting the refraction angle of the light emitted by the prism to each pixel.

[0147] In some embodiments, the prism array may be a liquid crystal prism array, and the display device may further include a liquid crystal driving circuit for providing voltage to the liquid crystal prism array to achieve switching between two-dimensional and three-dimensional display. See also Figure 12 As shown, Figure 12 This is a cross-sectional structural schematic diagram of a display device provided in another embodiment of this application.

[0148] When a preset voltage is applied, the liquid crystal molecules in the liquid crystal prism rearrange themselves, changing the refraction path of light and thus achieving a 3D display effect. The specific display effect depends on the amplitude and waveform of the preset voltage, as well as the characteristics and design of the liquid crystal prism.

[0149] When the pressure is stopped or a lower voltage is applied, the liquid crystal molecules will return to their natural state when no electric field is applied. At this time, the liquid crystal prism no longer refracts light or changes its propagation direction, resulting in a 2D display effect or a state with no display.

[0150] In some embodiments, the liquid crystal prism may specifically be a liquid crystal resin prism.

[0151] The technical solutions of this application have been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A display panel, characterized by, The display panel comprises a plurality of gate lines, a plurality of data lines and a plurality of pixel unit groups arranged in an array, a plurality of pixel unit groups in the same row direction are connected with the same gate line, and a plurality of pixel unit groups in the same column direction are connected with the same data line, wherein each pixel unit group comprises a left-eye pixel and a right-eye pixel, and the left-eye pixel and the right-eye pixel in the same pixel unit group are driven by a pixel circuit; the pixel circuit comprises a shared sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a first light-emitting device and a second light-emitting device, and the first end of the first light-emitting control sub-circuit and the first end of the second light-emitting control sub-circuit are connected with the shared sub-circuit through a common connection end; the shared sub-circuit is configured to provide driving current for the first light-emitting control sub-circuit and the second light-emitting control sub-circuit through the common connection end; the second end of the first light-emitting control sub-circuit is configured to be connected with the first light-emitting device and to provide the driving current to the first light-emitting device in response to a first light-emitting control signal; the second end of the second light-emitting control sub-circuit is configured to be connected with the second light-emitting device and to provide the driving current to the second light-emitting device in response to a second light-emitting control signal; wherein the first light-emitting device and the second light-emitting device correspond to different pixels, the first light-emitting device corresponds to the left-eye pixel, the second light-emitting device corresponds to the right-eye pixel, the effective potentials of the first light-emitting control signal and the second light-emitting control signal do not overlap in time, and the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are configured to alternately turn on in response to the effective potentials of the respective light-emitting control signals, so that the left-eye pixel and the right-eye pixel are alternately displayed; the plurality of gate lines comprises a first gate drive signal line and a second gate drive signal line; the display panel further comprises an initial signal line, a first light-emitting control signal line, a second light-emitting control signal line and a third light-emitting control signal line; wherein the initial signal line, the first gate drive signal line, the second gate drive signal line, the third light-emitting control signal line, the first light-emitting control signal line and the second light-emitting control signal line are sequentially arranged in parallel in the column direction; the shared sub-circuit of the pixel circuit is arranged in a region between the initial signal line and the first light-emitting control signal line and between adjacent two data lines, and partially overlaps with the corresponding connected data line; the first light-emitting control sub-circuit and the second light-emitting control sub-circuit of the pixel circuit are arranged between the adjacent two data lines and are arranged in the row direction with a spacing, the first light-emitting control sub-circuit partially overlaps with the first light-emitting control signal line, and the second light-emitting control sub-circuit partially overlaps with the second light-emitting control signal line; the common connection end is arranged between the third light-emitting control signal line and the first light-emitting control signal line, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are connected with the common connection end, and are connected with the shared sub-circuit through a connection wire connected with the common connection end at one end and extending in parallel to the column direction.

2. The display panel of claim 1, wherein, The left-eye pixel and the right-eye pixel in each of the pixel unit groups are arranged in a column direction or in a row direction.

3. The display panel of claim 1, wherein, The first light-emitting control sub-circuit comprises a first transistor, a first end of the first transistor is connected with the common connection end, a second end of the first transistor is connected with the first light-emitting device, and a control end of the first transistor is used for receiving the first light-emitting control signal.

4. The display panel of claim 1, wherein, The second light-emitting control sub-circuit comprises a second transistor, a first end of the second transistor is connected with the common connection end, a second end of the second transistor is connected with the second light-emitting device, and a control end of the second transistor is used for receiving the second light-emitting control signal.

5. The display panel of any one of claims 1 to 4, wherein, The common sub-circuit comprises a reset unit, an energy storage unit, a data writing unit, a driving unit, a compensation unit and a light-emitting control unit. A first end of the reset unit is used for receiving an initial signal, and a second end of the reset unit is connected with a first node, and the reset unit is used for transmitting the initial signal to the first node in a reset stage of each pixel driving period. A first end of the energy storage unit is used for receiving a first power signal, and a second end of the energy storage unit is connected with the first node. A first end of the compensation unit is connected with the common connection end, and a second end of the compensation unit is connected with the first node. A first end of the data writing unit is used for receiving a data signal, and a second end of the data writing unit is connected with a second node, and the data writing unit is used for providing the data signal and a threshold voltage to the first node through the compensation unit in a writing stage of each pixel driving period. A first end of the driving unit is connected with the second node, a second end of the driving unit is connected with the common connection end, and a control end of the driving unit is connected with the first node. A first end of the light-emitting control unit is used for receiving the first power signal, and a second end of the light-emitting control unit is connected with the second node, and the light-emitting control unit is used for turning on to provide the first power signal to the second node in a light-emitting stage of each pixel driving period; and the driving unit is used for providing a driving current to the common connection end based on signals provided by the first node and the second node.

6. The display panel of claim 5, wherein The reset unit comprises a third transistor, a first end of the third transistor is used for receiving the initial signal, a second end of the third transistor is connected with the first node, and a control end of the third transistor is used for receiving a first gate driving signal. The energy storage unit comprises a storage capacitor, a first end of the storage capacitor is used for receiving the first power signal, and a second end of the storage capacitor is connected with the first node. The compensation unit comprises a fourth transistor, a first end of the fourth transistor is connected with the common connection end, and a second end of the fourth transistor is connected with the first node. The data writing unit comprises a fifth transistor, a first end of the fifth transistor is configured to receive the data signal, a second end of the fifth transistor is connected with the second node, and control ends of the fifth transistor and the fourth transistor are configured to receive a second gate driving signal. The driving unit comprises a sixth transistor, a first end of the sixth transistor is connected with the second node, and a second end of the sixth transistor is connected with the common connection end, and the control end of the driving unit is connected with the first node. The light emitting control unit comprises a seventh transistor, a first end of the seventh transistor is configured to receive the first power supply signal, a second end of the seventh transistor is connected with the second node, and a control end of the seventh transistor is configured to receive the third light emitting control signal.

7. The display panel of any one of claims 1-4, wherein, The pixel circuit further comprises: A first reset sub-circuit, configured to reset the second end of the first light emitting control sub-circuit in a reset stage of a pixel driving period.

8. The display panel of claim 7, wherein, The first reset sub-circuit comprises an eighth transistor, a first end of the eighth transistor is configured to receive an initial signal, a second end of the eighth transistor is connected with the second end of the first light emitting control sub-circuit, and a control end of the eighth transistor is configured to receive a first gate driving signal.

9. The display panel of any of claims 1-4, wherein, The pixel circuit further comprises: A second reset sub-circuit, configured to reset the second end of the second light emitting control sub-circuit in a reset stage of a pixel driving period.

10. The display panel of claim 9, wherein, The second reset sub-circuit comprises a ninth transistor, a first end of the ninth transistor is configured to receive an initial signal, a second end of the ninth transistor is connected with the second end of the second light emitting control sub-circuit, and a control end of the ninth transistor is configured to receive a first gate driving signal.

11. A display device comprising: The display panel of any one of claims 1 to 10.

12. The display device of claim 11, wherein, The display device further comprises a prism array, and the prism array is located on a light emitting side of the display panel.

13. The display device of claim 12, wherein, The prism array is a liquid crystal prism array, and the display device further comprises a liquid crystal driving circuit, and the liquid crystal driving circuit is configured to provide a voltage to the liquid crystal prism array to realize switching between two-dimensional display and three-dimensional display.

14. A pixel circuit driving method, characterized by, The pixel circuit applied to the display panel of any one of claims 1 to 10, comprising: In a light emitting stage of a pixel driving period, the common sub-circuit provides driving current for the first light emitting control sub-circuit and the second light emitting control sub-circuit through the common connection end; The first light emitting control sub-circuit is turned on or turned off in response to the first light emitting control signal, and when the first light emitting control sub-circuit is turned on, the driving current is provided to the first light emitting device; The second light emitting control sub-circuit is turned on or turned off in response to the second light emitting control signal, and when the first light emitting control sub-circuit is turned on, the driving current is provided to the second light emitting device; The first light emitting device and the second light emitting device correspond to different pixels, the first light emitting device corresponds to a left eye pixel, the second light emitting device corresponds to a right eye pixel, effective potentials of the first light emitting control signal and the second light emitting control signal do not overlap in time, and the first light emitting control sub-circuit and the second light emitting control sub-circuit are configured to alternately conduct in response to effective potentials of respective light emitting control signals, so that the left eye pixel and the right eye pixel are alternately displayed.

Images