Light-emitting control circuit and display panel

Abstract

Embodiments of the present application provide a light-emitting control circuit and display panel, wherein the light-emitting control circuit includes multiple cascaded light-emitting control subcircuits, each of which controls a corresponding row of subpixels. Each subpixel includes a first light-emitting diode and a second light-emitting diode. Each light-emitting control subcircuit includes two output modules, capable of outputting two light-emitting signals, respectively, to control the first and second light-emitting diodes. This arrangement at least solves the problem of requiring two light-emitting control circuits for each row of subpixels in an anti-peep OLED display panel, each outputting two light-emitting control signals, which results in a large circuit footprint. This effectively reduces border space usage and enables a further narrow-border design.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a light-emitting control circuit and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) display panels with privacy protection typically divide a subpixel into two regions, each housing an LED. In privacy protection mode, one LED emits light under the control of a light control signal; in normal mode, the other LED emits light under the control of a light control signal. Therefore, two light control circuits are required for each row of subpixels, each outputting two light control signals. This requires at least four clock drive signals, resulting in a larger circuit footprint and a wider border for the display panel. Summary of the Invention

[0003] Embodiments of the present application provide a light emitting control circuit and a display panel to at least solve the problem that two light emitting control circuits are required for each row of sub-pixels in an anti-peeping OLED display panel, resulting in a large space occupied by the circuits.

[0004] In a first aspect, an embodiment of the present application provides a light-emitting control circuit, wherein the light-emitting control circuit includes a plurality of cascaded light-emitting control subcircuits, each of the light-emitting control subcircuits corresponding to a row of sub-pixels, each of the sub-pixels including a first light-emitting diode and a second light-emitting diode, and each of the light-emitting control subcircuits includes: an input module, which receives an input signal and a first clock signal, and connects a first node and a second node, and is configured to control the potential of the first node and the second node according to the input signal and the first clock signal; a first output module, which receives a first preset high potential and a first preset low potential, and connects the first node and the second node, and the first output module is configured to output the first preset low potential to a first output end under the control of the first node, or output the first preset low potential to a first output end under the control of the second node. Under the control of the third node, the first preset high potential is output to the first output terminal; the second output module is connected to the second preset high potential and the second preset low potential, and is connected to the third node and the fourth node; the first control transistor includes a control electrode connected to the preset potential, a first electrode connected to the first node, and a second electrode connected to the third node; the second control transistor includes a control electrode connected to the preset potential, a first electrode connected to the second node, and a second electrode connected to the fourth node; wherein the second output module is configured to output the second preset high potential to the second output terminal under the control of the third node, or output the second preset low potential to the second output terminal under the control of the fourth node; the first output terminal is connected to the first light-emitting diode, and the second output terminal is connected to the second light-emitting diode.

[0005] In one embodiment, the first control transistor and the second control transistor maintain an on state under the control of the preset potential.

[0006] In one embodiment, the first output module includes: a first output transistor, including a control electrode connected to the first node, a first electrode connected to a first preset low potential, and a second electrode connected to the first output end; a second output transistor, including a control electrode connected to the second node, a first electrode connected to a first preset high potential, and a second electrode connected to the first output end.

[0007] In one embodiment, the second output module includes: a third output transistor, including a control electrode connected to the third node, a first electrode connected to the second preset high potential, and a second electrode connected to the second output end; a fourth output transistor, including a control electrode connected to the fourth node, a first electrode connected to the second preset low potential, and a second electrode connected to the second output end.

[0008] In one embodiment, the light emitting control subcircuit further includes: a first capacitor including a first end connected to the first clock signal and a second end connected to the fourth node.

[0009] In one embodiment, the light-emitting control subcircuit further includes: a second capacitor, including a first end connected to the fifth node and a second end connected to the fourth node; a third control transistor, including a control electrode connected to the fourth node, a first electrode connected to the first clock signal, and a second electrode connected to the fifth node; a fourth control transistor, including a control electrode connected to the second clock signal, a first electrode connected to a preset potential, and a second electrode connected to the fifth node; wherein, the first clock signal is in phase with the second clock signal.

[0010] In one embodiment, the light-emitting control subcircuit further includes: a coupling pull-down module, which is connected to the second clock signal and the preset high potential, and is connected to the first node and the second node, and the coupling pull-down unit is configured to couple the voltage difference between the first node and the preset high potential under the control of the second node; a coupling pull-up module, which is connected to the preset low potential, and is connected to the second node, and the coupling pull-up unit is configured to couple the voltage difference between the second node and the preset low potential.

[0011] In one embodiment, the light-emitting control subcircuit also includes: a high-voltage output maintaining module, which is connected to the first clock signal, the second clock signal and the preset low voltage, and connects the first node and the second node. The high-voltage output maintaining module is configured to control the potential of the second node according to the first clock signal, the second clock signal, the preset low voltage and the potential of the first node.

[0012] In one embodiment, the light emitting control subcircuit further includes: an output short circuit prevention module, which is connected to the preset high potential and connects the first node and the second node.

[0013] In one embodiment, the light emitting control subcircuit further includes: an ultra-low potential blocking module, including a first blocking transistor and a second blocking transistor; wherein the first blocking transistor is arranged between the high potential output maintaining module and the second node, and the second blocking transistor is arranged between the input module and the first node.

[0014] In a second aspect, an embodiment of the present application further provides a display panel comprising any of the above-mentioned light-emitting control circuits.

[0015] The beneficial effects provided by the embodiments of the present application include at least:

[0016] Embodiments of the present application provide a light-emitting control circuit and display panel, wherein the light-emitting control circuit includes multiple cascaded light-emitting control subcircuits, each of which controls a corresponding row of subpixels. Each subpixel includes a first light-emitting diode and a second light-emitting diode. Each light-emitting control subcircuit includes two output modules, capable of outputting two light-emitting signals, respectively, to control the first and second light-emitting diodes. This arrangement at least solves the problem of requiring two light-emitting control circuits for each row of subpixels in an anti-peep OLED display panel, each outputting two light-emitting control signals, which results in a large circuit footprint. This effectively reduces border space usage and enables a further narrow-border design.

[0017] Other beneficial effects of the embodiments of the present application will be further described in the following specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic structural diagram of a display panel provided in an optional embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of an anti-peeping pixel arrangement provided in an optional embodiment of the present application;

[0020] Figure 3 is a structural schematic diagram of a light emitting control subcircuit provided in an optional embodiment of the present application;

[0021] Figure 4 is a structural diagram of another light-emitting control subcircuit provided in an optional embodiment of the present application;

[0022] Figure 5 is an output timing diagram of a light emitting control subcircuit provided in an optional embodiment of the present application;

[0023] Figure 6 is a structural diagram of another light-emitting control subcircuit provided in an optional embodiment of the present application;

[0024] Figure 7 This is a control timing diagram of another light-emitting control subcircuit provided in an optional embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0028] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0029] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of the embodiments of the present application.

[0030] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0031] The use of "configured to" in the embodiments of the present application is intended to be open and inclusive language, which does not exclude devices that are adapted for or configured to perform additional tasks or steps.

[0032] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0033] Reference Figure 1 As shown, an embodiment of the present application provides a display panel 1000 that can be integrated into a display device, which can be a TV, a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, etc., but is not limited thereto. A display panel refers to a component for displaying an image, which may include many pixel units, each of which can emit light, display color, or reflect light to produce an image. The type of display panel can be set according to actual conditions. For example, the display panel can be a liquid crystal display (LCD), an organic light-emitting diode panel (OLED), a mini light-emitting diode display panel (Mini-LED), or a micro light-emitting diode display panel (Micro-LED). The embodiments of the present application are not limited thereto. The pixel units included in the display panel may exist in the form of rows and / or columns.

[0034] The display panel 1000 includes an effective display area AA and a peripheral area NA located around the effective display area AA. A circuit board 1100 is provided in the peripheral area of ​​the display panel 1000 for providing a clock signal to the circuit inside the display panel 1000. The above-mentioned effective display area AA includes a plurality of sub-pixels 1500. For the convenience of explanation, the above-mentioned plurality of sub-pixels 1500 in this application are described as being arranged in a matrix form. In this case, the sub-pixels arranged in a row along the first direction (X direction) are called a row of sub-pixels, and the sub-pixels arranged in a row along the second direction (Y direction) are called a column of sub-pixels. A row of sub-pixels can be connected to a gate signal line GL and a light-emitting control signal line EM, and a column of sub-pixels can be connected to a data line DL. The X direction intersects the Y direction perpendicularly.

[0035] Each sub-pixel 1500 may include a pixel driving circuit 1510 and a light emitting device (eg Figure 1 The first light emitting diode 1520 and the second light emitting diode 1530 are shown. The light emitting device can emit at least three primary colors, such as red (Red, R), green (Green, G) and blue (Blue, B).

[0036] The pixel driving circuit 1510 , the gate driving circuit 1200 , and the data driving circuit 1300 in the embodiment of the present application can be implemented using any circuit in the art that can realize corresponding functions, and will not be elaborated on in detail.

[0037] The display panel 1000 also includes a gate driving circuit 1200, a data driving circuit 1300, and a light-emitting control circuit 1400 arranged in the NA area. The gate driving circuit 1200 includes a plurality of cascaded gate driving sub-circuits 1210, and the light-emitting control circuit 1400 includes a plurality of cascaded light-emitting control sub-circuits 1410. Each column of sub-pixels is connected to the data driving circuit 1300 through at least one DL, each row of sub-pixels is connected to at least one gate driving sub-circuit 1210 through at least one GL, and each row of sub-pixels is connected to at least one light-emitting control sub-circuit 1410 through at least one EM. It should be noted that, according to different circuit application scenarios, a row of sub-pixels can be connected to two or three or more gate driving sub-circuits through two or three or more GLs, and a row of sub-pixels can be connected to two or three or more light-emitting control sub-circuits through two or three or more EMs. Figure 1 Only one signal line is used as an example for illustrative description, which is not intended to limit the scope of this application.

[0038] For example, in some anti-peep OLED display panels, a sub-pixel is generally divided into two areas, and a light-emitting diode is set in each area. Figure 1 and Figure 2 As shown, each sub-pixel 1500 includes two light-emitting diodes. In anti-peeping mode, one of the light-emitting diodes (for example, the first light-emitting diode 1520) emits light, and in normal display mode, the other light-emitting diode (for example, the second light-emitting diode 1530) emits light. By setting some shielding layers, the visibility at a wide viewing angle in anti-peeping mode can be made weaker, thereby achieving an anti-peeping function. In the current related technology, generally one light-emitting control sub-circuit 1410 controls one light-emitting diode. When a sub-pixel 1500 contains two light-emitting diodes, two light-emitting control sub-circuits 1410 need to be set to output corresponding light-emitting signals respectively. Correspondingly, the setting of the clock signal line also needs to be doubled, which will increase the power consumption of the display panel, and at the same time increase the border area (border) and layout space, affecting the aesthetics of the display screen.

[0039] In order to solve the above technical problems, an embodiment of the present application provides a light emitting control circuit. Figure 1 and Figure 3As shown, the light-emitting control circuit 1400 provided in the embodiment of the present application includes multiple cascaded light-emitting control subcircuits (EM subcircuits) 1410, each of which controls a row of sub-pixels. For simplicity of description, the following signal ports and the corresponding received or transmitted signals are described using the same symbols. For example, the first clock signal terminal and the first clock signal are both represented by XCK, the second clock signal terminal and the second clock signal are both represented by CK, the input terminal and the input signal are both represented by IN, and the output terminal and the output signal are both represented by OUT.

[0040] Reference Figure 3 As shown, each light-emitting control sub-circuit 1410 may include an input module 1411, a first output module 1412, and a second output module 1413. The input module 1411 receives an input signal IN and a first clock signal XCK, and connects a first node Q to a second node P. The input module 1411 is configured to control the potentials of the first node Q and the second node P based on the input signal IN and the first clock signal XCK. The first output module 1412 receives a first preset high potential VGH1 and a first preset low potential VGL1, and connects the first node Q to the second node P. The first output module 1412 is configured to output the first preset low potential to the first output terminal OUT1 under the control of the first node Q, or to output the first preset high potential to the first output terminal OUT1 under the control of the second node P. The second output module 1413 receives a second preset high potential VGH2 and a second preset low potential VGL2, and connects the third node Q1 to the fourth node P1.

[0041] In some embodiments, the light emitting control subcircuit further includes a first control transistor T16 and a second control transistor T17. The first control transistor T16 includes a transistor connected to a preset potential (refer to Figure 3 The second control transistor T17 includes a control electrode connected to a preset potential (reference voltage VGL), a first electrode connected to the first node Q, and a second electrode connected to the third node Q1; Figure 3 The second output module 1413 includes a control electrode connected to a second node P and a second electrode connected to a fourth node P1. The second output module 1413 is configured to output a second preset high potential VGH2 to a second output terminal OUT2 under the control of the third node Q1, or to output a second preset low potential VGL2 to the second output terminal OUT2 under the control of the fourth node P1. The first output terminal OUT1 is connected to a first light-emitting diode 1520, and the second output terminal OUT2 is connected to a second light-emitting diode 1530.

[0042] The light control circuit provided in the embodiments of the present application includes multiple cascaded light control subcircuits, each of which controls a row of subpixels. Each subpixel includes a first light-emitting diode and a second light-emitting diode. Each light control subcircuit includes two output modules, which can output two light control signals through two output terminals to control the first and second light-emitting diodes, respectively. This arrangement at least solves the problem of requiring two light control circuits for each row of subpixels in an anti-peep OLED display panel, each outputting two light control signals, which results in a large circuit footprint. This effectively reduces border space usage and enables a further narrow-border design.

[0043] It should be noted that the various units and control switches in the light-emitting control circuit can be implemented as a single transistor, a combination of multiple transistors, a capacitor, or a combination of a transistor and a capacitor. The transistors used in all embodiments of the present application can be thin film transistors (TFTs), field effect transistors (MOSs), or other devices with similar characteristics, and the embodiments of the present application do not limit this.

[0044] For example, the transistor may be a TFT. The TFT may be manufactured using an a-Si process, an oxide semiconductor process, a low-temperature polysilicon (LTPS) process, or a high-temperature polysilicon (HTPS) process. The embodiments of the present application are not limited thereto.

[0045] The embodiments of the present application do not limit the type of transistor. The transistor can be an N-type transistor or a P-type transistor, an enhancement-type transistor, or a depletion-type transistor. In the embodiments of the present application, all transistors are P-type transistors as an example to illustrate the present application. P-type transistors are turned on by a low-level voltage signal and turned off by a high-level voltage signal; that is, the operating voltage of the P-type transistor is a low-level voltage, and the turn-off voltage is a high-level voltage.

[0046] In the embodiments of the present application, the gate of the transistor is the control electrode. At the same time, in order to distinguish the two electrodes of the transistor other than the gate, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode. In this case, the first electrode of the transistor can be one of the source and drain of the transistor, and the second electrode can be the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally the same.

[0047] The capacitor in the embodiments of the present application can be a capacitive device independently manufactured through a process, for example, by manufacturing a dedicated capacitor electrode to realize the capacitive device. The individual capacitor electrodes (first plate and second plate) of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. The capacitor can also be a parasitic capacitance between transistors, or realized by the transistor itself and other devices or circuits, or by utilizing the parasitic capacitance between the circuits within the circuit itself.

[0048] Each of the above transistors may further include at least one switch connected in parallel with each transistor. The embodiments of this application are merely examples of the pixel driving circuit and the gate driving circuit. Other structures having the same functions as the pixel driving circuit and the gate driving circuit are not described in detail here, but all of them should fall within the scope of protection of this application.

[0049] The "first node", "second node", etc. in the embodiments of the present application do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes that are equivalent to the junction points of related electrical connections in the circuit diagram.

[0050] In one embodiment, the first control transistor T16 and the second control transistor T17 are kept in the on state under the control of a preset potential. Figures 3 to 5 The first control transistor T16 and the second control transistor T17 are both implemented by PMOS transistors, and therefore, their control electrodes are connected to a preset low potential VGL. If the first control transistor T16 or the second control transistor T17 is implemented by NMOS transistors, their control electrodes are connected to a preset high potential VGH.

[0051] Reference Figure 4 As shown, in some embodiments, the input module can be implemented by a transistor T3, wherein the control electrode of T3 is connected to the first clock signal XCK, the first electrode is connected to the input signal IN, and the second electrode is connected to the first node Q.

[0052] In some embodiments, the first output module may include: a first output transistor T9 and a second output transistor T10. T9 includes a control electrode connected to the first node Q, a first electrode connected to a first preset low potential VGL1, and a second electrode connected to the first output terminal OUT1. The second output transistor T10 includes a control electrode connected to the second node P, a first electrode connected to a first preset high potential VGH1, and a second electrode connected to the first output terminal OUT1. When the potential at point P is low and the potential at point Q is high, T10 turns on, T9 turns off, OUT1 outputs VGH1, and the corresponding first light-emitting diode is not illuminated. When the potential at point P is high and the potential at point Q is low, T9 turns on, T10 turns off, OUT1 outputs VGL1, and the corresponding first light-emitting diode is illuminated.

[0053] In some embodiments, the second output module includes a third output transistor T14 and a fourth output transistor T15. The third output transistor T14 includes a control electrode connected to the third node Q1, a first electrode connected to the second preset high potential VGH2, and a second electrode connected to the second output terminal OUT2. The fourth output transistor T15 includes a control electrode connected to the fourth node P1, a first electrode connected to the second preset low potential VGL2, and a second electrode connected to the second output terminal OUT2. When the potential at point P is low and the potential at point Q is high, T10 turns on, T9 turns off, OUT1 outputs VGH1, and the corresponding first light-emitting diode is not illuminated. Simultaneously, when the potential at point P1 is low and the potential at point Q1 is high, T15 turns on, T16 turns off, OUT2 outputs VGL2, and the corresponding second light-emitting diode is illuminated. When the potential at point P is high and the potential at point Q is low, T9 is turned on, T10 is turned off, OUT 1 outputs VGL 1, and the corresponding controlled first light-emitting diode emits light; at the same time, the potential at point P1 is high and the potential at point Q1 is low, T15 is turned off, T16 is turned on, OUT2 outputs VGH 2, and the corresponding controlled second light-emitting diode does not emit light.

[0054] It should be noted that VGL1 and VGL2 in the embodiment of the present application can be connected to the same VGL or different VGLs, and VGH1 and VGH2 can be connected to the same VGH or different VGHs. They can be freely selected according to usage requirements, and the embodiment of the present application does not limit this.

[0055] In some embodiments, the light-emission control subcircuit may further include a first capacitor C4, having a first terminal connected to the first clock signal XCK and a second terminal connected to the fourth node P4. When VGL 2 and XCK are at the same low potential, the threshold voltage of T15 causes the low potential output by OUT 2 to be significantly higher than VGL 2. By providing the first capacitor C4 with one terminal connected to XCK, the potential of the P1 node can be further lowered, such that the low potential output by the second output terminal OUT 2 is substantially consistent with VGL.

[0056] In some embodiments, the light emitting control subcircuit further includes a coupling pull-down module (including Figure 4 The coupling pull-down unit is configured to couple the voltage difference between the first node Q and the preset high potential VGH under the control of the second node P. The coupling pull-up module (including Figure 4 C2) is connected to a preset low potential VGL and is connected to the second node P, and the coupling pull-up unit is configured to couple a voltage difference between the second node P and the preset low potential VGL.

[0057] In some embodiments, the light emitting control subcircuit further includes: a high potential output maintaining module (including Figure 4 The first clock signal XCK, the second clock signal CK, and the preset low potential VGL are input to the high potential output maintaining module, and the first node Q and the second node P are connected. The high potential output maintaining module is configured to control the potential of the second node P according to the first clock signal XCK, the second clock signal CK, the preset low potential VGL, and the potential of the first node Q.

[0058] In some embodiments, the light emitting control subcircuit further includes: an output short circuit prevention module (including Figure 4 As shown in T8), a preset high potential VGH is connected, and the first node Q and the second node P are connected.

[0059] In one embodiment, the light-emission control subcircuit further includes an ultra-low potential blocking module, which includes a first blocking transistor T11 and a second blocking transistor T12. The first blocking transistor T11 is disposed between the high-potential output maintaining module and the second node P, and the second blocking transistor T12 is disposed between the input module and the first node Q. The ultra-low potential blocking module is configured to block the ultra-low potential transmitted to the first node or the second node to prevent gate breakdown.

[0060] pass Figures 3 and 4 The circuit structure shown can realize that a light-emitting control subcircuit outputs two light-emitting control signals to control the two light-emitting diodes to emit light alternately. Figure 5As shown, OUT 1 and OUT 2 can output control signals of the same radial direction and opposite phase.

[0061] According to another embodiment of the present application, the light emitting control subcircuit can also be implemented through another structure. Figure 6 As shown, the structure of the light emitting control sub-circuit in this embodiment is similar to the light emitting control sub-circuit described in the above embodiment. Figure 4 The circuit structure shown differs in that the first capacitor C4 is replaced by a second capacitor C5, and two transistors T18 and T19 are added. The light control subcircuit in this embodiment includes a second capacitor C5, a third control transistor T18, and a fourth control transistor T19. The second capacitor C5 includes a first terminal connected to the fifth node W and a second terminal connected to the fourth node P1. The third control transistor T18 includes a control electrode connected to the fourth node P1, a first terminal connected to the first clock signal XCK, and a second terminal connected to the fifth node W. The fourth control transistor T19 includes a control electrode connected to the second clock signal CK, a first terminal connected to the preset potential VGH, and a second terminal connected to the fifth node W. The first clock signal XCK is in phase opposition to the second clock signal CK. Figure 6 The functional modules in the light emitting control subcircuit are Figure 4 The structures and functions of the functional modules in the light emitting control subcircuit shown are the same, and the contents already described will not be repeated here. Figure 6 The second capacitor C5 is not directly connected to CK or XCK, and is connected to CK or XCK only when T18 or T19 is turned on, which can save power consumption of the clock signal.

[0062] Figure 7 The output timing simulation diagram of the light-emitting control subcircuit in the embodiment of the present application is shown. It can be seen that in the light-emitting control subcircuit provided in the embodiment of the present application, when the Q point outputs a normal pulse signal, the potentials of the P point and the P1 node remain consistent and are high; when P1 outputs a normal pulse signal, the potentials of the Q point and the Q1 point remain consistent and are high. The CK signal and the XCK signal are inverted, and the signals output by OUT 1 and OUT 2 are inverted. Therefore, two light-emitting signals can be output through the two output terminals of a light-emitting control subcircuit to control the first light-emitting diode and the second light-emitting diode respectively. Through the above-mentioned setting, at least the problem of setting two light-emitting control circuits for each row of sub-pixels in the anti-peep OLED display panel and outputting two light-emitting control signals respectively, which results in a large space occupied by the circuit, is solved, effectively saving border space occupation and realizing a further narrow border design.

[0063] The principles and implementation methods of the present application are explained using specific examples in the embodiments of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

[0064] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A light emitting control circuit, characterized in that: The light emitting control circuit includes a plurality of cascaded light emitting control subcircuits, each of which controls a row of sub-pixels, each of which includes a first light emitting diode and a second light emitting diode, and each of which includes: an input module receiving an input signal and a first clock signal, connecting a first node and a second node, and configured to control the potentials of the first node and the second node according to the input signal and the first clock signal; a first output module, connected to a first preset high potential and a first preset low potential, and connected to the first node and the second node, wherein the first output module is configured to output the first preset low potential to the first output terminal under the control of the first node, or to output the first preset high potential to the first output terminal under the control of the second node; The second output module is connected to the second preset high potential and the second preset low potential, and is connected to the third node and the fourth node; a first control transistor comprising a control electrode connected to a preset potential, a first electrode connected to the first node, and a second electrode connected to the third node; a second control transistor comprising a control electrode connected to a preset potential, a first electrode connected to the second node, and a second electrode connected to the fourth node; Wherein, the second output module is configured to output the second preset high potential to the second output end under the control of the third node, or to output the second preset low potential to the second output end under the control of the fourth node; the first output end is connected to the first light-emitting diode, and the second output end is connected to the second light-emitting diode.

2. The light emitting control circuit according to claim 1, characterized in that: The first control transistor and the second control transistor maintain a conductive state under the control of the preset potential.

3. The light emitting control circuit according to claim 1, wherein: The first output module includes: a first output transistor comprising a control electrode connected to the first node, a first electrode connected to a first preset low potential, and a second electrode connected to the first output terminal; The second output transistor includes a control electrode connected to the second node, a first electrode connected to a first preset high potential, and a second electrode connected to the first output end.

4. The light emitting control circuit according to claim 1, wherein: The second output module includes: a third output transistor, comprising a control electrode connected to the third node, a first electrode connected to the second preset high potential, and a second electrode connected to the second output terminal; The fourth output transistor includes a control electrode connected to the fourth node, a first electrode connected to the second preset low potential, and a second electrode connected to the second output end.

5. The light emitting control circuit according to claim 1, wherein: The light emitting control subcircuit further includes: The first capacitor includes a first end connected to the first clock signal and a second end connected to the fourth node.

6. The light emitting control circuit according to claim 1, wherein: The light emitting control subcircuit further includes: a second capacitor comprising a first end connected to the fifth node and a second end connected to the fourth node; a third control transistor comprising a control electrode connected to the fourth node, a first electrode connected to the first clock signal, and a second electrode connected to the fifth node; a fourth control transistor, comprising a control electrode connected to the second clock signal, a first electrode connected to a preset potential, and a second electrode connected to the fifth node; The first clock signal and the second clock signal are in opposite phases.

7. The light emitting control circuit according to claim 1, characterized in that: The light emitting control subcircuit further includes: a coupling pull-down module, receiving a second clock signal and a preset high potential, and connecting the first node and the second node, wherein the coupling pull-down module is configured to couple a voltage difference between the first node and the preset high potential under the control of the second node; The coupling pull-up module is connected to a preset low potential and is connected to the second node. The coupling pull-up module is configured to couple a voltage difference between the second node and the preset low potential.

8. The light emitting control circuit according to claim 7, characterized in that: The light emitting control subcircuit further includes: A high-voltage output maintaining module is connected to the first clock signal, the second clock signal and the preset low voltage, and connects the first node and the second node. The high-voltage output maintaining module is configured to control the potential of the second node according to the first clock signal, the second clock signal, the preset low voltage and the potential of the first node.

9. The light emitting control circuit according to claim 8, characterized in that: The light emitting control subcircuit further includes: The output short circuit prevention module is connected to the preset high potential and is connected to the first node and the second node.

10. The light emitting control circuit according to claim 8, characterized in that: The light emitting control subcircuit further includes: The ultra-low potential blocking module includes a first blocking transistor and a second blocking transistor; wherein the first blocking transistor is arranged between the high potential output maintaining module and the second node, and the second blocking transistor is arranged between the input module and the first node.

11. A display panel, characterized in that: The light emitting control circuit comprises the light emitting control circuit according to any one of claims 1 to 10.

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