Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device to solve the problem that an array substrate in the prior art is prone to being damaged by static electricity when a binding area on one side is removed. The array substrate comprises a control chip area which is located in the non-display area and used for being electrically connected with a control chip; the binding area is located in the non-display area, located on one side of the control chip area and used for being electrically connected with a circuit board; the first electrostatic protection pad is located in the non-display area, and the first electrostatic protection pad and the binding area are located on the different sides of the control chip area; the grounding wire is located in the non-display area and comprises a first grounding wire part and a second grounding wire part; wherein one end of the first electrostatic protection pad surrounds the display area through the first grounding wiring part and is electrically connected with a terminal included in the binding area.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] In recent years, the design requirements of array substrates have changed with each passing day. In order to meet the demand for narrow borders of products, the design optimization is carried out based on the original chip on glass technology (Chip On Glass, COG) design, and Chip On Film (Chip On Film, COF) Like is proposed, such as Figure 1 a- Figure 1 As shown in c. For the solution of placing the chip on a glass substrate, in order to further achieve a narrow frame, the FPC can be split and placed on both sides of the IC. Summary of the invention

[0003] The present disclosure provides an array substrate, a display panel and a display device, so as to improve the problem that the array substrate in the prior art is easily damaged by static electricity when a binding area on one side is removed.

[0004] An embodiment of the present disclosure provides an array substrate, comprising a display area and a non-display area located outside the display area, wherein the array substrate comprises:

[0005] A control chip area, located in the non-display area and used for being electrically connected to the control chip;

[0006] A binding area, located in the non-display area and on one side of the control chip area, and used for being electrically connected to a circuit board;

[0007] A first electrostatic protection pad is located in the non-display area and is located on a different side of the control chip area from the binding area;

[0008] The grounding trace is located in the non-display area and includes: a first grounding trace portion; wherein one end of the first electrostatic protection pad surrounds the display area through the first grounding trace portion and is electrically connected to a terminal included in the binding area.

[0009] In a possible implementation manner, the grounding trace further includes: a second grounding trace portion; and the other end of the first electrostatic protection pad is electrically connected to a terminal included in the control chip area through the second grounding trace portion.

[0010] In a possible implementation manner, the array substrate further includes: a second electrostatic protection pad; the grounding trace further includes: a third grounding trace portion;

[0011] The second electrostatic protection pad is implemented by the third ground wiring portion and the terminal included in the binding area.

[0012] In a possible implementation manner, the grounding trace further includes: a fourth grounding trace portion; and the control chip area and the binding area are electrically connected via the fourth grounding trace portion.

[0013] In a possible embodiment, the array substrate also includes: a fifth ground routing portion; the fifth ground routing portion is located on a side of the control chip area away from the display area, and one end is electrically connected to a terminal included in one end of the control chip area, and the other end is electrically connected to a terminal included in the other end of the control chip area.

[0014] In a possible implementation manner, the length of the fifth ground wiring portion is substantially equal to the length of the control chip region.

[0015] In a possible implementation manner, at least a portion of at least one of the first ground routing portion, the second ground routing portion, the third ground routing portion, the fourth ground routing portion, and the fifth ground routing portion is arc-shaped.

[0016] In a possible implementation manner, the control chip region extends along a first direction and has a first symmetry axis perpendicular to the first direction;

[0017] The first electrostatic protection pad and the second electrostatic protection pad are symmetrical about the first symmetrical line.

[0018] In a possible implementation manner, the outer contour of the array substrate is circular, elliptical, hexagonal or octagonal.

[0019] In a possible implementation manner, the first electrostatic protection pad and the second electrostatic protection pad are distributed in a figure eight shape.

[0020] The embodiment of the present disclosure also provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and also includes: an opposing substrate arranged opposite to the array substrate, a control chip arranged in the control chip area, and a circuit board arranged in the binding area.

[0021] In a possible implementation, the display panel further includes: a conductive colloid; the conductive colloid partially covers a portion around the counter substrate and partially extends along a side edge of the counter substrate to the first electrostatic protection pad and / or the second electrostatic protection pad of the array substrate.

[0022] In a possible implementation manner, the opposite substrate is further provided with a conductive layer on a side away from the array substrate; and the conductive colloid is overlapped with the conductive layer.

[0023] In a possible implementation manner, the array substrate includes a first region overlapping with the counter substrate, and a second region extending from the first region;

[0024] The control chip area, the binding area, and the grounding trace are all located in the second area of ​​the array substrate.

[0025] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0026] An embodiment of the present disclosure further provides a display device, which includes the array substrate provided by the embodiment of the present disclosure.

[0027] The beneficial effects of the embodiments of the present disclosure are as follows: In the embodiments of the present disclosure, for the first electrostatic protection pad on the different side of the binding area, the first grounding wiring portion surrounds the display area and is electrically connected to the terminals included in the binding area on the other side of the control chip area, so that when the circuit board on the side where the first electrostatic protection pad is located is removed, the first electrostatic protection pad on this side can still be connected to the circuit board on the other side of the control chip area, and the first electrostatic protection pad on this side can still play an electrostatic protection effect, without weakening the effect of the first electrostatic protection pad on improving the electrostatic shielding effect, thereby improving the problem of the array substrate in the prior art being easily damaged by static electricity when the binding area on one side is removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of an array substrate with control chip areas located at different positions;

[0029] Figure 2 A schematic diagram of an array substrate in which two circular binding areas are arranged on different sides of a control chip area;

[0030] Figure 3 One of the schematic diagrams of the array substrate provided in the embodiment of the present disclosure;

[0031] Figure 4A for Figure 3 A partial enlarged schematic diagram of

[0032] Figure 4B One of the wiring schematic diagrams at the control chip area provided in the embodiment of the present disclosure;

[0033] Figure 4C A second wiring diagram of the control chip area provided in an embodiment of the present disclosure;

[0034] Figure 4D The third wiring diagram of the control chip area provided in the embodiment of the present disclosure;

[0035] Figure 4E for Figure 4AAn enlarged schematic diagram at the dotted line coil S2;

[0036] Figure 5 One of the schematic diagrams of a display panel provided in an embodiment of the present disclosure;

[0037] Figure 6 This is one of the cross-sectional schematic diagrams of the array substrate provided in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0041] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0042] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0043] In recent years, the market demand for special-shaped / round wearable products has been increasing. In order to reduce the panel border, COF Like design is also used. Figure 2 As shown. However, in the actual product production process, due to the "figure eight" design of FPC1 and FPC2, there are problems that the bonding equipment cannot automatically correspond, and the use of manual bonding is time-consuming and labor-intensive with a high defect rate. Therefore, the design cancels one side of the FPC and only uses the other side of the FPC to transmit the panel function signal. This design requirement poses a challenge to the panel, and there are the following problems: After canceling the single-sided FPC, the grounding protection structure on this side (such as the Ag glue point) cannot be connected to the original FPC ground (GND) signal terminal, and the peripheral GND routing on this side loses the effective signal line connection. This change causes the product to have an electrostatic discharge (ESD) risk.

[0044] In view of this, see Figure 3 and Figure 4A As shown, an embodiment of the present disclosure provides an array substrate having a display area AA and a non-display area BB located outside the display area AA, wherein the array substrate includes:

[0045] The control chip area 1 is located in the non-display area BB and is used to be electrically connected to the control chip; specifically, the control chip area 1 may be provided with a plurality of first terminals, and the control chip area 1 may be electrically connected to the control chip through the plurality of first terminals;

[0046] The binding area 2 is located in the non-display area BB and on one side of the control chip area 1, and is used to be electrically connected to the circuit board; for example, Figure 3As shown, the binding area 2 is located on the right side of the control chip area 1; specifically, the binding area 2 has a plurality of second terminals, and the binding area 2 can be electrically connected to the circuit board through the plurality of second terminals;

[0047] The first electrostatic protection pad 31 is located in the non-display area BB and is located on a different side of the control chip area 1 from the binding area 2; for example, Figure 3 As shown, the binding area 2 is located on the right side of the control chip area 1, and the first electrostatic protection pad 31 is located on the left side of the control chip area 1;

[0048] The grounding trace is located in the non-display area BB and includes: a first grounding trace portion E1E4; wherein one end of the first electrostatic protection pad 31 surrounds the display area AA through the first grounding trace portion E1E4 and is electrically connected to the terminal (ie, the second terminal) included in the binding area 2.

[0049] In the embodiment of the present disclosure, for the first electrostatic protection pad 31 on the different side of the binding area 2, the first grounding wiring portion E1E4 surrounds the display area AA and is electrically connected to the terminal (i.e., the second terminal) included in the binding area 2 on the other side of the control chip area 1, so that when the circuit board 20 on the side where the first electrostatic protection pad 31 is located is removed, the first electrostatic protection pad 31 on this side can still be connected to the circuit board 20 on the other side of the control chip area 1, and the first electrostatic protection pad 31 on this side can still play an electrostatic protection effect, without weakening the effect of the first electrostatic protection pad 31 on improving the electrostatic shielding effect, thereby improving the problem of the array substrate in the prior art being easily damaged by static electricity when the binding area on one side is removed.

[0050] In one possible implementation, see Figure 3 and Figure 4A As shown, the array substrate further includes: a second grounding wiring portion E2E5, and the other end of the first electrostatic protection pad 31 is electrically connected to the terminal (i.e., the first terminal) included in the control chip area 1 through the second grounding wiring portion E2E5. In the embodiment of the present disclosure, the other end of the first electrostatic protection pad 31 is also electrically connected to the terminal included in the control chip area 1 through the second grounding wiring portion E2E5, which can enhance the conduction effect of removing static electricity when static electricity occurs on one side of the circuit board.

[0051] In one possible implementation, see Figure 3 and Figure 4A As shown, the array substrate further includes: a second electrostatic protection pad 32; the grounding trace further includes: a third grounding trace portion E4E7; the second electrostatic protection pad 32 is electrically connected to the terminal included in the binding area 2 through the third grounding trace portion E4E7. In the embodiment of the present disclosure, for the second electrostatic protection pad 32 on one side of the circuit board 20 that is not removed, it can be electrically connected to the terminal included in the adjacent binding area 2 to have a better static electricity conduction effect.

[0052] In one possible implementation, see Figure 3 and Figure 4A As shown, the array substrate further includes: a fourth ground wiring portion E3E6; the control chip area 1 and the binding area 2 are electrically connected via the fourth ground wiring portion E3E6.

[0053] In one possible implementation, see Figure 3 and Figure 4A As shown, the array substrate further includes: a fifth grounding wiring portion E5E6; the fifth grounding wiring portion E5E6 is located on the side of the control chip area 1 away from the display area AA, and one end of the fifth grounding wiring portion E5E6 is electrically connected to a terminal included at one end of the control chip area 1, and the other end is electrically connected to a terminal included at the other end of the control chip area 1. In the disclosed embodiment, the fifth grounding wiring portion E5E6 is further provided on the side of the control chip area 1 away from the display area AA, which can make the anti-static capability better and have a high performance advantage.

[0054] In one possible implementation, see Figure 4B As shown, Figure 4B Can be Figure 4A One of the enlarged schematic diagrams at the dotted line coil S1, the control chip area 1 may include a plurality of first terminals P1, the control chip may be electrically connected to the first terminal P1 by means of conductive glue (such as anisotropic conductive glue ACF glue) or welding, and the plurality of first terminals P1 may include a plurality of first lead-in terminals P11 arranged in sequence along the first direction X, and a plurality of second lead-out terminals P12 arranged in sequence along the first direction X, wherein the first lead-in terminal P11 may be connected to Figure 4E The second terminal P2 disposed in the binding area 2 is electrically connected through the signal line, and the second lead-out terminal P12 can be electrically connected to a plurality of data lines included in the display panel. Specifically, the display area of ​​the display panel may include scan lines extending along rows and data lines extending along columns. The scan lines and the data lines cross to define sub-pixel units. One end of the fifth ground wiring portion E5E6 (such as Figure 4A The left end of the fifth ground wiring portion E5E6) and one end of the control chip area 1 (such as Figure 4A The left end of the control chip area 1 in the middle) is electrically connected to the first lead-in terminal P11 (specifically, it can be the ground terminal in the first lead-in terminal P11), and the other end (such as Figure 4A The right end of the fifth grounding wiring portion E5E6) and the other end of the control chip area 1 (such as Figure 4A The first lead-in terminal P11 (specifically, the ground terminal in the first lead-in terminal P11) included in the right end of the control chip area 1 in the middle is electrically connected. Optionally, a plurality of first lead-in terminals P11 are provided, wherein the ground terminal (electrically connected to the ground terminal in the binding area) can be a terminal arranged near both ends of the plurality of first lead-in terminals arranged in sequence; Figure 4E As shown, Figure 4AIn the enlarged schematic diagram of the dotted coil S2 in the middle, the fourth ground routing portion E3E6 led out from the first introduction terminal P11 at the right end of the control chip area 1 is connected to the second terminal P2 of the binding area 2 (specifically, it can be the ground terminal in the second terminal P2, and optionally, the ground terminal included in the second terminal P2 can be a terminal arranged near both ends of a plurality of second terminals arranged in sequence), and the second terminal P2 of the binding area 2 can be electrically connected to the circuit board 20 by means of conductive glue (such as anisotropic conductive glue ACF glue) or welding, wherein the ground terminal in the second terminal P2 and the ground signal line in the circuit board 20 are electrically connected.

[0055] In another possible implementation, see Figure 4C As shown, the fifth grounding wiring portion E5E6 may not be electrically connected to the terminal included in the control chip area 1, that is, not connected to the control chip area 1, and the other end of the second electrostatic protection pad 32 (such as Figure 4A The right end in the figure) is directly electrically connected to the terminal included in the binding area 2.

[0056] In another possible implementation, see Figure 4D As shown, when the fifth ground wiring portion E5E6 is not electrically connected to the terminal included in the control chip area 1, it can also be wired in the gap area between the first lead-in terminal P11 and the second lead-in terminal P12 in the control chip area 1. Figure 4B and Figure 4C As shown, the fifth ground wiring portion E5E6 is wired on the side of the control chip area 1 away from the display area AA. The fifth ground wiring portion E5E6 in the disclosed embodiment is wired in the gap area between the first introduction terminal P11 and the second introduction terminal P12 in the control chip area 1, which can further reduce the border width of the display panel, which is conducive to achieving a narrow border of the display panel.

[0057] In one possible implementation, see Figure 3 and Figure 4A As shown, the length of the fifth ground wiring portion E5E6 is substantially equal to the length of the control chip region 1 .

[0058] In one possible implementation, see Figure 3 and Figure 4A As shown, at least a portion of at least one of the first ground routing portion E1E4, the second ground routing portion E2E5, the third ground routing portion E4E7, the fourth ground routing portion E3E6, and the fifth ground routing portion E5E6 is arc-shaped.

[0059] In one possible implementation, see Figure 3 and Figure 4AAs shown, the control chip area 1 extends along the first direction X and has a first symmetry axis k perpendicular to the first direction X; the first electrostatic protection pad 31 and the second electrostatic protection pad 32 are symmetrical about the first symmetry line k. Specifically, the first electrostatic protection pad 31 and the second electrostatic protection pad 32 may be strip-shaped, and the extension line of the outer edge of the first electrostatic protection pad 31 along the long side direction may not overlap with the extension line of the outer edge of the second electrostatic protection pad 31 along the long side direction.

[0060] In a possible implementation, the outer contour of the array substrate is a circle, an ellipse, a hexagon or an octagon, or a polygon with other numbers of sides, such as a triangle, a quadrilateral, a pentagon, a heptagon, a nonagon, a decagon, a dodecagon, a hexadecagon or an octagon.

[0061] In one possible implementation, see Figure 3 or Figure 4A As shown, the first electrostatic protection pad 31 and the second electrostatic protection pad 32 are distributed in an eight-shaped shape.

[0062] Based on the same inventive concept, the present disclosure also provides a display panel, see Figure 5 As shown, it includes an array substrate 4 provided in an embodiment of the present disclosure, and also includes: an opposing substrate 5 arranged opposite to the array substrate 4, a control chip 10 arranged in the control chip area 1, and a circuit board 20 arranged in the binding area 2. Specifically, the control chip 10 can be a source control chip (Source IC) to provide data signals for the display panel.

[0063] In one possible implementation, see Figure 6 As shown, Figure 6 Can be Figure 5 In the cross-sectional schematic diagram of the dotted line at the first electrostatic protection pad 31, the display panel also includes: a conductive colloid 33; wherein the conductive colloid 33 partially covers the portion around the counter substrate 5, and partially extends along the side of the counter substrate 4 to the first electrostatic protection pad 31 and / or the second electrostatic protection pad 32 of the array substrate 4. In this way, the static electricity generated by the counter substrate 5 can be guided to the first electrostatic protection pad 31 and / or the second electrostatic protection pad 32 of the array substrate through the conductive colloid 33, and further guided to the ground terminal of the circuit board 2 through the first electrostatic protection pad 31 and / or the second electrostatic protection pad 32, so as to achieve static electricity release. Specifically, the conductive colloid 33 may include: silver glue.

[0064] In one possible implementation, see Figure 6As shown, the counter substrate 5 is further provided with a conductive layer 6 on the side away from the array substrate 4, and the conductive colloid 33 is overlapped with the conductive layer 6 of the counter substrate 5. Specifically, the conductive layer 6 can be a transparent conductive layer, and specifically, the material of the conductive layer 6 can include: indium tin oxide and / or aluminum-doped zinc oxide (AZO). Optionally, the conductive layer can be provided as a whole layer, and a polarizer 7 is provided on the side of the conductive layer away from the array substrate 4. It should be noted that in this case, the polarizer 7 can optionally have a conductive function. When the polarizer 7 has a conductive function, the conductive colloid can be directly overlapped on the polarization (that is, overlapped on the side of the polarizer away from the base substrate to achieve the effect of conducting static electricity). In this case, the conductive layer 6 can be omitted to reduce the thickness of the display device.

[0065] It should be noted that if Figure 6 As shown, the first electrostatic protection pad 31 and / or the second electrostatic protection pad 32 can be a silver glue point contact for electrically connecting to the conductive layer 6 on one side of the opposing substrate 5 to achieve the purpose of conducting away the static electricity on one side of the opposing substrate 5; in another possible embodiment, it can also be a conductive structure arranged on one side of the array substrate 4 (not used for connecting to the silver glue point) to electrically connect the ground traces on both sides of the control chip 10.

[0066] In one possible implementation, see Figure 3 , Figure 4A , Figure 5 and Figure 6 As shown, the control chip area 1 , the binding area 2 , and the grounding wiring may all be located on the array substrate 4 .

[0067] In one possible implementation, see Figure 3 , Figure 4A and Figure 5 As shown, the array substrate 4 includes a first area BB1 overlapping with the opposite substrate 5, and a second area BB2 extending from the first area BB1; the control chip area 1, the binding area 2, and the grounding trace are all located in the second area BB2 of the array substrate. Figure 3 , Figure 4A and Figure 5 As shown, C1 can be the projection line of the outer edge of the opposing substrate 5 on the array substrate 4, C2 can be the outer edge of the array substrate 4, and the area between C1 and C2 can be the second area BB2, that is, the area of ​​the array substrate 4 protruding relative to the opposing substrate 5 is used as the second area BB2.

[0068] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0069] The beneficial effects of the embodiments of the present disclosure are as follows: In the embodiments of the present disclosure, for the first electrostatic protection pad 31 on the different side of the binding area 2, the first grounding wiring portion E1E4 surrounds the display area AA and is electrically connected to the terminal (i.e., the second terminal) included in the binding area 2 on the other side of the control chip area 1, so that when the circuit board 20 on the side where the first electrostatic protection pad 31 is located is removed, the first electrostatic protection pad 31 on this side can still be connected to the circuit board 20 on the other side of the control chip area 1, and the first electrostatic protection pad 31 on this side can still play an electrostatic protection effect, without weakening the effect of the first electrostatic protection pad 31 on improving the shielding effect of electrostatics, thereby improving the problem of the array substrate in the prior art being easily damaged by static electricity when the binding area on one side is removed.

[0070] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, including the above display panel provided by the embodiment of the present disclosure. The implementation of the display device can refer to the embodiment of the above display panel, and the repeated parts will not be repeated.

[0071] In specific implementation, in the embodiments of the present disclosure, the display device may be a wearable product in a circular, elliptical, hexagonal or octagonal shape. Other essential components of the display device should be understood by those skilled in the art, and will not be described in detail here, nor should they be used as limitations to the present disclosure.

[0072] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0073] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, comprising a display area and a non-display area located outside the display area, wherein: The array substrate comprises: A control chip area, located in the non-display area and used for being electrically connected to the control chip; A binding area, located in the non-display area and on one side of the control chip area, and used for being electrically connected to a circuit board; A first electrostatic protection pad is located in the non-display area and is located on a different side of the control chip area from the binding area; The grounding trace is located in the non-display area and includes: a first grounding trace portion; wherein one end of the first electrostatic protection pad surrounds the display area through the first grounding trace portion and is electrically connected to a terminal included in the binding area.

2. The array substrate according to claim 1, wherein: The grounding trace further includes: a second grounding trace portion; the other end of the first electrostatic protection pad is electrically connected to a terminal included in the control chip area through the second grounding trace portion.

3. The array substrate according to claim 1 or 2, wherein: The array substrate further includes: a second electrostatic protection pad; the grounding trace further includes: a third grounding trace portion; The second electrostatic protection pad is implemented by the third ground wiring portion and the terminal included in the binding area.

4. The array substrate according to any one of claims 1 to 3, wherein: The grounding trace further includes: a fourth grounding trace portion; the control chip area and the binding area are electrically connected via the fourth grounding trace portion.

5. The array substrate according to any one of claims 1 to 4, wherein: The array substrate also includes: a fifth grounding wiring portion; the fifth grounding wiring portion is located on a side of the control chip area away from the display area, and one end of the fifth grounding wiring portion is electrically connected to a terminal included at one end of the control chip area, and the other end is electrically connected to a terminal included at the other end of the control chip area.

6. The array substrate according to claim 5, wherein: The length of the fifth ground wiring portion is substantially equal to the length of the control chip region.

7. The array substrate according to claim 5, wherein: At least a portion of at least one of the first ground routing portion, the second ground routing portion, the third ground routing portion, the fourth ground routing portion, and the fifth ground routing portion is arc-shaped.

8. The array substrate according to any one of claims 1 to 6, wherein: The control chip area extends along a first direction and has a first symmetry axis perpendicular to the first direction; The first electrostatic protection pad and the second electrostatic protection pad are symmetrical about the first symmetrical line.

9. The array substrate according to any one of claims 1 to 8, wherein: The outer contour of the array substrate is circular, elliptical, hexagonal or octagonal.

10. The array substrate according to claim 9, wherein: The first electrostatic protection pad and the second electrostatic protection pad are distributed in an eight-shaped shape.

11. A display panel, wherein: It comprises the array substrate as described in any one of claims 1 to 10, and further comprises: an opposite substrate arranged opposite to the array substrate, a control chip arranged in the control chip area, and a circuit board arranged in the binding area.

12. The display panel according to claim 11, wherein: The display panel further includes: a conductive colloid; the conductive colloid partially covers a portion around the opposite substrate, and partially extends along a side edge of the opposite substrate to the first electrostatic protection pad and / or the second electrostatic protection pad of the array substrate.

13. The array substrate according to claim 8, wherein: The opposite substrate is further provided with a conductive layer on a side away from the array substrate; and the conductive colloid is overlapped with the conductive layer.

14. The array substrate according to claim 11, wherein: The array substrate comprises a first region overlapping with the opposite substrate, and a second region extending from the first region; The control chip area, the binding area, and the grounding trace are all located in the second area of ​​the array substrate.

15. A display device, wherein: Comprising a display panel as described in any one of claims 11-14.

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