Display device

Abstract

A display device is provided. A display device according to an embodiment includes: a display area including a first display area and a sensor area; a first pixel positioned in the first display area and including a first pixel circuit and a first light emitting element connected to the first pixel circuit; and a second pixel positioned in the sensor area and including a second pixel circuit and a second light emitting element connected to the second pixel circuit, the structures of the first pixel circuit and the second pixel circuit being different. The second pixel circuit includes a switching element connected between a power supply line and a second light emitting element and turned on by an off control signal, an off voltage of the second light emitting element being applied to the power supply line.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0087729 filed on July 6, 2023, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosed embodiments relate to a display device. Background Art

[0003] As multimedia technology develops, the importance of display devices has been steadily increasing. Therefore, various types of display devices such as liquid crystal display devices, organic light emitting display devices, etc. have been developed.

[0004] The display device may include various sensors to provide various functions. For example, the display device may include an infrared proximity sensor. Summary of the invention

[0005] A disclosed aspect provides a display device capable of preventing unintentional emission from pixels at a position corresponding to a sensor area due to operation of a sensor.

[0006] However, aspects of the disclosure are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0007] According to the disclosed aspects, a display device may include: a display area including a first display area and a sensor area; a first pixel positioned in the first display area and including a first pixel circuit and a first light-emitting element connected to the first pixel circuit; and a second pixel positioned in the sensor area and including a second pixel circuit and a second light-emitting element connected to the second pixel circuit, wherein the first pixel circuit and the second pixel circuit have different structures. The second pixel circuit may include a switch element, the switch element is connected between a power line and a second light-emitting element, and is turned on by a cut-off control signal, and a cut-off voltage of the second light-emitting element is applied to the power line.

[0008] In an embodiment, the display device may further include: a driving circuit that supplies a turn-off control signal to the second pixel.

[0009] In an embodiment, the display device may further include: a signal line connected between the driving circuit and the second pixel, and transmitting a cutoff control signal from the driving circuit to the second pixel. The switching element may include: a gate electrode connected to the signal line; a first electrode connected to an electrode of the second light-emitting element; and a second electrode connected to a power line.

[0010] In an embodiment, the display device may further include: a substrate including a main area and a sub-area, the main area including a display area in which pixels including a first pixel and a second pixel are arranged, the sub-area being positioned at one side of the main area in the first direction; and a data driving circuit being disposed in the sub-area and supplying a data signal to the pixel. The display area may include: a central area positioned at the center of the display area in a second direction intersecting the first direction and aligned with the sub-area in the first direction, and in which a first data line and some pixels connected to the first data line are arranged in the central area; and an edge area positioned at least one side of the central area in the second direction, and in which a second data line and other pixels connected to the second data line are arranged in the edge area.

[0011] In an embodiment, the display device may further include: a connection line disposed on the substrate and connected between the data driving circuit and the second data line. Each of the connection lines may include: a first connection line connected between the data driving circuit and one of the second data lines and extending in the first direction in the display area; and a second connection line connected between the first connection line and one of the second data lines and extending in the second direction in the display area.

[0012] In an embodiment, the display device may further include: a circuit layer disposed on the substrate and including a pixel circuit of a pixel including a first pixel circuit and a second pixel circuit, a first data line, a second data line, a power line, and a signal line.

[0013] In an embodiment, the circuit layer may further include: a semiconductor layer, including an active layer of the switching element; a first gate conductive layer, including a gate electrode of the switching element; a first source-drain conductive layer, including a second connecting line; and a second source-drain conductive layer, including the first connecting line.

[0014] In an embodiment, the power supply line may be connected to the second electrode of the switching element in the sensor region.

[0015] In an embodiment, the signal line may be connected to the gate electrode of the switching element in the sensor region.

[0016] In an embodiment, the display device may further include: a light emitting element layer provided on the circuit layer and including light emitting elements of the pixel including a first light emitting element and a second light emitting element.

[0017] In an embodiment, the display device may further include: a first pixel power line connected to the first pixel circuit and the second pixel circuit and supplied with a first pixel power voltage; and a second pixel power line connected to the first light-emitting element and the second light-emitting element and supplied with a second pixel power voltage having a lower potential than the first pixel power voltage.

[0018] In an embodiment, the switching element may be connected to the second pixel power supply line.

[0019] In an embodiment, the power line that may be connected to the switching element is separated from the first pixel power line and the second pixel power line.

[0020] In an embodiment, a power supply line may be connected between the driving circuit and the second pixel, and the driving circuit may supply a turn-off voltage of the second light emitting element to the power supply line.

[0021] In an embodiment, the display device may further include: a sensor provided in the sensor region, and the driving circuit may supply a turn-off control signal to the second pixel during a period in which the sensor operates.

[0022] In an embodiment, the sensor may emit infrared light that passes through the area of ​​the sensor where the second pixel is located.

[0023] In an embodiment, the sensor may be an infrared proximity sensor.

[0024] In an embodiment, each of the first pixel circuit and the second pixel circuit may include a pixel transistor and a capacitor that control a driving current in response to a scan signal and a data signal supplied to the first pixel or the second pixel, and in addition to the pixel transistor and the capacitor, the second pixel circuit may also include a switching element.

[0025] In an embodiment, the first display area may not overlap the sensor area in a plan view, and the switching element may be provided only in the second pixel.

[0026] In an embodiment, the second pixel may include a plurality of second pixels in the sensor area, and each of the plurality of second pixels may include a switching element connected between the power line and the second light emitting element and simultaneously turned on by a turn-off control signal.

[0027] The display device according to the embodiment may include a second pixel located in the sensor area. The second pixel may include a switching element, the switching element is turned on by a cut-off control signal, and the light-emitting element is connected to a power line to which a cut-off voltage of the light-emitting element is applied. According to the embodiment, by turning on the switching element by a cut-off control signal when the sensor is operating, the second pixel can be prevented from emitting light in an unexpected form. Therefore, the image quality problem of the display device that may be caused by the operation of the sensor can be prevented or improved.

[0028] In an embodiment, the non-display area of ​​the display device can be reduced by connecting the data line located in the edge area of ​​the display area to the data driving circuit via the connection line passing through the central area of ​​the display area. In addition, some of the dummy lines formed in the display area in a form corresponding to the connection line can be used as a part of the control signal line (e.g., the control signal line inside the display area) that transmits the cutoff control signal to the switching element of the second pixel. Therefore, the second pixel can be connected to the control signal line without forming an additional signal line in the display area.

[0029] However, the effects according to the disclosed embodiments are not limited to the above-mentioned effects, and various other effects are included therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the disclosure will become more apparent by describing in detail embodiments of the disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a perspective view showing a display device according to an embodiment;

[0032] Figure 2 It is shown Figure 1 A plan view of a display device;

[0033] Figure 3 is a schematic diagram of an equivalent circuit of a first pixel according to an embodiment;

[0034] Figure 4 is a schematic diagram of an equivalent circuit of a second pixel according to an embodiment;

[0035] Figure 5 is a schematic diagram of an equivalent circuit of a second pixel according to an embodiment;

[0036] Figure 6 is a graph showing a characteristic change of a pixel transistor according to an embodiment;

[0037] Figure 7 is a schematic cross-sectional view showing a display panel according to an embodiment;

[0038] Figure 8 is a plan view showing a display panel according to one embodiment;

[0039] Fig. 9 is a plan view showing a display panel according to one embodiment;

[0040] Fig.10 is a plan view schematically showing data lines, first dummy lines, and connection lines in a central area and an edge area according to one embodiment;

[0041] Fig.11is a plan view showing a ninth transistor of a second pixel according to an embodiment;

[0042] Fig.12 is a plan view showing a ninth transistor of a second pixel according to an embodiment;

[0043] Fig.13 is a plan view showing a ninth transistor of a second pixel according to an embodiment; and

[0044] Fig.14 is a plan view showing prevention of stains that may occur in a display area when a second pixel is turned off. DETAILED DESCRIPTION

[0045] The disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the disclosure are shown. However, the disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0046] When an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. In addition, when an element is referred to as being "in contact with" or "contacting" another element, etc., the element may be "in electrical contact with" or "in physical contact with" the other element; or "indirectly in contact with" or "directly in contact with" the other element.

[0047] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the disclosed teachings, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0048] The features of each of the various disclosed embodiments may be partially or completely combined with each other and may interact with each other technically differently, and the various embodiments may be implemented independently of each other or may be implemented together in relation to each other.

[0049] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B". In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or".

[0050] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an ideal or overly formal sense unless clearly defined in the specification.

[0051] Figure 1 is a perspective view showing a display device 10 according to one embodiment.

[0052] Reference Figure 1 The display device 10 may be a device for displaying a moving image or a still image. The display device 10 may be used as a display screen of various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs).

[0053] The display device 10 may be a light-emitting display device such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or a micro light-emitting display using a micro- or nano-light-emitting diode (LED). Hereinafter, an embodiment in which the display device 10 is an organic light-emitting display device is described, but the type of the display device 10 is not limited thereto.

[0054] In one embodiment, the display device 10 may be formed to be flat. For example, the display device 10 may be formed to be substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a thickness (e.g., a predetermined or selectable thickness (or height)) in the third direction DR3. In another embodiment, the display device 10 may include a curved surface in at least a portion including an edge region, etc. The display device 10 may be formed to be flexible so that it can be bent, curved, folded, or curled.

[0055] In one embodiment, the first direction DR1 may be a vertical direction, a column direction, or a perpendicular direction relative to the image display surface of the display device 10, and the second direction DR2 may be a direction intersecting the first direction DR1 (e.g., a width direction, a row direction, or a horizontal direction). The third direction DR3 may be a thickness direction or a height direction of the display device 10.

[0056] The display device 10 may include a display panel 100, a data driving circuit 200, a circuit board 300, and a driving circuit 310. The display device 10 may further include a sensor 400 located below the display panel 100 to overlap a portion of the display panel 100 (e.g., a portion of the display area DA) in a plan view.

[0057] The display panel 100 may include a main area MA and a sub area SBA positioned at one side of the main area MA. For example, the sub area SBA may be positioned at one side of the main area MA in the first direction DR1.

[0058] The main area MA may include a display area DA where pixels are arranged and a non-display area NA adjacent to the display area DA. The main area MA may also include a sensor area SA where the sensor 400 is provided or disposed. In one embodiment, the sensor area SA may be located inside the display area DA. For example, the sensor 400 may be disposed under the pixel to overlap with the pixel located in a portion of the display area DA in a plan view.

[0059] The display area DA may overlap with the sensor area SA, or may include the sensor area SA. For example, the display area DA may include a first display area DA1 and a second display area DA2, and the second display area DA2 may be an area corresponding to the sensor area SA of the display area DA. For example, the second display area DA2 may be a portion of the display area DA that includes the sensor area SA or overlaps with the sensor area SA. For example, the second display area DA2 and the sensor area SA may be substantially the same area. The first display area DA1 may be another portion of the display area DA (e.g., the remaining portion of the display area DA that does not include the sensor area SA or overlaps with the sensor area SA).

[0060] The display area DA may overlap with at least one sensor area SA, and at least one sensor 400 may be disposed in each of the sensor areas SA. By overlapping the display area DA with the sensor area SA (e.g., disposing the sensor area SA inside the display area DA), the non-display area NA may be reduced, and the display area DA may be expanded.

[0061] In one embodiment, the sensor 400 may be located under a pixel positioned in the second display area DA2 (e.g., the sensor area SA), and may emit infrared rays that pass through the second display area DA2 including at least a portion of the sensor area SA. For example, the sensor 400 may be an infrared proximity sensor that includes a light emitting element (e.g., an infrared light emitting diode) that emits infrared rays and a sensing element (e.g., an infrared receiving diode) that receives the infrared rays and outputs a corresponding electrical signal.

[0062] The non-display area NA may be located adjacent to the display area DA. For example, in a plan view, the non-display area NA may surround the display area DA. Wirings connected to pixels may be disposed in the non-display area NA.

[0063] In one embodiment, embedded circuits may be disposed in the non-display area NA. For example, embedded circuits including a scan driving circuit and the like may be disposed in the non-display area NA located on one side (eg, left or right) or both sides of the display area DA.

[0064] The sub-region SBA may protrude from one side of the main region MA in the first direction DR1. For example, the sub-region SBA may protrude from a lower end of the main region MA in the first direction DR1 and may have a narrower width than the main region MA in the second direction DR2.

[0065] In one embodiment, the data driving circuit 200 may be mounted in the sub-area SBA. The circuit board 300 may be disposed in a portion of the sub-area SBA (eg, a pad area located at one end in the first direction DR1).

[0066] In the sub-area SBA, wirings (or a portion of wirings) connected to pixels of the display area DA, the data driving circuit 200, and the circuit board 300 may be disposed. In describing the embodiments, the term "connection" may include electrical connection and / or physical connection.

[0067] The data driving circuit 200 may generate a data signal for driving a pixel corresponding to the image data. In one embodiment, the data driving circuit 200 may be implemented as an integrated circuit chip (IC) and mounted in the sub-area SBA. In another embodiment, the data driving circuit 200 may be disposed on the circuit board 300 in the sub-area SBA, or may be disposed on another circuit board connected to the display panel 100 through the circuit board 300.

[0068] The circuit board 300 may be disposed in a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad located at an end of the sub-area SBA, and may supply or transmit a power supply voltage and a driving signal for driving the display panel 100 to the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF), but is not limited thereto.

[0069] In one embodiment, the driving circuit 310 may be mounted on the circuit board 300. For example, the driving circuit 310 may be provided as an integrated circuit chip and mounted on the circuit board 300. In another embodiment, at least a portion of the driving circuit 310 may be mounted in the sub-area SBA together with the data driving circuit 200, or may be provided on another circuit board connected to the circuit board 300.

[0070] The driving circuit 310 may supply input image data (e.g., digital image data), a driving signal including a timing signal, and / or a driving voltage to the display panel 100 and the data driving circuit 200. For example, the driving circuit 310 may include a timing control circuit and / or a power management integrated circuit (PMIC).

[0071] In one embodiment, during a period in which the sensor 400 operates (eg, a sensing period in which the proximity sensor operates), the driving circuit 310 may provide a signal to pixels located in the second display area DA2 (eg, Figure 2 The pixels of the second display area DA2 supplied with the turn-off control signal may be turned off (eg, not emitted) corresponding to the turn-off control signal.

[0072] Figure 2 It is shown Figure 1 FIG. 1 is a plan view of a display device 10 . Figure 1 The display device 10 is shown unfolded and not bent. Figure 2 The display device 10 is shown to be bent in the sub-area SBA. For example, Figure 1 The sub-area SBA is shown to be developed in parallel with the main area MA. Figure 2A state in which the sub-region SBA is bent such that a portion of the sub-region SBA is below the main region MA is shown.

[0073] Reference Figure 1 and Figure 2 , the display area DA may include long sides in the first direction DR1 and short sides in the second direction DR2, and may be formed as a plane having an approximately rectangular shape in a plan view. Corner portions where the long sides and short sides of the display area DA intersect may be rounded or right-angled. The shape of the display area DA in a plan view is not limited to a rectangular shape, but may be formed in other polygonal shapes, a circular shape, an elliptical shape, etc.

[0074] The display area DA may occupy most of the main area MA. The display area DA may be disposed at the center of the main area MA.

[0075] The display area DA may include pixels PX. In one embodiment, the pixels PX may include first pixels PX1 located in the first display area DA1 and second pixels PX2 located in the second display area DA2 (eg, the sensor area SA).

[0076] The first pixel PX1 may have substantially the same or similar structure and / or configuration, and the second pixel PX2 may have substantially the same or similar structure. The first pixel PX1 and the second pixel PX2 may have different structures and / or configurations. For example, each of the second pixels PX2 may further include at least one switching element compared to each of the first pixels PX1.

[0077] The non-display area NA may be located at an edge of the main area MA. In one embodiment, the non-display area NA may be located outside the display area DA and may surround the display area DA in a plan view. The non-display area NA may contact the sub-area SBA. For example, the sub-area SBA may extend from one end of the non-display area NA in the first direction DR1.

[0078] At least a portion of the sub-area SBA may be formed to be flexible so that it can be bent, curved, folded, or curled. The sub-area SBA may be bent at a portion adjacent to the non-display area NA. Therefore, a portion of the sub-area SBA where the data driving circuit 200 is installed may be located below the main area MA.

[0079] The data driving circuit 200 may be connected to the pixels PX (eg, the first pixel PX1 and the second pixel PX2 of the display area DA). The data driving circuit 200 may supply corresponding driving signals (eg, data signals of the first pixel PX1 and the second pixel PX2) to the first pixel PX1 and the second pixel PX2.

[0080] Figure 3 is a schematic diagram of an equivalent circuit of a first pixel PX1 according to an embodiment.

[0081] exist Figure 3 , an embodiment in which a first pixel circuit PXC1 provided to a first pixel PX1 includes a first transistor T1 to an eighth transistor T8 will be described. In one embodiment, the scan line SL connected to the first pixel PX1 may include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fourth scan line SL4, and the power line PL connected to the first pixel PX1 may include a first pixel power line VDL, a second pixel power line VSL, a first initialization power line VIL1, a second initialization power line VIL2, and a bias power line VOBL. The first pixel PX1 may also be connected to an emission control line ECL. The configuration of the first pixel circuit PXC1 and the type and number of wirings connected to the first pixel circuit PXC1 may be variously changed according to the embodiment.

[0082] Apart from Figure 1 and Figure 2 In addition, refer to Figure 3 , each of the pixels PX (e.g., the first pixel PX1 and the second pixel PX2) may include a pixel circuit PXC and a light emitting element EL connected to the pixel circuit PXC. For example, each of the first pixels PX1 may include a first pixel circuit PXC1 (e.g., the pixel circuit PXC of the first pixel PX1) and a first light emitting element EL1 (e.g., the light emitting element EL of the first pixel PX1) connected to the first pixel circuit PXC1.

[0083] The first pixel circuit PXC1 may control the emission time point and brightness of the first light emitting element EL1 by controlling the driving current supplied to the first light emitting element EL1. For example, the first pixel circuit PXC1 may include a pixel transistor T and a capacitor Cst that control the driving current in response to at least one scan signal and a data signal supplied to the corresponding first pixel PX1. In one embodiment, the pixel transistor T of the first pixel circuit PXC1 may include a first transistor T1 to an eighth transistor T8.

[0084] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode connected to the first pixel power line VDL via a fifth transistor T5, and a second electrode connected to the light emitting element EL via a sixth transistor T6. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode. The first transistor T1 may control a driving current (e.g., a source-drain current of the first transistor T1) flowing between the first electrode and the second electrode according to a voltage applied to the gate electrode (e.g., a voltage of the first node N1 corresponding to a voltage of a data signal). For example, the first transistor T1 may be a driving transistor of the first pixel PX1.

[0085] The second transistor T2 may include a gate electrode connected to the first scan line SL1, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the first transistor T1. The second transistor T2 may be turned on by the first scan signal supplied to the first scan line SL1 to connect the first electrode of the first transistor T1 to the data line DL. When the second transistor T2 is turned on, the voltage of the data signal supplied to the data line DL may be applied to the first electrode of the first transistor T1.

[0086] The third transistor T3 may include a gate electrode connected to the second scan line SL2, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the gate electrode (or the first node N1) of the first transistor T1. The third transistor T3 may be turned on by the second scan signal supplied to the second scan line SL2 to connect the gate electrode of the first transistor T1 to the second electrode thereof. When the third transistor T3 is turned on, the first transistor T1 may be driven as a diode.

[0087] The fourth transistor T4 may include a gate electrode connected to the third scan line SL3, a first electrode connected to the gate electrode of the first transistor T1, and a second electrode connected to the first initialization power line VIL1. The fourth transistor T4 may be turned on by the third scan signal supplied to the third scan line SL3 to connect the gate electrode of the first transistor T1 to the first initialization power line VIL1. When the fourth transistor T4 is turned on, the first initialization voltage VINT1 (e.g., gate initialization voltage) of the first initialization power line VIL1 may be applied to the gate electrode of the first transistor T1.

[0088] The fifth transistor T5 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a first pixel power line VDL, and a second electrode connected to a first electrode of the first transistor T1. The fifth transistor T5 may be turned on by an emission control signal supplied to the emission control line ECL, and thus may connect the first electrode of the first transistor T1 to the first pixel power line VDL to which a first pixel power voltage ELVDD is applied. When the fifth transistor T5 is turned on, the first pixel power voltage ELVDD may be applied to the first electrode of the first transistor T1. In one embodiment, the first pixel power voltage ELVDD may be a high potential pixel driving voltage.

[0089] The sixth transistor T6 may include a gate electrode connected to an emission control line ECL, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the first light emitting element EL1. The sixth transistor T6 may be turned on by an emission control signal supplied to the emission control line ECL to connect the first transistor T1 to the first light emitting element EL1. In the case where all of the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current having an amplitude corresponding to the voltage of the gate electrode of the first transistor T1 may flow through the first light emitting element EL1.

[0090] The seventh transistor T7 may include a gate electrode connected to the fourth scan line SL4, a first electrode connected to the first electrode (e.g., an anode electrode) of the first light emitting element EL1, and a second electrode connected to the second initialization power line VIL2. The seventh transistor T7 may be turned on by the fourth scan signal supplied to the fourth scan line SL4 to connect the first electrode of the first light emitting element EL1 to the second initialization power line VIL2. The fourth scan signal and the first scan signal may be the same signal or different signals. When the seventh transistor T7 is turned on, the second initialization voltage VINT2 (e.g., an anode initialization voltage) of the second initialization power line VIL2 may be applied to the first electrode of the first light emitting element EL1.

[0091] The eighth transistor T8 may include a gate electrode connected to the fourth scan line SL4, a first electrode connected to the bias power line VOBL, and a second electrode connected to the first electrode of the first transistor T1. The eighth transistor T8 may be turned on by the fourth scan signal supplied to the fourth scan line SL4 to connect the first electrode of the first transistor T1 to the bias power line VOBL. In the case where the eighth transistor T8 is turned on, the bias voltage VOBS supplied to the bias power line VOBL may be applied to the first electrode of the first transistor T1. In one embodiment, the bias voltage VOBS may have a voltage level suitable for compensating for the hysteresis characteristic of the first transistor T1. When the eighth transistor T8 is turned on, the first electrode of the first transistor T1 may be initialized to the bias voltage VOBS.

[0092] The capacitor Cst may be connected between the gate electrode (or the first node N1) of the first transistor T1 and the first pixel power line VDL. The capacitor Cst may be charged with a voltage corresponding to a voltage of a data signal applied to the gate electrode of the first transistor T1.

[0093] The active layer (e.g., semiconductor pattern including the channel region) of each of the pixel transistors T (e.g., the first transistor T1 to the eighth transistor T8) may include one semiconductor material among polysilicon, amorphous silicon, and an oxide semiconductor. In one embodiment, some of the pixel transistors T and other pixel transistors T may be formed by transistors of different conductivity types. Some of the pixel transistors T and other pixel transistors T may include different types of semiconductor materials.

[0094] For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be formed by a P-type transistor (e.g., a P-type MOSFET) including an active layer formed of polysilicon, and the third transistor T3 and the fourth transistor T4 may be formed by an N-type transistor (e.g., an N-type MOSFET) including an active layer formed of an oxide semiconductor. In one embodiment, the transistor including an active layer formed of polysilicon and the transistor including an active layer formed of an oxide semiconductor may be formed in a circuit layer (e.g., Figure 7 The circuit layer 120 is arranged in different layers.

[0095] However, the disclosure is not limited thereto. For example, the pixel transistor T may be formed by transistors of the same conductivity type. For example, all of the first transistor T1 to the eighth transistor T8 may be formed by a P-type transistor (e.g., a P-type MOSFET) including an active layer formed of polysilicon. The type and / or construction structure of each of the pixel transistors T constituting the pixel circuit PXC may be changed differently according to the embodiment.

[0096] The first light emitting element EL1 may be connected between the first pixel circuit PXC1 and the second pixel power supply line VSL. The second pixel power supply voltage ELVSS may be applied to the second pixel power supply line VSL. In one embodiment, the second pixel power supply voltage ELVSS may be a low potential pixel driving voltage. The potential difference between the first pixel power supply voltage ELVDD and the second pixel power supply voltage ELVSS may be greater than or equal to the threshold voltage of the first light emitting element EL1 (or each of the light emitting elements EL). The first light emitting element EL1 may emit light corresponding to the driving current supplied from the first pixel circuit PXC1. For example, the first light emitting element EL1 may be the light source of the first pixel PX1.

[0097] In one embodiment, the first pixel PX1 may include a single first light emitting element EL1, but is not limited thereto. For example, the first pixel PX1 may include at least two first light emitting elements EL1.

[0098] The first light emitting element EL1 may be an organic light emitting diode, but is not limited thereto. For example, the first light emitting element EL1 may be an inorganic light emitting element, a quantum dot light emitting element, or other types of light emitting elements.

[0099] Figure 4 is a schematic diagram of an equivalent circuit of a second pixel PX2 according to an embodiment. Figure 5 is a schematic diagram of an equivalent circuit of a second pixel PX2 according to an embodiment. For example, Figure 4 and Figure 5 Different embodiments are shown with regard to the power supply line PL connected to the ninth transistor T9.

[0100] Apart from Figures 1 to 3 In addition, refer to Figure 4 and Figure 5 The second pixel PX2 may include a second pixel circuit PXC2 (eg, the pixel circuit PXC of the second pixel PX2 ) and a second light emitting element EL2 (eg, the light emitting element EL of the second pixel PX2 ) connected to the second pixel circuit PXC2 .

[0101] The second pixel circuit PXC2 may have a structure different from that of the first pixel circuit PXC1. For example, the second pixel circuit PXC2 may include a pixel transistor T (e.g., a first transistor T1 to an eighth transistor T8) and a capacitor Cst, the pixel transistor T controlling the driving current in response to at least one scan signal and a data signal supplied to the corresponding second pixel PX2, and the second pixel circuit PXC2 may also include a switching element SW (e.g., a ninth transistor T9) for preventing or blocking the emission of the second pixel PX2 during a period in which the sensor 400 operates. For example, the pixel transistor T of the second pixel circuit PXC2 may include a first transistor T1 to a ninth transistor T9.

[0102] Each of the second pixel circuits PXC2 may also be connected to a signal line to which a control signal for controlling the operation of the ninth transistor T9 is applied. For example, the second pixel circuit PXC2 may also be connected to a control signal line CSL to which a cutoff control signal for turning on the ninth transistor T9 is applied.

[0103] In one embodiment, the first pixel circuit PXC1 of the first pixel PX1 and the second pixel circuit PXC2 of the second pixel PX2 may differ in that the second pixel circuit PXC2 further includes a ninth transistor T9, and the remaining configurations may be substantially the same or similar to each other. For example, each of the first pixels PX1 located in the first display area DA1 not overlapping the sensor area SA may not include the ninth transistor T9, while each of the second pixels PX2 located in the second display area DA2 corresponding to the sensor area SA may include the ninth transistor T9. During the period in which the sensor 400 operates, the emission of the second pixels PX2 may be independently and / or individually controlled by using the ninth transistor T9.

[0104] A plurality of second pixels PX2 may be provided and / or disposed in the sensor area SA. The second pixels PX2 may include a power line PL (e.g., a second pixel power line VSL or a cut-off power line VOFL) and each of the switch elements SW connected between the corresponding second light emitting elements EL2 (e.g., each of the ninth transistors T9), the power line PL supplies a cut-off voltage of a specific level or range (hereinafter, referred to as "the cut-off voltage of the second light emitting element EL2"), which may prevent or block the emission of the second light emitting element EL2 when the cut-off voltage is applied to the first electrode of each of the second light emitting elements EL2. Each of the ninth transistors T9 may be turned on by a cut-off control signal supplied to the control signal line CSL (or the fifth scan line).

[0105] During the period of operation of the sensor 400, the emission of the second pixel PX2 can be independently and / or individually controlled by using the ninth transistor T9. For example, the drive circuit 310 can supply a cut-off control signal that turns on each of the ninth transistors T9 to the second pixel PX2 through the control signal line CSL during the period of operation of the sensor 400. In the case where the ninth transistor T9 of the second pixel PX2 is turned on, the cut-off voltage can be transmitted to the first electrode of the second light-emitting element EL2 of each of the second pixels PX2. Therefore, during the period of operation of the sensor 400, the second light-emitting element EL2 of the second pixel PX2 can be prevented from emitting light in an unexpected form by the cut-off control signal supplied to the second pixel PX2.

[0106] The first transistor T1 to the eighth transistor T8 of the second pixel circuit PXC2 may be elements corresponding to the first transistor T1 to the eighth transistor T8 of the first pixel circuit PXC1. For example, the first transistor T1 to the eighth transistor T8 of the second pixel circuit PXC2 and the first transistor T1 to the eighth transistor T8 of the first pixel circuit PXC1 may be substantially the same, respectively. Therefore, a redundant description of the first transistor T1 to the eighth transistor T8 of the second pixel circuit PXC2 will be omitted.

[0107] The ninth transistor T9 may be connected between the power line PL supplying the cut-off voltage of the second light emitting element EL2 and the second light emitting element EL2, and may be turned on by a cut-off control signal applied to a control signal line CSL (also referred to as a "signal line" or a "fifth scan line"). For example, the ninth transistor T9 may include a gate electrode connected to the control signal line CSL, a first electrode connected to a first electrode (e.g., an anode electrode) of the second light emitting element EL2, and a second electrode connected to the power line PL supplying the cut-off voltage of the second light emitting element EL2.

[0108] In one embodiment, the second electrode of the ninth transistor T9 may be connected to Figure 4 In another embodiment, the second electrode of the ninth transistor T9 may be connected to a separate power line PL (eg, Figure 5 The cut-off power line VOFL) shown in FIG.

[0109] The off power line VOFL may be a separate power line separated from the power lines PL commonly connected to the first pixel PX1 and the second pixel PX2 (e.g., the first pixel power lines VDL and the second pixel power lines VSL, the first initialization power lines VIL1 and the second initialization power lines VIL2, and the bias power line VOBL). The off voltage VOFF may be applied to the off power line VOFL.

[0110] The cut-off voltage VOFF may have a voltage level suitable for controlling the second light emitting element EL2 not to emit light. For example, the cut-off voltage VOFF may be a constant voltage (e.g., a DC voltage) having a voltage value substantially the same as or similar to the second pixel power supply voltage ELVSS. For example, the potential difference between the cut-off voltage VOFF and the second pixel power supply voltage ELVSS may be less than the threshold voltage of the second light emitting element EL2 (or each of the light emitting elements EL).

[0111] In one embodiment, the ninth transistor T9 may be formed of a P-type transistor (eg, a P-type MOSFET) including an active layer formed of polysilicon, but is not limited thereto. For example, the ninth transistor T9 may be formed of an N-type transistor (eg, an N-type MOSFET).

[0112] A first electrode of the second light emitting element EL2 may be connected to the second electrode of the sixth transistor T6, the first electrode of the seventh transistor T7, and the first electrode of the ninth transistor T9. A second electrode of the second light emitting element EL2 may be connected to the second pixel power line VSL.

[0113] The ninth transistor T9 may be turned on by the cut-off control signal supplied to the control signal line CSL, and may connect the first electrode of the second light emitting element EL2 to the second pixel power line VSL or the cut-off power line VOFL. When the ninth transistor T9 is turned on, the second pixel power voltage ELVSS or the cut-off voltage VOFF may be applied to the first electrode of the second light emitting element EL2. Therefore, during the period in which the cut-off control signal is supplied to the second pixel PX2, the second light emitting element EL2 may maintain a non-emission state.

[0114] In one embodiment, the second pixels PX2 disposed in the sensor area SA may have substantially the same or similar structure. For example, each of the second pixels PX2 may include a corresponding switching element SW (eg, a corresponding ninth transistor T9).

[0115] In one embodiment, the ninth transistor T9 of the (multiple) second pixel PX2 can be supplied with a cut-off control signal substantially at the same time during the period in which the sensor 400 operates, and can be turned on at the same time by the cut-off control signal. For example, the gate electrode of the ninth transistor T9 provided in the second pixel PX2 can be connected to the control signal line CSL in common, and the second electrode of the ninth transistor T9 can be connected to the second pixel power line VSL or the cut-off power line VOFL in common. Therefore, during the period in which the cut-off control signal of the gate-on voltage is supplied to the control signal line CSL, the (multiple) second pixel PX2 can simultaneously maintain a non-emitting state.

[0116] Figure 6is a graph showing the characteristic variation of the pixel transistor T according to one embodiment. For example, Figure 6 is a graph schematically showing changes in the drain current Id of a P-type transistor according to the gate-source voltage Vgs by infrared irradiation.

[0117] Apart from Figures 1 to 5 In addition, refer to Figure 6 , when the P-type transistor is irradiated with infrared light, the drain current Id may be changed according to the gate-source voltage Vgs. For example, the P-type transistor may exhibit a current characteristic in the shape of a first current curve I_REF when not irradiated with infrared light, and may exhibit a current characteristic in which the drain current Id increases in the shape of a second current curve I_IR when irradiated with infrared light.

[0118] Therefore, in the case where the second pixel PX2 is located in the second display area DA2 corresponding to the sensor area SA, when infrared rays are emitted according to the operation of the sensor 400, the characteristics of the P-type transistors (e.g., the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and / or the ninth transistor T9) included in the second pixel PX2 may be changed. Therefore, during the period in which the sensor 400 operates, the second pixel PX2 may emit light with unexpected brightness, which may be visually recognized as a screen defect such as stain or flicker in the display area DA.

[0119] However, in an embodiment, during a period in which the sensor 400 operates (e.g., a sensing period in which the sensor 400 operates and emits infrared rays in a call or the like), a cutoff control signal may be supplied from the driving circuit 310 to the second pixel PX2 so that the ninth transistor T9 of the second pixel PX2 may be turned on. Therefore, the second pixel PX2 may be controlled not to emit light in an abnormal manner during the period in which the sensor 400 operates.

[0120] In an embodiment, the second pixel PX2 can be turned off (or not emitted) separately from the operation of the first pixel PX1 by using a cutoff control signal. Therefore, only the second pixel PX2 in the second display area DA2 can be selectively turned off as needed during the period of operation of the sensor 400, etc., and a desired image can be displayed by the first pixel PX1 in the first display area DA1. Since the emission of the second pixel PX2 can be controlled individually without simultaneously controlling the pixels PX of each horizontal line, the emission of the pixels PX located in the display area DA can be more locally controlled without forming a separate scan driver, etc. Therefore, the display device 10 can be easily controlled in more forms, and user convenience can be enhanced.

[0121] Figure 7is a schematic cross-sectional view showing a display panel 100 according to an embodiment. For example, Figure 7 A cross section of a portion of the display area DA corresponding to a pixel area PXA where one pixel PX is located is schematically shown.

[0122] Apart from Figures 1 to 6 In addition, refer to Figure 7 The display panel 100 may include a substrate 110, a circuit layer 120 disposed on the substrate 110, a light emitting element layer 130, and an encapsulation layer 140. The circuit layer 120, the light emitting element layer 130, and the encapsulation layer 140 may be sequentially arranged or stacked on the substrate 110 in the third direction DR3.

[0123] The substrate 110 may be a base member for forming the display panel 100, and may include a main area MA including a display area DA and a non-display area NA, and a sub-area SBA located at one side of the main area MA. The substrate 110 may be made of a material having a flexible property capable of bending, folding, curling, etc. The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide.

[0124] The circuit layer 120 may include pixel circuits PXC and wirings, and the pixel circuits PXC include first pixel circuits PXC1 and second pixel circuits PXC2. For example, the circuit layer 120 may include circuit elements (e.g., pixel transistors T and capacitors Cst) constituting the pixel circuits PXC (e.g., first pixel circuits PXC1 or second pixel circuits PXC2) of each of the pixels PX and wirings (e.g., power lines PL, scan lines SL, emission control lines ECL, data lines DL, and various power lines and signal lines including at least one control signal line CSL) connected to the pixels PX. In one embodiment, the circuit layer 120 may be completely formed on the surface of the substrate 110 including the main area MA and the sub-area SBA.

[0125] Among the elements that may be provided on the circuit layer 120, Figure 7 A first thin film transistor TFT1 (also referred to as a "first pixel transistor"), a second thin film transistor TFT2 (also referred to as a "second pixel transistor"), and a capacitor Cst are shown in the pixel region PXA of each of the pixels PX. In one embodiment, the first thin film transistor TFT1 may be a first type transistor (e.g., a P-type transistor) including a first semiconductor material (e.g., polysilicon) among the pixel transistors T constituting each of the pixel circuits PXC. For example, the first thin film transistor TFT1 may be one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9. Figure 7A transistor (eg, a first light emitting element EL1 or a second light emitting element EL2) among the first type transistors is shown connected to the light emitting element EL (eg, the first light emitting element EL1 or the second light emitting element EL2) through at least one connection electrode CNE (eg, the first connection electrode CNE1 and the second connection electrode CNE2). Figures 3 to 5 The sixth transistor T6 of the pixel transistor T2 is used as the first thin film transistor TFT1. In one embodiment, the second thin film transistor TFT2 may be a second type transistor (e.g., an N-type transistor) including a second semiconductor material (e.g., an oxide semiconductor) among the pixel transistors T. For example, the second thin film transistor TFT2 may be one of the third transistor T3 and the fourth transistor T4.

[0126] The cross section of the pixel PX may be variously changed according to the type and / or structure of each of the pixels PX and the display panel 100 including the pixel PX. For example, the positions and formation order of the first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may vary according to embodiments.

[0127] The circuit layer 120 may include a semiconductor layer for forming circuit elements, wirings, etc., a conductive layer, and an insulating layer disposed between and / or around the semiconductor layer and the conductive layer. For example, the circuit layer 120 may include a first semiconductor layer SCL1 (e.g., a polycrystalline silicon semiconductor layer), a first insulating layer 123 (e.g., a first gate insulating layer), a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 124 (e.g., a second gate insulating layer), a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 125 (e.g., a first interlayer insulating layer), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126 (e.g., a third gate insulating layer), a third conductive layer CDL3 (e.g., a third gate conductive layer), a fifth insulating layer 127 (e.g., a second interlayer insulating layer), a fourth conductive layer CDL4 (e.g., a first source-drain conductive layer), a sixth insulating layer 128 (e.g., a first via layer or a first planarizing layer), a fifth conductive layer CDL5 (e.g., a second source-drain conductive layer) and a seventh insulating layer 129 (e.g., a second via layer or a second planarizing layer). In one embodiment, the circuit layer 120 may further include a lower conductive layer BCDL disposed between the substrate 110 and the first semiconductor layer SCL1 , a barrier layer 121 disposed between the substrate 110 and the lower conductive layer BCDL, and a buffer layer 122 disposed between the lower conductive layer BCDL and the first semiconductor layer SCL1 .

[0128] The barrier layer 121 may be disposed on the substrate 110. The barrier layer 121 may protect the elements disposed on the circuit layer 120 and the light emitting element layer 130 from moisture penetrating through the substrate 110 (which may be susceptible to moisture penetration). The barrier layer 121 may include at least one inorganic layer containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). The material of the barrier layer 121 may be variously changed according to the embodiment.

[0129] The lower conductive layer BCDL may be disposed on the barrier layer 121. The lower conductive layer BCDL may include a lower metal layer BML and / or at least one wiring (or a portion of at least one wiring) overlapping with an active layer (e.g., a first active layer ACT1 and / or a second active layer ACT2) of at least one pixel transistor T in a plan view. Figure 7 The lower metal layer BML is shown to be disposed entirely in the pixel region PXA, but the disclosure is not limited thereto. For example, the lower metal layer BML may be patterned in an appropriate size and / or shape as required and positioned only in a portion of the pixel region PXA. Figures 3 to 5 In one embodiment, the lower metal layer BML may also be used as a light blocking pattern and / or a back gate electrode of at least one pixel transistor T, etc.

[0130] The buffer layer 122 may be disposed on the lower conductive layer BCDL to cover the lower conductive layer BCDL. The buffer layer 122 may include at least one inorganic layer including an inorganic insulating material.

[0131] The first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may be disposed on a surface of the substrate 110 on which the buffer layer 122 is disposed. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2. In one embodiment, the second thin film transistor TFT2 may further include a back gate electrode BG. The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2.

[0132] For example, the first semiconductor layer SCL1 may be disposed on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first thin film transistor TFT1. For example, the first semiconductor layer SCL1 may include a first active layer ACT1 corresponding to each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9.

[0133] The first active layer ACT1 may be disposed in the first semiconductor layer SCL1 and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions formed to have conductivity by doping ions or impurities into a semiconductor used to form the first active layer ACT1. In one embodiment, the first source region S1 may be a source electrode of the first thin film transistor TFT1. In another embodiment, the first thin film transistor TFT1 may include a separate source electrode connected to the first source region S1. In one embodiment, the first drain region D1 may be a drain electrode of the first thin film transistor TFT1. In another embodiment, the first thin film transistor TFT1 may include a separate drain electrode connected to the first drain region D1.

[0134] The first insulating layer 123 may be disposed on the first semiconductor layer SCL1. The first insulating layer 123 may cover the first semiconductor layer SCL1.

[0135] The first conductive layer CDL1 may be disposed on the first insulating layer 123. The first conductive layer CDL1 may include a first gate electrode G1 of the first thin film transistor TFT1. The first gate electrode G1 may be disposed on the first active layer ACT1 to overlap with a portion of the first active layer ACT1 (e.g., the first channel area CHA1) in a plan view. In one embodiment, the first conductive layer CDL1 may further include at least one wiring (or a portion of at least one wiring), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode. For example, the first conductive layer CDL1 may further include a first capacitor electrode CAE1 of a capacitor Cst.

[0136] In one embodiment, the first capacitor electrode CAE1 may be formed integrally with the gate electrode of at least one first thin film transistor TFT1. Figures 3 to 5 For example, the first capacitor electrode CAE1 and the gate electrode of the first transistor T1 may be formed as one conductive pattern, and the second capacitor electrode CAE2 may be disposed to overlap the conductive pattern in a plan view.

[0137] The second insulating layer 124 may be disposed on the first conductive layer CDL1. The second insulating layer 124 may cover the first conductive layer CDL1.

[0138] The second conductive layer CDL2 may be disposed on the second insulating layer 124. The second conductive layer CDL2 may include an electrode of the capacitor Cst (e.g., the second capacitor electrode CAE2). In one embodiment, the second conductive layer CDL2 may also include at least one electrode, a wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the second conductive layer CDL2 may also include a back gate electrode BG connected to the second gate electrode G2 of the second thin film transistor TFT2.

[0139] The third insulating layer 125 may be disposed on the second conductive layer CDL2. The third insulating layer 125 may cover the second conductive layer CDL2.

[0140] The second semiconductor layer SCL2 may be disposed on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second thin film transistor TFT2. For example, the second semiconductor layer SCL2 may include a second active layer ACT2 corresponding to each of the third transistor T3 and the fourth transistor T4.

[0141] The second active layer ACT2 may be disposed in the second semiconductor layer SCL2 and may include a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0142] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 may be disposed on one side of the second channel region CHA2, and the second drain region D2 may be disposed on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be conductive regions formed by doping ions or impurities into a semiconductor used to form the second active layer ACT2. In one embodiment, the second source region S2 may be a source electrode of the second thin film transistor TFT2. In another embodiment, the second thin film transistor TFT2 may include a separate source electrode connected to the second source region S2. In one embodiment, the second drain region D2 may be a drain electrode of the second thin film transistor TFT2. In another embodiment, the second thin film transistor TFT2 may include a separate drain electrode connected to the second drain region D2.

[0143] The fourth insulating layer 126 may be disposed on the second semiconductor layer SCL2. The fourth insulating layer 126 may cover the second semiconductor layer SCL2.

[0144] The third conductive layer CDL3 may be disposed on the fourth insulating layer 126. The third conductive layer CDL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may be disposed on the second active layer ACT2 to overlap with a portion of the second active layer ACT2 (e.g., the second channel area CHA2) in a plan view. In one embodiment, the third conductive layer CDL3 may further include at least one wiring (or a portion of at least one wiring), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0145] In one embodiment, each of the electrodes, conductive patterns, and wirings disposed in the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may include a conductive material (e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), etc., alloys thereof, or other conductive materials), and each may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and wirings disposed in the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may include molybdenum (Mo) or another metal. At least two conductive layers among the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may include the same material or may include different materials. The material of each of the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 is not limited and may be changed differently according to the embodiment.

[0146] The fifth insulating layer 127 may be disposed on the third conductive layer CDL3. The fifth insulating layer 127 may cover the third conductive layer CDL3.

[0147] In one embodiment, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be an inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material), and each may have a single-layer or multi-layer structure. At least two insulating layers among the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may include the same material or may include different materials. The material of each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be changed differently according to the embodiment.

[0148] The fourth conductive layer CDL4 may be disposed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a first connection electrode CNE1 (or a drain electrode of the first thin film transistor TFT1), a first bridge electrode BE1 (or a source electrode of the second thin film transistor TFT2), and a second bridge electrode BE2 (or a drain electrode of the second thin film transistor TFT2). The first connection electrode CNE1 may be disposed in the fourth conductive layer CDL4 and may be connected to the first drain region D1 of the first active layer ACT1 through a contact hole CH (e.g., a first contact hole CH1) penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The first bridge electrode BE1 may be disposed in the fourth conductive layer CDL4 and may be connected to the second source region S2 of the second active layer ACT2 through a contact hole CH (e.g., a second contact hole CH2) penetrating the fourth insulating layer 126 and the fifth insulating layer 127. The second bridging electrode BE2 may be connected to the second drain region D2 of the second active layer ACT2 through a contact hole CH (e.g., a third contact hole CH3) penetrating the fourth insulating layer 126 and the fifth insulating layer 127. In one embodiment, the fourth conductive layer CDL4 may further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridging pattern). For example, the fourth conductive layer CDL4 may include a portion of a power line PL (e.g., a first pixel power line VDL and / or a second pixel power line VSL) disposed inside and / or outside the display area DA.

[0149] The sixth insulating layer 128 may be disposed on the fourth conductive layer CDL4. The sixth insulating layer 128 may cover the fourth conductive layer CDL4.

[0150] The fifth conductive layer CDL5 may be disposed on the sixth insulating layer 128. The fifth conductive layer CDL5 may include a second connection electrode CNE2. The second connection electrode CNE2 may be disposed in the fifth conductive layer CDL5 and may be connected to the first connection electrode CNE1 through a contact hole CH (e.g., a fourth contact hole CH4 (or a first via hole)) penetrating the sixth insulating layer 128. In one embodiment, the fifth conductive layer CDL5 may further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the fifth conductive layer CDL5 may include a portion of a power line PL (e.g., a first pixel power line VDL and / or a second pixel power line VSL) disposed inside and / or outside the display area DA.

[0151] In one embodiment, each of the electrodes, conductive patterns, and wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include a conductive material (e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), etc., alloys thereof, or other conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be formed by a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include the same material or may include different materials. The material of each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be changed differently according to the embodiment.

[0152] The seventh insulating layer 129 may be disposed on the fifth conductive layer CDL5. The seventh insulating layer 129 may cover the fifth conductive layer CDL5.

[0153] In one embodiment, the sixth insulating layer 128 and the seventh insulating layer 129 may be organic insulating layers including an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.) to planarize the circuit layer 120, and each may have a single-layer or multi-layer structure. The sixth insulating layer 128 and the seventh insulating layer 129 may include the same material or may include different materials. The material of each of the sixth insulating layer 128 and the seventh insulating layer 129 may be changed differently according to the embodiment.

[0154] The light emitting element layer 130 may be disposed on the circuit layer 120 and may be located in the display area DA. For example, the light emitting element layer 130 may be disposed on the circuit layer 120 in the display area DA.

[0155] The light emitting element layer 130 may include the light emitting elements EL of the pixel PX including the first light emitting element EL1 and the second light emitting element EL2. For example, the light emitting element layer 130 may include a pixel defining layer 131 that divides the emission area EA of the pixel PX and each light emitting element EL located in each emission area EA. In one embodiment, the light emitting element layer 130 may further include a spacer 132 disposed on a portion of the pixel defining layer 131.

[0156] Each of the light emitting elements EL may include a first electrode ET1 (e.g., an anode electrode) and a light emitting layer EML and a second electrode ET2 (e.g., a cathode electrode) sequentially disposed on the first electrode ET1, and the first electrode ET1 (e.g., an anode electrode) is connected to at least one pixel transistor T (e.g., a first thin film transistor TFT1) included in the corresponding pixel PX through at least one connection electrode CNE. In one embodiment, the light emitting element EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) disposed between the first electrode ET1 and the light emitting layer EML and a second intermediate layer (e.g., an electron layer including an electron transport layer) disposed between the light emitting layer EML and the second electrode ET2.

[0157] The first electrode ET1 of the light emitting element EL may include a conductive material and may be disposed on the circuit layer 120. For example, the first electrode ET1 may be disposed on the seventh insulating layer 129 to correspond to each emission area EA. The first electrode ET1 may be connected to the second connection electrode CNE2 through a contact hole CH (e.g., a fifth contact hole CH5 (or a second via hole)) penetrating the seventh insulating layer 129.

[0158] In one embodiment, the first electrode ET1 may include a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure including molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a single-layer structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni) (e.g., ITO / Mg, ITO / MgF 2 , ITO / Ag and ITO / Ag / ITO).

[0159] The light-emitting layer EML of the light-emitting element EL may include a polymer material or a low-molecular material. The light emitted from the light-emitting layer EML may contribute to image display. In one embodiment, the light-emitting layer EML may be provided for each pixel PX, and the light-emitting layer EML of each pixel PX may emit visible light of a color corresponding to the corresponding pixel PX. In another embodiment, the light-emitting layer EML may be a common layer shared by pixels PX of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light expected to be emitted from each pixel PX may be arranged in the emission area EA of at least some of the pixels PX.

[0160] The second electrode ET2 of the light emitting element EL may include a conductive material and may be connected to a second pixel power supply line VSL. In one embodiment, the second electrode ET2 may be a common layer formed across the entire display area DA to cover the light emitting layer EML and the pixel defining layer 131. In one embodiment, the second electrode ET2 may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). In the case where the second electrode ET2 is made of a semi-transmissive conductive material, an improvement in light output efficiency due to the microcavity effect can be expected.

[0161] The pixel defining layer 131 may have an opening corresponding to each of the emission areas EA and may surround the emission area EA in a plan view. For example, the pixel defining layer 131 may be formed to cover the edge of the first electrode ET1 of the light emitting element EL and may include an opening that exposes the remaining portion of the first electrode ET1. The region where the exposed first electrode ET1 and the light emitting layer EML overlap (or a region including the region) may be defined as the emission area EA of each pixel PX.

[0162] In one embodiment, the pixel defining layer 131 may include at least one organic layer including an organic insulating material. For example, the pixel defining layer 131 may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), etc.

[0163] The spacer 132 may be disposed on a portion of the pixel defining layer 131. The spacer 132 may include at least one organic layer containing an organic insulating material. The spacer 132 and the pixel defining layer 131 may include the same material or may include different materials. In one embodiment, the pixel defining layer 131 and the spacer 132 may be sequentially formed by separate mask processes. In another embodiment, the pixel defining layer 131 and the spacer 132 may be simultaneously formed using a halftone mask, and the pixel defining layer 131 and the spacer 132 may be a single insulating layer integral with each other. The organic insulating material constituting the spacer 132 is not particularly limited and may be changed differently according to the embodiment.

[0164] The encapsulation layer 140 may be disposed on the light emitting element layer 130 in the main area MA. For example, the encapsulation layer 140 may be disposed in the display area DA and the non-display area NA to cover the light emitting element layer 130. The encapsulation layer 140 may block oxygen or moisture from penetrating into the light emitting element layer 130, and may reduce the optical and / or physical effects on the circuit layer 120 and the light emitting element layer 130.

[0165] In one embodiment, the encapsulation layer 140 may include a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143 sequentially disposed on the light emitting element layer 130. The first and second inorganic encapsulation layers 141 and 143 may include inorganic materials, and the organic encapsulation layer 142 may include organic materials.

[0166] In one embodiment, the organic encapsulation layer 142 may be prepared by dropping an organic material in a liquid state onto the first inorganic encapsulation layer 141, spreading it to cover the display area DA, and curing it. The display panel 100 may further include at least one dam for limiting the diffusion range of the organic material of the organic encapsulation layer 142. The dam may be provided in the non-display area NA adjacent to the display area DA to surround the display area DA in a plan view.

[0167] Figure 8 is a plan view showing a display panel 100 according to one embodiment. Fig. 9 is a plan view showing a display panel 100 according to an embodiment. For example, Figure 8 and Fig. 9 Different embodiments are shown with regard to the sensor area SA. Figure 8 and Fig. 9 The display panel 100 is shown in an unbent and unfolded state.

[0168] Apart from Figures 1 to 7 In addition, refer to Figure 8 and Fig. 9 The display area DA may include data lines DL and pixels PX connected to the data lines DL. The display area DA may also include scan lines SL (eg, Figures 3 to 5 scanning line SL), emission control line ECL (for example, Figures 3 to 5 Emission control line ECL), power line PL (for example, Figures 3 to 5 A power supply line PL) and at least one control signal line CSL (for example, Figure 4 or Figure 5 part of the control signal line CSL).

[0169] The non-display area NA may include other parts of the scan line SL, the emission control line ECL, the power line PL, and at least one control signal line CSL connected to the pixel PX. In one embodiment, the non-display area NA may also include at least one embedded circuit SDR. For example, the embedded circuit SDR may be disposed in the non-display area NA on both sides of the display area DA in the second direction DR2.

[0170] The data line DL may be provided or disposed in each pixel column. Each of the data lines DL may be connected to a pixel PX positioned in a corresponding pixel column.

[0171] The pixels PX may be arranged in each pixel row and each pixel column. The pixels PX may emit light at brightness corresponding to each of data signals (eg, data voltages) supplied from the data lines DL.

[0172] The display area DA may be divided or separated into sub-areas corresponding to different portions in the second direction DR2. For example, the display area DA may include a central area CDA located at the center of the display area DA with respect to the second direction DR2 and an edge area EDA located at at least one side of the central area CDA.

[0173] The central area CDA may be aligned with the sub area SBA in the first direction DR1. The first data line DL1 and the pixels PX connected to the first data line DL1 may be arranged in the central area CDA.

[0174] The first data line DL1 may extend from the sub-area SBA to the main area MA. The sub-area SBA may include a driving circuit mounting area ICA where the data driving circuit 200 is disposed or mounted and a pad area PA where a pad (also called a "pad" or "pad") PD is disposed or provided, and may optionally further include a bending area BA where the display panel 100 is bendable.

[0175] The first data line DL1 may connect the data driving circuit 200 to the pixels PX of the central area CDA. For example, the first data line DL1 may extend from the driving circuit mounting area ICA to the central area CDA of the display area DA via the bending area BA and the non-display area NA.

[0176] The connection line CLI (or a portion of the connection line CLI) may be further disposed in the central area CDA. The connection line CLI may be disposed on the substrate 110 and may connect the data driving circuit 200 to the second data line DL2 located at the edge area EDA of the display area DA. For example, the connection line CLI may be disposed in the circuit layer 120 of the display panel 100 and may be connected between the data driving circuit 200 and the second data line DL2.

[0177] Each of the connection lines CLI may include a first connection line CLI1 electrically connected between the data driving circuit 200 and the second data line DL2 and a second connection line CLI2 connected between the second data line DL2 and the first connection line CLI1. In one embodiment, the first connection line CLI1 may extend in a first direction DR1 at least in the display area DA (e.g., the center area CDA), and the second connection line CLI2 may extend in a second direction DR2 in the display area DA.

[0178] In one embodiment, the connection line CLI may be disposed only in a portion of the central area CDA, and may not be disposed in the remaining portion of the central area CDA. For example, the central area CDA may include a first central area CDA1, a second central area CDA2, and a third central area CDA3 sequentially disposed in the second direction DR2, and the connection line CLI may be disposed only in the first central area CDA1 and the third central area CDA3 but not in the second central area CDA2. In the second direction DR2, the second central area CDA2 may be positioned at the center of the central area CDA, and the first central area CDA1 and the third central area CDA3 may be positioned on the side of the second central area CDA2. The first central area CDA1 and the third central area CDA3 may be adjacent to the first edge area EDA1 and the second edge area EDA2, respectively. The connection line CLI connected to the second data line DL2 of the first edge area EDA1 may be disposed in the first central area CDA1, and the connection line CLI connected to the second data line DL2 of the second edge area EDA2 may be disposed in the third central area CDA3.

[0179] The second central area CDA2 not provided with the connection line CLI may include a wiring form similar to that of the first central area CDA1 and the third central area CDA3 provided with the connection line CLI. For example, the second central area CDA2 may include a dummy line DML (or a portion of at least one power line PL) in a form corresponding to the connection line CLI and the dummy line DML provided in the first central area CDA1 and the third central area CDA3.

[0180] The second data line DL2 and the pixel PX connected to the second data line DL2 may be arranged in the edge area EDA. In one embodiment, the edge area EDA may include a first edge area EDA1 and a second edge area EDA2 positioned at the side of the center area CDA. For example, the edge area EDA may include a first edge area EDA1 adjacent to the first center area CDA1 and a second edge area EDA2 adjacent to the third center area CDA3.

[0181] The second data line DL2 positioned in the first edge area EDA1 may be connected to the data driving circuit 200 through the connection line CLI passing through the first central area CDA1. The second data line DL2 positioned in the second edge area EDA2 may be connected to the data driving circuit 200 through the connection line CLI passing through the third central area CDA3.

[0182] In one embodiment, the first data line DL1 and the first connection line CLI1 may extend from the driving circuit mounting area ICA into the display area DA, and may extend substantially in the first direction DR1 in the display area DA and the non-display area NA. For example, the first data line DL1 and the first connection line CLI1 may be formed as a straight line extending substantially in the first direction DR1 from the non-display area NA below the display area DA, etc.

[0183] Therefore, the non-display area NA can be reduced. For example, in order to directly connect the second data line DL2 to the data driving circuit 200 instead of connecting the second data line DL2 to the data driving circuit 200 through the first connection line CLI1 and the second connection line CLI2, the second data line DL2 can be formed as a fan-out type wiring having an inclined profile in the non-display area NA below the display area DA, and the non-display area NA can be expanded to ensure the space required for arranging the second data line DL2 in a fan-out configuration at least in the first direction DR1. However, in an embodiment, since the first data line DL1 and the first connection line CLI1 are formed as straight lines extending substantially in the first direction DR1 from the non-display area NA below the display area DA, etc., it is not necessary to ensure the space required for the fan-out arrangement of the wiring. Therefore, the non-display area NA can be reduced or the non-display area NA can be used more effectively.

[0184] In one embodiment, a dummy line DML separated from the data line DL and the connection line CLI may be further provided in the display area DA. The dummy line DML may be formed in the display area DA in a form corresponding to the connection line CLI. For example, the dummy line DML may include a first dummy line DML1 and a second dummy line DML2. The first dummy line DML1 may extend in a first direction DR1 in the display area DA in a form corresponding to the first connection line CLI1. The first dummy line DML1 and the first connection line CLI1 may be positioned at the same layer, but may be spaced apart from each other. The second dummy line DML2 may extend in a second direction DR2 in the display area DA in a form corresponding to the second connection line CLI2. The second dummy line DML2 and the second connection line CLI2 may be positioned at the same layer, but may be spaced apart from each other.

[0185] In one embodiment, the connection lines CLI and the dummy lines DML may be uniformly formed throughout the display area DA. For example, the connection lines CLI and the dummy lines DML may be formed in the display area DA at an overall uniform density and / or interval. Thus, the wiring may be uniformly disposed throughout the display area DA.

[0186] In one embodiment, some of the dummy lines DML may be used as power lines PL. For example, some of the first dummy lines DML1 may be connected to a power line PL supplying a type of power supply voltage and used as a vertical power line VPL forming a portion of the power line PL. Therefore, a drop in the power supply voltage applied to the power line PL may be prevented or reduced, and the power supply voltage may be stably applied to the pixel PX. In one example, some of the first dummy lines DML1 may be connected to a second pixel power line VSL supplying a second pixel power supply voltage ELVSS and used as a vertical power line VPL forming a portion of the second pixel power line VSL. At least some of the second dummy lines DML2 may be connected to a power line PL supplying a type of power supply voltage and used as a horizontal power line HPL forming a portion of the power line PL. The use of the dummy lines DML may be changed differently according to the embodiment.

[0187] In one embodiment, some other dummy lines of the dummy lines DML may be used as control signal lines CSL. For example, at least some of the first dummy lines DML1 passing through the sensor area SA may be used as control signal lines CSL. In one example, some of the first dummy lines DML1 passing through the sensor area SA may be connected to a first electrode (e.g., a gate electrode) of a switching element SW provided in at least one second pixel PX2 in the sensor area SA. Therefore, the second pixel PX2 may be appropriately and / or easily connected to the control signal line CSL without forming a separate signal line in the display area DA.

[0188] In one embodiment, the sensor 400 may be Figure 8 4. For example, at least one of the first central area CDA1, the second central area CDA2, and the third central area CDA3 may include at least one sensor area SA provided with the sensor 400. In one embodiment, at least one sensor 400 may be provided and / or disposed in each of the first central area CDA1, the second central area CDA2, and the third central area CDA3.

[0189] In another embodiment, the sensor 400 may be Fig. 9 For example, at least one of the first central area CDA1, the second central area CDA2, and the third central area CDA3 and at least one of the first edge area EDA1 and the second edge area EDA2 may include at least one sensor area SA where the sensor 400 is disposed.

[0190] In another embodiment, the sensor 400 may not be positioned in the center area CDA but may be positioned only in the edge area EDA. However, the disclosure is not limited thereto, and the number, location, arrangement structure, etc. of the sensor 400 may be variously changed according to embodiments.

[0191] The sub-area SBA may include a pad area PA. In the display device 10 where the data driving circuit 200 and the like are mounted in the sub-area SBA, the sub-area SBA may further include a driving circuit mounting area ICA. In the display device 10 where the sub-area SBA is bendable, the sub-area SBA may further include a bending area BA.

[0192] The pad area PA may be located in a portion (eg, a lower edge area) of the sub-area SBA. The pad area PA may include pads PD for connecting the display panel 100 to the circuit board 300, etc. In one embodiment, the pads PD may include power pads PP, signal pads SP, and data pads DP.

[0193] A power supply voltage for driving the pixel PX, the embedded circuit SDR, the data driving circuit 200 , etc. may be supplied to the power supply pad PP. Figure 8 and Fig. 9 Only a power pad PP (eg, second pixel power pad VSP) for transmitting one power voltage (eg, second pixel power voltage ELVSS) is shown, but the pad PD may include corresponding power pads PP required for supplying various power voltages required to drive the display panel 100 .

[0194] In one embodiment, at least one of the power lines PL connected to the power pads PP may be formed in the non-display area NA to surround the display area DA in a plan view, and may be connected to at least two power pads PP. For example, the second pixel power line VSL may be formed in the non-display area NA to surround the display area DA in a plan view. Figure 8 and Fig. 9 A second pixel power line VSL is shown formed outside the display area DA, but the disclosure is not limited to this, and the second pixel power line VSL may also be disposed inside the display area DA to be connected to the second pixel power line VSL outside the display area DA to transmit the second pixel power voltage ELVSS to the pixel PX.

[0195] In one embodiment, the second pixel power line VSL may be connected to at least one first dummy line DML1 and / or at least one second dummy line DML2. For example, some of the dummy lines DML may be used as the second pixel power line VSL.

[0196] Signals for controlling the embedded circuit SDR, the data driving circuit 200 , etc. may be supplied to the signal pad SP.

[0197] Image data (or an image signal) for generating a data signal may be supplied to the data pad DP.

[0198] The bending area BA may be an area where the display panel 100 may be bent. For example, the display panel 100 may be bent in the bending area BA so that a portion of the sub-area SBA may be positioned behind the main area MA. In one embodiment, the bending area BA may be positioned adjacent to the main area MA. For example, the bending area BA may be positioned between the main area MA and the drive circuit mounting area ICA, and may be adjacent to a boundary between the main area MA and the sub-area SBA. Thus, the frame area may be reduced or minimized.

[0199] The data driving circuit 200 may be mounted in the driving circuit mounting area ICA. The data driving circuit 200 may generate a driving signal required to drive the pixel PX. For example, the data driving circuit 200 may generate a data signal corresponding to image data and supply the data signal to the pixel PX.

[0200] Fig.10 is a plan view schematically showing a data line DL, a first dummy line DML1 and a connection line CLI in a central area CDA and an edge area EDA according to one embodiment. Fig.10 An arrangement structure of the data line DL, the first dummy line DML1, and the connection line CLI positioned in a portion of the first center area CDA1 and a portion of the first edge area EDA1 is schematically illustrated.

[0201] Apart from Figures 1 to 9 In addition, refer to Fig.10 , the first data line DL1, the dummy line DML including the first dummy line DML1 (or the power line PL including the vertical power line VPL), and the connection line CLI including the first connection line CLI1 and the second connection line CLI2 (a portion of each of the second connection line CLI2) may be disposed in the central area CDA.

[0202] The first data line DL1, the first dummy line DML1, and the first connection line CLI1 may extend substantially in the first direction DR1 in the central area CDA. In one embodiment, at least one of the first data line DL1, the first dummy line DML1, and the first connection line CLI1 may have a partially bent and / or protruding shape to be properly or easily connected to a corresponding element (e.g., a circuit element, an electrode, a wiring and / or a bridge pattern, etc.) within the display area DA.

[0203] In one embodiment, the first data line DL1, the first dummy line DML1, and the first connection line CLI1 may be regularly arranged in the second direction DR2 in the central area CDA. Figure 8 and Fig. 9 As shown in FIG. 1 , the first data lines DL1 , the first dummy lines DML1 , and the first connection lines CLI1 may be alternately arranged in the second direction DR2 in the central area CDA. Fig.10 As shown in , two first data lines DL1 may be adjacent to each other based on two pixel columns in the central area CDA, and at least one first dummy line DML1 and / or at least one first connection line CLI1 may be disposed at one side of the two first data lines DL1.

[0204] Another portion of each of the second connection lines CLI2, the second data line DL2, and the dummy line DML including the first dummy line DML1 (or the power line PL including the vertical power line VPL) may be disposed in the edge area EDA. The first connection line CLI1 may not be disposed in the edge area EDA. For example, the first dummy line DML1 may be disposed at a position corresponding to the first connection line CLI1 in each pixel column.

[0205] The second data line DL2 and the first dummy line DML1 may extend substantially in the first direction DR1 in the edge area EDA. In one embodiment, at least one of the second data line DL2 and the first dummy line DML1 may have a partially bent and / or protruding shape to be properly or easily connected to a corresponding element within the display area DA.

[0206] In one embodiment, the second data lines DL2 and the first dummy lines DML1 may be regularly arranged in the second direction DR2 in the edge area EDA. Figure 8 and Fig. 9 As shown in FIG. 1 , the second data lines DL2 and the first dummy lines DML1 may be alternately arranged in the edge area EDA in the second direction DR2. Fig.10 As shown in , the two second data lines DL2 may be adjacent to each other based on two pixel columns in the edge area EDA, and the two first dummy lines DML1 may be disposed on the left and right sides of the two second data lines DL2, respectively.

[0207] The second connection lines CLI2 may extend in the second direction DR2 between each of the first connection lines CLI1 and the second data line DL2. For example, each of the second connection lines CLI2 may extend across the central area CDA and the edge area EDA in the second direction DR2 to connect the first connection line CLI1 and the second data line DL2 as a pair corresponding to each other. In one embodiment, each of the second connection lines CLI2 may include an end portion intersecting the pair of the first connection lines CLI1 and the second data line DL2, and may be electrically connected to the pair of the first connection lines CLI1 and the second data line DL2 through at least one contact hole CH at each end portion.

[0208] In one embodiment, the first connection line CLI1 and the second connection line CLI2 may be disposed in different layers. For example, the first connection line CLI1 may be disposed in the second source-drain conductive layer (eg, Figure 7 The second connection line CLI2 may be disposed in the first source-drain conductive layer (eg, the fifth conductive layer CDL5) of the circuit layer 120. Figure 7 In the fourth conductive layer CDL4).

[0209] In one embodiment, the data line DL, the first dummy line DML1 and the first connection line CLI1 may be disposed in the same layer. For example, the data line DL and the first dummy line DML1 may be disposed in the second source-drain conductive layer of the circuit layer 120 .

[0210] In one embodiment, Figure 8 and Fig. 9 As shown in , the display area DA may be provided with a second dummy line DML2 extending in the second direction DR2 in a form corresponding to the second connection line CLI2. In one embodiment, the second dummy line DML2 and the second connection line CLI2 may be provided in the same layer. For example, the second dummy line DML2 may be provided in the first source-drain conductive layer of the circuit layer 120.

[0211] However, the disclosure is not limited thereto, and the arrangement structures of the data lines DL, the dummy lines DML, and the connection lines CLI may be variously changed.

[0212] Fig.11 is a plan view showing a ninth transistor T9 of a second pixel PX2 according to an embodiment. For example, Fig.11 1 is a plan view schematically showing a ninth transistor T9 provided in two second pixels PX2 (referred to as a “twenty-first pixel PX21” and a “twenty-second pixel PX22”) positioned in two adjacent pixel columns in the sensor area SA, and a second pixel power line VSL and a control signal line CSL connected to the ninth transistor T9. Fig.11 Each of the second pixels PX2 of the embodiment may include Figure 4 The ninth transistor T9 of the embodiment.

[0213] Apart from Figures 1 to 10 In addition, refer to Fig.11, each of the second pixels PX2 may include a ninth transistor T9 having an active layer ACT, a gate electrode G, a first electrode S (e.g., a source electrode), and a second electrode D (e.g., a drain electrode). The first electrode S of the ninth transistor T9 may be a source region included in the active layer ACT of the ninth transistor T9 and / or a bridge electrode connected to the source region. The second electrode D of the ninth transistor T9 may be a drain region included in the active layer ACT of the ninth transistor T9 and / or a bridge electrode connected to the drain region.

[0214] The active layer ACT of the ninth transistor T9 may be provided in one of the semiconductor layers provided in the circuit layer 120 of the display panel 100. For example, the active layer ACT of the ninth transistor T9 may be provided in Figure 7 In the first semiconductor layer SCL1 (or the second semiconductor layer SCL2).

[0215] The active layer ACT of the ninth transistor T9 may include a channel region overlapping with the gate electrode G in a plan view, a source region positioned on one side of the channel region and connected to the first electrode S (or bridging electrode) through at least one contact portion CNT, and a drain region positioned on the other side of the channel region and connected to the second electrode D (or bridging electrode) through at least one other contact portion CNT. For example, the active layer ACT of the ninth transistor T9 disposed in the twenty-first pixel PX21 may include a channel region overlapping with the gate electrode G of the ninth transistor T9 in a plan view, a source region connected to the first electrode S of the ninth transistor T9, and a drain region connected to the second electrode D of the ninth transistor T9. Similarly, the active layer ACT of the ninth transistor T9 disposed in the twenty-second pixel PX22 may include a channel region overlapping with the gate electrode G of the ninth transistor T9 in a plan view, a source region connected to the first electrode S of the ninth transistor T9, and a drain region connected to the second electrode D of the ninth transistor T9. For simplicity, in Fig.11 In the drawings, only one contact portion CNT is marked with a reference numeral. Each contact portion CNT may include at least one contact hole and / or via.

[0216] In one embodiment, the active layers ACT of the ninth transistors T9 disposed in at least two adjacent second pixels PX2 may be integrated with each other. For example, the active layer ACT of the ninth transistor T9 disposed in the twenty-first pixel PX21 and the active layer ACT of the ninth transistor T9 disposed in the twenty-second pixel PX22 may be integrally formed as a single semiconductor pattern.

[0217] The gate electrode G of the ninth transistor T9 may be disposed in one of the gate conductive layers disposed in the circuit layer 120. For example, the gate electrode G of the ninth transistor T9 may be disposed in Figure 7In another example, the gate electrode G of the ninth transistor T9 may be disposed in the first conductive layer CDL1 (eg, the first gate conductive layer). Figure 7 The gate electrode G of the ninth transistor T9 may overlap with the active layer ACT of the ninth transistor T9 in a plan view, and at least one insulating layer is interposed between the gate electrode G of the ninth transistor T9 and the active layer ACT of the ninth transistor T9.

[0218] In one embodiment, the gate electrodes G of the ninth transistors T9 disposed in at least two adjacent second pixels PX2 may be integrated with each other. For example, the gate electrode G of the ninth transistor T9 disposed in the twenty-first pixel PX21 and the gate electrode G of the ninth transistor T9 disposed in the twenty-second pixel PX22 may be integrally formed as a single electrode or conductive pattern.

[0219] The gate electrode G of the ninth transistor T9 may be connected to the control signal line CSL. For example, the gate electrode G of the ninth transistor T9 may be electrically connected to the control signal line CSL via at least one contact portion CNT and / or the first bridge pattern BRP1. In one embodiment, the first bridge pattern BRP1 may be disposed in a conductive layer between a conductive layer provided with the gate electrode G of the ninth transistor T9 and a conductive layer provided with the control signal line CSL. For example, the first bridge pattern BRP1 may be disposed in a conductive layer between a conductive layer provided with the gate electrode G of the ninth transistor T9 and a conductive layer provided with the control signal line CSL. Figure 7 In the fourth conductive layer CDL4 (eg, the first source-drain conductive layer).

[0220] The control signal line CSL may be connected between the driving circuit 310 and the second pixel PX2. The control signal line CSL may transmit a cutoff control signal output from the driving circuit 310 to the second pixel PX2. For example, the control signal line CSL may be connected to the gate electrode G of the ninth transistor T9 of each of the second pixels PX2, and may transmit a cutoff control signal output from the driving circuit 310 to the gate electrode G of the ninth transistor T9.

[0221] In one embodiment, the control signal line CSL, the data line DL, and the first dummy line DML1 (or the vertical power line VPL of the second pixel power line VSL) in the display area DA can be arranged in the same layer. For example, the control signal line CSL can be arranged in the display area DA together with the data line DL and the first dummy line DML1. Figure 7 In the fifth conductive layer CDL5 (eg, the second source-drain conductive layer).

[0222] In one embodiment, some of the first dummy lines DML1 passing through the second display area DA2 (e.g., the sensor area SA) may be used as the control signal line CSL. Another first dummy line DML1 may be used as the power line PL. For example, another first dummy line DML1 may be used as the second pixel power line VSL. In this way, as needed, only some of the first dummy lines DML1 may be used as the control signal line CSL, and another first dummy line DML1 may be used as the power line PL, thereby reducing or minimizing the drop in the power supply voltage.

[0223] In one embodiment, the control signal line CSL may be disposed outside the display area DA (eg, in the non-display area NA and the sub-area SBA) in one of the gate conductive layers disposed in the circuit layer 120. For example, the control signal line CSL may be disposed outside the display area DA. Figure 7 In one embodiment, the wiring portions of the control signal line CSL disposed in different conductive layers of the circuit layer 120 may be electrically connected to each other through at least one contact portion CNT and / or the second bridge pattern BRP2. In one embodiment, the second bridge pattern BRP2 may be disposed at Figure 7 In the fourth conductive layer CDL4.

[0224] The first electrode S of the ninth transistor T9 may be disposed in one of the source-drain conductive layers disposed in the circuit layer 120. For example, the first electrode S of the ninth transistor T9 may be disposed in Figure 7 In the fourth conductive layer CDL4.

[0225] The first electrode S of the ninth transistor T9 may be connected to the first electrode ET1 of the light emitting element EL disposed in the corresponding second pixel PX2. For example, the first electrode S of the ninth transistor T9 disposed in the twenty-first pixel PX21 may be electrically connected to the first electrode ET1 of the light emitting element EL disposed in the twenty-first pixel PX21 through at least one contact portion CNT and / or the connection electrode CNE. The first electrode S of the ninth transistor T9 disposed in the twenty-second pixel PX22 may be electrically connected to the first electrode ET1 of the light emitting element EL disposed in the twenty-second pixel PX22 through at least one contact portion CNT and / or the connection electrode CNE.

[0226] The second electrode D of the ninth transistor T9 may be disposed in one of the source-drain conductive layers disposed in the circuit layer 120. For example, the second electrode D of the ninth transistor T9 may be disposed in Figure 7 In the fourth conductive layer CDL4.

[0227] The second electrode D of the ninth transistor T9 may be connected to the second pixel power line VSL. For example, the second electrode D of the ninth transistor T9 may be electrically connected to the second pixel power line VSL through at least one contact portion CNT.

[0228] In one embodiment, the second electrodes D of the ninth transistors T9 disposed in at least two adjacent second pixels PX2 may be integrated with each other. For example, the second electrode D of the ninth transistor T9 disposed in the twenty-first pixel PX21 and the second electrode D of the ninth transistor T9 disposed in the twenty-second pixel PX22 may be integrally formed as a single electrode or conductive pattern.

[0229] The second pixel power line VSL may be connected to a power pad PP (eg, Figure 8 and Fig. 9 The second pixel power line VSL may be connected between the power pad PP and the second electrode ET2 of the light emitting element EL provided in the pixel PX. The second pixel power line VSL may transmit the second pixel power supply voltage ELVSS supplied from the power pad PP or the like to the pixel PX.

[0230] In one embodiment, the second pixel power line VSL may also be connected to a ninth transistor T9 disposed in the second pixel PX2. For example, the second pixel power line VSL may be electrically connected to a second electrode D of a ninth transistor T9 disposed in the second pixel PX2 in the second display area DA2.

[0231] In one embodiment, the first dummy line DML1 disposed in the display area DA may be used as the second pixel power line VSL. For example, the second pixel power line VSL may include a vertical power line VPL disposed at the same layer as the data line DL. In one embodiment, the second pixel power line VSL may be disposed at Figure 7 In one embodiment, the second pixel power line VSL can even be arranged outside the display area DA. Figure 7 However, the disclosure is not limited thereto, and the structure and / or position of the second pixel power line VSL may be variously changed according to embodiments.

[0232] Fig.12 is a plan view showing a ninth transistor T9 of a second pixel PX2 according to an embodiment. For example, Fig.12 Schematically shows Fig.11 A modified embodiment of the embodiment, Fig.12 The second pixel power line VSL may include a bridge line BRL adjacent to the display area DA and disposed on a different conductive layer. Fig.12 In the embodiment of Fig.11 The components of the embodiments are described redundantly with respect to similar or identical components.

[0233] Apart from Figures 1 to 11 In addition, refer to Fig.12 , the display device 10 may further include at least one wiring (e.g., a first pixel power line VDL) in the non-display area NA, the at least one wiring being arranged in the same conductive layer (e.g., a fifth conductive layer CDL5) as the second pixel power line VSL, and passing through an area between the second pixel power line VSL and the display area DA. The second pixel power line VSL may include a bridge line BRL, which is arranged on a different conductive layer from the first pixel power line VDL and the control signal line CSL at an intersection with the first pixel power line VDL and the control signal line CSL. Fig.12 , a separate reference numeral is assigned to the bridge line BRL, but the bridge line BRL may be a part of the second pixel power line VSL.

[0234] In one embodiment, the bridge line BRL may be provided in one of the gate conductive layers provided in the circuit layer 120. For example, the bridge line BRL may be provided in the first conductive layer CDL1 (e.g., the first gate conductive layer), the second conductive layer CDL2 (e.g., the second gate conductive layer), or the third conductive layer CDL3 (e.g., the third gate conductive layer).

[0235] The wiring portions of the second pixel power supply line VSL disposed in different conductive layers of the circuit layer 120 may be electrically connected to each other through at least one contact portion CNT, the third bridge pattern BRP3, and / or the fourth bridge pattern BRP4. In one embodiment, the third bridge pattern BRP3 and / or the fourth bridge pattern BRP4 may be disposed at Figure 7 In the fourth conductive layer CDL4.

[0236] Fig.13 is a plan view showing a ninth transistor T9 of a second pixel PX2 according to an embodiment. For example, Fig.13 Schematically shows Fig.11 A modified embodiment of the embodiment, Fig.13 Each of the second pixels PX2 may include a Figure 5 In describing the ninth transistor T9 of the embodiment Fig.13 In the embodiment of Fig.11 The components of the embodiments are described redundantly with respect to similar or identical components.

[0237] Apart from Figures 1 to 12 In addition, refer to Fig.13, the display device 10 may include a cut-off power line VOFL connected between the driving circuit 310 and the second pixel PX2, and the ninth transistor T9 of the second pixel PX2 may be connected to the cut-off power line VOFL. For example, the second electrode D of each of the ninth transistors T9 may be connected to the cut-off power line VOFL.

[0238] In one embodiment, the off power line VOFL may be disposed in the same conductive layer as the control signal line CSL and may be separated from the control signal line CSL and the second pixel power line VSL. For example, the off power line VOFL may be disposed in the same layer as the control signal line CSL in the display area DA (e.g., Figure 7 The fifth conductive layer CDL5 may be provided in the same layer as the control signal line CSL outside the display area DA (eg, Figure 7 In one embodiment, the wiring portions of the off power line VOFL disposed in different conductive layers of the circuit layer 120 may be electrically connected to each other through at least one contact portion CNT and / or the fifth bridge pattern BRP5. In one embodiment, the fifth bridge pattern BRP5 may be disposed at Figure 7 In the fourth conductive layer CDL4.

[0239] During the period in which the sensor 400 operates, the driving circuit 310 may supply a cut-off control signal to the control signal line CSL to turn on the ninth transistor T9, and may supply a cut-off voltage of a level to prevent the light emitting element EL of the second pixel PX2 from emitting light to the cut-off power line VOFL. Therefore, during the period in which the sensor 400 operates, the second pixel PX2 may maintain a closed state (e.g., a non-emitting state).

[0240] Fig.14 is a plan view showing prevention of stains that may occur in the display area DA when the second pixel PX2 is turned off.

[0241] Apart from Figures 1 to 13 In addition, refer to Fig.14 , in a display device to which the above-described embodiment is not applied (for example, a display device in which the pixel PX at a position corresponding to the sensor area SA does not include a separate switching element SW controlled by the driving circuit 310), when the sensor 400 operates, the characteristics of at least some of the pixel transistors T provided in the pixel PX in the area corresponding to the sensor 400 may be changed, causing the pixel PX to emit unintentionally. Therefore, stains may be visually recognized in the display area DA'. For example, even in the case where a black screen is displayed in the display area DA' when the sensor 400 is operating, the pixel PX at the position corresponding to the sensor 400 may emit light, making it possible to visually recognize an image quality defect DFA in the form of stains.

[0242] However, in the display device 10 according to the above-described embodiment, during a period in which the sensor 400 operates, a turn-off voltage (e.g., the second pixel power supply voltage ELVSS or a separate turn-off voltage VOFF) capable of turning off the light emitting element EL may be applied to the first electrode ET1 of each of the light emitting elements EL of the second pixel PX2 through the ninth transistor T9 provided in the second pixel PX2 at a position corresponding to the sensor 400. This can prevent the second pixel PX2 from emitting light in an abnormal manner and prevent stains from occurring in the display area DA.

[0243] The above description is an example of the disclosed technical features, and a person skilled in the art will be able to make various modifications and changes.Therefore, the above disclosed embodiments can be implemented individually or in combination with each other.

[0244] Therefore, the embodiments disclosed in the disclosure are not intended to limit the disclosed technical spirit, but to describe the disclosed technical spirit, and the scope of the disclosed technical spirit is not limited by these embodiments. The disclosed protection scope should be interpreted by the claims, and should be interpreted as all technical spirits within the equivalent scope are included in the disclosed scope.

Claims

1. A display device, comprising: A display area, including a first display area and a sensor area; a first pixel positioned in the first display area and comprising a first pixel circuit and a first light emitting element connected to the first pixel circuit; as well as a second pixel, positioned in the sensor region and comprising a second pixel circuit and a second light emitting element connected to the second pixel circuit, the first pixel circuit and the second pixel circuit having different structures, The second pixel circuit includes a switch element, which is connected between a power line and the second light emitting element and is turned on by a cutoff control signal, and a cutoff voltage of the second light emitting element is applied to the power line.

2. The display device according to claim 1, further comprising: The driving circuit supplies the cut-off control signal to the second pixel.

3. The display device according to claim 2, further comprising: a signal line connected between the driving circuit and the second pixel and transmitting the cutoff control signal from the driving circuit to the second pixel, The switch element includes: a gate electrode connected to the signal line; a first electrode connected to an electrode of the second light-emitting element; and a second electrode connected to the power line.

4. The display device according to claim 3, further comprising: a substrate including a main area and a sub-area, the main area including the display area in which pixels including the first pixel and the second pixel are arranged, and the sub-area is positioned at one side of the main area in a first direction; as well as a data driving circuit disposed in the sub-region and supplying a data signal to the pixel, Wherein, the display area includes: a central area, which is positioned at the center of the display area in a second direction intersecting the first direction and aligned with the sub-area in the first direction, and in which a first data line and some of the pixels connected to the first data line are arranged; and an edge area, which is positioned on at least one side of the central area in the second direction, and in which a second data line and other pixels of the pixels connected to the second data line are arranged.

5. The display device according to claim 4, further comprising: a connecting line, disposed on the substrate and connected between the data driving circuit and the second data line, Wherein, each of the connecting lines includes: a first connecting line, which is connected between the data driving circuit and one of the second data lines, and extends in the first direction in the display area; and a second connecting line, which is connected between the first connecting line and one of the second data lines, and extends in the second direction in the display area.

6. The display device according to claim 2, further comprising: a first pixel power supply line connected to the first pixel circuit and the second pixel circuit and supplied with a first pixel power supply voltage; as well as A second pixel power supply line is connected to the first light emitting element and the second light emitting element and is supplied with a second pixel power supply voltage having a lower potential than the first pixel power supply voltage.

7. The display device according to claim 6, wherein: The switching element is connected to the second pixel power supply line.

8. The display device according to claim 6, wherein: The power line connected to the switching element is separated from the first pixel power line and the second pixel power line and connected between the driving circuit and the second pixel, and The drive circuit supplies the off voltage of the second light emitting element to the power supply line.

9. The display device according to claim 2, wherein: The display device further includes: a sensor disposed in the sensor region and emitting infrared rays that pass through the sensor region where the second pixel is located, The driving circuit supplies the cutoff control signal to the second pixel during a period in which the sensor operates.

10. The display device according to claim 1, wherein: The first display area does not overlap the sensor area in a plan view, and The switching element is provided only in the second pixel.

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