Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a substrate including a first display area and a second display area around the first display area, a plurality of pixels on the substrate, and a plurality of connection lines on the second display area, and a plurality of light emitting elements in the first display area and the second display area and connected to the corresponding plurality of pixel transistors, the plurality of connecting lines connecting the plurality of pixel transistors with the plurality of light emitting elements, respectively, each of the plurality of connecting lines includes one or more straight line portions extending in a first direction, and one or more inclined portions connected to the one or more straight line portions and extending in an inclined direction inclined by an angle equal to a multiple of 45 degrees with respect to the first direction, and wherein the one or more inclined portions are inclined by an angle equal to a multiple of 45 degrees with respect to the first direction, the angles formed by the straight portion and the inclined portion of the connecting line are equal to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0086217 filed in the Korean Intellectual Property Office on July 4, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0004] As multimedia technology develops, display devices have become increasingly important, and therefore, various display devices such as liquid crystal display devices and organic light emitting display devices are currently being developed.

[0005] A display device may include a display area where pixels are arranged and an image is displayed and a non-display area outside the display area. Recently, there is a demand for a display device capable of extending a display area by reducing the non-display area.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of some embodiments of the present disclosure include a display device in which a display area is expanded by reducing a non-display area and connection lines for connecting pixel driving units of pixels with emission units are uniformly arranged.

[0008] However, aspects of the embodiments according to the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0009] According to some embodiments of the present disclosure, a display device is provided, which includes a substrate, a plurality of pixels and a plurality of connecting lines, the substrate including a first display area and a second display area around the first display area, the plurality of pixels are on the substrate and include a corresponding plurality of pixel transistors in the first display area and a corresponding plurality of light-emitting elements in the first display area and the second display area and connected to the corresponding plurality of pixel transistors, the plurality of connecting lines respectively connecting the plurality of pixel transistors with the plurality of light-emitting elements, wherein each of the plurality of connecting lines includes one or more straight line portions extending in a first direction and one or more inclined portions connected to the one or more straight line portions and extending in an inclined direction at an angle equal to a multiple of 45° relative to the first direction, and wherein the angles formed by the straight line portions and the inclined portions of the connecting lines are equal to each other.

[0010] According to some embodiments, an angle formed by the straight portion and the inclined portion of each of the plurality of connection lines may be equal to 135°.

[0011] According to some embodiments, each of the plurality of connection lines may have a width of a first length.

[0012] According to some embodiments, straight line portions of two adjacent connection lines among the plurality of connection lines may be spaced apart from each other by an interval equal to the first length.

[0013] According to some embodiments, the plurality of pixels may also include a plurality of connection electrodes connected to a corresponding plurality of pixel transistors, a plurality of first connection portions overlapping the plurality of connection electrodes, and a plurality of second connection portions overlapping the plurality of first electrodes of a corresponding plurality of light-emitting elements, and each of the plurality of connection lines may be connected between the first connection portion and the second connection portion of one of the plurality of pixels.

[0014] According to some embodiments, the plurality of connection lines may include a first connection line including a single straight portion and a single inclined portion, and a second connection line adjacent to the first connection line and including at least two straight portions and at least two inclined portions.

[0015] According to some embodiments, the first connection portion connected to the first connection line and the first connection portion connected to the second connection line may be arranged in parallel in the first direction, and the second connection portion connected to the first connection line and the second connection portion connected to the second connection line may be arranged in parallel in the first direction.

[0016] According to some embodiments, each of the at least two straight line portions of the second connection line may be parallel to the straight line portion of the first connection line in a first direction or in a second direction orthogonal to the first direction.

[0017] According to some embodiments, the display device may further include a dummy pattern in a space between the plurality of connection lines and including a straight line pattern parallel to the straight line portions of the connection lines and an inclined pattern parallel to the inclined portions of the connection lines.

[0018] According to some embodiments, a plurality of connection lines and dummy patterns may be arranged at uniform intervals in a display area including the first display area and the second display area.

[0019] According to some embodiments, the dummy pattern may be in the same layer and include the same material as the plurality of connection lines.

[0020] According to some embodiments, the display device may further include a circuit layer on the substrate and including a plurality of pixel transistors, and a light emitting element layer overlapping the circuit layer and including a plurality of light emitting elements.

[0021] According to some embodiments, the display device may further include an embedded driver circuit in the circuit layer and including a driver transistor in the second display area.

[0022] According to some embodiments, the embedded driver circuit may overlap with the light emitting element of at least one of the plurality of pixels.

[0023] According to some embodiments, a first pixel among multiple pixels may include a first pixel transistor in a first display area and a first light-emitting element in a second display area, and a second pixel among multiple pixels may include a second pixel transistor in the first display area and a second light-emitting element in the first display area.

[0024] According to some embodiments, a connection line connecting the first pixel transistor with the first light emitting element may have a longer length than a connection line connecting the second pixel transistor with the second light emitting element.

[0025] According to some embodiments, each of the plurality of pixels may include a pixel driving unit and an emission unit, the pixel driving unit including at least one pixel transistor, the emission unit including at least one light emitting element, and among the plurality of pixels, at least two pixels having corresponding pixel driving units adjacent to each other and corresponding emission units adjacent to each other may form a unit pixel.

[0026] According to some embodiments, multiple pixel driving units and multiple emission units of multiple unit pixels formed by multiple pixels can be arranged in the first display area and the second display area, the multiple pixel driving units of the multiple unit pixels can be arranged in the first display area at a first spacing in the first direction, and the multiple emission units of the multiple unit pixels can be arranged in the first display area and the second display area at a second spacing larger than the first spacing in the first direction.

[0027] According to some embodiments, the straight portion and the inclined portion of each of the plurality of connection lines may be formed as one body.

[0028] According to some embodiments of the present disclosure, a method for manufacturing a display device is provided, wherein the display device includes a plurality of pixels, the plurality of pixels include a plurality of pixel transistors, a plurality of light-emitting elements, and a plurality of connecting lines connecting the plurality of pixel transistors with the plurality of light-emitting elements, the method including inputting positions of a plurality of first connecting parts connected to the plurality of pixel transistors and positions of a plurality of second connecting parts connected to the plurality of light-emitting elements into a design program, inputting line path exploration conditions for the plurality of connecting lines, sequentially exploring a plurality of line paths for the plurality of connecting lines under the line path exploration conditions, and forming a plurality of connecting lines between the plurality of first connecting parts and the plurality of second connecting parts based on the plurality of line paths found, wherein the line path exploration conditions include a condition that each square of a plurality of squares having four sides with a length equal to a multiple of a width of each of the plurality of connecting lines is a minimum moving unit and a condition that the path moves only in a straight line direction extending from the four sides of the square and in a diagonal direction of the square.

[0029] According to some embodiments, both the first display area where the pixel driving unit is located and the second display area around the first display area (e.g., the area where the embedded driver circuit is located) can be used as the display area. Therefore, the non-display area of ​​the display device can be relatively reduced, while the display area can be expanded.

[0030] In addition, according to some embodiments, the connection lines can be arranged at regular intervals, and the length of the connection lines can be relatively shortened. Therefore, it may be possible to uniformly form the connection lines and reduce or minimize voltage drops and voltage drop deviations in the connection lines.

[0031] However, characteristics according to the embodiments of the present disclosure are not limited to those described above, and various other characteristics are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing in more detail various aspects of some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a plan view showing a display device according to some embodiments of the present disclosure.

[0034] Figure 2 is a cross-sectional view illustrating a structure of a display device according to some embodiments of the present disclosure.

[0035] Figure 3is a circuit diagram illustrating a pixel according to some embodiments of the present disclosure.

[0036] Figure 4 is a circuit diagram illustrating a pixel according to some embodiments of the present disclosure.

[0037] Figure 5 is a plan view showing a display area according to some embodiments of the present disclosure.

[0038] Figure 6 is a cross-sectional view showing a display device according to some embodiments of the present disclosure.

[0039] Figure 7 is a plan view showing a first connection portion and a second connection portion according to some embodiments of the present disclosure.

[0040] Figure 8 is a plan view showing connection lines according to some embodiments of the present disclosure.

[0041] Fig. 9 is a plan view showing a portion of a connection line according to some embodiments of the present disclosure.

[0042] Fig.10 is a flow chart illustrating a method of forming a connection line according to some embodiments of the present disclosure.

[0043] Fig.11 is a plan view showing found line paths according to some embodiments of the present disclosure.

[0044] Fig.12 is a plan view showing connection lines and dummy patterns according to some embodiments of the present disclosure.

[0045] Fig.13 is a plan view partially illustrating connection lines and dummy patterns according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0046] Now hereinafter will refer to the accompanying drawings showing various aspects of some embodiments of the present invention to more fully describe various aspects of some embodiments of the present invention. However, the present invention can be implemented in different forms, and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will more fully convey the scope of embodiments according to the present invention to those skilled in the art.

[0047] It will also be understood that when an element or layer is referred to as being 'on' another element or layer, it can be directly on the other element or layer, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0048] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0049] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other and may technically interact with each other in various ways, and the respective embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0050] Hereinafter, various aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0051] Figure 1 is a plan view showing a display device 10 according to some embodiments of the present disclosure. Figure 1 , the structure of the display device 10 is schematically shown, focusing on the display panel including the display area DA.

[0052] Reference Figure 1 , the display device 10 may include a substrate 100 (or a base member), and pixels PX and an embedded driver circuit SDR positioned on the substrate 100. The pixels PX and the embedded driver circuit SDR (or a portion of the embedded driver circuit SDR) may be positioned in the display area DA.

[0053] The display device 10 may be implemented in various shapes. According to some embodiments of the present disclosure, the display device 10 may be implemented as follows: Figure 1 The rectangular panel shown in Figure 1 In the example shown in FIG. 1 , the display device 10 includes sharp corners, but the display device 10 may include rounded corners.

[0054] According to some embodiments, the display device 10 may have various shapes. For example, the display device 10 may be implemented in a non-rectangular shape. For example, the display device 10 may be implemented in a polygonal shape (for example, a hexagonal shape), a circular shape, or an elliptical shape other than a rectangular shape.

[0055] The display device 10 may be implemented as a substantially flat 2D panel or a 3D panel having a curve in a thickness direction or the like. The display device 10 may be a substantially non-deformable rigid display device or a deformable (ie, at least partially folded, bent, or rolled) flexible display device.

[0056] For the convenience of illustration, Figure 1In the example shown in , the display device 10 has a rectangular flat planar shape. The horizontal direction (e.g., row direction or X direction) of the display device 10 is referred to as a first direction DR1, the vertical direction (e.g., column direction or Y direction) of the display device 10 is referred to as a second direction DR2, and the thickness direction (e.g., height direction or Z direction) of the display device 10 is referred to as a third direction DR3.

[0057] The substrate 100 is a base member for manufacturing or providing the display device 10, and may form, for example, a base surface of the display device 10. The substrate 100 may include a display area DA where the pixels PX are located and a non-display area NA other than the display area DA. In the display area DA, an image may be displayed by the pixels PX. The non-display area NA may be an area other than the display area DA (e.g., an area at the periphery of the display area DA or an area outside the footprint of the display area DA).

[0058] The display area DA may include a first display area DA1 and a second display area DA2. The second display area DA2 may be positioned on at least one side of the first display area DA1 and may be closer to an edge of the display device 10 than the first display area DA1. According to some embodiments, the second display area DA2 where the embedded driver circuit SDR (or a portion of the embedded driver circuit SDR) is positioned may be positioned on each of both sides of the first display area DA1 in the first direction DR1.

[0059] The display device 10 may include pixels PX that emit light of different colors. For example, the display device 10 may include a first color pixel PX_C1 that emits light of a first color (e.g., red light having a wavelength range of about 610nm to 680nm and a peak wavelength in the range of 610nm to 650nm), a second color pixel PX_C2 that emits light of a second color (e.g., green light having a wavelength range of about 500nm to 570nm and a peak wavelength in the range of 510nm to 550nm), and a third color pixel PX_C3 that emits light of a third color (e.g., blue light having a wavelength range of about 430nm to 500nm and a peak wavelength in the range of 440nm to 480nm). The colors of light emitted from different pixels PX may vary according to the embodiment.

[0060] At least one first color pixel PX_C1, at least one second color pixel PX_C2, and at least one third color pixel PX_C3 positioned adjacent to each other (e.g., their emission units EMU are positioned adjacent to each other and their pixel driving units PDU are positioned adjacent to each other) may form a single unit pixel UPX. For example, each unit pixel UPX may include one first color pixel PX_C1, one second color pixel PX_C2, and one third color pixel PX_C3. The type, number, and / or ratio of the pixels PX forming the unit pixel UPX may vary according to the embodiment. By individually controlling the emission brightness of the first color pixel PX_C1, the second color pixel PX_C2, and the third color pixel PX_C3 forming each unit pixel UPX, light of various colors can be emitted from the unit pixel UPX.

[0061] Each pixel PX may include an emission unit EMU including at least one light-emitting element and a pixel driving unit PDU (e.g., a pixel circuit) electrically connected to the emission unit EMU. For example, each first color pixel PX_C1 may include a first emission unit EMU1 including at least one light-emitting element and emitting light of a first color and a first pixel driving unit PDU1 electrically connected to the first emission unit EMU1. Each second color pixel PX_C2 may include a second emission unit EMU2 including at least one light-emitting element and emitting light of a second color and a second pixel driving unit PDU2 electrically connected to the second emission unit EMU2. Each third color pixel PX_C3 may include a third emission unit EMU3 including at least one light-emitting element and emitting light of a third color and a third pixel driving unit PDU3 electrically connected to the third emission unit EMU3.

[0062] The emission units EMU of the pixels PX may have substantially the same size or different sizes. For example, the first emission unit EMU1 of the first color pixel PX_C1 may have an area that is the same as or different from the area of ​​the second emission unit EMU2 of the second color pixel PX_C2 and / or the third emission unit EMU3 of the third color pixel PX_C3. The size, shape and / or ratio of the emission units EMU of the pixels PX may vary according to different embodiments. In addition, in various embodiments, the arrangement direction and / or arrangement structure of the pixels PX may vary. For example, the arrangement direction and / or arrangement structure of the emission units EMU of the pixels PX may vary according to different embodiments. Similarly, the arrangement direction and / or arrangement structure of the pixel driving unit PDU of the pixels PX may vary according to different embodiments.

[0063] The emission unit EMU of the pixel PX may be positioned in the display area DA including the first display area DA1 and the second display area DA2. The pixel driving unit PDU of the pixel PX may be positioned only in the first display area DA1 but may not be positioned in the second display area DA2. The embedded driver circuit SDR may be positioned in the second display area DA2. The embedded driver circuit SDR may overlap with at least some of the emission units EMU of the pixel PX positioned in the second display area DA2.

[0064] Since the emission unit EMU of the pixel PX is positioned in an area (e.g., a display area DA including the first display area DA1 and the second display area DA2) larger than the area (e.g., the first display area DA1) where the pixel driving unit PDU is positioned, the emission unit EMU of the pixel PX may be arranged at a pitch larger than the pixel driving unit PDU. For example, the pixel driving unit UPDU and the emission unit UEMU of the unit pixel UPX, each including at least one first color pixel PX_C1, at least one second color pixel PX_C2, and at least one third color pixel PX_C3, may be arranged in the display area DA at least along the first direction DR1 (e.g., along the first direction DR1 and the second direction DR2). The pixel driving unit UPDU of the unit pixel UPX may be arranged in the first display area DA1 at a first pitch PI1 in the first direction DR1. The emission unit UEMU of the unit pixel UPX may be arranged in the first display area DA1 and the second display area DA2 at a second pitch PI2 greater than the first pitch PI1 in the first direction DR1. At least some of the emission units EMU of the pixel PX positioned in the second display area DA2 may overlap with the embedded driver circuit SDR. Therefore, by using the area where the embedded driver circuit SDR is located as the display area DA, the non-display area NA can be reduced, and the display area DA can be expanded.

[0065] The display device 10 may further include a driver circuit (e.g., a scan driver circuit, a data driver circuit, and a timing controller) for driving the pixel PX. According to some embodiments of the present disclosure, a portion of the driver circuit may be implemented as an embedded driver circuit SDR formed and / or positioned inside the display panel, while another portion of the driver circuit may be positioned in the non-display area NA of the display panel and / or mounted on a circuit board electrically connected to the display panel.

[0066] The embedded driver circuit SDR may be positioned in the second display area DA2. The embedded driver circuit SDR may be positioned on at least one side of the first display area DA1. For example, the embedded driver circuit SDR may be positioned on one side (e.g., the left side or the right side) of the first display area DA1, or on both sides (e.g., the left side and the right side) of the first display area DA1.

[0067] The embedded driver circuit SDR may be located and / or formed in the display panel together with the pixel PX. For example, the embedded driver circuit SDR may include a circuit layer (e.g., Figure 2 and Figure 6 According to some embodiments of the present disclosure, the circuit elements (or some of the circuit elements) of the embedded driver circuit SDR and the lines connected thereto may be formed together with the circuit elements of the pixel driving unit PDU forming the pixel PX.

[0068] According to some embodiments of the present disclosure, the embedded driver circuit SDR may include a gate driver circuit such as a scan driver circuit or a portion of the gate driver circuit. The gate driver circuit may be connected to the pixel PX through a scan line and the like, and may supply a corresponding gate signal (e.g., a corresponding scan signal) to the pixel PX.

[0069] The non-display area NA may be arranged around the display area DA (e.g., at the periphery of the display area DA or outside the footprint of the display area DA). Lines and / or pads connected to the pixels PX and / or the embedded driver circuit SDR of the display area DA may be positioned in the non-display area NA.

[0070] Figure 2 is a cross-sectional view showing the structure of a display device 10 according to some embodiments of the present disclosure.

[0071] Reference Figure 1 and Figure 2 , the display device 10 may include a substrate 100 and a circuit layer 200, a light emitting element layer 300, and an encapsulation layer 400 sequentially arranged on the substrate 100. However, it should be understood that the structure of the display device 10 is not limited thereto. For example, the circuit layer 200 and the light emitting element layer 300 may overlap each other, and the order in which the circuit layer 200 and the light emitting element layer 300 are positioned may be changed. The encapsulation layer 400 may be positioned or formed to encapsulate at least the light emitting element layer 300.

[0072] The substrate 100 may be a rigid or flexible substrate and may have a single-layer or multi-layer structure. According to some embodiments of the present disclosure, the substrate 100 may be, but is not limited to, one of a glass substrate, a quartz substrate, a glass ceramic substrate, a film substrate including a polymer organic material, and a plastic substrate.

[0073] The circuit layer 200 (also referred to as the panel circuit layer or backplane layer) may include circuit elements and lines positioned inside the display panel. For example, the circuit layer 200 may include circuit elements (e.g., pixel transistors and capacitors) positioned in the first display area DA1 and forming a pixel drive unit PDU for each of the pixels PX, circuit elements (e.g., drive unit transistors (e.g., driver transistors) and capacitors) positioned in the second display area DA2 and forming an embedded driver circuit SDR, and lines connected to the pixels PX and / or the embedded driver circuit SDR. In the following description of the embodiments, the term "connection" may include electrical connection and / or physical connection.

[0074] The light emitting element layer 300 (also referred to as a light source unit or a light emitting element unit) may include a light emitting element used as a light source of the pixel PX. For example, the light emitting element layer 300 may include a self-luminous element positioned or formed in an emission region of the pixel PX. For example, each of the pixels PX may include an organic light emitting diode, a quantum dot light emitting diode, an inorganic micro light emitting diode (e.g., a micro LED), an inorganic nano light emitting diode (e.g., a nano LED), or other types of self-luminous elements.

[0075] The encapsulation layer 400 may be positioned on the light emitting element layer 300. For example, the encapsulation layer 400 may be positioned on the light emitting element layer 300 to encapsulate the display area DA where the light emitting element of the pixel PX is positioned.

[0076] According to some embodiments of the present disclosure, the display device 10 may further include additional elements. For example, the display device 10 may further include at least one of a touch sensor layer, a color filter layer, a polarizing layer, and a protective layer. Each of the touch sensor layer, the color filter layer, the polarizing layer, and the protective layer may be directly formed or positioned on the surface of the substrate 100 where the pixels PX are positioned, or may be formed separately from the display panel including the pixels PX, and then may be attached to the display panel.

[0077] Figure 3 is a circuit diagram illustrating a pixel PX according to some embodiments of the present disclosure. Figure 4 is a circuit diagram showing a pixel PX according to some embodiments of the present disclosure. For example, Figure 3 and Figure 4 Different embodiments are shown with regard to the type of pixel transistor Tpx.

[0078] exist Figure 3 and Figure 4 In the example shown in FIG. 1 , the scan lines SL connected to the pixel PX include a scan initialization line GIL, a scan control line GCL, a first scan line GWL1, and a second scan line GWL2. Figure 3 and Figure 4In the embodiment shown in , the power lines PL connected to the pixels PX include a first power voltage line VDL, a second power voltage line VSL, a first initialization voltage line VIL1, and a second initialization voltage line VIL2. The types and numbers of the scan lines SL and the power lines PL connected to each pixel PX may vary according to the structure of the pixel PX.

[0079] Combination Figure 1 and Figure 2 Reference Figure 3 and Figure 4 The pixel PX may include an emission unit EMU including at least one light emitting element EL and a pixel driving unit PDU connected to the emission unit EMU.

[0080] The light emitting element EL may be connected between the second power supply voltage line VSL to which the second power supply voltage ELVSS is applied and the pixel driving unit PDU. The light emitting element EL is a light source of the pixel PX and may emit light in response to a driving current supplied from the pixel driving unit PDU. As the driving current increases, the light emitting element EL may emit light with higher brightness.

[0081] The light emitting element EL may be, but is not limited to, an organic light emitting diode. For example, the light emitting element EL may be an inorganic light emitting element, a quantum dot light emitting element, or other types of light emitting elements.

[0082] The pixel driving unit PDU may control the emission timing and brightness of the light emitting element EL by controlling the driving current supplied to the light emitting element EL. The pixel driving unit PDU may include at least one pixel transistor Tpx and a capacitor Cst. According to some embodiments of the present disclosure, the pixel driving unit PDU may include a pixel transistor Tpx including a driving transistor DT and a switching element. The switching element may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0083] The driving transistor DT may include a gate electrode connected to the first node N1, a first electrode connected to the first power supply voltage line VDL via a fourth transistor T4, and a second electrode connected to the emission unit EMU via a fifth transistor T5. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode. The driving transistor DT may control a source-drain current (hereinafter referred to as a driving current) flowing between the first electrode and the second electrode in response to a voltage applied to the gate electrode (e.g., a voltage of the first node N1 corresponding to a voltage of a data signal).

[0084] The first transistor T1 may include a gate electrode connected to the first scan line GWL1, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the driving transistor DT. The first transistor T1 may be turned on by a first scan signal supplied to the first scan line GWL1 to connect the first electrode of the driving transistor DT to the data line DL. When the first transistor T1 is turned on, the voltage of the data signal supplied to the data line DL may be applied to the first electrode of the driving transistor DT.

[0085] The second transistor T2 may include a gate electrode connected to the scan control line GCL, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the gate electrode (or the first node N1) of the driving transistor DT. The second transistor T2 may be turned on by a scan control signal supplied to the scan control line GCL to connect the gate electrode of the driving transistor DT to the second electrode. When the second transistor T2 is turned on, the driving transistor DT may operate like a diode.

[0086] The third transistor T3 may include a gate electrode connected to the scan initialization line GIL, a first electrode connected to the gate electrode of the driving transistor DT, and a second electrode connected to the first initialization voltage line VIL1. The third transistor T3 may be turned on by a scan initialization signal supplied to the scan initialization line GIL to connect the gate electrode of the driving transistor DT to the first initialization voltage line VIL1. When the third transistor T3 is turned on, the first initialization voltage VINT of the first initialization voltage line VIL1 may be applied to the gate electrode of the driving transistor DT.

[0087] The fourth transistor T4 may include a gate electrode connected to the emission control line ECL, a first electrode connected to the first power supply voltage line VDL, and a second electrode connected to the first electrode of the driving transistor DT. The fourth transistor T4 may be turned on by an emission control signal supplied to the emission control line ECL to connect the first electrode of the driving transistor DT to the first power supply voltage line VDL to which the first power supply voltage ELVDD is applied. When the fourth transistor T4 is turned on, the first power supply voltage ELVDD may be applied to the first electrode of the driving transistor DT.

[0088] The fifth transistor T5 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a second electrode of the driving transistor DT, and a second electrode connected to the light emitting element EL. The fifth transistor T5 may be turned on by an emission control signal supplied to the emission control line ECL to connect the driving transistor DT to the light emitting element EL. When both the fourth transistor T4 and the fifth transistor T5 are turned on, a driving current corresponding to a voltage of the gate electrode of the driving transistor DT may flow through the light emitting element EL.

[0089] The sixth transistor T6 may include a gate electrode connected to the second scan line GWL2, a first electrode connected to the anode of the light emitting element EL, and a second electrode connected to the second initialization voltage line VIL2. The sixth transistor T6 may be turned on by a second scan signal supplied to the second scan line GWL2 to connect the anode of the light emitting element EL to the second initialization voltage line VIL2. The second scan signal may be the same as or different from the first scan signal. When the sixth transistor T6 is turned on, the second initialization voltage VAINT of the second initialization voltage line VIL2 may be applied to the anode of the light emitting element EL.

[0090] The capacitor Cst may be connected between the gate electrode of the driving transistor DT and the first power supply voltage line VDL. The capacitor Cst may store a voltage corresponding to a voltage of a data signal applied to the gate electrode of the driving transistor DT.

[0091] According to some embodiments of the present disclosure, the active layer (e.g., a semiconductor pattern including a channel region) of each of the pixel transistors Tpx (e.g., the driving transistor DT and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6) may be formed of one of polycrystalline silicon, amorphous silicon, and an oxide semiconductor. Figure 3 In an embodiment of the present invention, all of the pixel transistors Tpx may be implemented as p-type transistors (eg, p-type MOSFETs). An active layer of each of the pixel transistors Tpx may be formed of polysilicon or an oxide semiconductor.

[0092] Alternatively, as in Figure 4 In some embodiments of the present disclosure, some of the pixel transistors Tpx (e.g., the driving transistor DT and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6) may be implemented as p-type transistors, and some other transistors of the pixel transistor Tpx (e.g., the second transistor T2 and the third transistor T3) may be implemented as n-type transistors (e.g., n-type MOSFETs). According to some embodiments of the present disclosure, the active layers of the driving transistor DT and each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 implemented as p-type transistors may be formed of polysilicon, and the active layers of each of the second transistor T2 and the third transistor T3 implemented as n-type transistors may be formed of an oxide semiconductor. According to some embodiments of the present disclosure, a transistor including an active layer formed of polysilicon and a transistor including an active layer formed of an oxide semiconductor may be positioned in different layers on the substrate 100.

[0093] The structure of the pixel PX may be changed according to some embodiments. For example, according to some embodiments, the pixel PX may include additional components or fewer components without departing from the spirit and scope of the embodiments according to the present disclosure.

[0094] Figure 5 is a plan view showing a display area DA according to some embodiments of the present disclosure. Figure 1 , the structure of the display device 10 is schematically shown, focusing on the display panel including the display area DA, and Figure 5 The display area DA in Figure 1 Corresponding to the display area DA in.

[0095] Reference Figures 1 to 5 , the pixel driving unit PDU of the pixel PX may be positioned in the first display area DA1, and the emission unit EMU of the pixel PX may be positioned in the first display area DA1 and the second display area DA2. The emission unit EMU of the pixel PX may be positioned at a shifted position in the first direction DR1 and / or the second direction DR2 relative to the pixel driving unit PDU. For example, the emission unit EMU of the pixel PX may be positioned from the center of at least the display area DA in the first direction DR1 (e.g., including the emission unit EMU of the pixel PX). Figure 5 The region of the virtual center line CL indicated by the dotted line in FIG. 1 is positioned at a shifted position in two directions relative to the pixel driving unit PDU. For example, the emission unit EMU of the pixel PX may be positioned at Figure 5 At the ends of the connection line CNL in the pixel driving unit PDU, the pixel driving unit PDU is at a shifted position in two directions (eg, left and right directions) in the first direction DR1 in the direction of the arrow indicated.

[0096] The emission unit EMU of the pixel PX may be connected to the corresponding pixel driving unit PDU through the corresponding connection line CNL. The connection line CNL may be connected to the corresponding pixel driving unit PDU at the first connection part CP1 (or the first contact pad formed on the first connection part CP1), and may be connected to the corresponding emission unit EMU at the second connection part CP2 (or the second contact pad formed on the second connection part CP2). For example, one end of each of the connection lines CNL may be located at the first connection part CP1 of the corresponding pixel PX, and may be electrically connected to at least one pixel transistor Tpx included in the pixel driving unit PDU of the corresponding pixel PX at the first connection part CP1. The other end of each of the connection lines CNL may be located at the second connection part CP2 of the corresponding pixel PX, and may be electrically connected to the light emitting element EL included in the emission unit EMU of the corresponding pixel PX at the second connection part CP2. The connection line CNL may also be regarded as an element included in the corresponding pixel PX.

[0097] Each of the first connection portions CP1 may be positioned at a pixel driving unit PDU where the pixel PX is positioned, or at a connection electrode (eg, Figure 6 Each of the second connection portions CP2 may be located in an emission unit EMU where a pixel PX is located, or an electrode (eg, Figure 6 The first electrode ET1) or the region of the bridge pattern connected to the electrode of the light emitting element EL.

[0098] According to some embodiments of the present disclosure, the second connection portion CP2 formed in one pixel PX may be positioned farther from the center of the display area DA in at least the first direction DR1 than the first connection portion CP1 formed in the corresponding pixel PX. According to some embodiments of the present disclosure, the second connection portion CP2 may be positioned at a shifted position in the first direction DR1 and the second direction DR2 relative to the first connection portion CP1 associated therewith, but embodiments of the present disclosure are not limited thereto. For example, the positions of the first connection portion CP1 and the second connection portion CP2 may be variously changed according to the design structure of the pixel PX.

[0099] Figure 6 is a cross-sectional view showing a display device 10 according to some embodiments of the present disclosure. For example, Figure 6 A cross section of a portion of a display area DA where pixel transistors Tpx and light emitting elements EL of first, second, and third pixels PX1, PX2, and PX3 are located is shown. Each of the first, second, and third pixels PX1, PX2, and PX3 may be a first color pixel PX_C1, a second color pixel PX_C2, or a third color pixel PX_C3.

[0100] Reference Figures 1 to 6 , the display device 10 may include a substrate 100 and a circuit layer 200, a light emitting element layer 300, and an encapsulation layer 400 sequentially positioned on the substrate 100. The circuit layer 200, the light emitting element layer 300, and the encapsulation layer 400 may overlap each other and may be sequentially arranged or stacked in the third direction DR3.

[0101] The circuit layer 200 may include circuit elements forming a pixel driving unit PDU, circuit elements forming an embedded driver circuit SDR, and lines. Figure 6The pixel transistors Tpx located in the pixel driving units PDU of the first pixel PX1, the second pixel PX2 and the third pixel PX3 and connected to the light emitting elements EL of the pixels PX and a driver transistor Tsd located in the circuit elements of the embedded driver circuit SDR are shown among the elements located in the circuit layer 200. For example, Figure 6 Shown are a pixel transistor Tpx (hereinafter referred to as the first pixel transistor Tpx1) connected to the light emitting element EL of the first pixel PX1 (hereinafter referred to as the first light emitting element EL1), a pixel transistor Tpx (hereinafter referred to as the second pixel transistor Tpx2) connected to the light emitting element EL of the second pixel PX2 (hereinafter referred to as the second light emitting element EL2), a pixel transistor Tpx (hereinafter referred to as the third pixel transistor Tpx3) connected to the light emitting element EL of the third pixel PX3 (hereinafter referred to as the third light emitting element EL3), and a driver transistor Tsd positioned in the embedded driver circuit SDR.

[0102] The pixel transistor Tpx may be positioned in the first display area DA1 in the circuit layer 200, and the driver transistor Tsd may be positioned in the second display area DA2 in the circuit layer 200. Each of the transistors T (e.g., each of the pixel transistors Tpx and each of the driver transistors Tsd) may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0103] The circuit layer 200 may include at least one semiconductor layer, a conductive layer, and an insulating layer for forming circuit elements and lines. For example, the circuit layer 200 may include a first insulating layer 210 (e.g., a buffer layer), a semiconductor layer, a second insulating layer 220 (e.g., a gate insulator), a first conductive layer (e.g., a gate conductive layer), a third insulating layer 230 (e.g., an interlayer dielectric layer), a second conductive layer (e.g., a first source-drain conductive layer), a fourth insulating layer 240 (e.g., a first via layer or a first planarization layer), a third conductive layer (e.g., a second source-drain conductive layer), a fifth insulating layer 250 (e.g., a second via layer or a second planarization layer), a fourth conductive layer (e.g., an intermediate conductive layer or a connecting conductive layer) and a sixth insulating layer 260 (e.g., a third via layer or a third planarization layer) sequentially positioned on the substrate 100 in the third direction DR3.

[0104] Despite Figure 6In the example shown in FIG. 2 , the fourth conductive layer and the sixth insulating layer 260 are included in the circuit layer 200, but the embodiments of the present disclosure are not limited thereto. For example, the fourth conductive layer and the sixth insulating layer 260 may be included in the light emitting element layer 300, or may be included in an intermediate layer positioned between the circuit layer 200 and the light emitting element layer 300.

[0105] The first insulating layer 210 may include at least one inorganic film including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). However, it should be understood that the embodiments of the present disclosure are not limited thereto. The material of the first insulating layer 210 may be changed.

[0106] According to some embodiments of the present disclosure, an additional conductive layer may be positioned between the substrate 100 and the first insulating layer 210. For example, between the substrate 100 and the first insulating layer 210, a bottom metal layer overlapping the active layer ACT of at least one transistor T and / or a conductive layer (e.g., a lower conductive layer) including at least one line (or a portion of at least one line) may be positioned.

[0107] The semiconductor layer may include an active layer ACT of each of the transistors T. The semiconductor layer may include polycrystalline silicon (eg, low temperature polycrystalline silicon), single crystal silicon, amorphous silicon, or an oxide semiconductor. The active layer ACT may include a channel region, a source region, and a drain region.

[0108] The second insulating layer 220 may include at least one inorganic film including an inorganic insulating material (eg, the inorganic insulating materials listed above as the material of the first insulating layer 210 or other inorganic insulating materials). According to some embodiments, the material for the second insulating layer 220 may vary.

[0109] The first conductive layer may include a gate electrode GE of each of the transistors T. Each gate electrode GE may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), other metals, alloys thereof, and other conductive materials), and may be a single-layer or multi-layer electrode. The first conductive layer may also include at least one line (or a portion of at least one line) containing a conductive material, a bridge pattern, and / or a capacitor electrode.

[0110] The third insulating layer 230 may include at least one inorganic film including an inorganic insulating material (eg, the inorganic insulating materials listed above as the material of the first insulating layer 210 or other inorganic insulating materials). According to some embodiments, the material for the third insulating layer 230 may vary.

[0111] The second conductive layer may include a source electrode SE and a drain electrode DE of each of the transistors T. The source electrode SE or the drain electrode DE may include a conductive material and may be a single-layer or multi-layer electrode. According to some embodiments, the source electrode SE and the drain electrode DE of each of the transistors T may be formed integrally with the source region and the drain region of the active layer ACT. The third conductive layer may include a bridge pattern connected to the source electrode SE or the drain electrode DE of at least one transistor T.

[0112] In order to provide a flat surface in the circuit layer 200, the fourth insulating layer 240 may include at least one organic film including an organic insulating material (e.g., acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or other organic insulating material). According to some embodiments, the organic insulating material forming the fourth insulating layer 240 may be variously changed.

[0113] The third conductive layer may include connection electrodes CNE of the pixels PX. For example, the third conductive layer may include connection electrodes CNE (or bridge patterns) respectively connected to the pixel transistors Tpx. The connection electrodes CNE may be respectively positioned above the pixel transistors Tpx, and may electrically connect the pixel transistors Tpx to the light emitting elements EL of the pixels PX together with the connection lines CNL. Each of the connection electrodes CNE may include a conductive material, and may be a single-layer or multi-layer electrode.

[0114] The third conductive layer may further include at least one line (or a portion of at least one line) including a conductive material, a bridge pattern and / or a capacitor electrode. For example, the third conductive layer may include at least one power line PL (or a portion of at least one power line PL).

[0115] The fifth insulating layer 250 may include at least one organic film including an organic insulating material (e.g., the organic insulating material listed above as the material of the fourth insulating layer 240 or other organic insulating materials) to provide a flat surface in the circuit layer 200. According to some embodiments, the organic insulating material forming the fifth insulating layer 250 may be variously changed.

[0116] The fourth conductive layer may include a connection line CNL including a conductive material. Optionally, the fourth conductive layer may further include at least some of the lines (or at least parts of some of the lines) positioned in the display panel and / or a bridge pattern. The connection line CNL may be positioned in an intermediate layer between a layer where the transistor T is positioned and a layer where the light emitting element EL is positioned. For example, the connection line CNL may be positioned in an intermediate layer, and the intermediate layer is positioned above the layer where the transistor T is positioned and below the layer where the light emitting element EL is positioned.

[0117] According to some embodiments of the present disclosure, the connection line CNL may include, but is not limited to, a transparent conductive layer including a transparent conductive material (TCO) such as ITO and IZO. For example, according to some embodiments, the conductive material forming the connection line CNL may be variously changed.

[0118] The connection lines CNL may overlap with the pixel transistors Tpx of the pixels PX and / or the connection electrodes CNE respectively connected to the pixel transistors Tpx, and may be respectively connected to the pixel transistors Tpx and / or the connection electrodes CNE. For example, one end of each of the connection lines CNL may be positioned on the connection electrode CNE of the corresponding pixel PX, and may be electrically connected to the connection electrode CNE of the corresponding pixel PX through the first contact hole CH1 in the first connection portion CP1 of the corresponding pixel PX.

[0119] Each first connection portion CP1 may be formed at a position that coincides with the corresponding connection electrode CNE. For example, each first connection portion CP1 may be formed at a position that overlaps the corresponding connection electrode CNE. A portion of the connection electrode CNE positioned at the first connection portion CP1 and / or a portion of the connection line CNL may form a first contact pad positioned on the first connection portion CP1.

[0120] In addition, the connection lines CNL may overlap the light emitting elements EL of the pixels PX and / or the electrodes connected to the light emitting elements EL, respectively, and may be connected to the light emitting elements EL. For example, the other end of each of the connection lines CNL may be positioned below the first electrode ET1 of the light emitting element EL of the corresponding pixel PX, and may be electrically connected to the light emitting element EL of the corresponding pixel PX through the second contact hole CH2 in the second connection portion CP2 of the corresponding pixel PX.

[0121] Each second connection portion CP2 may be formed at a position that coincides with the corresponding light emitting element EL. For example, each second connection portion CP2 may be formed at a position that overlaps with the first electrode ET1 included in the light emitting element EL of the corresponding pixel PX. A portion of the connection line CNL positioned at the second connection portion CP2 and / or a portion of the first electrode ET1 of the light emitting element EL may form a second contact pad positioned on the second connection portion CP2.

[0122] For example, a connection line of the first pixel PX1 (hereinafter referred to as the first pixel connection line CNL_P1) may connect a first pixel transistor Tpx1 positioned in a pixel driving unit PDU of the first pixel PX1 to a first light emitting element EL1 positioned in an emission unit EMU of the first pixel PX1. According to some embodiments of the present disclosure, the first pixel connection line CNL_P1 may be regarded as an element included in the first pixel PX1.

[0123] A connection line of the second pixel PX2 (hereinafter referred to as the second pixel connection line CNL_P2) may connect a second pixel transistor Tpx2 positioned in the pixel driving unit PDU of the second pixel PX2 to a second light emitting element EL2 positioned in the emission unit EMU of the second pixel PX2. According to some embodiments of the present disclosure, the second pixel connection line CNL_P2 may be regarded as an element included in the second pixel PX2.

[0124] A connection line of the third pixel PX3 (hereinafter referred to as a third pixel connection line CNL_P3) may connect a third pixel transistor Tpx3 positioned in a pixel driving unit PDU of the third pixel PX3 to a third light emitting element EL3 positioned in an emission unit EMU of the third pixel PX3. According to some embodiments of the present disclosure, the third pixel connection line CNL_P3 may be regarded as an element included in the third pixel PX3.

[0125] Each of the connection lines CNL may have a length equal to the distance between the pixel driving unit PDU and the emission unit EMU of the corresponding pixel PX. For example, if the pixel driving unit PDU and the emission unit EMU of the first pixel PX1 are spaced apart from each other by a greater distance than the pixel driving unit PDU and the emission unit EMU of the second pixel PX2, the first pixel connection line CNL_P1 may have a greater length than the second pixel connection line CNL_P2. Similarly, if the pixel driving unit PDU and the emission unit EMU of the second pixel PX2 are spaced apart from each other by a greater distance than the pixel driving unit PDU and the emission unit EMU of the third pixel PX3, the second pixel connection line CNL_P2 may have a greater length than the third pixel connection line CNL_P3.

[0126] The connection lines CNL of the pixels PX may be respectively positioned on the pixel transistors Tpx of the pixels PX and / or the connection electrodes CNE connected to the pixel transistors Tpx, and may be respectively connected to the pixel transistors Tpx and / or the connection electrodes CNE.

[0127] The sixth insulating layer 260 may include at least one organic film including an organic insulating material (e.g., the organic insulating material listed above as the material of the fourth insulating layer 240 or other organic insulating materials) to provide a flat surface in the circuit layer 200. According to some embodiments, the organic insulating material forming the sixth insulating layer 260 may be variously changed.

[0128] The light emitting element layer 300 may be positioned on the sixth insulating layer 260. The light emitting element layer 300 may include a light emitting element EL positioned in the emission area EA of the pixel PX. For example, the light emitting element layer 300 may include a first light emitting element EL1 positioned in the emission area EA (e.g., the first emission area EA1) of the first pixel PX1, a second light emitting element EL2 positioned in the emission area EA (e.g., the second emission area EA2) of the second pixel PX2, and a third light emitting element EL3 positioned in the emission area EA (e.g., the third emission area EA3) of the third pixel PX3. The light emitting element layer 300 may also include a pixel defining film 310 that defines the emission area EA.

[0129] Each of the light emitting elements EL may include a first electrode ET1 (e.g., an anode) connected to a corresponding pixel transistor Tpx through a corresponding connection line CNL, and an emission layer EML and a second electrode ET2 (e.g., a cathode) sequentially arranged on the first electrode ET1. According to some embodiments of the present disclosure, each of the light emitting elements EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) between the first electrode ET1 and the emission layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) between the emission layer EML and the second electrode ET2.

[0130] The first electrode ET1 of each of the light emitting elements EL may include a conductive material and may be positioned on the circuit layer 200. For example, the first electrode ET1 may be positioned on the sixth insulating layer 260 in each of the emission areas EA. According to some embodiments of the present disclosure, the first electrode ET1 may include a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a single-layer structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and a multilayer structure of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni) (for example, ITO / Mg, ITO / MgF, ITO / Ag, ITO / Ag / ITO, etc.).

[0131] The emission layer EML of each of the light emitting elements EL may include a polymer substance or a low molecular substance. The light emitted from the emission layer EML may contribute to displaying an image. According to some embodiments of the present disclosure, the emission layer EML may be positioned in each of the pixels PX, and the emission layer EML of each of the pixels PX may emit visible light of a color associated with the corresponding pixel PX. According to some embodiments, the emission layer EML may be a common layer shared by pixels PX of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of the light to be emitted from the pixel PX may be positioned in the emission area EA of at least some of the pixels PX.

[0132] The second electrode ET2 of each of the light emitting elements EL may include a conductive material and may be connected to a second power supply voltage line VSL. According to some embodiments of the present disclosure, the second electrode ET2 may be a common layer formed throughout the entire display area DA to cover the emission layer EML and the pixel defining film 310. According to some embodiments of the present disclosure, the second electrode ET2 may be formed of a transparent conductive material (TCO) such as ITO and IZO (e.g., a transparent metal material) capable of transmitting light or a semi-transmissive conductive material (e.g., a semi-transmissive metal material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode ET2 is made of a semi-transmissive conductive material, the emission efficiency can be improved by a microcavity effect.

[0133] The pixel defining film 310 may have an opening associated with the emission area EA and may surround the emission area EA. For example, the pixel defining film 310 may be formed to cover the edge of the first electrode ET1 of each of the light emitting elements EL and may include an opening that exposes the rest of the first electrode ET1 of each of the light emitting elements EL. The region where the exposed first electrode ET1 and the emission layer EML overlap each other (or the region including the same) may be defined as the emission area EA of each pixel PX.

[0134] The pixel defining film 310 may include at least one organic film including an organic insulating material. According to some embodiments of the present disclosure, the pixel defining film 310 may include an organic insulating material such as a polyacrylate resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and benzocyclobutene (BCB). The organic insulating material forming the pixel defining film 310 is not particularly limited and may vary according to different embodiments.

[0135] At least some of the pixels PX positioned in the display area DA may include a pixel transistor Tpx positioned in the first display area DA1 and a light emitting element EL positioned in the second display area DA2. Figure 6The first pixel PX1 shown in the figure may include a first pixel transistor Tpx1 positioned in the first display area DA1 and a first light emitting element EL1 positioned in the second display area DA2. In this case, the first pixel connection line CNL_P1 may extend from the first connection portion CP1 of the first pixel PX1 positioned in the first display area DA1 to the second connection portion CP2 of the first pixel PX1 positioned in the second display area DA2. At least some of the pixels PX including the light emitting element EL positioned in the second display area DA2 may overlap with the embedded driver circuit SDR positioned in the second display area DA2. For example, the first light emitting element EL1 of the first pixel PX1 may overlap with at least one driver transistor Tsd.

[0136] Other pixels PX among the pixels PX positioned in the display area DA may include a pixel transistor Tpx positioned in the first display area DA1 and a light emitting element EL positioned in the first display area DA1. Figure 6 The second pixel PX2 shown in the figure may include a second pixel transistor Tpx2 positioned in the first display area DA1 and a second light emitting element EL2 positioned in the first display area DA1, and the third pixel PX3 may include a third pixel transistor Tpx3 positioned in the first display area DA1 and a third light emitting element EL3 positioned in the first display area DA1. In this case, the second pixel connection line CNL_P2 may extend from the first connection part CP1 of the second pixel PX2 to the second connection part CP2 in the first display area DA1. The third pixel connection line CNL_P3 may extend from the first connection part CP1 of the third pixel PX3 to the second connection part CP2 in the first display area DA1.

[0137] According to some embodiments of the present disclosure, in a pixel PX (e.g., a first pixel PX1) including a pixel transistor Tpx positioned in the first display area DA1 and a light emitting element EL positioned in the second display area DA2, the pixel driving unit PDU and the light emitting element EL may be spaced apart from each other by a distance greater than that in a pixel PX (e.g., a second pixel PX2 or a third pixel PX3) including a pixel transistor Tpx positioned in the first display area DA1 and a light emitting element EL positioned in the second display area DA2. In this case, a connection line CNL (e.g., a first pixel connection line CNL_P1) of a pixel PX including a pixel transistor Tpx positioned in the first display area DA1 and a light emitting element EL positioned in the second display area DA2 may have a distance greater than that of a connection line CNL (e.g., a second pixel connection line CNL_P2 or a third pixel connection line CNL_P3) of a pixel PX including a pixel transistor Tpx positioned in the first display area DA1 and a light emitting element EL.

[0138] The encapsulation layer 400 may be positioned at least on the light emitting element layer 300 in the display area DA. The encapsulation layer 400 can block oxygen or moisture from penetrating into the light emitting element layer 300 and can mitigate electrical or physical impact on the circuit layer 200 and the light emitting element layer 300.

[0139] According to some embodiments of the present disclosure, encapsulation layer 400 may include first encapsulation layer 410, second encapsulation layer 420, and third encapsulation layer 430 sequentially positioned on light emitting element layer 300. First encapsulation layer 410 and third encapsulation layer 430 may include inorganic insulating materials, and second encapsulation layer 420 may include organic insulating materials.

[0140] According to some embodiments of the present disclosure, an additional layer may be positioned on the encapsulation layer 400. For example, at least one of a sensor layer (eg, a touch sensor layer), a polarization layer, and a protection layer may be positioned on the encapsulation layer 400.

[0141] according to Figures 1 to 6 The display device 10 of the embodiment also includes a first display area DA1 where the pixel driving unit PDU of the pixel PX is located and a second display area DA2 around the first display area DA1, and therefore, it can include a more extended display area DA. For example, the emission unit EMU of the pixel PX can be located in the first display area DA1 and the second display area DA2. According to some embodiments, both the first display area DA1 where the pixel driving unit PDU is located and the second display area DA2 where the embedded driver circuit SDR is located can be used as the display area DA. As a result, the non-display area NA of the display device 10 can be reduced, and the display area DA can be extended.

[0142] Figure 7 is a plan view showing a first connection portion CP1 and a second connection portion CP2 according to some embodiments of the present disclosure. For example, Figure 7 An example of the first connection portion CP1 and the second connection portion CP2 positioned at a portion of the display area DA is shown.

[0143] Figure 8 is a plan view showing a connection line CNL according to some embodiments of the present disclosure. For example, Figure 8 An example of a connection line CNL connecting the first connection portion CP1 and the second connection portion CP2 is shown.

[0144] Fig. 9 is a plan view showing a portion of a connection line CNL according to some embodiments of the present disclosure. For example, Fig. 9 It is shown Figure 8 An enlarged plan view of area A.

[0145] Combination Figures 1 to 6 Reference Figures 7 to 9 , adjacent ones of the first connection portions CP1 positioned in the display area DA may be arranged in parallel in the first direction DR1. For example, a plurality of first connection portions CP1 may be sequentially and / or continuously arranged in the first direction DR1.

[0146] A plurality of second connection portions CP2 associated with the plurality of first connection portions CP1 (e.g., a plurality of second connection portions CP2 connected to the plurality of first connection portions CP1) may be located at positions spaced apart from the first connection portions CP1 in at least the first direction DR1. For example, the second connection portions CP2 associated with the first connection portions CP1 may be located at positions spaced apart from the first connection portions CP1 in the first direction DR1 and the second direction DR2, respectively. For example, the second connection portion CP2 of the pixel PX may be located at positions spaced apart from the first connection portion CP1 of the pixel PX in both the first direction DR1 and the second direction DR2.

[0147] Each of the connection lines CNL may have a structure bent at at least one bending portion BTP at an angle θ equal to a multiple of 45°. For example, each of the connection lines CNL may include at least one straight portion STP extending in the first direction DR1 and at least one oblique portion OBP connected to the straight portion STP and extending in an oblique direction inclined at an angle θ equal to a multiple of 45° relative to the first direction DR1.

[0148] The connection line CNL may be bent at the same angle θ at the bending portion BTP where the straight portion STP and the inclined portion OBP intersect. For example, the angles θ between the straight portion STP and the inclined portion OBP of the connection line CNL may all be equal. According to some embodiments of the present disclosure, the angle θ between the straight portion STP and the inclined portion OBP of the connection line CNL may be 135°, which is a multiple of 45° within the obtuse angle range.

[0149] The connection lines CNL may be a pattern in which the straight line portion STP and the oblique portion OBP are formed as one body. For example, the straight line portion STP and the oblique portion OBP of each of the connection lines CNL may be formed as one body and patterned at the same time.

[0150] According to some embodiments of the present disclosure, the connection lines CNL may include a first group of connection lines CNL1 (e.g., first to seventh connection lines CNL11 to CNL17 of the first group), the first group of connection lines CNL1 connecting at least some of the first connection parts CP1 arranged in parallel in the first direction DR1 with second connection parts CP2 shifted in the same direction relative to the first direction DR1 and the second direction DR2. For example, the first group of connection lines CNL1 may connect the first connection parts CP1 with the second connection parts CP2 positioned further to the left and upper side than the first connection parts CP1 and arranged in parallel in the first direction DR1. The first group of connection lines CNL1 may include inclined parts OBP extending in substantially the same direction.

[0151] According to some embodiments of the present disclosure, one connection line CNL among the first group of connection lines CNL1 may have a shape and / or length corresponding to the shortest path among the paths that may extend from the first connection part CP1 of the corresponding pixel PX to the second connection part CP2 within a range where the portion forming the connection line CNL (e.g., the straight line portion STP and the oblique portion OBP) satisfies the angle condition described above. For example, one connection line CNL may include a single straight line portion STP and a single oblique portion OBP. For example, among the first group of connection lines CNL1, the first connection line CNL11 positioned at the rightmost position in the first direction DR1 may have the shortest length and may include a single straight line portion STP and a single oblique portion OBP.

[0152] Among the first group of connection lines CNL1, each of the lines other than the first connection line CNL11 may include at least two straight line portions STP and at least two oblique portions OBP. For example, among the first group of connection lines CNL1, the second connection line CNL12 adjacent to the first connection line CNL11 may include two straight line portions STP and two oblique portions OBP. Each of the straight line portions STP of the second connection line CNL12 may be arranged in parallel with the straight line portions STP of the first connection line CNL11 in the first direction DR1 or in the second direction DR2 orthogonal to the first direction DR1.

[0153] According to some embodiments of the present disclosure, the straight portions STP of the first group of connection lines CNL1 may extend in the same direction and may be substantially parallel to each other. Similarly, the oblique portions OBP of the first group of connection lines CNL1 may extend in the same direction and may be substantially parallel to each other.

[0154] According to some embodiments of the present disclosure, the connection lines CNL may further include a second group of connection lines CNL2 arranged in a direction different from the first group of connection lines CNL1 relative to the first connection parts CP1 in at least one of the first direction DR1 and the second direction DR2. For example, the connection lines CNL may further include a second group of connection lines CNL2 (e.g., the first connection lines CNL21 to the eighth connection lines CNL28 of the second group) connecting some other first connection parts of the first connection parts CP1 arranged in parallel in the first direction DR1 with the second connection parts CP2 shifted in the same direction relative to the first direction DR1 and the second direction DR2. For example, the second group of connection lines CNL2 may connect the first connection part CP1 with the second connection part CP2 positioned further to the left and lower side than the first connection part CP1 and arranged in parallel in the first direction DR1. The second group of connection lines CNL2 may include an inclined portion OBP extending in substantially the same direction.

[0155] According to some embodiments of the present disclosure, one connection line CNL among the second group of connection lines CNL2 may have a shape and / or length corresponding to the shortest path among the paths that may extend from the first connection part CP1 of the corresponding pixel PX to the second connection part CP2 within a range in which the portion (e.g., the straight line portion STP and the oblique portion OBP) forming the connection line CNL satisfies the angle condition described above. For example, one connection line CNL may include a single straight line portion STP and a single oblique portion OBP. For example, among the second group of connection lines CNL2, the first connection line CNL21 positioned at the rightmost position in the first direction DR1 may have the shortest length and may include a single straight line portion STP and a single oblique portion OBP. Among the second group of connection lines CNL2, each of the lines other than the first connection line CNL21 may include at least two straight line portions STP and at least two oblique portions OBP. For example, among the second group of connection lines CNL2, the second connection line CNL22 adjacent to the first connection line CNL21 may include two straight line portions STP and two oblique portions OBP. Each of the straight line portions STP of the second connection lines CNL22 may be arranged in parallel with the straight line portions STP of the first connection lines CNL21 in the first direction DR1 or in the second direction DR2.

[0156] According to some embodiments of the present disclosure, the straight portions STP of the second group of connection lines CNL2 may extend in the same direction and may be substantially parallel to each other. Similarly, the oblique portions OBP of the second group of connection lines CNL2 may extend in the same direction and may be substantially parallel to each other.

[0157] According to some embodiments of the present disclosure, the connection lines CNL may have substantially the same width WD. As used herein, the statement that the connection lines CNL have substantially the same width WD may mean that each of the connection lines CNL has a width WD of a specific length (e.g., a first length L1), or has a width WD within a range that can be determined to be substantially equal to a specific length under a tolerance range (e.g., a set or predetermined tolerance range).

[0158] According to some embodiments of the present disclosure, a group of connection lines CNL adjacent to each other (e.g., the first group of connection lines CNL1 or the second group of connection lines CNL2) may be arranged at substantially uniform intervals SP. As used herein, the statement that the connection lines CNL have substantially the same intervals SP may mean that the connection lines CNL may be uniformly arranged sequentially and / or continuously at intervals SP of a specific length or at intervals SP that can be determined to be substantially equal to a specific length within a tolerance range (e.g., a set or predetermined tolerance range).

[0159] According to some embodiments of the present disclosure, a group of connection lines CNL adjacent to each other may be sequentially and / or continuously arranged at intervals SP of the same length (e.g., intervals SP of the first length L1) substantially equal to the width WD of each of the connection lines CNL. For example, the first group of connection lines CNL1 (e.g., the first connection lines CNL11 to the seventh connection lines CNL17 of the first group) may be sequentially and / or continuously arranged such that they are spaced apart from each other at least at the straight line portion STP by an interval SP of the first length L1 equal to the width WD of each of the connection lines CNL. For example, if each of the connection lines CNL has a width WD of about 3 μm, the first group of connection lines CNL1 or the second group of connection lines CNL2 may be sequentially and / or continuously arranged such that they are spaced apart from each other at least at the straight line portion STP by an interval SP of about 3 μm.

[0160] According to the above-described embodiment, the connection lines CNL may be arranged at regular intervals in the display area DA. In addition, the connection lines CNL may be formed to have a smaller length (e.g., the shortest length corresponding to the shortest path among the paths that can reach the second connection part CP2 from the first connection part CP1 while the straight line part STP and the inclined part OBP extend in a direction and / or at an angle) while maintaining a uniform interval and not intersecting each other.

[0161] In this way, the connection lines CNL having the target width WD can be formed more uniformly, and the resistance of each of the connection lines CNL and the resistance deviation of the connection lines CNL can be reduced or minimized. For example, since the connection lines CNL are arranged at substantially uniform intervals, it is possible to prevent or reduce process errors and / or process deviations that may occur due to differences in exposure conditions in a patterning process (e.g., a patterning process including a photolithography process) for forming the connection lines CNL, and form the connection lines CNL having a more uniform width WD. In addition, by forming the connection lines CNL to an optimized length (e.g., a shorter length), it may be possible to reduce or minimize the resistance of each of the connection lines CNL.

[0162] Therefore, according to the above-described embodiment, the pixel PX can emit light with more uniform brightness in response to the corresponding data signal. Therefore, the image quality of the display device 10 can be improved.

[0163] Fig.10 is a flow chart showing a method for forming a connection line CNL according to some embodiments of the present disclosure. For example, Fig.10 A method of designing connection lines CNL is schematically shown, which includes exploring an optimal line path for each of the connection lines CNL.

[0164] Fig.11 is a plan view showing the found line paths according to some embodiments of the present disclosure. For example, Fig.11 An example of a line path that satisfies the specified line path search condition is shown.

[0165] Combination Figures 1 to 9 Reference Fig.10 and Fig.11 , the display device 10 may include a pixel PX, the pixel PX includes a pixel transistor Tpx, a light emitting element EL, and a connection line CNL connecting the pixel transistor Tpx to the light emitting element EL, respectively. The method of manufacturing the display device 10 may include: sequentially exploring an optimal line path of the connection line CNL according to the following steps; and forming the connection line CNL according to the found line path. For example, before the process of forming the pixel PX, in the step of designing the connection line CNL of the pixel PX, a setting line path including the following steps may be performed. The connection line CNL formed along the line path set or designed by the following steps may be formed into a pattern having a position, shape and / or length that satisfies the path exploration conditions set or specified in the following design steps:

[0166] <ST10: Input connection part position>

[0167] Initially, in order to set a line path for forming the connection line CNL (e.g., a moving path or a connection path from the first connection portion CP1 to the second connection portion CP2 corresponding to each of the connection lines CNL), the positions of the corresponding connection portions connected to the corresponding connection lines CNL may be input into a design program. For example, based on a graphic design system (GDS), the coordinates of a start point SRP associated with the first connection portion CP1 (e.g., the first connection portion CP1 connected to the pixel transistor Tpx) and the coordinates of an end point EDP associated with the second connection portion CP2 (e.g., the second connection portion CP2 connected to the light emitting element EL) may be input.

[0168] <ST20: Input line path search conditions>

[0169] Then, the desired line path exploration conditions may be input for the connection line CNL. Fig.11 As shown in , the minimum moving unit applied to the process of exploring the line path for the connection line CNL can be set to a square in a plurality of squares having four sides of a second length L2 equal to a multiple (e.g., twice) of the width WD of each of the connection lines CNL (i.e., each square in a squared shape in a plurality of squares having four sides of a second length L2 equal to a multiple (e.g., twice) of the width WD of each of the connection lines CNL). For example, when each of the connection lines CNL has a width WD of a first length L1, the minimum moving unit of the line movement applied in the process of exploring the path for the connection line CNL can be set to a square in a plurality of squares having four sides of a second length L2 equal to twice the first length L1 (i.e., each square in a squared shape in a plurality of squares having four sides of a second length L2 equal to twice the first length L1). Each of the connection lines CNL thus formed can have a width WD of the first length L1, and adjacent connection lines CNL can be evenly arranged at intervals SP of the first length L1.

[0170] In addition, the moving direction from one point to the next point on the moving path applied in the process of exploring the line path for the connection line CNL may be limited to the first direction DR1 (e.g., X direction) and the second direction DR2 (e.g., Y direction) extending only on the sides of the square (i.e., grid) and the diagonal direction of the grid (e.g., fourth direction DR4 and fifth direction DR5). For example, at the point where the line path of each connection line CNL starts or bends, it may be moved only in the X direction or the Y direction to reach the next point, or it may be moved to a point located in the diagonal direction separated by the same distance in the X direction and the Y direction. Each of the connection lines CNL thus formed may include at least one straight portion STP and at least one inclined portion OBP extending in an inclined direction inclined at an angle θ equal to a multiple of 45° relative to the first direction DR1 extending the straight portion STP.

[0171] In addition, when the connection lines CNL are positioned in the same layer, when sequentially exploring line paths for the connection lines CNL, a path for at least one connection line CNL that is first found may be selected as an obstacle to be avoided in exploring line paths for subsequent connection lines CNL. In this way, it may be possible to explore a line path for a target connection line CNL by avoiding the path of at least one connection line CNL, and therefore, it may be possible to set the paths of the connection lines CNL so that the connection lines CNL do not intersect with each other.

[0172] <ST30 to ST60: Sequential exploration of line paths>

[0173] Subsequently, under the set line path exploration conditions, the line path for the connecting line CNL can be explored sequentially. For example, based on a specific direction and / or position, a priority is assigned to the starting point SRP associated with the first connecting part CP1, and based on a depth-first exploration (DFS) algorithm, the best line path can be explored from the line path from the target starting point SRP to the corresponding end point EDP (for example, the end point EDP associated with the second connecting part CP2 connected to the selected first connecting part CP1). For example, sequence numbers are assigned to the starting point SRPs, respectively. The starting point SRP assigned No. 1 (N=1) and the corresponding end point EDP are selected as the targets of the line path exploration. Then, the best line path from the selected starting point SRP to the end point EDP can be explored. Subsequently, by increasing the sequence numbers one by one, the best line path can be explored for the starting point SRP corresponding to the next sequence number (for example, No. 2) to the corresponding end point EDP, etc. In this way, the best line path can be explored sequentially for the starting point SRPs assigned No. 1 to the last number to the corresponding end point EDP.

[0174] According to some embodiments of the present disclosure, the exploration condition of the optimal line path may be the shortest distance. Fig.11As shown in , among the line paths that can reach the end point EDP from the starting point SRP of the target for line path exploration, the first line path R1, the second line path R2, and the third line path R3 can be found under the line path exploration condition (e.g., the set or predetermined or selected line path exploration condition). In this case, among the first line path R1, the second line path R2, and the third line path R3 found, the line path with the shortest distance (e.g., the first line path R1) can be selected as the best line path, and accordingly, the line path exploration for the target point (e.g., the starting point SRP and the end point EDP of the sequence number) can be completed. For example, within the range of satisfying the previously input line path exploration condition, the line paths (e.g., the first line path R1, the second line path R2, and the third line path R3) that can reach the end point EDP from the selected starting point SRP can be received as feedback, and the path with the shortest distance (e.g., the first line path R1) can be found as the best line path for the target point.

[0175] According to some embodiments of the present disclosure, each of the line paths may be output in the form of coordinates corresponding to the path through which the connection line CNL passes, and the position and pattern shape of the connection line CNL corresponding to the line path may be derived based on the GDS. Fig.10 and Fig.11 As described above, the Figure 7 The line path of the connection line CNL connecting the first connection part CP1 and the second connection part CP2 is designed. Figure 8 The position and shape of the connection line CNL shown in FIG. 5 are possible.

[0176] Once the design of the connection line CNL is completed, the connection line CNL may be formed between the first connection portion CP1 and the second connection portion CP2 through a process of manufacturing a display panel including a pixel forming process.

[0177] Fig.12 is a plan view showing a connection line CNL and a dummy pattern DMP according to some embodiments of the present disclosure. For example, Fig.12 It is shown Figure 8 FIG. 1 is a plan view of an example of connection lines CNL and dummy patterns DMP located between the connection lines CNL.

[0178] Fig.13 is a plan view partially showing a connection line CNL and a dummy pattern DMP according to some embodiments of the present disclosure. For example, Fig.13 It is shown Fig.12 An enlarged plan view of area B.

[0179] Combination Figures 1 to 11 Reference Fig.12 and Fig.13, the display device 10 may further include a dummy pattern DMP positioned in a space between the connection lines CNL. According to some embodiments of the present disclosure, the dummy pattern DMP may have a shape that conforms to the connection line CNL. For example, the dummy pattern DMP may include at least one straight line pattern STPP parallel to the straight line portion STP of the connection line CNL and at least one oblique pattern OBPP parallel to the oblique portion OBP of the connection line CNL.

[0180] The connection lines CNL and the dummy patterns DMP may be arranged at substantially uniform intervals in the display area DA including the first and second display areas DA1 and DA2. For example, the dummy patterns DMP may have substantially the same width as the connection lines CNL and may be arranged at substantially the same intervals as the connection lines CNL.

[0181] The dummy pattern DMP may be formed together with the connection line CNL. For example, in a process of forming the connection line CNL, the dummy pattern DMP may be formed on the same layer as the connection line CNL using the same material as the connection line CNL.

[0182] According to some embodiments of the present disclosure, the dummy pattern DMP may be formed only at some parts of the display area DA. For example, the dummy pattern DMP may be arranged only around each group of connection lines CNL (for example, the first group of connection lines CNL1 and the second group of connection lines CNL2). However, it should be understood that the embodiments of the present disclosure are not limited thereto. For example, the connection lines CNL and the dummy pattern DMP may be formed substantially uniformly in the display area DA. Each dummy pattern DMP may overlap with the first connection portion CP1 and / or the second connection portion CP2 positioned around it, or may not overlap with the first connection portion CP1 and / or the second connection portion CP2 positioned around it. Even if at least one dummy pattern DMP overlaps with the first connection portion CP1 and / or the second connection portion CP2 positioned around it, at least one dummy pattern DMP may not be electrically connected to the first connection portion CP1 and / or the second connection portion CP2.

[0183] According to some embodiments of the present disclosure, the dummy pattern DMP may be formed at a position spaced apart from the nearby signal lines (e.g., a scan line SL and / or a data line DL) by a distance (e.g., a set or predetermined distance) in consideration of noise that may occur between the nearby signal lines (e.g., the scan line SL and / or the data line DL). According to some embodiments of the present disclosure, the dummy pattern DMP may be connected to the power line PL. For example, the dummy pattern DMP may be connected to one of the first power supply voltage line VDL, the second power supply voltage line VSL, the first initialization voltage line VIL1, and the second initialization voltage line VIL2.

[0184] According to the above-described embodiment, the connection lines CNL and the dummy patterns DMP may be arranged at uniform intervals in the display area DA. Therefore, it may be possible to prevent or reduce process errors and / or process deviations of the connection lines CNL, and the connection lines CNL can be more uniformly formed.

[0185] As described above, the display device 10 according to some embodiments may include an emission unit EMU of a pixel PX located in a first display area DA1 where a pixel driving unit PDU of the pixel PX is located and a second display area DA2 (e.g., an area where an embedded driver circuit SDR is located) around the first display area DA1. As a result, the non-display area NA of the display device 10 can be reduced, and the display area DA can be expanded.

[0186] In addition, the display device 10 according to some embodiments may include connection lines CNL that each connect the pixel driving unit PDU of the corresponding pixel PX to the emission unit EMU. The connection lines CNL may have a shape that can be formed at uniform intervals and / or widths, may be positioned or arranged at uniform intervals in the display area DA, and may have an optimized length (e.g., a shorter length). As a result, the connection lines CNL can be formed more uniformly, and the voltage drop and / or voltage drop deviation in the connection lines CNL can be reduced or suppressed.

[0187] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications can be made to the embodiments without departing substantially from the spirit and scope of the embodiments according to the present invention. Therefore, the disclosed embodiments of the present invention are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: a substrate comprising a first display area and a second display area around the first display area; a plurality of pixels on the substrate and including a corresponding plurality of pixel transistors in the first display area and a corresponding plurality of light emitting elements in the first display area and the second display area and connected to the corresponding plurality of pixel transistors; as well as a plurality of connection lines, wherein the plurality of connection lines respectively connect the plurality of pixel transistors with the plurality of light emitting elements, wherein each of the plurality of connecting lines comprises one or more straight line portions extending in a first direction and one or more inclined portions connected to the one or more straight line portions and extending in an inclined direction inclined at an angle equal to a multiple of 45° relative to the first direction, and Wherein, the angles formed by the straight portion and the inclined portion of the connecting line are equal to each other.

2. The display device according to claim 1, wherein: The angle formed by the straight portion and the inclined portion of each of the plurality of connection lines is equal to 135°.

3. The display device according to claim 1, wherein: Each of the plurality of connection lines has a width of a first length.

4. The display device according to claim 3, wherein: Straight line portions of two adjacent connection lines among the plurality of connection lines are spaced apart from each other by an interval equal to the first length.

5. The display device according to claim 1, wherein: The plurality of pixels further comprises: a plurality of connection electrodes, the plurality of connection electrodes being connected to corresponding plurality of pixel transistors; a plurality of first connection portions, the plurality of first connection portions overlapping the plurality of connection electrodes; and a plurality of second connection portions, the plurality of second connection portions overlapping the plurality of first electrodes of the corresponding plurality of light emitting elements, and Each of the plurality of connection lines is connected between the first connection portion and the second connection portion of one of the plurality of pixels.

6. The display device according to claim 5, wherein: The plurality of connecting lines include: a first connecting line, the first connecting line comprising a single straight portion and a single inclined portion; and A second connecting line is adjacent to the first connecting line and includes at least two straight sections and at least two inclined sections.

7. The display device according to claim 6, wherein: The first connection portion connected to the first connection line and the first connection portion connected to the second connection line are arranged in parallel in the first direction, and Wherein, the second connection portion connected to the first connection line and the second connection portion connected to the second connection line are arranged in parallel in the first direction.

8. The display device according to claim 7, wherein: Each of the at least two straight line portions of the second connection line is parallel to the straight line portion of the first connection line in the first direction or in a second direction orthogonal to the first direction.

9. The display device according to claim 1, further comprising: A dummy pattern is in a space between the plurality of connection lines and includes a straight line pattern parallel to the straight line portions of the connection lines and an inclined pattern parallel to the inclined portions of the connection lines.

10. The display device according to claim 9, wherein: The plurality of connection lines and the dummy patterns are arranged at uniform intervals in a display area including the first display area and the second display area.

11. The display device according to claim 9, wherein: The dummy pattern is in the same layer as the plurality of connection lines and includes the same material as the plurality of connection lines.

12. The display device according to claim 1, further comprising: a circuit layer on the substrate and including the plurality of pixel transistors; as well as A light emitting element layer overlaps the circuit layer and includes the plurality of light emitting elements.

13. The display device according to claim 12, further comprising: An embedded driver circuit is in the circuit layer and includes a driver transistor in the second display area.

14. The display device according to claim 13, wherein: The embedded driver circuit overlaps the light emitting element of at least one of the plurality of pixels.

15. The display device according to claim 13, wherein: A first pixel among the plurality of pixels includes a first pixel transistor in the first display area and a first light emitting element in the second display area, and The second pixel among the plurality of pixels includes a second pixel transistor in the first display area and a second light emitting element in the first display area.

16. The display device according to claim 15, wherein: The connection line connecting the first pixel transistor and the first light emitting element has a longer length than the connection line connecting the second pixel transistor and the second light emitting element.

17. The display device according to claim 1, wherein: Each of the plurality of pixels includes a pixel driving unit and an emission unit, the pixel driving unit includes at least one pixel transistor, the emission unit includes at least one light emitting element, and Among the plurality of pixels, at least two pixels having corresponding pixel driving units adjacent to each other and corresponding emission units adjacent to each other form a unit pixel.

18. The display device according to claim 17, wherein: A plurality of pixel driving units and a plurality of emission units of a plurality of unit pixels formed by the plurality of pixels are in the first display area and the second display area, wherein the plurality of pixel driving units of the plurality of unit pixels are in the first display area at a first pitch in the first direction, and The plurality of emission units of the plurality of unit pixels are located in the first display area and the second display area at a second interval greater than the first interval in the first direction.

19. The display device according to claim 1, wherein: The straight portion and the inclined portion of each of the plurality of connection lines are formed as one body.

20. A method for manufacturing a display device, wherein: The display device includes a plurality of pixels, the plurality of pixels include a plurality of pixel transistors, a plurality of light emitting elements, and a plurality of connection lines connecting the plurality of pixel transistors with the plurality of light emitting elements, and the method includes: inputting positions of a plurality of first connection portions connected to the plurality of pixel transistors and positions of a plurality of second connection portions connected to the plurality of light emitting elements into a design program; inputting line path exploration conditions for the plurality of connecting lines; sequentially exploring a plurality of line paths for the plurality of connection lines under the line path exploration condition; and forming the plurality of connection lines between the plurality of first connection parts and the plurality of second connection parts according to the plurality of line paths found, Among them, the line path exploration conditions include the condition that each square in a grid of multiple squares having four sides with a length equal to a multiple of the width of each of the multiple connecting lines is a minimum moving unit and the condition that the path moves only in the straight line direction extending from the four sides of the square and in the diagonal direction of the square.

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